LDPC decoding with trap block management

Abstract

A method and apparatus for decoding, wherein a first failed decoding operation is performed by an LDPC decoder on the original bit values ​​of an FEC block. When the FEC block is determined to be a trap block, an updated LLR map is generated; if the number of unsatisfied check nodes (i.e., syndrome weight) is less than a threshold, the FEC block is determined to be a trap block; the updated LLR map and the original bit values ​​of the FEC block or a failed decoded output block from a previous failed decoding operation on the trap block are provided to the LDPC decoder; a decoding operation of the LDPC decoder is performed on the bit values ​​of the FEC block or the failed decoded output block from the previous failed decoding operation using the updated LLR map; and the generating, providing, and performing are repeated until the decoding operation is successful or until a predetermined number of trap block decoding iterations have been performed. When the decoding operation successfully decodes the FEC block, the codeword is output.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 249,556 filed on September 28, 2021, the contents of which are incorporated herein by reference in their entirety. Background Art

[0003] Error correction solutions are subject to an error floor, where further reductions in the input error rate no longer achieve significant improvements in error correction performance. The frame error rate (FER) defines the error floor performance, where the actual performance of a particular decoding process begins to deviate significantly from the theoretical performance of the particular decoding process. The expected performance of a particular decoding process is sometimes referred to as the "waterfall" of the decoding process, and it extends below the error floor.

[0004] Floor breaking methods employed in previous devices typically alter the low-density parity check (LDPC) decoding algorithm itself. However, these methods rely on recycling challenging blocks through a standard LDPC decoder, which itself does not have the ability to handle error floor conditions. Furthermore, FER and error floor are inversely related, so that improving one of these factors results in a degradation of the other.

[0005] The property of the error floor is that when a performance curve (e.g., a curve of frame errors versus bit error rate (BER)) approaches the error floor, there are few bit errors remaining in the forward error correction (FEC) block, but the errors are located in a way that makes the standard LDPC algorithm ineffective in correcting the erroneous bits. The conditions that produce these decoding failures near the location where the performance curve approaches the error floor are generally referred to as "trap sets." The trap sets produced when the performance curve approaches the error floor exhibit decoding failures even though the number of failed check nodes in the block that failed to decode is ultra-low. The syndrome of the block that failed to decode indicates the number of failed check nodes for that particular decoding operation. Therefore, these trap sets produce decoding failures even if the syndrome of the block is ultra-low (e.g., less than 20 failed check nodes).

[0006] Therefore, there is a need for a method and apparatus that will reduce the number of errors caused by trap sets in order to extend the performance curve below the error floor for a particular LDPC decoding process. Summary of the invention

[0007] A decoding circuit for a memory controller includes an input for receiving an original bit value of an FEC block; and an LDPC decoder coupled to the input. The LDPC decoder performs a failed decoding operation on the original bit value of the FEC block and outputs a syndrome of the failed decoding operation and a failed decoding output block.

[0008] The decoding circuit includes a trap detection comparator coupled to the LDPC decoder, and a trap controller coupled to the input of the LDPC decoder and the trap detection comparator. The trap detection comparator determines whether the FEC block is a trap block by comparing the number of failed check nodes indicated by the syndrome with an error threshold. When the number of failed check nodes indicated by the syndrome is less than the error threshold, the FEC block is determined to be a trap block. When the FEC block is determined to be a trap block, the trap controller uses the LDPC decoder to perform trap block decoding iterations until the decoding operation is successful or until a predetermined number of trap block decoding iterations have been performed. At each trap block decoding iteration, the trap controller generates an updated log-likelihood ratio (LLR) map; and provides the updated LLR map and the original bit value of the FEC block or a failed decoded output block from a previously failed decoding operation to the LDPC decoder; and sends an indication to the LDPC decoder to perform a decoding operation. In response to the indication, the LDPC decoder uses the updated LLR map to perform a decoding operation on the corresponding bits of the original bit value of the FEC block or the failed decoded output block from the previously failed decoding operation. When the FEC block is not determined to be a trap block, the decoding circuit outputs an error indication at the output of the decoding circuit. When the decoding operation is successful to generate a codeword, the decoding circuit outputs the codeword.

[0009] A memory controller having a decoding circuit is disclosed, the decoding circuit comprising an input for receiving an original bit value of an FEC block; a block buffer memory coupled to the input to store the received original bit value of the FEC block; and an LDPC decoder coupled to the block buffer memory. The LDPC decoder performs a failed decoding operation on the original bit value of the FEC block and outputs a syndrome of the failed decoding operation and a failed decoding output block. The decoding circuit comprises a trap detection comparator coupled to the LDPC decoder and a trap controller coupled to the block buffer memory. The trap detection comparator determines whether the FEC block is a trap block by comparing the number of failed check nodes indicated by the syndrome with an error threshold, and when the number of failed check nodes indicated by the syndrome is less than the error threshold, the FEC block is determined to be a trap block. When the FEC block is determined to be a trap block, the trap controller uses the LDPC decoder to perform trap block decoding iterations until the decoding operation is successful or until a predetermined number of trap block decoding iterations have been performed. At each trap block decoding iteration, the trap controller generates an updated LLR map; and provides the updated LLR map and the original bit value of the FEC block or the failed decoded output block from a previously failed decoding operation to the LDPC decoder; and sends an indication to the LDPC decoder to perform a decoding operation. In response to the indication, the LDPC decoder uses the updated LLR map to perform a decoding operation on the corresponding bits of the original bit value of the FEC block or the failed decoded output block from the previously failed decoding operation. When the FEC block is not determined to be a trap block, the memory controller outputs an error message. When the decoding operation is successful so as to generate a codeword, the memory controller outputs the codeword.

[0010] A solid state drive (SSD) is disclosed, the solid state drive comprising a plurality of flash memory devices and a memory controller coupled to the plurality of flash memory devices. The memory controller has a decoding circuit, the decoding circuit comprising an input for receiving an original bit value of an FEC block; a block buffer memory coupled to the input to store the received original bit value of the FEC block; and an LDPC decoder coupled to the block buffer memory. The LDPC decoder performs a failed decoding operation on the original bit value of the FEC block, and outputs a syndrome of the failed decoding operation and a failed decoding output block. The decoding circuit comprises a trap detection comparator coupled to the LDPC decoder and a trap controller coupled to the block buffer memory. The trap detection comparator determines whether the FEC block is a trap block by comparing the number of failed check nodes indicated by the syndrome with an error threshold. When the number of failed check nodes indicated by the syndrome is less than the error threshold, the FEC block is determined to be a trap block. When the FEC block is determined to be a trap block, the trap controller uses the LDPC decoder to perform a trap block decoding iteration until the decoding operation is successful or until a predetermined number of trap block decoding iterations have been performed. At each trap block decoding iteration, the trap controller generates an updated LLR map; and provides the updated LLR map and the original bit value of the FEC block or the failed decoded output block from a previously failed decoding operation to the LDPC decoder; and sends an indication to the LDPC decoder to perform a decoding operation. In response to the indication, the LDPC decoder uses the updated LLR map to perform a decoding operation on the corresponding bits of the original bit value of the FEC block or the failed decoded output block from the previously failed decoding operation. When the FEC block is not determined to be a trap block, the memory controller outputs an error message. When the decoding operation is successful so as to generate a codeword, the memory controller outputs the codeword.

[0011] A method for decoding is disclosed, the method comprising: performing a first failed decoding operation on the original bit value of an FEC block by an LDPC decoder that outputs a syndrome of a failed decoding operation and a failed decoding output block. The method comprises determining whether the FEC block is a trap block by comparing the number of failed check nodes indicated by the syndrome with an error threshold, and when the number of failed check nodes indicated by the syndrome is less than the error threshold, the FEC block is determined to be a trap block. When the FEC block is not determined to be a trap block, an error indication is output. When the FEC block is determined to be a trap block, the method includes: generating an updated LLR map; providing the updated LLR map and the original bit value of the FEC block or a failed decoded output block from a previously failed decoding operation on the trap block to the LDPC decoder; performing a decoding operation of the LDPC decoder on the bit value of the FEC block or the failed decoded output block from the previously failed decoding operation on the trap block using the updated LLR map; and repeating the generating, providing and performing until the decoding operation is successful or until a predetermined number of trap block decoding iterations have been performed. When the decoding operation successfully decodes the FEC block, the codeword is output. When the decoding operation does not successfully decode the FEC block and a predetermined number of trap block decoding iterations have been performed, an error indication is output.

[0012] The method and apparatus of the present invention reduces the number of errors caused by trap sets in order to extend the performance curve below the normal error floor of a particular LDPC decoding process. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate various examples. The drawings referred to in this brief description are not drawn to scale.

[0014] Figure 1 is a diagram showing an example of a decoding circuit including a block buffer memory.

[0015] Figure 2 It is shown that Figure 1 A diagram of an example of a decoding circuit for a memory controller is shown.

[0016] Figure 3 It is shown that Figure 1 A diagram of an example of a decoding circuit for an SSD is shown.

[0017] Figure 4 is a diagram showing an example of decoding that fails for the first time.

[0018] Figure 5is a diagram illustrating an example of a trapping block decoding iteration, where a decoding operation is performed on a failed decoded output block from a previous iteration.

[0019] Figure 6 is a diagram illustrating an example of a trapping block decoding iteration, where decoding operations are performed on the original bit values ​​of an FEC block.

[0020] Figure 7 is a diagram showing an example of a first failed decode and N trapping block decoding iterations.

[0021] Fig. 8A is a diagram showing an example in which an updated LLR map is generated using weak bit values ​​and random probability values.

[0022] Figure 8B is a diagram illustrating an example in which an updated LLR map is generated using weak bit values ​​and random probability values, and in which the random probability values ​​are generated using percentage changes.

[0023] Figure 8C is a diagram illustrating an example in which an updated LLR map is generated using weak bit values ​​and random probability values, and in which the random probability values ​​are generated using percentage changes.

[0024] Fig.8D is a diagram showing a table indicating an example of generating updated LLRs.

[0025] Fig. 8E is a diagram illustrating an example in which updated LLR values ​​are generated using input received at a decoding circuit and / or a memory controller.

[0026] Fig.9A An example of a decoding circuit that does not include the block buffer memory 5 is shown.

[0027] Fig. 9B It is shown that Fig.9A A diagram of an example of a decoding circuit for a memory controller is shown.

[0028] Fig. 9C It is shown that Fig.9A A diagram of an example of a decoding circuit for an SSD is shown.

[0029] Fig.10 is a diagram illustrating a method for decoding in which a trapping block is identified and actions are performed to attempt to decode the trapping block.

[0030] Fig.11 It is shown Fig.10 FIG. 1 is a diagram of an example of a first trapping block decoding iteration in a method of where decoding is performed on the original bit values ​​of the FEC block.

[0031] Fig.12 It is shown Fig.10 FIG. 1 is a diagram of an example of a trapping block decoding iteration in a method of performing decoding on a failed decoded output block from a previously failed decoding operation on a trapping block.

[0032] Fig.13 It shows that except Fig.10 The method may also be executed in addition to the blocks shown in the block diagram.

[0033] Fig.14 is a graph showing frame errors on the vertical axis and bit error rate on the horizontal axis, which shows a performance curve and waterfall of a conventional LDPC decoder.

[0034] Fig.15 is a graph showing frame errors on the vertical axis and bit error rates on the horizontal axis, which shows Figures 1 to 13 Example performance curves of the method and apparatus are shown. DETAILED DESCRIPTION

[0035] Figure 1 A decoding circuit 1 is shown, which includes a block buffer memory 5, an LDPC decoder 3 coupled to the block buffer memory 5, a trap detection comparator 4 coupled to the LDPC decoder 3, and a trap controller 2. The trap controller 2 is coupled to the block buffer memory 5, the LDPC decoder 3, and the trap detection comparator 4. The decoding circuit 1 includes an input 14, which may be referred to as a "decoding circuit input" 14 hereinafter, which is coupled to the block buffer memory 5 and the trap controller 2. The LDPC decoder 3 includes an input 10 for receiving an FEC block from the block buffer memory 5, which may be referred to as a "FEC block input" 10 hereinafter; an input 11 for receiving an LLR map from the trap controller 2, which may be referred to as a "LLR map input" 11 hereinafter; and an input 16, which may be referred to as a "control input" 16, which is coupled to an output of the trap controller 2. The term "LLR map" as used in this application is a table or other list indicating LLR values ​​to be used in a particular LDPC decoding operation. In this example, the LDPC decoder 3 includes an output 12 for outputting a decoded block to the trap controller 2, which output may be referred to as the "decoded block output" 12 hereinafter; and an output 13 for outputting a syndrome to the trap detection comparator 4, which output may be referred to as the "syndrome output" 13 hereinafter. The syndrome of an FEC block that fails to be decoded in the LDPC decoder 3 indicates the number of failed check nodes for a particular decoding operation. Although two inputs 11, 16 are shown to couple the LDPC decoder 3 to the trap controller 2, it should be understood that alternatively a single input may be used to couple the LDPC decoder 3 to the trap controller 2. The trap controller 2 has an output 15 that forms the output of the decoding circuit, which output may be referred to as the "decoding circuit output" 15.

[0036] In one example, the decoding circuit 1 is implemented as an integrated circuit (IC) device formed on one or more semiconductor dies, which may be an application specific integrated circuit (ASIC) or a programmable logic device (PLD), such as a field programmable gate array (FPGA), but is not limited thereto. Figure 1 In the example shown, for illustration purposes, the decoding circuit 1 is shown as having a single input 14 and a single output 15. However, in other examples, the decoding circuit 1 includes multiple inputs 14 and multiple outputs 15 that may be coupled to the trap controller 2 or to other components of the decoding circuit 1.

[0037] exist Figure 2 In the example shown, the decoding circuit 1 is implemented in the memory controller 6. In one example, the memory controller 6 is implemented as an IC device formed on a single semiconductor die, which may be an ASIC or a PLD (such as an FPGA), but is not limited thereto. The memory controller 6 includes a local memory 8. In one example, the local memory 8 is a register or a static random access memory (SRAM) block that is individually accessible by one or more of the trap controller 2, the LDPC decoder 3, the trap detection comparator 4, or other circuits of the memory controller 6 or the decoding circuit 1. Although the local memory 8 is shown as being in the memory controller 6, portions of the local memory 8 may be located within one or more of the trap controller 2, the LDPC decoder 3, the trap detection comparator 4, and the decoding circuit 1, and may include registers or SRAM blocks that are accessible by the corresponding ones of the trap controller 2, the LDPC decoder 3, the trap detection comparator 4, and the decoding circuit 1. In Figure 2 In the example shown, the memory controller 6 is shown as having one or more inputs 18 (memory controller inputs) and one or more outputs 19 (memory controller outputs). The one or more inputs 18 and one or more outputs 19 are coupled to the corresponding inputs 14 and outputs 15 of the decoding circuit 1 through the circuitry of the memory controller 6.

[0038] Figure 3An example is shown in which the decoding circuit 1 is implemented in a solid-state drive (SSD) 9. The SSD 9 includes a memory controller 6 coupled to a plurality of memory devices 7. Each memory device 7 is a packaged semiconductor die or "chip" that is coupled to the memory controller 6 by a conductive path 18a that couples instructions, data, and other information between each flash memory device 7 and the memory controller 6. In one example, the memory device 7 is a flash NAND memory device that is implemented as a separately packaged IC device or an IC device packaged in a multi-chip module. In one example, each flash memory device 7 includes NAND memory cells organized into blocks and pages, where each block is composed of NAND strings that share the same set of word lines. The memory device 7 may be a single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), or penta-level cell (PLC) device, but is not limited thereto. The memory device 7 may be any type of memory storage device.

[0039] In the following discussion, Figure 3 The operation and various components of the decoding circuit 1 are discussed in the context of the memory controller 6 of the SSD 9. However, it should be understood that the decoding circuit 1 can be implemented as Figure 1 Standalone devices as shown or in Figure 2 The memory controller 6 is shown as a separate device.

[0040] The memory controller 6 receives read and write instructions from the host computer, and performs programming operations, erasing operations, and reading operations on the memory cells of the memory device 7 to complete the instructions from the host computer. For example, when a write instruction including data to be stored is received from the host computer, the memory controller 6 generates a codeword including the received data, and encodes the codeword into an FEC block, which is sent to one or more memory devices in the memory device 7 together with the corresponding program instruction. The memory device 7 executes the requested program instruction and stores the FEC block by programming the memory cells of the corresponding memory device 7 (for example, as a logical page). The memory controller 6 can also erase the cells of the memory device 7. When a read instruction is received from the host computer, the memory controller 6 sends the read instruction to one or more memory devices in the memory device 7, and in response, one or more memory devices in the memory device 7 perform a read and couple the read result in the form of the original bit value of the FEC block to the memory controller 6. In response to receiving the original bit value of the FEC block, the memory controller 6 couples the original bit value of the FEC block to the decoding circuit 1 for decoding.

[0041] In one example, some or all of the trap controller 2, the LDPC decoder 3, the trap detection comparator 4, the block buffer memory 5, and the controller 6 include circuits that are dedicated circuits for performing operations. In another example, some or all of the trap controller 2, the LDPC decoder 3, the trap detection comparator 4, the block buffer memory 5, and the controller 6 include firmware that includes instructions executed on one or more processors, wherein the instructions are stored in registers of one or more of the memory controller 6, the trap controller 2, the LDPC decoder 3, the trap detection comparator 4 and / or stored in the local memory 8. In one example, some or all of the memory controller 6, the trap controller 2, the LDPC decoder 3, and the trap detection comparator 4 include a processor (not shown) for executing instructions, and one or more firmware images are loaded into the memory controller 6 prior to operation of the memory controller 6, the firmware image including instructions to be executed by one or more of the memory controller 6, the trap controller 2, the LDPC decoder 3, and the trap detection comparator 4.

[0042] Although examples of the present invention are described as "firmware", it should be understood that embodiments of the present invention may or may not include firmware. In one example, one or more software programs are used to perform some or all of the method blocks and functions described in this application. In a specific example, one or more software stacks are stored in the decoding circuit 1 and / or the memory controller 6, which can operate on one or more processors to perform some or all of the various functions and method blocks described in this application.

[0043] In one example, a read operation is performed in which the controller 6 reads one or more memory devices 7 and in response receives the original bit values ​​of the FEC block coupled to the decoding circuit input 14. The original bit values ​​of the FEC block received at the decoding circuit input 14 are coupled to the block buffer memory 5. The block buffer memory 5 stores the original bit values ​​of the received FEC block. The block buffer memory 5 can be a register or SRAM block that can be accessed separately by the LDPC decoder 3, but is not limited thereto.

[0044] The original bit values ​​of the FEC block are coupled to the LDPC decoder 3 at the FEC block input 10. The LDPC decoder 3 performs a decoding operation on the original bit values ​​of the FEC block and outputs a syndrome at a syndrome output 13, and generates an output at a decoding block output 12. When the decoding is successful, the output at the decoding block output 12 is the stored codeword. When the decoding is unsuccessful (i.e., a failed decoding operation), the output at the decoding block output 12 is a failed decoding output block. The term "failed decoding output block" as used herein is an output from an LDPC decoder from a failed decoding operation. The term "failed decoding" as used in this application is a decoding operation of an FEC block that does not successfully identify a stored codeword corresponding to the FEC block (e.g., a decoding operation that does not result in a syndrome of 0).

[0045] When the LDPC decoder 3 performs a failed decoding operation on the original bit values ​​of the FEC block, the LDPC decoder 3 outputs a syndrome of the failed decoding operation at the syndrome output 13 and outputs a failed decoding output block at the decoded block output 12 .

[0046] When an FEC block is not determined to be a trap block, Figures 1 to 3 The memory controller 6 outputs an error indication at the decoding circuit output 15, which may be, for example, an error flag. In response to the error indication, the memory controller 6 outputs an error message at the memory controller output 19. In one example, the decoding circuit output 15 is coupled to the memory controller output 19, and the error indication output at the decoding circuit output 15 is coupled to the memory controller output 19 and the output at the memory controller output. In response to the error message, the host computer may then perform a RAID process to recover the codeword, or a recovery process may be performed by the memory controller 6 in which additional reading and soft decoding are performed.

[0047] Figure 4 A failed decoding operation is shown, which may be referred to as a "first failed decoding operation" hereinafter. The term "first failed decoding operation" as used in this application refers to the first time that a particular FEC block fails to be successfully decoded when the particular FEC block is determined to be a trap block (e.g., a particular FEC block on which a decoding operation is performed, where the output of the decoding operation indicates that the particular block is a trap block). Figure 4In the example shown, the original bit values ​​of the FEC block 21 are received from the block buffer memory 5 at the FEC block input 10, and the LLR map 22 (which may be referred to as the "initial LLR map") is generated by the trap controller 2 and coupled to the LDPC decoder 3 via the LLR map input 11. The term "LLR map" as used in the present application is an indication of a plurality of LLR values, and may be in the form of one or more words or a sequence of ones and zeros indicating corresponding LLR values ​​in the plurality of LLR values. In this example, the LDPC decoder 3 fails to decode the FEC block corresponding to the original bit values ​​of the FEC block 21, so the LDPC decoder 3 generates a failed decoded output block 24 at the decoded block output 12 and a syndrome 45 at the syndrome output 13. In one example, the first failed decoding operation is a soft decoding operation in which the initial LLR map 22 is used (e.g., a 3-bit soft decoding operation in which the input of each bit position includes 1 or 0 and an LLR value). Alternatively, the first failed decoding operation may be a hard decoding operation. When the first failed decoding is a hard decoding, the initial LLR map is not generated or provided to the LDPC decoder 3.

[0048] The trap detection comparator 4 determines whether the FEC block is a trap block by comparing the number of failed check nodes indicated by the syndrome with an error threshold. When the number of failed check nodes indicated by the syndrome is less than the error threshold, the FEC block is determined to be a trap block. In one example, the error threshold is coupled to the trap detection comparator 4 from the trap controller 2. Alternatively, the error threshold is stored in a local memory 8 accessible to the trap detection comparator 4 or in a portion of the local memory 8 within the trap detection comparator 4. In one example, the error threshold is received at inputs 14, 18, thereby allowing a user of the memory controller 6 to set the error threshold to a desired value. Alternatively, a default error threshold is set by the trap controller 2.

[0049] exist Figure 4In the example shown, syndrome 45 has a value less than the error threshold and therefore FEC block 21 is a trap block. When the FEC block is determined to be a trap block, the decoding circuit 1 performs iterations using the LDPC decoder 3 until the decoding operation is successful or until a predetermined number of decoding iterations have been performed. These iterations are hereinafter referred to as "trap block" decoding iterations. The term "trap block decoding iteration" as used in this application is an iteration performed to decode an FEC block that has been determined to be a trap block. At each trap block decoding iteration, the trap controller 2 generates an updated LLR map; provides the updated LLR map and the original bit values ​​of the FEC block or a failed decoded output block from a previously failed decoding operation to the LDPC decoder, and sends an indication to the LDPC decoder 3 to perform a decoding operation. In response to the indication, the LDPC decoder 3 uses the updated LLR map to perform a decoding operation on the corresponding bits of the original bit values ​​of the FEC block or the failed decoded output block from the previously failed decoding operation. When the maximum number of trap block decoding iterations is reached and the LDPC decoder 3 fails to successfully decode the FEC block, the LDPC decoder 3 performs a decoding operation on the corresponding bits of the original bit values ​​of the FEC block. Figures 1 to 3 The decode circuit output 15 outputs an error indication, which may be, for example, an error flag. In response to the error indication, the memory controller 6 outputs an error message at the memory controller output 19. In response to the error message, the host computer may then perform a RAID process to recover the codeword.

[0050] When the decoding operation is successful so as to generate a codeword, the decoding circuit 1 outputs the codeword at a decoding circuit output 15. In response to the output of the codeword at the decoding circuit output 15, the memory controller 6 outputs the codeword at a memory controller output 19.

[0051] Figure 5 An example of a trap block decoding iteration is shown. As used herein, the term "trap block decoding iteration" refers to a decoding iteration of a block that has been determined to be a trap block. At each trap block decoding iteration, the trap controller 2 generates an updated LLR map. Figure 5In the example shown, the original bit values ​​of the FEC link 21 are coupled to the trap controller 2 via the link 17, which couples the trap controller 2 to the block buffer memory 5, and the trap controller 2 uses the received original bit values ​​of the FEC link 21 to generate an updated LLR map 30 (which may also be referred to as a "first updated LLR map"). The trap controller 2 provides the updated LLR map 30 and the failed decoded output block from the previously failed decoding operation 25 to the LDPC decoder 3; and sends an instruction to the LDPC decoder 3 via the control input 16 to perform a decoding operation. In this example, the trap controller 2 couples the failed decoded blocks from the previously failed decoding operation 25 to the LDPC decoder 3 by storing the failed decoded output blocks from the previously failed decoding operation 25 in the block buffer memory 5 (e.g., overwriting the previously stored original bit values ​​of the FEC link 21). In response to each instruction, the LDPC decoder 3 performs a decoding operation on the failed decoded output blocks from the previously failed decoding operation 25 using the updated LLR map 30. In the first trap block decoding iteration, the failed decoded output block from the previously failed decoding operation 25 will be the one from Figure 4 The failed decoding output block 24. In the event of a successful decoding, the resulting codeword is output at 12, and the trap controller 2 outputs the codeword at the decoding circuit output 15. When the LDPC decoding is unsuccessful, the iterative process continues until the decoding operation is successful or until a predetermined number of trap block decoding iterations have been performed.

[0052] In one example, all trapping block decoding iterations are performed using failed decoded output blocks from previously failed decoding operations 25. However, alternatively, one or more trapping block decoding iterations may be performed on the original bit values ​​of FEC block 21.

[0053] Figure 6 An example of a trap block decoding iteration is shown, where a decoding operation is performed on the original bit values ​​of FEC block 21. In this example, Figure 4 In the example of , the original bit values ​​of the FEC block 21 stored in the block buffer memory 5 are not changed and are used again to perform a decoding operation. In this example, the updated LLR map 30 and the original bit values ​​of the FEC block 21 stored in the block buffer memory 5 are coupled to the LDPC decoder 3. The trap controller 2 sends an instruction to the LDPC decoder 3 (e.g., via the control input 16) to perform a decoding operation. In response to the instruction, the LDPC decoder 3 uses the first updated LLR map 30 to perform a decoding operation on the original bit values ​​of the FEC block 21. Figure 6In the event that the decoding of the FEC block 21 is successful, the resulting codeword is output at 12, and the trap controller 2 outputs the codeword at the decoding circuit output 15. In one example, all trap block decoding iterations are performed using the original bit values ​​of the FEC block 21. In another example, one or more trap block decoding iterations are performed using the original bit values ​​of the FEC block 21, and then one or more trap block decoding iterations are performed using the failed decoded output block from the previously failed decoding operation 25.

[0054] Figure 7 An example is shown in which there are N trap block decoding iterations. In this example, in the first failed decoding 20a, the original bit values ​​of the FEC block 21 and the initial LLR map 22 are input to the LDPC decoder 3; and the LDPC decoder 3 performs a decoding operation on the original bit values ​​of the FEC block 21 using the initial LLR map 22 to output a failed decoding output block 24 at the decoding block output 12. In the first trap block decoding iteration 40a, the trap controller 2 generates a first updated LLR map 30, and couples the first updated LLR map 30 and the failed decoding output block 24 or the original bit values ​​of the FEC block 21 to the LDPC decoder 3. The LDPC decoder 3 then performs a decoding operation on the failed decoding output block 24 or the original bit values ​​of the FEC block 21 using the first updated LLR map 30. In this example, the decoding process is unsuccessful, resulting in a failed decoding output block 34 at the decoding block output 12. In the second trap block decoding iteration 40b, the trap controller 2 generates a second updated LLR map 31, and couples the second updated LLR map 31 and the original bit values ​​of the failed decoded output block 34 or FEC block 21 to the LDPC decoder 3. The LDPC decoder 3 then performs a decoding operation on the original bit values ​​of the failed decoded output block 34 or FEC block 21 using the second updated LLR map 31. In this example, the decoding operation is unsuccessful, resulting in a failed decoded output block 35 at the decoded block output 12. In the third trap block decoding iteration 40c, the trap controller 2 generates a third updated LLR map 32, and couples the third updated LLR map 32 and the original bit values ​​of the failed decoded output block 35 or FEC block 21 to the LDPC decoder 3. The LDPC decoder 3 then performs a decoding operation on the original bit values ​​of the failed decoded output block 35 or FEC block 21 using the third updated LLR map 32. In this example, the decoding process is unsuccessful, resulting in a failed decoded output block 36 being output at the decoded block output 12.

[0055] This process continues until the decoding operation is successful or until a predetermined number (e.g., "N" times) of trap block decoding iterations have been performed. In the present example, "N" iterations are performed, and in the Nth iteration, the N-times updated LLR map 33 and the original bit values ​​of the FEC block 21 or the failed decoded output block 37 from the previously failed decoding iteration are used in the decoding operation. If the LDPC decoding operation is successful, the codeword 38 is output at the decoding block output 12. If the Nth decoding operation is unsuccessful, the failed decoded output block 39 is output at the decoding block output 12, and an error message is output from the decoding circuit 1.

[0056] In one example, the trap controller 2 includes a counter that counts the number of trap block decoding iterations in which the LDPC decoder 3 fails to decode the FEC block determined to be a trap block. The trap controller 2 compares the value in the counter with the maximum number of iterations and determines that the maximum number of iterations has been reached when the counter is equal to the maximum number of iterations. In one example, when the decoding operation of the LDPC decoder 3 is successful, the counter in the trap controller 2 is cleared. In one example, when the trap detection comparator 4 determines that the FEC block is a trap block, the counter is cleared.

[0057] In one example, N is equal to the number of different LLR mappings generated by the trap controller 2, and the trap controller 2 continues to perform iterations until a codeword has been identified or all LLR mappings have been tried.

[0058] The LLR values ​​in updated LLR maps 30 - 32 may be generated in any of a number of different ways, and may be a function of corresponding ones of the original bit values ​​of FEC block 21 . FIG. 8A to FIG. 8D An example of a method for generating updated LLR maps 30-33 is shown. Fig. 8A In the example shown in , the trap controller 2 generates an updated LLR map (43) using weak bit values ​​corresponding to each bit in the FEC block (41) and random probability values ​​corresponding to each bit in the FEC block (42). In one example, the H matrix in the decoding performed by the LDPC decoder 3 is analyzed to identify corresponding bits that are considered to be weak bits. Bits that are not identified as weak bits are referred to as "strong" bits hereinafter. Weak bits are bits that exhibit poor decoding performance and can be identified by performing tests (e.g., in a test lab) to identify bit positions in the H matrix that are more likely to fail in an LDPC decoding operation using a particular H matrix. In one example, the test includes encoding a codeword using a particular H matrix, storing the codeword on a memory device and decoding the stored codeword using the H matrix, and identifying the bit positions with the highest number of bit errors.

[0059] exist Figure 8BIn the example shown, the trap controller applies a percentage change (52) to each of the original bit values ​​of the FEC block to generate (53) a random probability value. In this example, the weak bit values ​​(51) and the generated random probability values ​​(53) are used to generate an updated LLR map (54). Referring back to Figure 5 In one example, the trap controller 2 reads the original bit values ​​of the FEC block 21 from the block buffer memory 5, and generates the random probability value by changing one or more of the bit values ​​of the original bit values ​​of the FEC block 21 to different bit values ​​to generate the random probability value. In one example, some or all of the original bit values ​​of the FEC block 21 are changed in a manner corresponding to the percentage change 52, so that the random probability value exhibits the percentage change 52. In one example, the random probability value is generated by changing the sign of the corresponding LLR (e.g., positive to negative or negative to positive) so that zero is randomly flipped to one or one is flipped to zero.

[0060] exist Figure 8C In the example shown, the percentage change (65) is used to generate the random probability value (66), and the weak bit value includes a weak LLR value (W) at 62 and a weak LLR delta value (Wd) at 64. In this example, the trap controller uses the strong LLR value (S) at 61, W at 62, the strong LLR delta value (Sd) at 63, Wd at 64, and the generated random probability value (66) to generate an updated LLR map 68. The term "strong" is used in this application only to indicate LLR values ​​associated with bit positions that do not correspond to weak bits (i.e., corresponding to strong bits), and the term is not intended to have any other meaning. In one example, the weak bit value is determined by identifying a weak column in the H matrix. In this example, each LLR value corresponding to a weak column of the H matrix in the updated LLR map has an LLR value equal to W, and each LLR value corresponding to a column of the H matrix that is not a weak column in the updated LLR map has an LLR value equal to S.

[0061] In one example, S is a conventional LLR value that would normally be used to decode a particular bit position, and W is a value used to decode the bit position when the particular bit position is determined to correspond to a weak bit in the H matrix. In one example, the conventional input values ​​are each half of the maximum input LLR value (LLR MAX ), such as LLR MAX / 2. Sd is a value different from the corresponding conventional LLR value that would normally be used to decode a specific bit position, and may be a function of the corresponding S of the specific bit position (e.g., Sd=1 / 2*S). Wd is a value different from the corresponding W value, and may be a function of the corresponding W of the specific bit position (e.g., Wd=1 / 2*W). In one example, each S is set to a first predetermined value and each W is set to a second predetermined value different from the first predetermined value. Alternatively, each S and W in the original bit value of FEC block 21 may be set to different values. In another example, the S of a specific bit position is equal to the LLR value of the specific bit position in the initial LLR map 22, the W of each bit position is a function of the LLR value of the specific bit position in the initial LLR map 22, the Sd of each bit position is a function of the corresponding S of the specific bit position, and the Wd of each bit position is a function of the corresponding W of the specific bit position.

[0062] Fig.8DA function that can be used to generate an LLR map is shown, where the original bit value is indicated in the first column 71, the random bit value is indicated in the second column 72, the weak bit value 73 is indicated in the third column 73, and the function used to determine the LLR for the particular bit position is indicated in column 74. In this example, the weak bit is given a weak bit value of 1, and the bits that are not weak bits are given a weak bit value of 0. As indicated by row 70a, when the particular bit position has the original bit value "0", the random bit value "0", and is not a weak bit (has a weak bit value of "0"), the input LLR for the bit position is positive S. As indicated by row 70b, when the particular bit position has the original bit value "0", the random bit value "0", and is not a weak bit (has a weak bit value of "1"), the input LLR for the bit position is positive W. As indicated by row 70c, when a particular bit position has an original bit value of “0”, a random bit value of “1”, and is not a weak bit (has a weak bit value of “0”), the input LLR of the bit position is positive (S+Sd). As indicated by row 70d, when a particular bit position has an original bit value of “0”, a random bit value of “1”, and is a weak bit (has a weak bit value of “1”), the input LLR of the bit position is positive (W+Wd). As indicated by row 70e, when a particular bit position has an original bit value of “1”, a random bit value of “0”, and is not a weak bit (has a weak bit value of “0”), the input LLR of the bit position is negative S. As indicated by row 70f, when a particular bit position has an original bit value of “1”, a random bit value of “0”, and is a weak bit (has a weak bit value of “1”), the input LLR of the bit position is negative W. As indicated by row 70g, when a particular bit position has an original bit value of "1", a random bit value of "1", and is not a weak bit (has a weak bit value of "0"), the input LLR of that bit position is negative (S+Sd). As indicated by row 70h, when a particular bit position has an original bit value of "1", a random bit value of "1", and is a weak bit (has a weak bit value of "1"), the input LLR of that bit position is negative (W+Wd). In one example S-8, W=4, SD=2, and Wd=1, so that the strong input is twice the weak input. In another example, S=8, W=2, Sd=0, Wd=2. In yet another example, the S value is 8, and the weak value is randomly 4 or 0. In Fig. 8E In one example shown, user input is received (e.g., received at input 14 and / or 18) indicating a weak bit value at 81, and in this example, the user input includes S at 61, W at 62, Sd at 63, and WD at 64. User input is received at 82 indicating a percentage change (e.g., received at input 14 and / or 18), and the trap controller 2 applies the percentage change to the respective bit values ​​in the original bit values ​​of the FEC bits to generate a random probability value corresponding to each bit in the FEC block at 66.

[0063] At 83, the trap controller 2 generates an updated LLR map using the generated random probability values ​​S, W, Sd, and Wd. In one example, the user input is provided by the manufacturer of the SSD by uploading the user input at input 18 before the SSD 9 is shipped to the customer. Fig. 8E As shown, in addition to receiving an input indicating a weak bit value and an input indicating a percentage change, an input indicating an error threshold may also be received (e.g., at input 14 and / or 18) to allow the manufacturer of the SSD 9 to vary the weak bit value, percentage change, and error threshold to meet the needs of a particular customer or group of customers.

[0064] In one example, all positive values ​​of the LLR map represent 0, and all negative values ​​of the LLR map represent 1. The magnitude represents confidence. In one example, a magnitude of 0 indicates a low confidence metric (i.e., no confidence as to whether a particular bit is 1 or 0), and the amount of confidence increases as the magnitude approaches 15. In this example, an LLR of 2 is a very weak 0, an LLR of 4 is a weak 0, and an LLR of 15 is a strong 0. Similarly, an LLR of 12 is a very weak 1, an LLR of -4 is a weak 1, and an LLR of -15 is a strong 1.

[0065] Subsequent updated LLR maps 31-33 may be generated in the same manner as first updated LLR map 30. Alternatively, one or more of the following factors: S, Sd, W, Wd, and percentage change 52 may be changed when generating subsequent updated LLR maps 31-33 compared to first updated LLR map 30.

[0066] In one example, as a result of changing one or more of the random probability values ​​S, W, Sd, and Wd, the subsequently updated LLR maps 31-33 are different from each other. In one example, the updated LLR maps 31-33 are generated in the same manner as the updated LLR map 30, except that one or more of S, W, Sd, and Wd are changed, or a function is performed on one or more of S, W, Sd, and Wd to change the result.

[0067] In another example, each updated LLR map is a function of the bit values ​​in the failed decoded output block from the previous iteration 25. In one example, the failed decoded output block from the previous iteration 25 at the FEC block input 10 is used, and an updated LLR map generated in the same manner as the subsequent updated LLR map 30 is used to compare the bit values ​​in the previous iteration 25 with the FEC block input 10. Fig.8D Each trap block decoding iteration is performed in the same manner as shown, except that the bit values ​​of the failed decoded output block from the previous iteration 25 are used in the calculation instead of using Fig.8D The original bit values ​​of FEC block 21 in column 71 of Figure 7 In the first trap block decoding iteration shown, Fig.8D The function shown is applied to the individual bit values ​​in the failed decoded output block 24 to generate the LLR values ​​in the first updated LLR map 30. In the second trapping block decoding iteration 40b, Fig.8D The function shown is applied to the individual bit values ​​in the failed decoded output block 34 to generate the LLR values ​​in the second updated LLR map 31. In the third trapping block decoding iteration 40c, Fig.8D The function shown is applied to the individual bit values ​​in the failed decoded output block 35 to generate the LLR values ​​in the LLR map 32 for the third update.

[0068] In one example, the first failed decode operation and the trap block decode iteration are both soft decodes, where three different information bits (original, strong / weak, and random) are incorporated into each LLR value in the LLR map, where 8 values ​​correspond to each input bit. In one example, both the initial LLR map 22 and the updated LLR maps 30-33 include LLR values ​​that can be any of eight different values, 4 different ones (each with one of 4 different confidence levels) and 4 different zeros (each with one of 4 different confidence levels). In one example, 3-bit soft decoding is used, where each individual LLR map 22 and 30-33 indicates a single LLR value corresponding to each original bit position, which is a single signed value corresponding to a particular original bit position.

[0069] In one example, the number of trap block decoding iterations is equal to the number of updated LLR maps generated by the trap controller 2, wherein each trap block decoding iteration uses a different LLR mapping until all LLR mappings have been tried. In one example, the trap controller 2 generates eight different LLR mappings, and each trap block decoding iteration uses a different one of the eight LLR mappings, wherein the trap block decoding iterations continue until the decoding operation successfully identifies a codeword or all eight different LLR mappings have been tried.

[0070] exist Figure 4 In the example shown, the first failed decoding is described as a hard decoding operation or a soft decoding operation (eg, 3-bit soft decoding). However, alternatively, the first failed decoding operation is performed in FIG. 8A to FIG. 8E The initial LLR map is generated in the manner shown in one or more of . In one such example, the first failed decode is a soft decode with three different information bits (original, strong / weak, and random bits), where 8 different possible values ​​correspond to each input bit (4 different 1s with 4 different confidence levels and 4 different 0s with 4 different confidence levels).

[0071] Fig.9A An example of a decoding circuit 1a is shown which does not include a block buffer memory 5. In this example, the decoding circuit input 14 is directly coupled to the FEC block input 10 and the trap controller 2. The decoding circuit 1a is coupled to the FEC block input 10 and the trap controller 2. Figure 1 The decoding circuit 1 operates in the same manner as discussed above with respect to FIG. 8 , except as described below. Fig. 9B FIG. 4 shows an example of a memory controller 6a having a decoding circuit 1a that does not include a block buffer memory 5. The memory controller 6a is configured to Figure 1 The memory controller 6 operates in the same manner as discussed above with respect to FIG. 8 , except as described below. Fig. 9C FIG. 2 shows an example of an SSD 9a having a memory controller 6a and a decoding circuit 1a that does not include a block buffer memory 5. The SSD 9a is configured to be Figure 1 The SSD 9 operates in the same manner as discussed above with respect to FIG. 8 , except as described below. 9A to 9C In the example of , the FEC block received at the decoding circuit input 14 is directly coupled from the decoding circuit input 14 to the FEC block input 10 of the LDPC decoder 3. In an example, the trap controller 2 is operable to store the original bit values ​​of the FEC block 21 and the failed decoded output blocks as needed to generate an updated LLR map, and couple the original bit values ​​of the FEC block 21 or the failed decoded output blocks to the LDPC decoder 3.

[0072] Fig.10A method (100) for decoding is shown, the method comprising performing (101) a first failed decoding operation on original bit values ​​of a forward error correction (FEC) block by a low density parity check (LDPC) decoder that outputs a syndrome of the failed decoding operation and a failed decoding output block. The method includes determining (102) whether the FEC block is a trap block by comparing the number of failed check nodes indicated by the syndrome to an error threshold. When the number of failed check nodes indicated by the syndrome is less than the error threshold, the FEC block is determined to be a trap block. When decoding fails (101) and the FEC block is not determined to be a trap block (103), an error indication (111) is output. When the FEC block is determined to be a trap block, the method includes performing trap block decoding iterations (104-109, 116). Each of the trap block decoding iterations includes: generating (104) an updated LLR map; (105) providing the updated LLR map and the original bit values ​​of the FEC block or the failed decoded output block from a previous failed decoding operation on the trap block to the LDPC decoder; (106) performing a decoding operation of the LDPC decoder on the bit values ​​of the FEC block or the failed decoded output block from a previous failed decoding operation on the trap block using the updated LLR map. The trap block decoding iterations of blocks 104-106 are performed until the decoding operation is successful (107, 110) or until a predetermined number of trap block decoding iterations (107-108, 117) have been performed. After each trap block decoding iteration, a counter of the trap controller 2 is incremented (I=I+1) (109) and the counter is used to determine in block 108 whether a maximum number of iterations has been reached. When the decoding operation successfully (107) decodes the FEC block, a codeword is output (110). When the decoding operation has not successfully decoded the FEC block and a predetermined number of trapping block decoding iterations have been performed (107-108, 117), an error indication is output via path 117 (111).

[0073] In one example, the error indication (111) is Figures 1 to 3 The decode circuit output 15 of the memory controller 6, 6a outputs an error message in response to the error indication. The host computer can then perform a RAID process to recover the codeword.

[0074] The decoding iterations of steps 104-106 may be performed using the original bit values ​​of the FEC block or using a failed decoded output block from a previously failed decoding operation on the trapping block. Fig.11An example is shown in which decoding is performed on the original bit values ​​of the FEC block. In this example, the trap block decoding iteration includes: generating (201) an updated LLR map; providing (202) the updated LLR map and the original bit values ​​of the FEC block to the LDPC decoder; and performing (203) a decoding operation on the original bit values ​​of the FEC block using the updated LLR map.

[0075] Fig.12 A decoding iteration in which steps 104-106 are performed using a failed decoded output block from a previously failed decoding operation on a trap block is shown. In this example, the trap block decoding iteration includes: generating (301) an updated LLR map; providing (302) the failed decoded output block from a previously failed decoding operation on the trap block and the updated LLR map to an LDPC decoder; and performing (303) a decoding operation on the failed decoded output block from a previously failed decoding operation on the trap block using the updated LLR map.

[0076] Fig.13 Examples of additional blocks that may be included in method 100 are shown. As shown in block 401, method 100 includes receiving an input indicating a percentage change, and generating a random probability value by applying the percentage change to respective ones of the raw bit values ​​of the FEC block.

[0077] As shown in block 402, method 100 includes storing the original bit values ​​of the FEC block or storing a failed decoded output block from a previously failed decoding operation on a trapped block. As shown in block 403, method 100 includes generating an updated LLR map using the stored original bit values ​​of the FEC block, the random probability values ​​corresponding to each bit in the FEC block, and the weak bit values ​​corresponding to each bit in the FEC block.

[0078] As indicated at block 404, method 100 includes receiving input indicating S, W, Sd, and Wd, wherein each LLR value in the updated LLR map corresponding to a weak column of the H matrix has an LLR value equal to W, and wherein each LLR value in the updated LLR map corresponding to a column of the H matrix that is not a weak column has an LLR value equal to S.

[0079] Fig.14 A graph showing frame errors on the vertical axis and bit error rate (BER) on the horizontal axis is shown. The figure shows a waterfall 93 and performance curve 91 of a conventional LDPC decoding process. It can be seen that performance curve 91 deviates laterally as it approaches error floor 94. The top of waterfall 93 is not visible because it extends along performance curve 91, and only the portion of waterfall 93 that extends below the location where performance curve 91 deviates from waterfall 92 is visible.

[0080] Fig.15A graph showing frame errors on the vertical axis and bit error rate (BER) on the horizontal axis is shown. Figures 1 to 13 The performance curve 92 of the example of the method and apparatus shown. It can be seen that the performance curve 92 Fig.14 The conventional LDPC decoding process is shown extending below the error floor 94 .

[0081] It should be understood that Figures 1 to 13 8 and before the first trap block decoding iteration 20b. In this first trap block decoding iteration, an LLR mapping is used for decoding including a predetermined set of LLR values, each LLR value being set to a predetermined low LLR value. For example, a conventional decoding operation can be added in which the LLR values ​​are set to a predetermined low value.

[0082] In addition, in this specification, for explanation, many specific details are set forth in order to provide a thorough understanding of the present invention. However, it is apparent to those of ordinary skill in the art that the present invention can be practiced without these specific details. In some cases, in order to avoid blurring the present invention, well-known structures and devices are shown in block diagram form rather than in detail. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the present invention, and it should be understood that other embodiments may be utilized without departing from the scope of the present invention, and logical, mechanical, electrical and other changes may be made.

Claims

1. A decoding circuit, the decoding circuit comprising: an input for receiving raw bit values ​​of a forward error correction (FEC) block; a low density parity check (LDPC) decoder coupled to the input, the LDPC decoder to perform a failed decoding operation on the original bit values ​​of the FEC block and output a syndrome of the failed decoding operation and a failed decoding output block; a trap detection comparator, the trap detection comparator being coupled to the LDPC decoder, the trap detection comparator determining whether the FEC block is a trap block by comparing the number of failed check nodes indicated by the syndrome with an error threshold, wherein the FEC block is determined to be a trap block when the number of failed check nodes indicated by the syndrome is less than the error threshold; as well as a trap controller coupled to the input, the trap detection comparator, and the LDPC decoder, wherein when the FEC block is determined to be a trap block, the trap controller performs trap block decoding iterations using the LDPC decoder until the decoding operation is successful or until a predetermined number of trap block decoding iterations have been performed, at each trap block decoding iteration, the trap controller: generating an updated log-likelihood ratio (LLR) map; providing the updated LLR map and the original bit values ​​of the FEC block or a failed decoded output block from a previously failed decoding operation to the LDPC decoder, and sending an instruction to the LDPC decoder to perform a decoding operation, and In response to the indication, the LDPC decoder performs a decoding operation on corresponding bits of the original bit values ​​of the FEC block or the failed decoded output block from the previously failed decoding operation using the updated LLR map, wherein when the FEC block is not determined to be a trap block, the decoding circuitry outputs an error indication at an output of the decoding circuitry, and When the decoding operation succeeds to generate a codeword, the decoding circuit outputs the codeword.

2. The decoding circuit of claim 1 , further comprising a block buffer memory coupled to the input to store the received original bit values ​​of the FEC block, coupled to the LDPC decoder and coupled to the trap controller, and Wherein the original bit values ​​of the FEC block or a failed decoded output block from a previously failed decoding operation are stored in the block buffer memory during a corresponding trapping block decoding iteration.

3. The decoding circuit of claim 2 , wherein in each trap block decoding iteration, the trap controller generating an updated LLR map; storing a failed decoded output block from a previously failed decode operation in the block buffer memory; providing the updated LLR map and the failed decoded output block from the previously failed decoding operation to the LDPC decoder; sending an instruction to the LDPC decoder to perform a decoding operation, and In response to each subsequent indication, the LDPC decoder performs a decoding operation on the failed decoded output block from the previously failed decoding operation using the updated LLR map.

4. The decoding circuit of claim 2, wherein the trap controller generates the updated LLR map using a weak bit value corresponding to each bit in the FEC block and a random probability value corresponding to each bit in the FEC block.

5. The decoding circuit according to claim 4, wherein the weak bit values ​​include weak LLR values ​​and weak LLRΔ values, and The trap controller generates the updated LLR map using the strong LLR value, the weak LLR value, the strong LLR delta value, the weak LLR delta value, and the random probability value.

6. A memory controller, the memory controller comprising: A decoding circuit, the decoding circuit comprising: an input for receiving raw bit values ​​of a forward error correction (FEC) block; a block buffer memory coupled to the input to store received original bit values ​​of the FEC block; a low density parity check (LDPC) decoder coupled to the block buffer memory, the LDPC decoder configured to perform a failed decoding operation on the original bit values ​​of the FEC block and output a syndrome of the failed decoding operation and a failed decoding output block; a trap detection comparator coupled to the LDPC decoder, the trap detection comparator determining whether the FEC block is a trap block by comparing the number of failed check nodes indicated by the syndrome with an error threshold, wherein the FEC block is determined to be a trap block when the number of failed check nodes indicated by the syndrome is less than the error threshold; and a trap controller coupled to the block buffer memory, the trap detection comparator, and the LDPC decoder, wherein when the FEC block is determined to be a trap block, the trap controller performs a trap block decoding iteration using the LDPC decoder until the decoding operation is successful or until a predetermined number of trap block decoding iterations have been performed, at each trap block decoding iteration, the trap controller: generating an updated log-likelihood ratio (LLR) map; providing the updated LLR map and the original bit values ​​of the FEC block or a failed decoded output block from a previously failed decoding operation to the LDPC decoder, and sending an instruction to the LDPC decoder to perform a decoding operation, In response to the indication, the LDPC decoder performs a decoding operation on corresponding bits of the original bit values ​​of the FEC block or the failed decoded output block from the previously failed decoding operation using the updated LLR map, When the FEC block is not determined as a trap block, the memory controller outputs an error message, and When the decoding operation is successful to generate a codeword, the memory controller outputs the codeword.

7. The memory controller of claim 6 , wherein the first failed decode operation is a decode operation in which the first failed decode operation is performed using an initial LLR mapping, and in, In each trap block decode iteration, the trap controller Generate an updated LLR map, storing a failed decoded output block from a previously failed decode operation in the block buffer memory, providing the updated LLR map and the failed decoded output block from the previously failed decoding operation to the LDPC decoder, sending an instruction to the LDPC decoder to perform a decoding operation, and In response to the indication, the LDPC decoder performs a decoding operation on the failed decoded output block from the previously failed decoding operation using the updated LLR map.

8. The memory controller of claim 6, wherein the trap controller generates the updated LLR map using a weak bit value corresponding to each bit in the FEC block and a random probability value corresponding to each bit in the FEC block.

9. The memory controller of claim 8, wherein the trap controller applies a percentage change to respective ones of the raw bit values ​​of the FEC block to generate the random probability value.

10. The memory controller according to claim 9, wherein the weak bit values ​​include weak LLR values ​​and weak LLRΔ values, and The trap controller generates the updated LLR map using the strong LLR value, the weak LLR value, the strong LLR delta value, the weak LLR delta value, and the random probability value.

11. The memory controller of claim 6, comprising an input: the input being for receiving an input indicating a percentage change, wherein the trap controller applies the percentage change to respective ones of the raw bit values ​​of the FEC block to determine a random probability value, wherein the trap controller generates a random probability value corresponding to each bit in the FEC block, receiving input indicating a strong LLR value, a weak LLR value, a strong LLR delta value, and a weak LLR delta value, and Wherein the trap controller generates the updated LLR map using the generated random probability value, the strong LLR value, the weak LLR value, the strong LLR delta value, and the weak LLR delta value.

12. A solid state drive (SSD), the solid state drive comprising: multiple memory devices; a memory controller coupled to the plurality of memory devices, the memory controller comprising a decoding circuit, the decoding circuit comprising: an input for receiving raw bit values ​​of a forward error correction (FEC) block read from one or more memory devices of the plurality of memory devices; a block buffer memory coupled to the input to store received original bit values ​​of the FEC block; a low density parity check (LDPC) decoder coupled to the block buffer memory, the LDPC decoder configured to perform a failed decoding operation on the original bit values ​​of the FEC block and output a syndrome of the failed decoding operation and a failed decoding output block; a trap detection comparator coupled to the LDPC decoder, the trap detection comparator determining whether the FEC block is a trap block by comparing the number of failed check nodes indicated by the syndrome with an error threshold, wherein the FEC block is determined to be a trap block when the number of failed check nodes indicated by the syndrome is less than the error threshold; and a trap controller coupled to the block buffer memory, the trap detection comparator, and the LDPC decoder, wherein when the FEC block is determined to be a trap block, the trap controller uses the LDPC decoder to perform a trap block decoding iteration until the decoding operation is successful or until a predetermined number of trap block decoding iterations have been performed, and at each trap block decoding iteration, the trap controller: generating an updated log-likelihood ratio (LLR) map; providing the updated LLR map and the original bit values ​​of the FEC block or a failed decoded output block from a previously failed decoding operation to the LDPC decoder, and sending an instruction to the LDPC decoder to perform a decoding operation, In response to the indication, the LDPC decoder performs a decoding operation on corresponding bits of the original bit values ​​of the FEC block or the failed decoded output block from the previously failed decoding operation using the updated LLR map, and When the FEC block is not determined as a trap block, the memory controller outputs an error message, and When the decoding operation is successful to generate a codeword, the memory controller outputs the codeword.

13. The SSD of claim 12, wherein the first failed decoding operation is a decoding operation in which the first failed decoding operation is performed using an initial LLR mapping, and Wherein at each trap block decode iteration, the trap controller: generating said updated LLR map, storing a failed decoded output block from a previously failed decode operation in the block buffer memory, providing the updated LLR map and the failed decoded output block from the previously failed decoding operation to the LDPC decoder, sending an instruction to the LDPC decoder to perform a decoding operation, and In response to each indication, the LDPC decoder performs a decoding operation on the failed decoded output block from the previously failed decoding operation using the updated LLR map.

14. A method for decoding, the method comprising: performing a first failed decoding operation on the original bit values ​​of the forward error correction (FEC) block by a low density parity check (LDPC) decoder, the LDPC decoder outputting a syndrome of the failed decoding operation and a failed decoding output block; determining whether the FEC block is a trap block by comparing the number of failed check nodes indicated by the syndrome with an error threshold, and determining the FEC block as a trap block when the number of failed check nodes indicated by the syndrome is less than the error threshold; When the FEC block is not determined to be a trap block, outputting an error indication; When the FEC block is determined to be a trap block: generating an updated log-likelihood ratio (LLR) map; providing the updated LLR map and the original bit values ​​of the FEC block or a failed decoded output block from a previously failed decoding operation on the trapping block to the LDPC decoder; performing a decoding operation of the LDPC decoder on the original bit values ​​of the FEC block or the failed decoded output block from the previously failed decoding operation on the trapping block using the updated LLR map; as well as repeating said generating, said providing and said executing until said decoding operation is successful or until a predetermined number of trapping block decoding iterations have been performed; and When the decoding operation successfully decodes the FEC block of the output codeword; and When the decoding operation fails to successfully decode the FEC block and the predetermined number of trapping block decoding iterations have been performed, an error indication is output.

15. The method of claim 14, wherein said performing a trapping block decoding iteration comprises: generating an updated LLR map; providing the failed decoded output block and the updated LLR map from the previously failed decoding operation on the trapping block to the LDPC decoder; as well as A decoding operation is performed on the failed decoded output block from the previously failed decoding operation on the trapping block using the updated LLR map.

16. The method of claim 14, further comprising storing the original bit values ​​of the FEC block or the failed decoded output block from a previous failed decoding operation on the trapping block.

17. The method of claim 14, wherein the updated LLR map is generated using the stored original bit values ​​of the FEC block, a random probability value corresponding to each bit in the FEC block, and a weak bit value corresponding to each bit in the FEC block.

18. The method of claim 17, comprising receiving an input indicating a percentage change, wherein the random probability value is generated by applying the percentage change to respective ones of the original bit values ​​of the FEC block.

19. The method according to claim 14, comprising: receiving an input indicating a strong LLR value, a weak LLR value, a strong LLR delta value, and a weak LLR delta value, wherein each LLR value corresponding to a weak column of the H matrix in the updated LLR map has an LLR value equal to the weak LLR value, and Wherein each LLR value in the updated LLR map corresponding to a column in the H matrix that is not a weak column has an LLR value equal to the strong LLR value.

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