A voltage source circuit of a high-side driver chip and a control method thereof

Abstract

The application provides a voltage source circuit of a high-side drive chip and a control method thereof, and aims at solving the technical problem that the threshold voltage of a PMOS tube is consumed in the low-voltage input condition of the voltage source circuit of the existing high-side drive chip, thereby causing the increase of the consumption of the high-side drive chip. The voltage source circuit of the high-side drive chip is characterized in that: a first current mirror is formed by a reference current source I1, a PMOS tube MP3, a PMOS tube MP5, a PMOS tube MP6 and a PMOS tube MP7; a second current mirror is formed by an NMOS tube MN3, an NMOS tube MN4, a first resistor R1 and a second resistor R2; when the input voltage Vbb is higher than a preset value or less than or equal to the preset value, the width-length ratio of the PMOS tube MP3, the PMOS tube MP5, the PMOS tube MP6 and the PMOS tube MP7 and / or the resistance value of the first resistor R1 and the second resistor R2 are adjusted to control the opening and closing of the NMOS tube MN5, so that the voltage source circuit is kept stable output and the wide range of the input voltage is realized.

Description

Technical Field

[0001] This invention relates to high-side driving chip circuits, and more particularly to a voltage source circuit for a high-side driving chip and its control method. Background Technology

[0002] High-side driver chips are widely used in power electronic systems, such as motor drives, lighting control, power management, and electric vehicles. A high-side driver chip is an electronic component used to control high-side loads. In circuits, high-side loads typically refer to loads connected to the positive terminal of the power supply, such as motors, light bulbs, and heaters. Because high-side loads do not share a common ground with the power supply, high-side driver chips are needed to control their switching and current.

[0003] Typically, high-side driver chips require a minimum operating voltage of 5V for undervoltage protection. For example... Figure 1 The diagram shown is a schematic of the structure of an existing high-side driver chip. Figure 2 The diagram shows the circuit topology of the existing voltage source within a traditional high-side driver chip. Due to limitations in the existing voltage source circuit structure, under low input voltage Vbb, the output voltage at the voltage source's output terminal, i.e., the VS terminal, is the threshold voltage Vth of the MOS transistor P1. The actual high-side power supply voltage (i.e., the voltage between Vbb and VS) is Vbb - Vth, which is lower than the minimum operating voltage. Therefore, it can be seen that the existing voltage source inside the high-side driver chip often consumes the threshold voltage Vth of a PMOS transistor under low input voltage conditions. This results in the voltage supplied to the power transistor through the charge pump often not reaching a sufficiently high potential, increasing the on-resistance of the power transistor and consequently increasing the losses in the high-side driver chip. Summary of the Invention

[0004] The purpose of this invention is to solve the technical problem that the existing voltage source inside the high-side driver chip needs to lose the threshold voltage of a PMOS transistor under low voltage input conditions, which leads to increased losses in the high-side driver chip. The invention provides a voltage source circuit and control method for the high-side driver chip.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] A voltage source circuit for a high-side driving chip is characterized by including an NMOS transistor MN1, a power supply module, a voltage sampling module, a voltage regulation and filtering module, an NMOS transistor MN5, a Vbb terminal, an IN terminal, and a VS1 terminal.

[0007] The Vbb and IN terminals are used to connect to the Vbb and IN pins of the high-side driver chip, respectively, and the VS1 terminal is used to output the voltage of the voltage source circuit.

[0008] The source and gate of the NMOS transistor MN1 are connected to the IN terminal, and its drain is connected to the Vbb terminal to provide pull-up current to the IN terminal.

[0009] The power supply module is connected to the IN terminal at one end and the Vbb terminal at the other end. Its output terminal is connected to the VS1 terminal and the voltage sampling module, and is used to provide a stable power supply voltage to the high-side driver chip.

[0010] The voltage sampling module includes a first current mirror, a Zener diode D2, and a second current mirror;

[0011] The first current mirror includes a reference current source I1, PMOS transistor MP3, PMOS transistor MP5, PMOS transistor MP6 and PMOS transistor MP7;

[0012] The second current mirror includes NMOS transistors MN3 and MN4, a first resistor R1, and a second resistor R2;

[0013] The current replication ratio of PMOS transistors MP3, MP5, MP6, and MP7 is 1:n:1:1, and the resistance ratio of the first resistor R1 and the second resistor R2 is 1:m, where m and n are both positive numbers. This is used to control the switching on and off of NMOS transistor MN5 by adjusting the values ​​of m and n.

[0014] Furthermore, the source of the PMOS transistor MP3 is connected to the Vbb terminal, and its gate and drain are shorted together and connected to the output terminal of the power supply module through the reference current source I1 to provide a reference current; the sources of the PMOS transistors MP5, MP6, and MP7 are all connected to the Vbb terminal, and their gates are all connected to the gate of the PMOS transistor MP3 to replicate the reference current.

[0015] The drain of NMOS transistor MN3 is connected to the drain of PMOS transistor MP6, with its gate and drain shorted together. Its source is connected to the IN terminal through the first resistor R1. The negative terminal of Zener diode D2 is connected to the drain of PMOS transistor MP5, and its positive terminal is connected between the source of NMOS transistor MN3 and the first resistor R1. The drain of NMOS transistor MN4 is connected to the drain of PMOS transistor MP7 and the gate of NMOS transistor MN5, with its gate connected to the gate of NMOS transistor MN3. Its source is connected to the IN terminal through the second resistor R2. The drain of NMOS transistor MN5 is connected to the output terminal of the power supply module, and its source is connected to the IN terminal.

[0016] Furthermore, the voltage sampling module also includes a protection module, which includes PMOS transistors MP8, MP9, and MP10. The gates of PMOS transistors MP8, MP9, and MP10 are all connected to the control voltage terminal of the power supply module, and their sources are respectively connected to the drains of PMOS transistors MP5, MP6, and MP7, for the purpose of protecting PMOS transistors MP5, MP6, and MP7.

[0017] The drain of NMOS transistor MN3 is connected to the drain of PMOS transistor MP9, the negative terminal of Zener diode D2 is connected to the drain of PMOS transistor MP8, and the drain of NMOS transistor MN4 is connected to the drain of PMOS transistor MP10 and the gate of NMOS transistor MN5.

[0018] Furthermore, the power supply module includes a Zener diode D1, a PMOS transistor MP2, a PMOS transistor MP1, and an NMOS transistor MN2;

[0019] The gate of the PMOS transistor MP2 is connected to the positive terminal of the Zener diode D1, and the negative terminal of the Zener diode D1 is connected to the Vbb terminal, which is used to form a stable voltage source through the PMOS transistor MP2 and the Zener diode D1; the drain of the PMOS transistor MP2 is connected to the IN terminal, and the source is connected to the VS1 terminal and the output terminal of the reference current source I1, respectively.

[0020] The drain and source of PMOS transistor MP1 are both connected to the Vbb terminal, and the gate is connected to the gate of PMOS transistor MP2, which is used to filter the input voltage at the Vbb terminal; the gate of PMOS transistor MP2 serves as the control voltage terminal of the power supply module and is connected to the gates of PMOS transistors MP8, MP9, and MP10 respectively.

[0021] The source and gate of the NMOS transistor MN2 are connected to the IN terminal, and the drain is connected to the positive terminal of the Zener diode D1 to protect the Zener diode D1.

[0022] Furthermore, the voltage sampling module also includes a PMOS transistor MP4;

[0023] The drain and source of the PMOS transistor MP4 are connected to the Vbb terminal, and the gate is connected to the source of the PMOS transistor MP2, which is used to filter the bias voltage.

[0024] Furthermore, the voltage regulation and filtering module includes a Zener diode D3 and a capacitor C1;

[0025] The negative terminal of the Zener diode D3 is connected to the gate of the NMOS transistor MN5, and the positive terminal is connected to the IN terminal, which is used to stabilize the gate voltage of the NMOS transistor MN5; the capacitor C1 is connected between the gate and the IN terminal of the NMOS transistor MN5, which is used to filter the gate voltage of the NMOS transistor MN5.

[0026] Furthermore, both NMOS transistors MN1 and MN2 are high-voltage depletion-type NMOS transistors;

[0027] The NMOS transistor MN5 is a high-voltage enhancement-mode NMOS transistor;

[0028] Both NMOS transistors MN3 and MN4 are low-voltage enhancement-mode NMOS transistors.

[0029] The PMOS transistors MP2, MP8, MP9, and MP10 are all high-voltage enhancement-mode PMOS transistors;

[0030] The PMOS transistors MP1, MP3, MP4, MP5, MP6, and MP7 are all low-voltage enhancement-mode PMOS transistors.

[0031] Furthermore, both NMOS transistors MN1 and MN2 are junction field-effect transistors;

[0032] The NMOS transistor MN5 is a high-voltage enhancement-mode NMOS transistor;

[0033] Both NMOS transistors MN3 and MN4 are low-voltage enhancement-mode NMOS transistors.

[0034] The PMOS transistors MP2, MP8, MP9, and MP10 are all high-voltage enhancement-mode PMOS transistors;

[0035] The PMOS transistors MP1, MP3, MP4, MP5, MP6, and MP7 are all low-voltage enhancement-mode PMOS transistors.

[0036] This invention also provides a control method for the voltage source circuit of the above-mentioned high-side driving chip, characterized in that it includes the following steps:

[0037] When the voltage at the Vbb terminal is higher than the preset value, the Zener diode D2 is turned on. By adjusting the current replication ratio of PMOS transistors MP3, MP5, MP6, and MP7 and / or the resistance values ​​of the first resistor R1 and the second resistor R2, n+1>m is made, and then NMOS transistor MN5 is pulled down and turned off. Therefore, the output voltage V of the voltage source circuit is... S1 =V D1 -V GS ;

[0038] When the voltage at the Vbb terminal is less than or equal to the preset value, the Zener diode D2 is cut off. Adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 to make m > 1 turns on the NMOS transistor MN5, thus increasing the output voltage V of the voltage source circuit. S1 =V IN ;

[0039] Among them, V S1 This represents the output voltage at the VS1 terminal, V. D1 This indicates the control voltage provided by the power supply module, V. GS V represents the gate-source voltage of PMOS transistor MP2. IN This indicates the voltage at the IN terminal.

[0040] The advantages of this invention compared to the prior art are as follows:

[0041] 1. The present invention provides a voltage source circuit for a high-side driving chip, which forms a first current mirror through a reference current source I1, PMOS transistors MP3, MP5, MP6, and MP7, and a second current mirror through NMOS transistors MN3 and MN4, a first resistor R1, and a second resistor R2. When the input voltage Vbb is higher than or lower than or equal to a preset value, the switching on and off of NMOS transistor MN5 is controlled by adjusting the width-to-length ratio of PMOS transistors MP3, MP5, MP6, and MP7 and / or the resistance values ​​of the first resistor R1 and the second resistor R, so that the voltage source circuit maintains a stable output and achieves a wide range of input voltage.

[0042] 2. The voltage source circuit of the high-side driving chip provided by the present invention can increase the voltage source to the threshold voltage Vth of a MOS transistor under low voltage input conditions, thereby reducing the on-resistance of the power transistor and system losses.

[0043] 3. Based on the voltage source circuit of the high-side driver chip mentioned above, the control method provided by this invention is simple to control and can effectively reduce the on-resistance of the power transistor and system losses under low-voltage input conditions. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the structure of an existing high-side driver chip;

[0045] Figure 2 This is a circuit topology diagram of the voltage source circuit in an existing high-side driver chip;

[0046] Figure 3 This is a circuit topology diagram of a voltage source circuit embodiment of a high-side driving chip according to the present invention. Detailed Implementation

[0047] To make the advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] A voltage source circuit for a high-side driver chip, such as Figure 3 As shown, it includes NMOS transistor MN1, power supply module, voltage sampling module, voltage regulation and filtering module, NMOS transistor MN5, Vbb terminal, IN terminal and VS1 terminal.

[0049] The Vbb terminal in the voltage source circuit is used to connect to the Vbb pin of the high-side driver chip, and the voltage is input to the voltage source circuit through the Vbb terminal; the IN terminal is used to connect to the IN pin of the high-side driver chip, and the high and low level signals are input to the voltage source circuit through the IN terminal; the VS1 terminal serves as the output terminal of the voltage source circuit and is used to connect to the voltage sampling module inside the high-side driver chip.

[0050] The source and gate of NMOS transistor MN1 are connected to the IN terminal, and its drain is connected to the Vbb terminal to provide pull-up current to the IN terminal.

[0051] The power supply module includes a Zener diode D1, a PMOS transistor MP2, an NMOS transistor MN2, and a Zener diode D1. The gate of PMOS transistor MP2 is connected to the positive terminal of Zener diode D1, its drain is connected to the IN terminal, and its source is connected to the VS1 terminal. The negative terminal of Zener diode D1 is connected to the Vbb terminal. This module provides a stable power supply voltage to the high-side driver chip through PMOS transistor MP2 and Zener diode D1. Zener diode D1 is used to stabilize the gate voltage of PMOS transistor MP2. Specifically, the voltage input at the Vbb terminal is denoted as V... bb Let the voltage across Zener diode D1 be denoted as V. D1 Then, Zener diode D1 stabilizes the gate voltage of PMOS transistor MP2 at a fixed value, namely V. bb -V D1 The PMOS transistor MP1 is equivalent to a capacitor, with its drain and source connected to the Vbb terminal, and its gate connected to the gate of the PMOS transistor MP2, used to filter the input voltage at the Vbb terminal. The source and gate of the NMOS transistor MN2 are connected to the IN terminal, and its drain is connected to the positive terminal of the Zener diode D1, used to protect the Zener diode D1 and prevent it from burning out due to excessive current.

[0052] The voltage sampling module includes a first current mirror, a PMOS transistor MP4, a protection module, a Zener diode D2, and a second current mirror.

[0053] The first current mirror includes a reference current source I1, PMOS transistors MP3, MP5, MP6, and MP7; the current replication ratio of PMOS transistors MP3, MP5, MP6, and MP7 is 1:n:1:1. The source of PMOS transistor MP3 is connected to Vbb, and its gate and drain are shorted and connected to the source of PMOS transistor MP2 through the reference current source I1 to provide the reference current. The sources of PMOS transistors MP5, MP6, and MP7 are all connected to Vbb, and their gates are all connected to the gate of PMOS transistor MP3, used to replicate the reference current and form the bias current. The drain and source of PMOS transistor MP4 are connected to Vbb, and its gate is connected to the source of PMOS transistor MP2, used to filter the bias voltage.

[0054] The protection module includes PMOS transistors MP8, MP9, and MP10. The gates of PMOS transistors MP8, MP9, and MP10 are all connected to the gate of PMOS transistor MP2 (i.e., the control voltage terminal of the power supply module), and their sources are connected to the drains of PMOS transistors MP5, MP6, and MP7, respectively. This is used to protect PMOS transistors MP5, MP6, and MP7 through PMOS transistors MP8, MP9, and MP10, respectively, to prevent excessive current from damaging the corresponding MOS transistors.

[0055] The second current mirror includes NMOS transistors MN3 and MN4, a first resistor R1, and a second resistor R2. The drain of NMOS transistor MN3 is connected to the drain of PMOS transistor MP9, with its gate shorted to the drain. Its source is connected to the IN terminal via the first resistor R1. The drain of PMOS transistor MP8 is connected to the negative terminal of Zener diode D2, and the positive terminal of Zener diode D2 is connected between the source of NMOS transistor MN3 and the first resistor R1. The point where the source of NMOS transistor MN3, the first resistor R1, and Zener diode D2 are connected is denoted as point M. The drain of NMOS transistor MN4 is connected to the drain of PMOS transistor MP10 and the gate of NMOS transistor MN5, with its gate connected to the gate of NMOS transistor MN3. Its source is connected to the IN terminal via the second resistor R2. The drain of NMOS transistor MN5 is connected to the source of PMOS transistor MP2, and its drain is connected to the IN terminal. Zener diode D2 is used to detect the input voltage Vbb. When the input voltage Vbb is higher than a preset value, Zener diode D2 conducts to raise the voltage at point M. The resistance ratio of the first resistor R1 and the second resistor R2 is 1:m, where m and n are both positive numbers. This invention controls the switching on and off of the NMOS transistor MN5 by adjusting the values ​​of m and n (i.e., adjusting the current replication ratio of PMOS transistors MP3, MP5, MP6, and MP7 and / or the resistance values ​​of the first resistor R1 and the second resistor R).

[0056] The voltage regulation and filtering module includes a Zener diode D3 and a capacitor C1. The negative terminal of the Zener diode D3 is connected to the gate of the NMOS transistor MN5, and the positive terminal is connected to the IN terminal, which is used to stabilize the gate voltage of the NMOS transistor MN5. The capacitor C1 is connected between the gate and the IN terminal of the NMOS transistor MN5, which is used to filter the gate voltage of the NMOS transistor MN5.

[0057] In this embodiment, NMOS transistors MN1 and MN2 are both high-voltage depletion-type NMOS transistors, NMOS transistor MN5 is a high-voltage enhancement-type NMOS transistor, and NMOS transistors MN3 and MN4 are both low-voltage enhancement-type NMOS transistors. PMOS transistors MP2, MP8, MP9, and MP10 are all high-voltage enhancement-type PMOS transistors, while PMOS transistors MP1, MP3, MP4, MP5, MP6, and MP7 are all low-voltage enhancement-type PMOS transistors. In other embodiments of the present invention, junction field-effect transistors (JFETs) can be used to replace the high-voltage depletion-type NMOS transistors for NMOS transistors MN1 and MN2.

[0058] The voltage source circuit principle of the high-side driving chip provided by this invention is as follows:

[0059] When the voltage at terminal Vbb is higher than the preset value, Zener diode D2 turns on. At this time, the voltage V across the first resistor R1 is... R1 =(I MP5 +I MP6 R1 = (n+1) * I MP6 *R1, the voltage V across the second resistor R2 R2 =I MP6 *R2=I MP6 *m*R1. Because the voltage V across the first resistor R1... R1 The voltage V across the second resistor R2 is greater than R2 At this time, the gate voltage of NMOS transistor MN5 is low, and NMOS transistor MN5 is pulled down and cut off. Therefore, when the voltage at the Vbb terminal is higher than the preset value, by adjusting the current replication ratio of PMOS transistors MP3, MP5, MP6, and MP7 and / or the resistance values ​​of the first resistor R1 and the second resistor R, that is, by raising the voltage at point M through the first current mirror, so that n+1>m, the output voltage V of the voltage source circuit can be guaranteed. S1 =V D1 -V MP2 Among them, V S1 This represents the output voltage at the VS1 terminal, V. D1 This represents the control voltage supplied by the power module (i.e., the voltage across Zener diode D1), V MP2This represents the gate voltage of PMOS transistor MP2. Typically, the current replication ratio of PMOS transistors MP5, MP6, and MP7 is achieved by adjusting their width-to-length ratio; the width-to-length ratio represents the ratio of the channel width to the channel length of the corresponding PMOS transistor, usually denoted by the symbol W / L.

[0060] When the voltage at the Vbb terminal is less than or equal to the preset value, i.e., under low-voltage input conditions, the Zener diode D2 is cut off. Since m=1 is the reversal point, i.e., when the resistances of the first resistor R1 and the second resistor R2 are the same, the gate voltage of MN5 changes from low to high. Only when m>1, i.e., the voltage V across the first resistor R1... R1 The voltage V across the second resistor R2 is greater than R2 At this time, the gate voltage of NMOS transistor MN5 is high, allowing MN5 to conduct. Therefore, when the voltage at the Vbb terminal is less than or equal to a preset value, adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 to make m > 1 ensures the output voltage V of the voltage source circuit. S1 =V IN Among them, V IN This indicates the input voltage at the IN terminal.

[0061] It can be seen that when the voltage at the Vbb terminal is less than or equal to the preset value, i.e. under low-voltage input conditions, the voltage source circuit of the high-side driving chip provided by the present invention can increase the voltage source by the threshold voltage Vth of a MOS transistor, thereby reducing the on-resistance of the power transistor and the system loss.

[0062] Based on the voltage source circuit of the high-side driving chip described above, the present invention also provides a control method for the voltage source circuit of the high-side driving chip, specifically including the following steps:

[0063] When the voltage at the Vbb terminal is higher than the preset value, the Zener diode D2 is turned on. Adjusting the current replication ratios of PMOS transistors MP3, MP5, MP6, and MP7, and / or the resistance values ​​of the first resistor R1 and the second resistor R, makes n+1 > m. Then, NMOS transistor MN5 is pulled down and cut off, and the output voltage V of the voltage source circuit... S1 =V D1 -V MP2 Specifically, when the voltage at the Vbb terminal is less than or equal to a preset value, the Zener diode D2 is cut off. Adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 to make m > 1 turns on the NMOS transistor MN5, and the output voltage V of the voltage source circuit increases. S1 =V IN .

[0064] The above description is only used to illustrate the technical solutions of the present invention, and is not intended to limit them. For those skilled in the art, modifications can be made to the specific technical solutions described in the above embodiments, or equivalent substitutions can be made to some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions protected by the present invention.

Claims

1. A voltage source circuit for a high-side driving chip, characterized in that: This includes NMOS transistor MN1, power supply module, voltage sampling module, voltage regulation and filtering module, NMOS transistor MN5, Vbb terminal, IN terminal and VS1 terminal; The Vbb and IN terminals are used to connect to the Vbb and IN pins of the high-side driver chip, respectively, and the VS1 terminal is used to output the voltage of the voltage source circuit. The source and gate of the NMOS transistor MN1 are connected to the IN terminal, and its drain is connected to the Vbb terminal to provide pull-up current to the IN terminal. The voltage sampling module includes a first current mirror, a Zener diode D2, and a second current mirror; The first current mirror includes a reference current source I1, PMOS transistors MP3, MP5, MP6, and MP7; the second current mirror includes NMOS transistors MN3 and MN4, a first resistor R1, and a second resistor R2. The current replication ratio of PMOS transistors MP3, MP5, MP6, and MP7 is 1:n:1:1, and the resistance ratio of the first resistor R1 and the second resistor R2 is 1:m, where m and n are both positive numbers. This is used to control the switching on and off of NMOS transistor MN5 by adjusting the values ​​of m and n. The source of PMOS transistor MP3 is connected to the Vbb terminal, and its gate and drain are shorted together and connected to the output terminal of the power supply module through the reference current source I1 to provide a reference current; the sources of PMOS transistors MP5, MP6, and MP7 are all connected to the Vbb terminal, and their gates are all connected to the gate of PMOS transistor MP3 to replicate the reference current. The drain of NMOS transistor MN3 is connected to the drain of PMOS transistor MP6, with its gate and drain shorted together. Its source is connected to the IN terminal through the first resistor R1. The negative terminal of Zener diode D2 is connected to the drain of PMOS transistor MP5, and its positive terminal is connected between the source of NMOS transistor MN3 and the first resistor R1. The drain of NMOS transistor MN4 is connected to the drain of PMOS transistor MP7 and the gate of NMOS transistor MN5, with its gate connected to the gate of NMOS transistor MN3. Its source is connected to the IN terminal through the second resistor R2. The drain of NMOS transistor MN5 is connected to the output terminal of the power supply module, and its source is connected to the IN terminal. The power supply module is used to provide a stable power supply voltage to the high-side driver chip, and includes a Zener diode D1, a PMOS transistor MP2, an NMOS transistor MP1, and an NMOS transistor MN2. The gate of the PMOS transistor MP2 is connected to the positive terminal of the Zener diode D1, and the negative terminal of the Zener diode D1 is connected to the Vbb terminal, which is used to form a stable voltage source through the PMOS transistor MP2 and the Zener diode D1; the drain of the PMOS transistor MP2 is connected to the IN terminal, and the source is connected to the VS1 terminal and the output terminal of the reference current source I1, respectively. The drain and source of the PMOS transistor MP1 are both connected to the Vbb terminal, and the gate is connected to the gate of the PMOS transistor MP2, which is used to filter the input voltage at the Vbb terminal; the gate of the PMOS transistor MP2 serves as the control voltage terminal of the power supply module. The source and gate of the NMOS transistor MN2 are connected to the IN terminal, and the drain is connected to the positive terminal of the Zener diode D1 to protect the Zener diode D1. The voltage regulation and filtering module is located between the gate and IN terminal of the NMOS transistor MN5, and is used to stabilize the gate voltage of the NMOS transistor MN5 and perform filtering.

2. The voltage source circuit for a high-side driving chip according to claim 1, characterized in that: The voltage sampling module also includes a protection module; The protection module includes PMOS transistors MP8, MP9, and MP10; the gates of PMOS transistors MP8, MP9, and MP10 are all connected to the control voltage terminal of the power supply module, and their sources are respectively connected to the drains of PMOS transistors MP5, MP6, and MP7, for the purpose of protecting PMOS transistors MP5, MP6, and MP7; The drain of NMOS transistor MN3 is connected to the drain of PMOS transistor MP9, the negative terminal of Zener diode D2 is connected to the drain of PMOS transistor MP8, and the drain of NMOS transistor MN4 is connected to the drain of PMOS transistor MP10 and the gate of NMOS transistor MN5.

3. The voltage source circuit for a high-side driving chip according to claim 2, characterized in that: The voltage sampling module also includes a PMOS transistor MP4; The drain and source of the PMOS transistor MP4 are connected to the Vbb terminal, and the gate is connected to the source of the PMOS transistor MP2, which is used to filter the bias voltage.

4. The voltage source circuit for a high-side driving chip according to claim 3, characterized in that: It also includes Zener diode D3 and capacitor C1; The negative terminal of the Zener diode D3 is connected to the gate of the NMOS transistor MN5, and the positive terminal is connected to the IN terminal, which is used to stabilize the gate voltage of the NMOS transistor MN5; the capacitor C1 is connected between the gate and the IN terminal of the NMOS transistor MN5, which is used to filter the gate voltage of the NMOS transistor MN5.

5. The voltage source circuit for a high-side driving chip according to claim 4, characterized in that: Both NMOS transistors MN1 and MN2 are high-voltage depletion-type NMOS transistors. The NMOS transistor MN5 is a high-voltage enhancement-mode NMOS transistor; Both NMOS transistors MN3 and MN4 are low-voltage enhancement-mode NMOS transistors. The PMOS transistors MP2, MP8, MP9, and MP10 are all high-voltage enhancement-mode PMOS transistors; The PMOS transistors MP1, MP3, MP4, MP5, MP6, and MP7 are all low-voltage enhancement-mode PMOS transistors.

6. The voltage source circuit for a high-side driving chip according to claim 4, characterized in that: Both NMOS transistors MN1 and MN2 are junction field-effect transistors. The NMOS transistor MN5 is a high-voltage enhancement-mode NMOS transistor; Both NMOS transistors MN3 and MN4 are low-voltage enhancement-mode NMOS transistors. The PMOS transistors MP2, MP8, MP9, and MP10 are all high-voltage enhancement-mode PMOS transistors; The PMOS transistors MP1, MP3, MP4, MP5, MP6, and MP7 are all low-voltage enhancement-mode PMOS transistors.

7. A control method for the voltage source circuit of the high-side driving chip according to any one of claims 1-6, characterized in that, Includes the following steps: When the voltage at the Vbb terminal is higher than the preset value, the Zener diode D2 is turned on. By adjusting the current replication ratio of PMOS transistors MP3, MP5, MP6, and MP7 and / or the resistance values ​​of the first resistor R1 and the second resistor R2, n+1>m is made, and then NMOS transistor MN5 is pulled down and turned off. Therefore, the output voltage V of the voltage source circuit is... S1 =V D1 -V GS ; When the voltage at the Vbb terminal is less than or equal to the preset value, the Zener diode D2 is cut off. Adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 to make m > 1 turns on the NMOS transistor MN5, and the output voltage V of the voltage source circuit is then... S1 =V IN ; Among them, V S1 This represents the output voltage at the VS1 terminal, V. D1 This indicates the control voltage provided by the power supply module, V. GS V represents the gate-source voltage of PMOS transistor MP2. IN This indicates the voltage at the IN terminal.

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