SPI interface system, SPI data writing method and SPI data reading method

Abstract

The present invention provides an SPI interface system, comprising an SPI interface module and at least one functional module; the SPI interface module is connected to an SPI main controller via an SPI_CK signal line, an SPI_MOSI signal line and an SPI_MISO signal line; the functional module is connected to the SPI interface module. The present invention is suitable for application scenarios with a long transmission link, and is also compatible with local applications with a short transmission link, providing an ideal solution for SPI transmission.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, in particular to the encoding, decoding and transmission of physical layer data, and more particularly to an SPI interface system, an SPI data writing method and an SPI data reading method. Background Art

[0002] SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus, and only occupies four lines on the chip pins, saving the chip pins, while saving space and providing convenience for PCB layout. SPI usually has four signal lines, including SPI_CSN signal line, SPI_CK signal line, SPI_MOSI signal line and SPI_MISO signal line. The SPI master controller connects to the SPI interface module through these four signal lines. The SPI master controller is the SPI master device, and the SPI interface module is the SPI slave device. The SPI master controller drives the SPI_CSN signal line, SPI_CK signal line, and SPI_MOSI signal line. The SPI interface module receives the SPI_CSN signal line, SPI_CK signal line, and SPI_MOSI signal line. The SPI interface module drives the SPI_MISO signal line, and the SPI master controller receives the SPI_MISO signal line. The SPI interface module receives and samples the data driven by the SPI master controller on the SPI_MOSI signal line at the rising or falling edge of the SPI_CK signal line. The SPI master controller receives and samples the data driven by the SPI interface module on the SPI_MISO signal line at the rising or falling edge of the SPI_CK signal line. In the SPI protocol, the SPI master controller drives the SPI_CK signal line, and the SPI master controller generates a clock edge on the SPI_CK signal line. The SPI master controller and the SPI interface module sample the data on the SPI_MISO signal line and the SPI_MOSI signal line at the rising or falling edge of the clock on the SPI_CK signal line, thereby realizing bidirectional data transmission between the SPI master controller and the SPI interface module. The SPI_CSN signal line is a selection signal. In the SPI protocol, data transmission is performed only when the SPI_CSN signal line is low. One SPI master controller can be connected to multiple SPI interface modules, that is, one SPI master device can be connected to multiple SPI slave devices, wherein the SPI master controller and multiple SPI interface modules share the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line, but each SPI interface module has an independent SPI_CSN signal line input, when the SPI_CSN signal line of one SPI interface module is high, this SPI interface module does not drive the SPI_MISO signal line (the driver output of this SPI interface module connected to the SPI_MISO signal line is in Hi-Z state), and one SPI interface module drives the SPI_MISO signal line only when its SPI_CSN signal line is low. When one SPI master controller is connected to multiple SPI interface modules, at any time, only one SPI interface module has its SPI_CSN signal line low, thereby avoiding conflicts caused by multiple SPI interface modules driving the SPI_MISO signal line at the same time.

[0003] When an SPI master controller is only connected to one SPI interface module, this SPI interface module can drive the SPI_MISO signal line at any time without causing conflict. In this case, there may be no SPI_CSN signal line between the SPI master controller and the SPI interface module, that is, when an SPI master controller is only connected to one SPI interface module, the SPI master controller and the SPI interface module may be connected only through the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line.

[0004] When transmitting data over a long distance, it is generally based on the mode of sending a command packet and then receiving a feedback packet. The feedback packet contains the status information of the execution command. When it is a read command, the feedback packet can also contain read data. In the existing SPI protocol, the data on the SPI_MISO signal line and the SPI_MOSI signal line are sampled at the rising or falling edge of the clock on the SPI_CK signal line to achieve bidirectional transmission of data between the SPI master controller and the SPI interface module. However, this data transmission can be considered as a data stream transmission and is not suitable for data transmission over a long distance. At present, there is a lack of a solution for long-distance data transmission based on the existing SPI protocol through the SPI interface signal. Summary of the invention

[0005] In order to solve the problem that the SPI protocol in the prior art cannot be used for long-distance transmission, an object of the present invention is to provide an SPI interface system, the SPI interface system comprising an SPI interface module, and at least one functional module;

[0006] The SPI interface module is connected to the SPI main controller via a SPI_CK signal line, a SPI_MOSI signal line and a SPI_MISO signal line, and the functional module is connected to the SPI interface module.

[0007] Another object of the present invention is to provide a SPI data writing method, which uses an SPI interface system to write data, comprising:

[0008] The SPI master controller generates a clock edge on the SPI_CK signal line, and sends a write command packet to the SPI interface module through the SPI_MOSI signal line, wherein the write command packet starts with a first identifier;

[0009] After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module sends the write command packet to the functional module;

[0010] The functional module receives the write command packet and executes the write command, and when the functional module completes the write command, returns a write status packet to the SPI interface module;

[0011] The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line.

[0012] When the SPI interface module receives the write status packet, the SPI interface module sends the write feedback packet through the SPI_MISO signal line, the write feedback packet starts with a second identifier, and the write feedback packet includes the status information included in the write status packet.

[0013] In a preferred embodiment, when the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the write command packet, the SPI interface module receives the write command packet.

[0014] In a preferred embodiment, the write command packet further includes a write command packet check code;

[0015] When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the write command packet, and the write command packet check code is verified to be correct, the SPI interface module receives the write command packet.

[0016] In a preferred embodiment, the SPI master controller generates a clock edge on the SPI_CK signal line, reads the write feedback packet through the SPI_MISO signal line,

[0017] When the SPI interface module does not receive the write status packet, the SPI interface module sends data that cannot be identified as the write feedback packet to the SPI master controller through the SPI_MISO signal line.

[0018] In a preferred embodiment, the SPI interface module includes a timeout timer;

[0019] When the SPI interface module does not receive the write status packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, the write feedback packet is read through the SPI_MISO signal line,

[0020] The SPI interface module then sends a write feedback packet to the SPI master controller via the SPI_MISO signal line.

[0021] In a preferred embodiment, the SPI master controller generates a clock edge on the SPI_CK signal line, and sends the write command packet to the SPI interface module via the SPI_MOSI signal line.

[0022] Then the SPI master controller generates a clock edge on the SPI_CK signal line, reads the write feedback packet through the SPI_MISO signal line, and after the SPI interface module sends the write feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets, which include write command packets and read command packets.

[0023] In a preferred embodiment, the write feedback packet is divided into a write success feedback packet and a write failure feedback packet;

[0024] The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line.

[0025] When the SPI interface module receives the write status packet and the status information contained in the write status packet is success, the SPI interface module sends the write success feedback packet through the SPI_MISO signal line, where the write success feedback packet starts with a third identifier;

[0026] When the SPI interface module receives the write status packet and the status information contained in the write status packet is failure, the SPI interface module sends the write failure feedback packet through the SPI_MISO signal line, and the write failure feedback packet starts with a fourth identifier.

[0027] In a preferred embodiment, the SPI interface module includes a timeout timer;

[0028] When the SPI interface module does not receive the write status packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, and reads the write feedback packet through the SPI_MISO signal line, the SPI interface module sends the write failure feedback packet to the SPI master controller through the SPI_MISO signal line.

[0029] Another object of the present invention is to provide a SPI data reading method, using an SPI interface system to read data, comprising:

[0030] The SPI master controller generates a clock edge on the SPI_CK signal line, and sends a read command packet to the SPI interface module through the SPI_MOSI signal line, wherein the read command packet starts with a fifth identifier;

[0031] After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module sends the read command packet to the functional module;

[0032] The functional module receives the read command packet and executes the read command, and when the functional module completes the read command, returns the read data packet to the SPI interface module;

[0033] The SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line.

[0034] When the SPI interface module receives the read data packet, the SPI interface module sends the read feedback packet through the SPI_MISO signal line, the read feedback packet starts with the sixth identifier, and the read feedback packet includes the read data included in the read data packet.

[0035] In a preferred embodiment, when the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the read command packet, the SPI interface module receives the read command packet.

[0036] In a preferred embodiment, the read command packet further includes a read command packet check code;

[0037] When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the read command packet, and the check code of the read command packet is verified to be correct, the SPI interface module receives the read command packet.

[0038] In a preferred embodiment, the SPI master controller generates a clock edge on the SPI_CK signal line, reads the read feedback packet through the SPI_MISO signal line,

[0039] When the SPI interface module does not receive the read data packet, the SPI interface module sends data that cannot be identified as the read feedback packet to the SPI master controller through the SPI_MISO signal line.

[0040] In a preferred embodiment, the SPI interface module includes a timeout timer;

[0041] When the SPI interface module does not receive the read data packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, the read feedback packet is read through the SPI_MISO signal line,

[0042] The SPI interface module then sends a read feedback packet to the SPI master controller via the SPI_MISO signal line.

[0043] In a preferred embodiment, the SPI master controller generates a clock edge on the SPI_CK signal line, and sends a read command packet to the SPI interface module via the SPI_MOSI signal line.

[0044] Then the SPI master controller generates a clock edge on the SPI_CK signal line, reads the read feedback packet through the SPI_MISO signal line, and after the SPI interface module sends the read feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets, which include read command packets and write command packets.

[0045] In a preferred embodiment, the read feedback packet is divided into a read success feedback packet and a read failure feedback packet;

[0046] The SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line;

[0047] When the SPI interface module receives the read data packet and the status information contained in the read data packet is success, the SPI interface module sends the read success feedback packet through the SPI_MISO signal line, and the read success feedback packet starts with the seventh identifier;

[0048] When the SPI interface module receives the read data packet and the status information contained in the read data packet is failure, the SPI interface module sends the read failure feedback packet through the SPI_MISO signal line, and the read failure feedback packet starts with the eighth identifier.

[0049] In a preferred embodiment, the SPI interface module includes a timeout timer;

[0050] When the SPI interface module does not receive the read data packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, and reads the read feedback packet through the SPI_MISO signal line, the SPI interface module sends the read failure feedback packet to the SPI master controller through the SPI_MISO signal line.

[0051] The present invention provides an SPI interface system, an SPI data writing method and an SPI data reading method, which are suitable for application scenarios with longer transmission links and are also compatible with local applications with shorter transmission links, thereby providing an ideal solution for SPI transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0053] Figure 1The structure block diagram of a SPI interface system of the present invention is schematically shown.

[0054] Figure 2 It is a schematic diagram of the data structure of the write command packet of the present invention.

[0055] Figure 3 It is a timing diagram of an SPI data writing method in one embodiment of the present invention.

[0056] Figure 4 It is a timing diagram of an SPI data writing method in an embodiment of the present invention with an SPI_CSN signal line.

[0057] Figure 5 It is a timing diagram of an SPI data writing method in another embodiment of the present invention with an SPI_CSN signal line.

[0058] Figure 6 It is a timing diagram of an SPI data writing method in the second embodiment of the present invention.

[0059] Figure 7 It is a timing diagram of an SPI data writing method in the third embodiment of the present invention.

[0060] Figure 8 It is a timing diagram of an SPI data writing method in the fourth embodiment of the present invention.

[0061] Fig. 9 It is a timing diagram of an SPI data writing method in the fifth embodiment of the present invention.

[0062] Fig.10 It is a timing diagram of an SPI data writing method in the sixth embodiment of the present invention.

[0063] Fig.11 It is a timing diagram of an SPI data writing method in the seventh embodiment of the present invention.

[0064] Fig.12 It is a schematic diagram of the data structure of a read command packet of the present invention.

[0065] Fig.13 It is a timing diagram of an SPI data reading method in the eighth embodiment of the present invention.

[0066] Fig.14 It is a timing diagram of an SPI data reading method in the ninth embodiment of the present invention.

[0067] Fig.15 It is a timing diagram of an SPI data reading method in the tenth embodiment of the present invention.

[0068] Fig.16It is a timing diagram of an SPI data reading method in the eleventh embodiment of the present invention.

[0069] Fig.17 It is a timing diagram of an SPI data reading method in the twelfth embodiment of the present invention.

[0070] Fig.18 It is a timing diagram of an SPI data reading method in the thirteenth embodiment of the present invention.

[0071] The meanings of the text symbols in the above drawings are as follows:

[0072] 100: SPI master controller 100; 200: SPI interface module 200; SPI: functional module 300; SPI_CK: SPI_CK signal line; SPI_MOSI: SPI_MOSI signal line; SPI_MISO: SPI_MISO signal line; SPI_CSN: SPI_CSN signal line. DETAILED DESCRIPTION

[0073] In order to make the above and other features and advantages of the present invention more clear, the present invention is further described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explaining to those skilled in the art and are only exemplary and not restrictive.

[0074] like Figure 1 As shown, according to an embodiment of the present invention, a SPI interface system is provided, including a SPI main controller 100 , a SPI interface module 200 , and at least one functional module 300 .

[0075] The SPI interface module 200 is connected to the SPI master controller 100 via the SPI_CK signal line, the SPI_MOSI signal line, and the SPI_MISO signal line. The functional module 300 is connected to the SPI interface module 200 .

[0076] The SPI interface module 200 may be connected to a plurality of functional modules 300 , such as functional module 1, . . . , functional module N. In this embodiment, the SPI interface module 200 is connected to one functional module 300 as an example for description.

[0077] The SPI master controller 100 is a SPI master device, and the SPI interface module 200 is a SPI slave device. The SPI master controller 100 drives the SPI_CK signal line and the SPI_MOSI signal line, and the SPI interface module 200 receives the SPI_CK signal line and the SPI_MOSI signal line. The SPI interface module 200 drives the SPI_MISO signal line, and the SPI master controller 100 receives the SPI_MISO signal line.

[0078] The present invention does not limit the connection method between the SPI interface module 200 and the functional module 300. The SPI interface module 200 can be connected to one or more functional modules 300 through one or more transmission lines. At the same time, the present invention does not limit the positions of the SPI interface module 200 and the functional module 300. The SPI interface module 200 and the functional module 300 can be located in the same integrated circuit chip, or in different integrated circuit chips on a PCB board, or the SPI interface module 200 and the functional module 300 can also be located in different system devices.

[0079] SPI data writing method

[0080] The SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line, wherein the write command packet starts with a first identifier;

[0081] After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the function module 300;

[0082] The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200.

[0083] The SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line.

[0084] When the SPI interface module 200 receives the write status packet, the SPI interface module 200 sends the write feedback packet through the SPI_MISO signal line, the write feedback packet starts with a second identifier, and the write feedback packet includes the status information included in the write status packet.

[0085] like Figure 2 As shown, four write command packet embodiments are given:

[0086] The write command packet may include a first identifier and a write command data field, and start with the first identifier.

[0087] The write command packet may also include a first identifier, a write command length field, and a write command data field, and start with the first identifier.

[0088] The write command packet may also include a first identifier, a write command data field, and a write command check code, and start with the first identifier.

[0089] The write command packet may also include a first identifier, a write command length field, a write command data field, and a write command check code, and start with the first identifier.

[0090] The first identifier, write command length field (if any), write command data field, and write command check code (if any) contained in the write command packet are composed of a binary bit sequence. The present invention does not limit the length of the binary bit sequence of the first identifier, write command length field (if any), write command data field, and write command check code (if any).

[0091] It should be noted that the present invention does not limit the format of the write command packet, that is, the format of the write command packet in the present invention is not limited to Figure 2 Four write command packet embodiments are shown. The SPI master controller 100 and the SPI interface module 200 may agree on other write command packet formats.

[0092] In the present invention, the SPI interface module 200 receives the write command packet, which means that the data received by the SPI interface module 200 from the SPI_MOSI signal line reaches the length of the write command packet. In the present invention, the data received by the SPI interface module 200 from the SPI_MOSI signal line reaches the length of the write command packet, which means that the SPI interface module 200 receives a complete write command packet, such as Figure 2 As shown, the write command packet may include a write command length field. The SPI interface module 200 may determine whether the received data reaches the length of the write command packet based on the write command length field (or part of the write command length field) according to the agreement between the SPI master controller 100 and the SPI master controller 100, that is, whether a complete write command packet is received. Figure 2 As shown, the write command packet may not include the write command length field. In this case, the SPI interface module 200 determines whether the received data reaches the length of the write command packet, that is, whether a complete write command packet is received, based on the agreement between the SPI master controller 100 (this agreement is not based on the write command length field).

[0093] When the write command packet includes a write command packet check code, when the data received by the SPI interface module 200 from the SPI_MOSI signal line reaches the length of the write command packet, and the write command packet check code is verified to be correct, the SPI interface module 200 receives the write command packet. The present invention does not limit which write command packet check code is used. The SPI interface module 200 can agree on a write command packet check code with the SPI master controller 100, such as using a common CRC code as a write command packet check code. In the present invention, the write command packet check code can be an error detection code and an error correction code. The error detection code only has error detection capability, such as a CRC code, while the error correction code can both correct and detect errors.

[0094] The SPI master controller 100 drives the SPI_CK signal line, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, the SPI master controller 100 samples the data on the SPI_MISO signal line at the rising edge or falling edge of the clock on the SPI_CK signal line, and the SPI interface module 200 samples the data on the SPI_MOSI signal line at the rising edge or falling edge of the clock on the SPI_CK signal line to realize bidirectional transmission of data between the SPI master controller 100 and the SPI interface module 200.

[0095] The present invention is not limited to sampling the data on the SPI_MISO signal line and the SPI_MOSI signal line at the rising edge or falling edge of the clock on the SPI_CK signal line. In the embodiments of the present invention described below, the data on the SPI_MISO signal line and the SPI_MOSI signal line are sampled at the rising edge of the clock on the SPI_CK signal line, that is, in the embodiments of the present invention described below, the rising edge of the clock on the SPI_CK signal line is the sampling clock edge. In other embodiments of the present invention, the data on the SPI_MISO signal line and the SPI_MOSI signal line may also be sampled at the falling edge of the clock on the SPI_CK signal line, that is, in these embodiments, the falling edge of the clock on the SPI_CK signal line is the sampling clock edge.

[0096] like Figure 3 As shown, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and drives the SPI_MOSI signal line at the same time, and sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line. The write command packet includes N bytes, each byte is 8-bit binary data, the first byte is the first identifier, and the 8-bit binary data of the first byte is C 10 , C 11 …C 17 Indicates that the Nth byte of the write command packet is the last byte of the write command packet, and the 8-bit binary data of the Nth byte of the write command packet is in C N0 , C N1 …C N7 express.

[0097] The SPI interface module 200 samples the data on the SPI_MOSI signal line at the rising edge of the clock on the SPI_CK signal line, receives a write command packet from the SPI_MOSI signal line, and N7 bits later, the data received from the SPI_MOSI signal line reaches the length of the write command packet, and the SPI interface module 200 receives the write command packet.

[0098] After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. In the present invention, when the SPI interface module 200 sends the write command packet to the functional module 300, the content in the write command packet can be modified, added or deleted, and the present invention does not limit or stipulate this.

[0099] The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200.

[0100] At moment ①, the SPI interface module 200 receives a write status packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, the SPI interface module 200 drives the SPI_MISO signal line, and sends a write feedback packet through the SPI_MISO signal line. The SPI master controller 100 samples the data on the SPI_MISO signal line at the rising edge of the clock on the SPI_CK signal line, and reads the write feedback packet, which starts with a second identifier and includes status information included in the write status packet. The status information included in the write status packet may be write success or write failure, or other status information.

[0101] The write feedback packet includes M bytes, each byte is 8-bit binary data, the first byte is the second identifier, and the 8-bit binary data of the first byte is A 10 , A 11 …A 17 Indicates that the Mth byte of the write feedback packet is the last byte of the write feedback packet, and the 8-bit binary data of the Mth byte of the write feedback packet is A M0 , A M1 …A M7 express.

[0102] For ease of understanding, Figure 3 In the illustrated embodiment and the following description of the present invention, each byte is described as 8-bit binary data, but the present invention is not limited to the number of bits of each byte, and each byte may also be other numbers of bits.

[0103] Figure 3In the illustrated embodiment, the length of the first identifier and the second identifier is one byte, and the length of the write command packet and the write feedback packet is an integer multiple of a byte. For ease of understanding, in the following description of the present invention, the length of the first to eighth identifiers is one byte, and the length of the write command packet, the read command packet, the write feedback packet (including a write success feedback packet and a write failure feedback packet), and the read feedback packet (including a read success feedback packet and a read failure feedback packet) is an integer multiple of a byte. However, the present invention does not limit the length of the first to eighth identifiers to one byte, nor does it limit the length of the first to eighth identifiers to an integer multiple of a byte. The present invention also does not limit the length of the write command packet, the read command packet, the write feedback packet (including a write success feedback packet and a write failure feedback packet), and the read feedback packet (including a read success feedback packet and a read failure feedback packet) to an integer multiple of a byte.

[0104] In the interval marked as “no clock edge”, the SPI master controller 100 does not generate a sampling clock edge on the SPI_CK signal line. Figure 3 In the description of the subsequent embodiments of the present invention, the levels of the SPI_MOSI and SPI_MISO signal lines remain unchanged in the "no clock edge" interval. The present invention is not limited to the levels of the SPI_MOSI and SPI_MISO signal lines in the "no clock edge" interval. The levels of the SPI_MOSI and SPI_MISO signal lines can also change in the "no clock edge" interval, but because the sampling of data on the SPI_MOSI and SPI_MISO signal lines is only performed on the sampling clock edge of the SPI_CK signal line ( Figure 3 In the embodiment shown, the sub-sampling clock edge is the rising edge of the clock, and level changes on the SPI_MOSI and SPI_MISO signal lines in the "no clock edge" interval will not be sampled and received.

[0105] exist Figure 3 In the illustrated embodiment, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and drives the SPI_MOSI signal line at the same time. When sending a write command packet through the SPI_MOSI signal line, the SPI interface module 200 has no write feedback packet to send. At this time, the SPI interface module 200 drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200 of the present invention can also drive the SPI_MISO signal line to a low level or a changing level. However, the SPI interface module 200 should ensure that the level value driven on the SPI_MISO signal line or the changing level value, if sampled by the SPI master controller 100 on the sampling clock edge of the SPI_CK signal line ( Figure 3 In the embodiment shown, the sub-sampling clock edge is the rising edge of the clock and is not identified as the second identifier. Figure 3Taking the illustrated embodiment as an example, since the SPI interface module 200 drives the SPI_MISO signal line to a high level (sampled as continuous binary bits 1) during this period, in order not to be identified as the second identifier, the value of the second identifier should not be 0xFF.

[0106] exist Figure 3 In the illustrated embodiment, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and the SPI interface module 200 drives the SPI_MISO signal line. When sending a write feedback packet through the SPI_MISO signal line, the SPI master controller 100 has no write command packet to send. At this time, the SPI master controller 100 drives the SPI_MOSI signal line to a high level. During this period, the SPI master controller 100 of the present invention can also drive the SPI_MOSI signal line to a low level or a changing level, but the SPI master controller 100 should ensure that the level value driven on the SPI_MOSI signal line or the changing level value, if it is sampled by the SPI interface module 200 on the sampling clock edge of the SPI_CK signal line ( Figure 3 In the embodiment shown, the sub-sampling clock edge is the rising edge of the clock and is not identified as the first identifier. Figure 3 Taking the illustrated embodiment as an example, since the SPI master controller 100 drives the SPI_MOSI signal line to a high level (sampled as continuous binary bits 1) during this period, in order not to be identified as the first identifier, the value of the first identifier should not be 0xFF.

[0107] The SPI interface module 200 can also be connected to the SPI master controller 100 through the SPI_CSN signal line in addition to the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line. The SPI master controller 100 drives the SPI_CSN signal line, the SPI_CK signal line and the SPI_MOSI signal line, and the SPI interface module 200 receives the SPI_CSN signal line, the SPI_CK signal line and the SPI_MOSI signal line. The SPI interface module 200 drives the SPI_MISO signal line, and the SPI master controller 100 receives the SPI_MISO signal line. The SPI_CSN signal line is a selection signal. In the SPI protocol, data transmission is performed only when the SPI_CSN signal line is low. One SPI master controller 100 can be connected to multiple SPI interface modules 200, wherein the SPI master controller 100 and multiple SPI interface modules 200 share the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line, but each SPI interface module 200 has an independent SPI_CSN signal line input, when the SPI_CSN signal line of one SPI interface module 200 is high, this SPI interface module 200 does not drive the SPI_MISO signal line (the driver of this SPI interface module 200 connected to the SPI_MISO signal line outputs the Hi-Z state), and one SPI interface module 200 drives the SPI_MISO signal line only when its SPI_CSN signal line is low. When one SPI master controller 100 is connected to multiple SPI interface modules 200, at any time, only one SPI interface module 200 has the SPI_CSN signal line low, thereby avoiding conflicts caused by multiple SPI interface modules 200 driving the SPI_MISO signal line at the same time.

[0108] When a SPI master controller 100 is connected to only one SPI interface module 200, the SPI interface module 200 can drive the SPI_MISO signal line at any time without causing a conflict. In this case, there may be no SPI_CSN signal line between the SPI master controller 100 and the SPI interface module 200. That is, when a SPI master controller 100 is connected to only one SPI interface module 200, the SPI master controller 100 and the SPI interface module 200 may be connected only through the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line. Figure 3 This is the case in the description of the illustrated embodiment.

[0109] like Figure 4 As shown, an embodiment of the SPI_CSN signal line between the SPI master controller 100 and the SPI interface module 200 is provided. Figure 4 The illustrated embodiment describes Figure 3 The same process as the embodiment shown, that is, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line, and after the SPI interface module 200 receives the write command packet from the SPI_MOSI signal line, sends the write command packet to the functional module 300, the functional module 300 receives the write command packet and executes the write command, when the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200, at the first moment, the SPI interface module 200 receives the write status packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and reads a write feedback packet from the SPI interface module 200 through the SPI_MISO signal line, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, drives the SPI_CSN signal line to be low before sending the write command packet to the SPI interface module 200 through the SPI_MOSI signal line, and drives the SPI_CSN signal line to be high after reading the write feedback packet sent by the SPI interface module 200 through the SPI_MISO signal line. During the "no clock edge" period, the SPI_CSN signal line remains low.

[0110] like Figure 5 As shown, another embodiment of the present invention is provided in which a SPI_CSN signal line exists between the SPI master controller 100 and the SPI interface module 200. Figure 5 The illustrated embodiment describes Figure 3The same process as the embodiment shown, that is, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line, and after the SPI interface module 200 receives the write command packet from the SPI_MOSI signal line, it sends the write command packet to the functional module 300, and the functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200. At the first moment, the SPI interface module 200 receives the write status packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and reads the SPI_MISO signal line from the SPI interface module 200. Write feedback packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, drives the SPI_CSN signal line low before sending the write command packet to the SPI interface module 200 through the SPI_MOSI signal line, and drives the SPI_CSN signal line high during the "no clock edge" period after sending the write command packet. The SPI master controller 100 generates a clock edge on the SPI_CK signal line and drives the SPI_CSN signal line low before reading the write feedback packet sent by the SPI interface module 200 through the SPI_MISO signal line, and drives the SPI_CSN signal line high after reading the write feedback packet sent by the SPI interface module 200 through the SPI_MISO signal line.

[0111] When a SPI master controller 100 is connected to only one SPI interface module 200, there may be no SPI_CSN signal line between the SPI master controller 100 and the SPI interface module 200. Figure 3 The description of the illustrated embodiment is for this case. Figure 4 and Figure 5 Described in Figure 3 Based on the embodiment shown in the figure, there is also an embodiment of the SPI_CSN signal line between the SPI master controller 100 and the SPI interface module 200. The following description of the present invention only describes the case where there is no SPI_CSN signal line between the SPI master controller 100 and the SPI interface module 200. Figure 4 and Figure 5 The illustrated embodiment can be easily extended to the case where a SPI_CSN signal line exists between the SPI master controller 100 and the SPI interface module 200. The following description of the present invention will not repeat the case where a SPI_CSN signal line exists between the SPI master controller 100 and the SPI interface module 200. Whether or not a SPI_CSN signal line exists between the SPI master controller 100 and the SPI interface module 200 is within the protection scope of the present invention.

[0112] The SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. When the SPI interface module 200 does not receive the write status packet, the SPI interface module 200 sends data that cannot be identified as the write feedback packet to the SPI master controller 100 through the SPI_MISO signal line.

[0113] by Figure 6 As shown in the figure as an example, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200. At the third moment, the SPI interface module 200 receives the write status packet. Before the third moment when the SPI interface module 200 receives the write status packet, between the first moment and the second moment, the SPI master controller 100 generates a clock edge on the SPI_CK signal line. Figure 6 In the embodiment shown, the SPI interface module 200 drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200 may also drive the SPI_MISO signal line to a low level or a changing level. However, the SPI interface module 200 should ensure that the level value driven on the SPI_MISO signal line or the changing level value, if sampled by the SPI master controller 100 at the sampling clock edge on the SPI_CK signal line ( Figure 3 In the embodiment shown, the sampling clock edge is the rising edge of the clock), which is not recognized as the second identifier, that is, when the SPI interface module 200 does not receive the write status packet, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line, the SPI interface module 200 sends data that cannot be recognized as the write feedback packet to the SPI master controller 100 through the SPI_MISO signal line. After the SPI interface module 200 receives the write status packet at the third moment, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the write feedback packet from the SPI interface module 200 through the SPI_MISO signal line.

[0114] exist Figure 7In the illustrated embodiment, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. After the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the write status packet, and the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and reads a write feedback packet from the SPI interface module 200 through the SPI_MISO signal line. At the second moment, the SPI master controller 100 completes reading the write feedback packet, the SPI interface module 200 completes sending the write feedback packet, and the SPI master controller 100 continues to generate a clock edge on the SPI_CK signal line. At this time, the SPI interface module 200 drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200 can also drive the SPI_MISO signal line to a low level or a changing level, but the SPI interface module 200 should ensure that the level value driven on the SPI_MISO signal line or the changing level value, if sampled by the SPI master controller 100 on the sampling clock edge of the SPI_CK signal line ( Figure 3 In the illustrated embodiment, the sampling clock edge is a rising clock edge), which is not identified as a second identifier.

[0115] The SPI interface module 200 may further include a timeout timer; the timeout timer starts timing when a write command packet is received or a write command packet is sent to the function module 300, or starts timing at a preset time after receiving the write command packet. When the SPI interface module 200 does not receive the write status packet before timeout, after timeout, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line, the write feedback packet is read through the SPI_MISO signal line, and the SPI interface module 200 sends a write feedback packet to the SPI master controller 100 through the SPI_MISO signal line. The write feedback packet includes status information, which is agreed upon by the SPI master controller 100 and the SPI interface module 200. The status information may include write command packet timeout information, or may be other status information agreed upon by the SPI master controller 100 and the SPI interface module 200.

[0116] In the present invention, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends the write command packet to the SPI interface module 200 through the SPI_MOSI signal line. After the SPI interface module 200 receives the write command packet from the SPI_MOSI signal line, it sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200. Then, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and reads the write feedback packet through the SPI_MISO signal line. Before the SPI master controller 100 reads the write feedback packet, if the SPI master controller 100 drives the SPI_MOSI signal line to send a command packet (including a write command packet and a read command packet described below in the present invention), the SPI interface module 200 does not receive the command packet sent by the SPI master controller 100 before reading the write feedback packet. After the SPI master controller 100 reads the write feedback packet, that is, after the SPI interface module 200 sends the write feedback packet through the SPI_MISO signal line, the SPI interface module 200 can continue to receive subsequent command packets, which include a write command packet and a read command packet described below in the present invention.

[0117] In the present invention, the write feedback packet can be divided into a write success feedback packet and a write failure feedback packet. The SPI master controller 100 generates a clock edge on the SPI_CK signal line. When the write feedback packet is read through the SPI_MISO signal line, if the SPI interface module 200 receives the write status packet and the status information contained in the write status packet is success, the SPI interface module 200 sends the write success feedback packet through the SPI_MISO signal line, and the write success feedback packet starts with a third identifier. If the SPI interface module 200 receives the write status packet and the status information contained in the write status packet is failure, the SPI interface module 200 sends the write failure feedback packet through the SPI_MISO signal line, and the write failure feedback packet starts with a fourth identifier.

[0118] like Figure 8As shown, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200. At the first moment, the SPI interface module 200 receives the write status packet, and the status information included in the write status packet is success. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a write feedback packet from the SPI interface module 200 through the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a write success feedback packet to the SPI master controller 100 through the SPI_MISO signal line. The write success feedback packet starts with a third identifier.

[0119] like Fig.10 As shown, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200. At the first moment, the SPI interface module 200 receives the write status packet, and the status information included in the write status packet is failure. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a write feedback packet from the SPI interface module 200 through the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a write failure feedback packet to the SPI master controller 100 through the SPI_MISO signal line, and the write failure feedback packet starts with the fourth identifier.

[0120] In the present invention, the third identifier is different from the fourth identifier. When the SPI master controller 100 reads a write feedback packet, it can be determined whether the read write success feedback packet or the write failure feedback packet is a write success feedback packet or a write failure feedback packet by whether the write feedback packet starts with the third identifier or the fourth identifier. Therefore, the write success feedback packet may only include the third identifier, and the write failure feedback packet may only include the fourth identifier, so that the SPI master controller 100 can distinguish whether the read write feedback packet is a write success feedback packet or a write failure feedback packet.

[0121] like Fig. 9As shown, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200. At the first moment, the SPI interface module 200 receives the write status packet, and the status information included in the write status packet is success. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a write feedback packet from the SPI interface module 200 through the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a write success feedback packet to the SPI master controller 100 through the SPI_MISO signal line, and the write success feedback packet only includes the third identifier.

[0122] like Fig.11 As shown, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200. At the first moment, the SPI interface module 200 receives the write status packet, and the status information included in the write status packet is failure. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a write feedback packet from the SPI interface module 200 through the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a write failure feedback packet to the SPI master controller 100 through the SPI_MISO signal line, and the write failure feedback packet only includes the fourth identifier.

[0123] The SPI interface module 200 may further include a timeout timer, which starts timing when a write command packet is received or a write command packet is sent to the functional module 300, or starts timing at a preset time after receiving the write command packet. When the SPI interface module 200 does not receive the write status packet before timeout, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line after timeout, the write feedback packet is read through the SPI_MISO signal line, and the SPI interface module 200 sends a write failure feedback packet to the SPI master controller 100 through the SPI_MISO signal line. The write feedback packet includes status information, which is agreed upon by the SPI master controller 100 and the SPI interface module 200. The status information may include write command packet timeout information, or may be other status information agreed upon by the SPI master controller 100 and the SPI interface module 200.

[0124] SPI data reading method

[0125] The SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a read command packet to the SPI interface module 200 through the SPI_MOSI signal line, wherein the read command packet starts with a fifth identifier;

[0126] After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300;

[0127] The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns the read data packet to the SPI interface module 200.

[0128] The SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line.

[0129] When the SPI interface module 200 receives the read data packet, the SPI interface module 200 sends the read feedback packet through the SPI_MISO signal line, the read feedback packet starts with the sixth identifier, and the read feedback packet includes the read data included in the read data packet.

[0130] like Fig.12 As shown, four read command packet embodiments are given:

[0131] The read command packet may include a fifth identifier and a read command data field, and start with the fifth identifier.

[0132] The read command packet may also include a fifth identifier, a read command length field, and a read command data field, and start with the fifth identifier.

[0133] The read command packet may also include a fifth identifier, a read command data field, and a read command check code, and start with the fifth identifier.

[0134] The read command packet may also include a fifth identifier, a read command length field, a read command data field, and a read command check code, and start with the fifth identifier.

[0135] The fifth identifier, read command length field (if any), read command data field, and read command check code (if any) contained in the read command packet are composed of a binary bit sequence. The present invention does not limit the length of the binary bit sequence of the fifth identifier, read command length field (if any), read command data field, and read command check code (if any).

[0136] It should be noted that the present invention does not limit the format of the read command packet, that is, the format of the read command packet in the present invention is not limited to Fig.12 Four read command packet embodiments are shown. The SPI master controller 100 and the SPI interface module 200 may agree on other read command packet formats.

[0137] In the present invention, the SPI interface module 200 receives the read command packet, which means that the data received by the SPI interface module 200 from the SPI_MOSI signal line reaches the length of the read command packet. In the present invention, the data received by the SPI interface module 200 from the SPI_MOSI signal line reaches the length of the read command packet, which means that the SPI interface module 200 receives a complete read command packet, such as Fig.12 As shown, the read command packet may include a read command length field. The SPI interface module 200 may determine whether the received data reaches the length of the read command packet based on the read command length field (or part of the read command length field) according to the agreement between the SPI master controller 100 and the SPI master controller 100, that is, whether a complete read command packet is received. Fig.12 As shown, the read command packet may not include the read command length field. In this case, the SPI interface module 200 determines whether the received data reaches the length of the read command packet, that is, whether a complete read command packet is received, based on the agreement between the SPI master controller 100 (this agreement is not based on the read command length field).

[0138] When the read command packet includes a read command packet check code, when the data received by the SPI interface module 200 from the SPI_MOSI signal line reaches the length of the read command packet, and the read command packet check code is verified to be correct, the SPI interface module 200 receives the read command packet. The present invention does not limit which read command packet check code is used. The SPI interface module 200 can agree on a read command packet check code with the SPI master controller 100, such as using a common CRC code as a read command packet check code. In the present invention, the read command packet check code can be an error detection code and an error correction code. The error detection code only has error detection capability, such as a CRC code, while the error correction code can both correct and detect errors.

[0139] like Fig.13 As shown, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and drives the SPI_MOSI signal line at the same time, and sends a read command packet to the SPI interface module 200 through the SPI_MOSI signal line. The read command packet includes N bytes, each byte is 8-bit binary data, the first byte is the fifth identifier, and the 8-bit binary data of the first byte is C 10 , C 11 …C 17 Indicates that the Nth byte of the read command packet is the last byte of the read command packet, and the 8-bit binary data of the Nth byte of the read command packet is in C N0 , C N1 …C N7 express.

[0140] The SPI interface module 200 samples the data on the SPI_MOSI signal line at the rising edge of the clock on the SPI_CK signal line, receives a read command packet from the SPI_MOSI signal line, and N7 bits later, the data received from the SPI_MOSI signal line reaches the length of the read command packet, and the SPI interface module 200 receives the read command packet.

[0141] After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. In the present invention, when the SPI interface module 200 sends the read command packet to the functional module 300, the content in the read command packet may be modified, added or deleted, and the present invention does not limit or stipulate this.

[0142] The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns the read data packet to the SPI interface module 200.

[0143] At moment ①, the SPI interface module 200 receives a read data packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, the SPI interface module 200 drives the SPI_MISO signal line, and sends a read feedback packet through the SPI_MISO signal line. The SPI master controller 100 samples the data on the SPI_MISO signal line at the rising edge of the clock on the SPI_CK signal line, and reads the read feedback packet, which starts with the sixth identifier and contains the read data contained in the read data packet.

[0144] The read data includes data read from the functional module 300, or read status information generated by the functional module 300 executing a read command, or both data read from the functional module 300 and read status information generated by the functional module 300 executing a read command. The read status information can be read success, read failure, or other status information.

[0145] The read feedback packet includes M bytes, each byte is 8-bit binary data, the first byte is the sixth identifier, and the 8-bit binary data of the first byte is A. 10 , A 11 …A 17 Indicates that the Mth byte of the read feedback packet is the last byte of the read feedback packet, and the 8-bit binary data of the Mth byte of the read feedback packet is in A M0 , A M1 …A M7 express.

[0146] exist Fig.13 In the illustrated embodiment, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and drives the SPI_MOSI signal line at the same time. When sending a read command packet through the SPI_MOSI signal line, the SPI interface module 200 has no read feedback packet to send. At this time, the SPI interface module 200 drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200 of the present invention can also drive the SPI_MISO signal line to a low level or a changing level. However, the SPI interface module 200 should ensure that the level value driven on the SPI_MISO signal line or the changing level value, if sampled by the SPI master controller 100 on the sampling clock edge of the SPI_CK signal line ( Fig.13 In the embodiment shown, the sub-sampling clock edge is the rising edge of the clock, which is not identified as the sixth identifier. Fig.13 Taking the illustrated embodiment as an example, since the SPI interface module 200 drives the SPI_MISO signal line to a high level (sampled as continuous binary bits 1) during this period, in order not to be identified as the sixth identifier, the value of the sixth identifier should not be 0xFF.

[0147] exist Fig.13 In the illustrated embodiment, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and the SPI interface module 200 drives the SPI_MISO signal line. When sending a read feedback packet through the SPI_MISO signal line, the SPI master controller 100 has no read command packet to send. At this time, the SPI master controller 100 drives the SPI_MOSI signal line to a high level. During this period, the SPI master controller 100 of the present invention can also drive the SPI_MOSI signal line to a low level or a changing level, but the SPI master controller 100 should ensure that the level value driven on the SPI_MOSI signal line or the changing level value, if it is sampled by the SPI interface module 200 on the sampling clock edge of the SPI_CK signal line ( Fig.13 In the embodiment shown, the sub-sampling clock edge is the rising edge of the clock and is not identified as the fifth identifier. Fig.13 Taking the illustrated embodiment as an example, since the SPI master controller 100 drives the SPI_MOSI signal line to a high level (sampled as continuous binary bits 1) during this period, in order not to be identified as the fifth identifier, the value of the fifth identifier should not be 0xFF.

[0148] The SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line. When the SPI interface module 200 does not receive the read data packet, the SPI interface module 200 sends data that cannot be identified as the read feedback packet to the SPI master controller 100 through the SPI_MISO signal line.

[0149] by Fig.14 As shown in the figure as an example, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a read command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns the read data packet to the SPI interface module 200. At the third moment, the SPI interface module 200 receives the read data packet. Before the third moment when the SPI interface module 200 receives the read data packet, between the first moment and the second moment, the SPI master controller 100 generates a clock edge on the SPI_CK signal line. Fig.14In the embodiment shown, the SPI interface module 200 drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200 may also drive the SPI_MISO signal line to a low level or a changing level. However, the SPI interface module 200 should ensure that the level value driven on the SPI_MISO signal line or the changing level value, if sampled by the SPI master controller 100 at the sampling clock edge on the SPI_CK signal line ( Fig.14 In the embodiment shown, the sampling clock edge is the rising edge of the clock), which is not identified as the sixth identifier, that is, when the SPI interface module 200 does not receive the read data packet, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line, the SPI interface module 200 sends data that cannot be identified as the read feedback packet to the SPI master controller 100 through the SPI_MISO signal line. At the third moment, after the SPI interface module 200 receives the read data packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the read feedback packet from the SPI interface module 200 through the SPI_MISO signal line.

[0150] exist Fig.15 In the illustrated embodiment, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a read command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns the read data packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the read data packet, and the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and reads a read feedback packet from the SPI interface module 200 through the SPI_MISO signal line. At the second moment, the SPI master controller 100 completes reading the read feedback packet, the SPI interface module 200 completes sending the read feedback packet, and the SPI master controller 100 continues to generate a clock edge on the SPI_CK signal line. At this time, the SPI interface module 200 drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200 can also drive the SPI_MISO signal line to a low level or a changing level, but the SPI interface module 200 should ensure that the level value driven on the SPI_MISO signal line or the changing level value, if sampled by the SPI master controller 100 on the sampling clock edge of the SPI_CK signal line ( Fig.15 In the illustrated embodiment, the sampling clock edge is a rising clock edge), which is not identified as the sixth identifier.

[0151] The SPI interface module 200 may further include a timeout timer; the timeout timer starts timing when a read command packet is received or a read command packet is sent to the functional module 300, or starts timing at a preset time after receiving the read command packet. When the SPI interface module 200 does not receive the read data packet before timeout, after timeout, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line, the read feedback packet is read through the SPI_MISO signal line, and the SPI interface module 200 sends the read feedback packet to the SPI master controller 100 through the SPI_MISO signal line. The read feedback packet includes status information, which is agreed upon by the SPI master controller 100 and the SPI interface module 200. The status information may include read command packet timeout information, or may be other status information agreed upon by the SPI master controller 100 and the SPI interface module 200.

[0152] In the present invention, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends the read command packet to the SPI interface module 200 through the SPI_MOSI signal line. After the SPI interface module 200 receives the read command packet from the SPI_MOSI signal line, it sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns the read data packet to the SPI interface module 200. Then, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends the read command packet to the SPI interface module 200 through the SPI_MISO signal line. Read the read feedback packet. Before the SPI master controller 100 reads the read feedback packet, if the SPI master controller 100 drives the SPI_MOSI signal line to send a command packet (including a read command packet and a write command packet), the SPI interface module 200 does not receive the command packet sent by the SPI master controller 100 before reading the read feedback packet. After the SPI master controller 100 reads the read feedback packet, that is, after the SPI interface module 200 sends the read feedback packet through the SPI_MISO signal line, the SPI interface module 200 can continue to receive subsequent command packets, which include a read command packet and a write command packet.

[0153] In the present invention, the read feedback packet can be divided into a read success feedback packet and a read failure feedback packet. The SPI master controller 100 generates a clock edge on the SPI_CK signal line. When the read feedback packet is read through the SPI_MISO signal line, if the SPI interface module 200 receives the read data packet and the status information contained in the read data packet is success, the SPI interface module 200 sends the read success feedback packet through the SPI_MISO signal line, and the read success feedback packet starts with the seventh identifier. If the SPI interface module 200 receives the read data packet and the status information contained in the read data packet is failure, the SPI interface module 200 sends the read failure feedback packet through the SPI_MISO signal line, and the read failure feedback packet starts with the eighth identifier.

[0154] like Fig.16 As shown, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a read command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns a read data packet to the SPI interface module 200. At the first moment, the SPI interface module 200 receives the read data packet, and the status information included in the read data packet is success. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a read feedback packet from the SPI interface module 200 through the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a read success feedback packet to the SPI master controller 100 through the SPI_MISO signal line, and the read success feedback packet starts with the seventh identifier.

[0155] like Fig.17As shown, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a read command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns a read data packet to the SPI interface module 200. At the first moment, the SPI interface module 200 receives the read data packet, and the status information included in the read data packet is failure. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a read feedback packet from the SPI interface module 200 through the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a read failure feedback packet to the SPI master controller 100 through the SPI_MISO signal line, and the read failure feedback packet starts with the eighth identifier.

[0156] In the present invention, the seventh identifier is different from the eighth identifier. When the SPI master controller 100 reads a read feedback packet, it can determine whether the read feedback packet is a read success feedback packet or a read failure feedback packet by whether the read feedback packet starts with the seventh identifier or the eighth identifier. The read success feedback packet starts with the seventh identifier and includes the data read from the functional module 300, while the read failure feedback packet may only include the eighth identifier.

[0157] like Fig.18 As shown, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and sends a read command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns a read data packet to the SPI interface module 200. At the first moment, the SPI interface module 200 receives the read data packet, and the status information included in the read data packet is failure. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a read feedback packet from the SPI interface module 200 through the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a read failure feedback packet to the SPI master controller 100 through the SPI_MISO signal line, and the read failure feedback packet only includes the eighth identifier.

[0158] The SPI interface module 200 may further include a timeout timer, which starts timing when a read command packet is received or a read command packet is sent to the functional module 300, or starts timing at a preset time after receiving the read command packet. When the SPI interface module 200 does not receive the read data packet before timeout, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line after timeout, the read feedback packet is read through the SPI_MISO signal line, and the SPI interface module 200 sends a read failure feedback packet to the SPI master controller 100 through the SPI_MISO signal line. The read feedback packet includes status information, which is agreed upon by the SPI master controller 100 and the SPI interface module 200. The status information may include read command packet timeout information, or may be other status information agreed upon by the SPI master controller 100 and the SPI interface module 200.

[0159] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations on the present invention. Any changes, modifications, substitutions and variations of the above embodiments made by a person skilled in the art within the scope of the present invention shall fall within the scope of protection of the present invention.

Claims

1. A method for writing SPI data. It is characterized in that An SPI interface system is used for data writing, wherein the SPI interface system comprises an SPI interface module and at least one functional module; the SPI interface module is connected to an SPI master controller via an SPI_CK signal line, an SPI_MOSI signal line and an SPI_MISO signal line, and the functional module is connected to the SPI interface module; The SPI data writing method comprises: The SPI master controller generates a clock edge on the SPI_CK signal line, and sends a write command packet to the SPI interface module through the SPI_MOSI signal line, wherein the write command packet starts with a first identifier; After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module sends the write command packet to the functional module; The functional module receives the write command packet and executes the write command, and when the functional module completes the write command, returns a write status packet to the SPI interface module; The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. When the SPI interface module receives the write status packet, the SPI interface module sends the write feedback packet through the SPI_MISO signal line, the write feedback packet starts with a second identifier, and the write feedback packet includes the status information included in the write status packet.

2. The SPI data writing method according to claim 1, It is characterized in that When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the write command packet, the SPI interface module receives the write command packet.

3. The SPI data writing method according to claim 1, It is characterized in that The write command packet also includes a write command packet verification code; When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the write command packet, and the write command packet check code is verified to be correct, the SPI interface module receives the write command packet.

4. The SPI data writing method according to claim 1, It is characterized in that The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. When the SPI interface module does not receive the write status packet, the SPI interface module sends data that cannot be identified as the write feedback packet to the SPI master controller through the SPI_MISO signal line.

5. The SPI data writing method according to claim 1, It is characterized in that The SPI interface module includes a timeout timer; When the SPI interface module does not receive the write status packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, the write feedback packet is read through the SPI_MISO signal line, The SPI interface module then sends a write feedback packet to the SPI master controller via the SPI_MISO signal line.

6. The SPI data writing method according to claim 1, It is characterized in that The SPI master controller generates a clock edge on the SPI_CK signal line, and sends the write command packet to the SPI interface module via the SPI_MOSI signal line. Then the SPI master controller generates a clock edge on the SPI_CK signal line, reads the write feedback packet through the SPI_MISO signal line, and after the SPI interface module sends the write feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets, which include write command packets and read command packets.

7. The SPI data writing method according to claim 1, It is characterized in that The write feedback packet is divided into a write success feedback packet and a write failure feedback packet; The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. When the SPI interface module receives the write status packet and the status information contained in the write status packet is success, the SPI interface module sends the write success feedback packet through the SPI_MISO signal line, where the write success feedback packet starts with a third identifier; When the SPI interface module receives the write status packet and the status information contained in the write status packet is failure, the SPI interface module sends the write failure feedback packet through the SPI_MISO signal line, and the write failure feedback packet starts with a fourth identifier.

8. The SPI data writing method according to claim 7, It is characterized in that The SPI interface module includes a timeout timer; When the SPI interface module does not receive the write status packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, and reads the write feedback packet through the SPI_MISO signal line, the SPI interface module sends the write failure feedback packet to the SPI master controller through the SPI_MISO signal line.

9. A method for reading SPI data. It is characterized in that An SPI interface system is used to read data, the SPI interface system comprising an SPI interface module and at least one functional module; the SPI interface module is connected to an SPI main controller via an SPI_CK signal line, an SPI_MOSI signal line and an SPI_MISO signal line, and the functional module is connected to the SPI interface module; The SPI data reading method comprises: The SPI master controller generates a clock edge on the SPI_CK signal line, and sends a read command packet to the SPI interface module through the SPI_MOSI signal line, wherein the read command packet starts with a fifth identifier; After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module sends the read command packet to the functional module; The functional module receives the read command packet and executes the read command, and when the functional module completes the read command, returns the read data packet to the SPI interface module; The SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line. When the SPI interface module receives the read data packet, the SPI interface module sends the read feedback packet through the SPI_MISO signal line, wherein the read feedback packet includes the read data included in the read data packet. The read feedback packet is a read success feedback packet or a read failure feedback packet. When the status information contained in the read data packet received by the SPI interface module is success, the SPI interface module sends a read success feedback packet, and the read success feedback packet starts with a seventh identifier. When the status information contained in the read data packet received by the SPI interface module is failure, the SPI interface module sends a read failure feedback packet, and the read failure feedback packet starts with an eighth identifier.

10. The SPI data reading method according to claim 9, It is characterized in that When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the read command packet, the SPI interface module receives the read command packet.

11. The SPI data reading method according to claim 9, It is characterized in that The read command packet also includes a read command packet check code; When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the read command packet, and the check code of the read command packet is verified to be correct, the SPI interface module receives the read command packet.

12. The SPI data reading method according to claim 9, It is characterized in that The SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line. When the SPI interface module does not receive the read data packet, the SPI interface module sends data that cannot be identified as the read feedback packet to the SPI master controller through the SPI_MISO signal line.

13. The SPI data reading method according to claim 9, It is characterized in that The SPI interface module includes a timeout timer; When the SPI interface module does not receive the read data packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, the read feedback packet is read through the SPI_MISO signal line, The SPI interface module then sends a read feedback packet to the SPI master controller via the SPI_MISO signal line.

14. The SPI data reading method according to claim 9, It is characterized in that The SPI master controller generates a clock edge on the SPI_CK signal line and sends a read command packet to the SPI interface module via the SPI_MOSI signal line. Then the SPI master controller generates a clock edge on the SPI_CK signal line, reads the read feedback packet through the SPI_MISO signal line, and after the SPI interface module sends the read feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets, which include read command packets and write command packets.

15. The SPI data reading method according to claim 9, It is characterized in that The SPI interface module includes a timeout timer; When the SPI interface module does not receive the read data packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, and reads the read feedback packet through the SPI_MISO signal line, the SPI interface module sends the read failure feedback packet to the SPI master controller through the SPI_MISO signal line.

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