Display panel

Abstract

The application discloses a display panel with a first display area and a second display area of different sizes along a first direction, and the display panel comprises m scanning lines, a first gate driving circuit, a second gate driving circuit and a synchronization controller. The first gate driving circuit is connected with the scanning lines, the second gate driving circuit is connected with the kth to mth scanning lines, and the first gate driving circuit and the second gate driving circuit scan in the same direction. The synchronization controller is connected with a control signal output end, an input end of a first-stage second driving unit and an output end of one of a first-stage first driving unit to a k-1 stage first driving unit. The application makes the second gate driving circuit work synchronously with the first gate driving circuit under preset conditions by arranging the synchronization controller, so that the first display area and the second display area are synchronously displayed.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel. Background Technology

[0002] With the rapid development of display technology, users have increasingly higher demands for the display effect of display panels, and display panels have evolved from regular display panels to irregular display panels. Irregular display panels generally include a first display area and a second display area. The gate driving circuit and the data driving circuit transmit electrical energy through the scan lines and data lines in the display panel to drive the first display area and the second display area to achieve display.

[0003] In practice, the inventors discovered that traditional gate drive circuits have the defect of failing to achieve synchronous display of the first and second display areas, resulting in screen tearing in the first and second display areas. Summary of the Invention

[0004] This application provides a display panel to solve the technical problem in the prior art that the first display area and the second display area of ​​the display panel cannot be displayed synchronously.

[0005] This application provides a display panel having a first display area, a second display area located on one side of the first display area, a first non-display area located on the side of the first display area away from the second display area, and a second non-display area located on the side of the second display area away from the first display area. The first display area has a first size along a first direction, and the second display area has a second size along the first direction. The first size is larger than the second size. The display panel includes:

[0006] m scan lines, wherein the scan lines are located in the first display area and the second display area;

[0007] A first gate driving circuit is located in the first non-display area. The first gate driving circuit is connected to the m scan lines. The first gate driving circuit includes multiple cascaded first driving units. The first driving units sequentially output scan signals to the multiple scan lines along the first direction.

[0008] The second gate driving circuit is located in the second non-display area. The second gate driving circuit is connected to the scan lines from k to m. The second gate driving circuit includes multiple cascaded second driving units. The second driving units output scan signals to the multiple scan lines in sequence along the first direction. k and m are both integers greater than 1, and m is greater than k.

[0009] A synchronization controller is connected to a control signal output terminal, an input terminal of the first-stage second drive unit, and an output terminal of one of the first-stage first drive units to the (k-1)th-stage first drive units.

[0010] In some embodiments provided in this application, the input terminal of the first driving unit at the k-th stage is connected to the output terminal of the first driving unit at the kp-th stage; the synchronization controller is connected to the output terminal of the first driving unit at the kp-th stage; p is an integer greater than or equal to 1, and k is greater than p.

[0011] In some embodiments provided in this application, the synchronization controller includes a switching transistor; the control terminal of the switching transistor is connected to the control signal output terminal, the input terminal of the switching transistor is connected to the output terminal of one of the first-stage first driving unit to the (k-1)th-stage first driving unit, and the output terminal of the switching transistor is connected to the input terminal of the first-stage second driving unit.

[0012] In some embodiments provided in this application, the synchronization controller is connected to the start signal line, and the start signal provided by the start signal line is the control signal provided by the control signal output terminal.

[0013] In some embodiments provided in this application, the m scan lines include k-1 first scan lines and m-k+1 second scan lines; the k-1 first scan lines are connected to the first driving unit of the first stage to the (k-1)th stage first driving unit; the m-k+1 second scan lines are respectively connected to the first driving unit of the kth stage to the first driving unit of the mth stage and the second gate driving circuit.

[0014] In some embodiments provided in this application, the length of the first scan line is less than the length of the second scan line; each of the first driving units from the first stage to the (k-1)th stage includes a first output transistor, and each of the first driving units from the kth stage to the mth stage includes a second output transistor, wherein the size of the first output transistor is greater than the size of the second output transistor.

[0015] In some embodiments provided in this application, each second scan line includes a first sub-scan line and a second sub-scan line that are insulated from each other, and the first sub-scan line and the second sub-scan line are collinear; m-k+1 first sub-scan lines are respectively connected to the first driving unit of the kth level to the first driving unit of the mth level, and m-k+1 second sub-scan lines are connected to the second driving unit of the first level to the second driving unit of the m-k+1th level.

[0016] In some embodiments provided in this application, the first display area includes a first sub-display area and a second sub-display area; wherein, the size of the second sub-display area along the first direction is the same as the size of the second display area along the first direction; the first scan line is disposed in the first sub-display area; the first sub-scan line is disposed in the second sub-display area; and the second sub-scan line is disposed in the second display area.

[0017] In some embodiments provided in this application, the display panel further includes a third gate driving circuit;

[0018] The third gate driving circuit includes multiple cascaded third driving units, which are disposed opposite to the first gate driving circuit and located in the first display area; wherein, the first-level third driving unit to the (k-1)th-level third driving unit are connected to the first scan line; and the k-th-m-th-level third driving unit is connected to the first sub-scan line.

[0019] The length of the first scan line is greater than the length of the second sub-scan line.

[0020] In some embodiments provided in this application, the length of the first scan line and the length of the first sub-scan line are both greater than the length of the second sub-scan line; the first driving unit includes a third output transistor, the second driving unit includes a fourth output transistor, and the size of the third output transistor is greater than the size of the fourth output transistor.

[0021] This application discloses a display panel. By connecting a synchronization controller to the input terminal of the first-stage second driving unit of the second gate driving circuit and the output terminal of one of the first-stage first driving units to the (k-1)th stage first driving units of the first gate driving circuit, the synchronization controller provides the output signal of one of the first-stage first driving units to the input terminal of the first-stage second driving unit. The first-stage second driving unit operates in response to the signal provided by the output terminal of the first driving unit connected to the synchronization controller. Simultaneously, since the multiple stages of first driving units are cascaded, the output signal of one of the first-stage first driving units to the (k-1)th stage first driving units is also provided to the input terminal of the next-stage first driving unit. Thus, the next-stage first driving unit operates in response to the signal provided by the output terminal of the first driving unit connected to the synchronization controller. Therefore, by setting a synchronization controller, this application can control the first-stage second driving unit and the corresponding first driving unit to operate synchronously under the control of the control signal provided by the control signal output terminal, achieving synchronous display of the first display area and the second display area. Attached Figure Description

[0022] Figure 1 This is a top view of a display panel in the prior art;

[0023] Figure 2 This is a first top view of the display panel provided in an embodiment of this application;

[0024] Figure 3 for Figure 2 A schematic diagram of a first specific structure of the display panel is shown;

[0025] Figure 4 A schematic diagram of a circuit structure of a driving unit provided in an embodiment of this application;

[0026] Figure 5 for Figure 2 A schematic diagram of a second specific structure of the display panel is shown;

[0027] Figure 6 for Figure 2 A schematic diagram of a third specific structure of the display panel is shown;

[0028] Figure 7 for Figure 2 A schematic diagram of a fourth specific structure of the display panel is shown;

[0029] Figure 8 This is a second top view of the display panel provided in an embodiment of this application;

[0030] Figure 9 This is a third top view of the display panel provided in an embodiment of this application;

[0031] Figure 10 This is a fourth top view of the display panel provided in an embodiment of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] Furthermore, the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0034] Figure 1This is a top view of a display panel in the prior art. For example... Figure 1 As shown, for a display panel with an irregularly shaped display area including a first display area and a second display area, the first display area 031 and the second display area 032 are arranged sequentially along the X direction, and the length of the first display area 031 in the Y direction is greater than the length of the second display area 032 in the Y direction, wherein the Y direction is perpendicular to the X direction. The display panel has a gate driving circuit 02 disposed on the side of the first display area 031 away from the second display area 032, or on the side of the second display area 032 away from the first display area 031. The display panel can also have a data driving circuit 01 and a gate driving circuit 02 disposed on opposite sides; for example, the data driving circuit 01 can be along the extension direction of the scan line, i.e. Figure 1 The data drive circuit 01 in the middle can be set along the X direction.

[0035] When the gate drive circuit 02 transmits the driving voltage to the display area 03 through the scan lines, since the length of the display area 03 in the X direction is not uniform, the lengths of the scan lines Scan01 and Scan02 extending from the gate drive circuit 02 to the display area 03 are not the same. Therefore, the impedances of the scan lines Scan01 and Scan02 are different, and the impedance of the scan line Scan02 is greater than that of the scan line Scan01. As a result, the time taken for one scan line Scan01 and one scan line Scan02 to complete one line of scanning is not the same, causing the display area 03 to experience screen refresh asynchrony.

[0036] To address this problem, embodiments of the present invention provide a display panel, please refer to... Figure 2 , Figure 2 This is a top view of a display panel provided in an embodiment of this application. Figure 2 As shown, the display panel 100 has a first display area AA1, a second display area AA2, a first non-display area NA1, and a second non-display area NA2.

[0037] The second display area AA2 is located to one side of the first display area AA1. The first non-display area NA1 is located on the side of the first display area AA1 away from the second display area AA2. The second non-display area NA2 is located on the side of the second display area AA2 away from the first display area AA1.

[0038] It should be understood that the first display area AA1 and the second display area AA2 are sub-regions of the display area of ​​the display panel 100 in this embodiment. Therefore, the first non-display area NA1 and the second non-display area NA2 can be located on opposite sides of the display area. The first non-display area NA1 and the second non-display area NA2 are non-display areas other than the display area in the display panel in this embodiment.

[0039] The first display area AA1 has a first dimension along a first direction, and the second display area AA2 has a second dimension along the first direction, with the first dimension being larger than the second dimension. In other words, the length of the first display area AA1 along the direction of the scan lines S1 is greater than the length of the second display area AA2 along the direction of the scan lines S1. Therefore, the display area formed by the first display area AA1 and the second display area AA2 is an irregular shape.

[0040] Specifically, the display panel 100 includes m scan lines, a first gate driving circuit 10, a second gate driving circuit 20, and a synchronization controller 30.

[0041] Among them, m scan lines S1 are located in the display area, that is, m scan lines S1 are located in the first display area AA1 and the second display area AA2.

[0042] The first gate driving circuit 10 is located in the first non-display area NA1. The first gate driving circuit 10 is used to scan the pixels of the display area line by line. The first gate driving circuit 10 is connected to the first scan line S1 to the m-th scan line S1.

[0043] The second gate driving circuit 20 is located in the second non-display area NA2. The second gate driving circuit 20 is used to scan the pixels of the display area line by line. Furthermore, the second gate driving circuit 20 is connected to the k-th scan line S1 to the m-th scan line S1.

[0044] It is worth mentioning that k and m are both integers greater than 1, and m is greater than k. The gate driving circuit in this embodiment is also the array substrate row driving circuit (Gate-driver On Array, GOA).

[0045] The synchronous controller 30 is connected to the first gate drive circuit 10 and the second gate drive circuit 20 respectively via control signal output terminals.

[0046] For details, please refer to Figure 3 , Figure 3 for Figure 2 A schematic diagram illustrating a specific structure of a display panel is shown. For example... Figure 3 As shown, the first gate driving circuit 10 includes multiple cascaded first driving units GA, and the second gate driving circuit 20 includes multiple cascaded second driving units GB.

[0047] It should be understood that cascading configuration refers to connecting a specific signal terminal of the upper-level drive unit to the input terminal of the lower-level drive unit, so that the signal of the upper-level drive unit serves as the drive signal of the lower-level drive unit, that is, the lower-level drive unit will respond to the signal of the upper-level drive unit to perform normal operation.

[0048] In this configuration, one first driving unit GA is connected to one scan line S1, and one scan line S1 controls the opening of a row of pixels to allow data signals to be written to that row of pixels. That is, the first scan line S1 to the m-th scan line S1 can be connected one-to-one with multiple cascaded first driving units GA. For example, the first scan line S1 is connected to the first-level first driving unit GA_1, the second scan line S1 is connected to the second-level first driving unit GA_2, and so on, with the (m-1)-th scan line S1 connected to the (m-1)-th level first driving unit GA_m-1, and the m-th scan line S1 connected to the m-th level first driving unit GA_m.

[0049] In this configuration, one second driving unit GB is connected to one of the scan lines from k to m. That is, scan lines S1 from k to m can be connected one-to-one with multiple cascaded second driving units GB. For example, scan line S1 is connected to the first-level second driving unit GB_1, scan line S1 (k+1) is connected to the second-level second driving unit GB_2, and so on, with scan line S1 (m-1) connected to the mk-th level second driving unit GB_m-k, and scan line S1 (m-k+1) connected to the m-k+1-th level second driving unit GB_m-k+1.

[0050] In this embodiment, the first driving unit GA sequentially outputs scan signals to multiple scan lines S1 along a first direction, and the second driving unit GB sequentially outputs scan signals to multiple scan lines S1 along the first direction. That is, the first gate driving circuit 10 and the second gate driving circuit 20 are gate driving circuits that scan in the same direction. In this embodiment, the first direction is the arrangement direction of the multiple scan lines S1, i.e. Figure 2 , Figure 3 The Y direction is shown in the figure.

[0051] Since the length of the second display area AA2 in the first direction is less than the length of the first display area AA1 in the first direction, the opening area NA21, the first display area AA1, and the second display area AA2 together form a regular shape, such as a rectangle.

[0052] It is worth mentioning that, although Figure 3 The opening region NA21 shown is irregular in shape, but this is only for illustration. In other embodiments of this application, the opening region NA21 may also be a regular rectangle or other shapes.

[0053] Specifically, the synchronous controller 30 is connected to the control signal output terminal, the input terminal of the first-stage second drive unit GB_1, and the output terminal of one of the first-stage first drive units GA_1 to the (k-1)th-stage first drive units GA_k-1.

[0054] Specifically, under the control of the signal provided at the control signal output terminal, the synchronization controller 30 enables the input terminal of the first-stage second drive unit GB_1 to start working after receiving the signal provided by the output terminal of one of the first-stage first drive units GA_1 to k-1th-stage first drive units GA_k-1. Simultaneously, one of the first-stage first drive units GA_1 to k-1th-stage first drive units GA_k-1 also transmits the signal provided by its output terminal to the connected lower-level first drive unit GA. The input terminal of the lower-level first drive unit GA_k starts working after receiving the scan signal provided by the output terminal of one of the first-stage first drive units GA_1 to k-1th-stage first drive units GA_k-1. Therefore, the synchronization controller 30 enables the first-stage second drive unit GB_1 to work synchronously with the corresponding first drive unit GA.

[0055] In some embodiments provided in this application, the input terminal of the k-th stage first drive unit GA_k is connected to the output terminal of the kp-th stage first drive unit GA_k-p. The synchronization controller 30 is connected to the output terminal of the kp-th stage first drive unit GA_k-p, the control signal output terminal, and the input terminal of the first stage second drive unit GB_1. Furthermore, p and k are both integers greater than or equal to 1, and k is greater than p.

[0056] In other words, in the display panel provided in this embodiment, the input terminal of the k-th stage first driving unit GA_k starts working after receiving the scan signal provided by the output terminal of the kp-th stage first driving unit GA_k-p. Simultaneously, the synchronization controller 30 causes the input terminal of the first stage second driving unit GB_1 to also start working after receiving the scan signal provided by the output terminal of the kp-th stage first driving unit GA_k-p. Therefore, the synchronization controller 30 enables the first stage second driving unit GB_1 to work synchronously with the k-th stage first driving unit GA_k.

[0057] Meanwhile, in the second gate driving circuit 20, the input terminal of the nth stage second driving unit GB_n is connected to the output terminal of the npth stage second driving unit GB_n-p, and the output terminal of the nth stage second driving unit GB_n is connected to the input terminal of the (n+p)th stage second driving unit GB_n+p. Wherein, n is greater than or equal to 1, n is less than or equal to n-k+1, and n is greater than p.

[0058] The scan line S1 connected to the k-th level first driving unit GA_k and the scan line S1 connected to the first level second driving unit GB_1 drive the same row of pixels to emit light in the display area. That is, the k-th row of pixels in the first display area AA1 is collinear with the first row of pixels in the second display area AA2. Therefore, under the control of the synchronization controller 30, the same row of pixels can be displayed synchronously in the second display area AA2 and the first display area AA1. Thus, when the display screen of the display panel in this embodiment is switched, the refresh timing of the first display area AA1 and the second display area AA2 will not be out of sync, thereby avoiding the defect of screen tearing in the first display area AA1 and the second display area AA2.

[0059] For details, please continue reading. Figure 3 ,like Figure 3 As shown, in the first gate driving circuit 10, the output terminal of the k-th stage first driving unit GA_k is connected to the input terminal of the (k+1)-th stage first driving unit GA_k+1, and the output terminal of the (k+1)-th stage first driving unit GA_k+1 is connected to the input terminal of the (k+2)-th stage first driving unit GA_k+2, that is... Figure 3 The diagram illustrates the specific connection structure between cascaded multi-stage first drive units (GAs) when p is 1.

[0060] For details, please continue reading. Figure 3 ,like Figure 3 As shown, for the second gate drive circuit 20, the output terminal of the first stage second drive unit GB_1 is connected to the input terminal of the second stage second drive unit GB_2, the output terminal of the second stage second drive unit GB_2 is connected to the input terminal of the third stage second drive unit GB_3, and so on, the output terminal of the mk-th stage second drive unit GB_m-k is connected to the input terminal of the m-k+1-th stage second drive unit GB_m-k+1.

[0061] It should be understood that Figure 3 The cascading structure shown should not be considered a limitation of this embodiment. In other embodiments provided in this application, the value of p can also be an integer greater than or equal to 2.

[0062] For details, please continue reading. Figure 3 ,like Figure 3 As shown, the m scan lines S1 include k-1 first scan lines S11 and m-k+1 second scan lines S12.

[0063] Among them, k-1 first scan lines S11 are connected to the first-stage first driving unit GA_1 to the (k-1)th stage first driving unit GA_k-1. That is, k-1 first scan lines S11 are connected one-to-one with the first-stage first driving unit GA_1 to the (k-1)th stage first driving unit GA_k-1.

[0064] It should be understood that, based on the connection relationship between the k-1 first scan lines S11 and the first-level first driving unit GA_1 to the k-1th first driving unit GA_k-1, the first gate driving circuit 10 provides single-sided driving for the first row of pixels to the k-1th row of pixels in the display area.

[0065] Among them, m-k+1 second scan lines S12 are respectively connected to the k-th stage first driving unit GA_k to the m-th stage first GOA unit GA_m and the second gate driving circuit 20. That is, one end of any second scan line S12 is connected to one of the k-th stage first driving unit GA_k to the m-th stage first GOA unit GA_m, and the other end of the second scan line S12 is connected to one of the first stage second driving unit GB_1 to the m-k+1 stage second driving unit GB_m-k+1.

[0066] It should be understood that, based on the connection relationship between the m-k+1 second scan lines S12 and the k-th level first driving unit GA_k to the m-th level first GOA unit GA_m and the second gate driving circuit 20, the first gate driving circuit 10 and the second gate driving circuit 20 provide bilateral driving for the k-th row pixels to the m-th row pixels of the display area.

[0067] It is worth mentioning that both the first driving unit GA and the second driving unit GB have a driving architecture consisting of at least four transistors and one capacitor (4T1C). For details, please refer to [link / reference needed]. Figure 4 , Figure 4 This is a schematic diagram of a circuit structure for a driving unit provided in an embodiment of this application. For example... Figure 4 As shown, the driving unit includes at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a storage capacitor C.

[0068] The gate and source of the first transistor T1 are connected to the output of the previous driving unit G(kp), and the drain of the first transistor T1 is connected to the pull-up node Q.

[0069] In this configuration, the gate of the second transistor T2 is connected to the pull-down node P, the source of the second transistor T2 is connected to the power supply terminal VSS, and the drain of the second transistor T2 is connected to the pull-up node Q.

[0070] In this circuit, the gate of the third transistor T3 is connected to the pull-down node P, the source of the third transistor T3 is connected to the power supply terminal VSS, and the drain of the third transistor T3 is connected to the output terminal of this stage.

[0071] In this circuit, the gate of the fourth transistor T4 is connected to the pull-up node Q, the source of the fourth transistor T4 is connected to the clock signal terminal CLK, and the drain of the fourth transistor T4 is connected to the output terminal of this stage.

[0072] The first terminal of the storage capacitor C is connected to the gate of the fourth transistor T4, and the second terminal of the storage capacitor C is connected to the drain of the fourth transistor T4.

[0073] The pull-down node P is connected to the output of the next-level drive unit G(k+p).

[0074] Specifically, the first transistor T1 is a charging transistor that precharges the storage capacitor C. The first transistor T1 is turned on based on the pulse signal provided by the output of the previous driving unit G(kp) to precharge the pull-up node Q, that is, to precharge the first end of the storage capacitor C.

[0075] Specifically, the fourth transistor T4 is an output transistor. The fourth transistor T4 is in an on or off state according to the level of the pull-up node Q, so as to control the output terminal of this stage to output the pulse signal.

[0076] Specifically, the second transistor T2 and the third transistor T3 are reset transistors. The pulse signal provided by the output terminal of the next stage driving unit G(k+p) is used as the reset signal input to the pull-down node P, which turns on the second transistor T2 and the third transistor T3. The turned-on second transistor T2 discharges to the pull-up node Q, and the turned-on third transistor T3 discharges to the output terminal output of this stage.

[0077] Based on the aforementioned 4T1C driving circuit, it is known that the conduction rate of the output transistor directly affects the time required for the current driving unit to complete the scan. Therefore, in some embodiments provided in this application, when the length of the first scan line S11 is different from the length of the second scan line S12, the output transistors of each stage of the first driving unit GA are different.

[0078] Specifically, each of the first-stage first driving units GA_1 to the (k-1)th-stage first driving unit GA_k-1 includes a first output transistor, and each of the k-th-stage first driving units GA_k to the m-th-stage first driving unit GA_m includes a second output transistor. Furthermore, the size of the first output transistor is larger than the size of the second output transistor. In this way, by relatively increasing the size of the first output transistor, the scanning rate of the first scan line S11 is increased, and the driving pressure of driving the first scan line S11 on one side is reduced.

[0079] It is worth mentioning that the length direction of scan line S1 refers to the extension direction of scan line S1, that is... Figure 3 The X direction is shown.

[0080] Please refer to some embodiments provided in this application. Figure 5 , Figure 5 for Figure 2 A schematic diagram of a second specific structure of the display panel is shown. (See diagram for example.) Figure 5 As shown, the difference between this embodiment and the previous embodiment is that the synchronous controller 30 includes a switching transistor NTAB. The control terminal of the switching transistor NTAB is connected to the control signal output terminal, the input terminal of the switching transistor NTAB is connected to the output terminal of one of the first-stage first drive units GA_1 to the (k-1)th-stage first drive units GA_k-1, and the output terminal of the switching transistor NTAB is connected to the input terminal of the first-stage second drive unit GB_1.

[0081] In this embodiment, the switching transistor NTAB is in the ON state based on the signal provided by the control signal output terminal, outputting the scan signal provided by the output terminal of one of the first-stage first driving units GA_1 to GA_k-1 of the (k-1)th stage first driving units to the input terminal of the first-stage second driving unit GB_1. Thus, the first-stage second driving unit GB_1 is in the OFF state, scanning the corresponding pixel row through the scan line S1 connected to the first-stage second driving unit GB_1. When the switching transistor NTAB is in the OFF state based on the signal provided by the control signal output terminal, the first-stage second driving unit GB_1 is not in the OFF state.

[0082] Specifically, when the switching transistor NTAB is an N-type transistor, the first-stage second driving unit GB_1 is in operation based on a high-level signal provided by the control signal output terminal. When the switching transistor NTAB is a P-type transistor, the first-stage second driving unit GB_1 is in operation based on a low-level signal provided by the control signal output terminal.

[0083] In other embodiments provided in this application, please refer to Figure 6 , Figure 6 for Figure 2 A schematic diagram of a third specific structure of the display panel is shown. (See diagram for example.) Figure 6 As shown, the synchronous controller 30 may include an AND gate. The first input of the AND gate is connected to the control signal output, the second input of the AND gate is connected to the output of one of the first-stage first drive units GA_1 to the (k-1)th-stage first drive units GA_k-1, and the output of the AND gate is connected to the input of the first-stage second drive unit GB_1.

[0084] Specifically, when the first level is the start signal for the first-stage second driving unit GB_1 to be in working state, if the signal provided by the control signal output terminal is a first-level signal, and the signal provided by the output terminal of one of the first-stage first driving units GA_1 to the (k-1)th-stage first driving units GA_k-1 is a second-level signal, then the output terminal of the AND gate is a second-level signal. If the signal provided by the control signal output terminal is a first-level signal, and the signal provided by the output terminal of one of the first-stage first driving units GA_1 to the (k-1)th-stage first driving units GA_k-1 is also a first-level signal, then the output terminal of the AND gate is a first-level signal, and the first-stage second driving unit GB_1 is in working state, that is, the signal provided by the output terminal of one of the first-stage first driving units GA_1 to the (k-1)th-stage first driving units GA_k-1 is transmitted to the input terminal of the first-stage second driving unit GB_1. If the signal provided by the control signal output terminal is a second level signal, then regardless of whether the signal provided by the output terminal of one of the first-stage first driving unit GA_1 to the (k-1)th-stage first driving unit GA_k-1 is a first level signal or a second level signal, the output terminal of the AND gate is a second level signal, that is, the first-stage second driving unit GB_1 is not in working state.

[0085] It should be understood that the first level signal is different from the second level signal. When the first level signal is either a high level signal or a low level signal, the second level signal is either a high level signal or a low level signal.

[0086] Please refer to some embodiments provided in this application. Figure 7 , Figure 7 for Figure 2 A schematic diagram of a fourth specific structure of the display panel is shown. (See diagram.) Figure 7 As shown, the display panel also includes a start signal line STV1 and a start signal line STV2. The start signal line STV1 is connected to the input terminal of the first-stage first driving unit GA_1 of the first gate driving circuit 10, so that the first-stage first driving unit GA_1 starts working under the control of the start signal provided by the start signal line STV1. The start signal line STV2 is connected to the synchronization controller 30, so that the first-stage second driving unit GB_1 starts working under the control of the start signal provided by the start signal line STV2. That is, in this embodiment, the start signal provided by the start signal line STV2 is a control signal provided by the control signal output terminal.

[0087] Please refer to some embodiments provided in this application. Figure 8 , Figure 8 This is a second top view of the display panel provided in an embodiment of this application. (See attached image.) Figure 8As shown, the difference between this embodiment and the previous embodiment is that in the display panel 100 provided in this embodiment, each second scan line S12 includes a first sub-scan line S121 and a second sub-scan line S122 that are insulated from each other. The first sub-scan line S121 and the second sub-scan line S122 are collinear.

[0088] In other words, the first sub-scan line S121 and the second sub-scan line S122 in each second scan line S12 scan the same row of pixels in the display area. For example, the first sub-scan line S121 and the first second sub-scan line S122 scan the k-th row of pixels in the display area.

[0089] It is worth mentioning that, since the first sub-scan line S121 and the second sub-scan line S122 are insulated, the first gate driving circuit 10 drives the first row of pixels to the nth row of pixels in the display area on one side, and the second gate driving circuit 20 drives the kth row of pixels to the nth row of pixels in the display area on one side. The synchronous controller 30 is configured so that pixels in the same row are scanned synchronously in the first display area AA1 and the second display area AA2, that is, the second display area AA2 and the first display area AA1 can be displayed synchronously. Therefore, when the display screen of the display panel 100 in this embodiment is switched, there will be no problem of asynchronous refresh timing of the first display area AA1 and the second display area AA2, thus avoiding the problem of screen tearing in the first display area AA1 and the second display area AA2 that is perceived by the user.

[0090] Specifically, when the lengths of the first scan line S11 and the first sub-scan line S121 are both greater than the length of the second sub-scan line S122, the impedances of the first scan line S11 and the first sub-scan line S121 are both greater than the impedance of the second sub-scan line S122. To achieve synchronous display of the first display area AA1 and the second display area AA2, a third output transistor can be set in each first driving unit GA, and a fourth output transistor can be set in each second driving unit GB. The size of the third output transistor is larger than the size of the fourth output transistor, thereby making the driving capability of the first gate driving circuit 10 stronger than that of the second gate driving circuit 20, and thus reducing the driving delay caused by the impedance difference between the first scan line S11, the first sub-scan line S121, and the second sub-scan line S122.

[0091] Specifically, the length of the first scan line S11 can be the same as the length of the first sub-scan line S121, and the length of the first scan line S11 is greater than the length of the second sub-scan line S122. In this way, the impedance of the first scan line S11 is the same as the impedance of the first sub-scan line S121, thus the driving capability of the third output transistor for the first scan line S11 is comparable to that for the first sub-scan line S121, avoiding driving delay caused by the impedance difference between the first scan line S11 and the first sub-scan line S121.

[0092] Please refer to some embodiments provided in this application. Figure 9 , Figure 9 This is a third top view of the display panel provided in an embodiment of this application. (See attached image.) Figure 9 As shown, the difference between this embodiment and the previous embodiment is that in the display panel 100 provided in this embodiment, the first display area AA1 includes a first sub-display area AA11 and a second sub-display area AA12.

[0093] The dimensions of the second sub-display area AA12 along the first direction are the same as those of the second display area AA2 along the first direction. The first scan line S11 is located in the first sub-display area AA11, the first sub-scan line S121 is located in the second sub-display area AA12, and the second sub-scan line S122 is located in the second display area AA2.

[0094] It should be understood that the first direction refers to the arrangement direction of the scan lines S1, that is... Figure 9 As shown in the Y direction, the second sub-display area AA12 and the second display area AA2 together form a rectangular display area.

[0095] It is worth noting that the dimensions of the first sub-display area AA11 along the X direction can be the same as or different from those of the second sub-display area AA12 along the X direction. In other words, the length of the first scan line S11 can be the same as or different from the length of the first sub-scan line S121. If the dimensions of the first sub-display area AA11 along the X direction are the same as those of the second sub-display area AA12 along the X direction, then the first display area AA1 is a rectangular display area. If the dimensions of the first sub-display area AA11 along the X direction are different from those of the second sub-display area AA12 along the X direction, then the first display area AA1 is an irregularly shaped display area.

[0096] Please refer to some embodiments provided in this application. Figure 10 , Figure 10 This is a fourth top view of the display panel provided in an embodiment of this application. (See attached image.) Figure 10 As shown, the difference between this embodiment and the previous embodiment is that the display panel 100 provided in this embodiment also includes a third gate driving circuit 40.

[0097] The third gate driving circuit 40 includes a cascaded multi-stage third driving unit GC. The third gate driving circuit 40 is disposed opposite to the first gate driving circuit 10, and is located in the first display area AA1.

[0098] Among them, the first-level third driving unit GC_1 to the (k-1)th-level third driving unit GC_k-1 are connected to the first scan line S11, and the k-th-level third driving unit GC_k to the m-th-level third driving unit GC_m are connected to the first sub-scan line S121.

[0099] Among them, the length of the first scan line S11 is greater than the length of the second sub-scan line S122, and the length of the first sub-scan line S121 is greater than the length of the second sub-scan line S122.

[0100] In this embodiment, by setting the third gate driving circuit 40 within the first display area AA1, the first scan line S11 and the first sub-scan line S121 can be driven on both sides, thereby avoiding the problem of poor driving capability on the side of the first display area AA1 closer to the second display AA2 caused by the first gate driving circuit 10 driving on one side, and further avoiding the display difference problem caused by the difference in driving capability.

[0101] It is worth mentioning that, in this embodiment, the length of the first scan line S11 can be greater than the length of the first sub-scan line S121, the length of the first scan line S11 can be less than the length of the first sub-scan line S121, and the length of the first scan line S11 can be equal to the length of the first sub-scan line S121.

[0102] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display panel, characterized by, The display panel has a first display area, a second display area located on one side of the first display area, a first non-display area located on the side of the first display area away from the second display area, and a second non-display area located on the side of the second display area away from the first display area. The first display area has a first size along a first direction, and the second display area has a second size along the first direction. The first size is greater than the second size. The display panel comprises: m scan lines located in the first display area and the second display area; a first gate drive circuit located in the first non-display area, connected with the m scan lines, comprising a plurality of cascaded first drive units, which sequentially output scan signals to the plurality of scan lines along the first direction; a second gate drive circuit located in the second non-display area, connected with the kth to mth scan lines, comprising a plurality of cascaded second drive units, which sequentially output scan signals to the plurality of scan lines along the first direction, k and m are integers greater than 1, and m is greater than k; a synchronization controller connected with a control signal output end, an input end of the first second drive unit, and an output end of one of the first first drive unit to the k-1 first drive unit.

2. The display panel of claim 1, wherein, The input end of the kth first drive unit is connected with the output end of the k-p first drive unit; The synchronization controller is connected with the output end of the k-p first drive unit, p is an integer greater than or equal to 1, and k is greater than p.

3. The display panel of claim 1, wherein, The synchronization controller comprises a switch tube; The control end of the switch tube is connected with the control signal output end, the input end of the switch tube is connected with the output end of one of the first first drive unit to the k-1 first drive unit, and the output end of the switch tube is connected with the input end of the first second drive unit.

4. The display panel of claim 1, wherein, The synchronization controller is connected with a start signal line, and a start signal provided by the start signal line provides a control signal for the control signal output end.

5. The display panel of claim 1, wherein, The m scan lines comprise k-1 first scan lines and m-k+1 second scan lines; The k-1 first scan lines are connected with the first first drive unit to the k-1 first drive unit; The m-k+1 second scan lines are respectively connected with the kth first drive unit to the mth first drive unit and the second gate drive circuit.

6. The display panel of claim 5, wherein, The length of the first scan line is less than the length of the second scan line; The first first drive unit to the k-1 first drive unit each comprises a first output transistor, and the kth first drive unit to the mth first drive unit each comprises a second output transistor. The size of the first output transistor is greater than the size of the second output transistor.

7. The display panel of claim 5, wherein, Each of the second scan lines comprises a first sub-scan line and a second sub-scan line which are arranged in an insulating manner, and the first sub-scan line and the second sub-scan line are collinear.

8. The display panel of claim 7, wherein, The first display area comprises a first sub-display area and a second sub-display area; wherein, The size of the second sub-display area along the first direction is the same as the size of the second display area along the first direction; The first scan line is arranged in the first sub-display area; The first sub-scan line is arranged in the second sub-display area; The second sub-scan line is arranged in the second display area.

9. The display panel of claim 8, wherein, The display panel further comprises a third gate drive circuit; The third gate drive circuit comprises a plurality of third drive units arranged in cascade, the third gate drive circuit is arranged opposite to the first gate drive circuit, and the third gate drive circuit is located in the first display area; wherein, The first to k-1th third drive units are connected with the first scan line, and the kth to mth third drive units are connected with the first sub-scan line; The length of the first scan line is greater than the length of the second sub-scan line, and the length of the first sub-scan line is greater than the length of the second sub-scan line.

10. The display panel of claim 7, wherein, The length of the first scan line and the length of the first sub-scan line are both greater than the length of the second sub-scan line; The first drive unit comprises a third output transistor, and the second drive unit comprises a fourth output transistor, and the size of the third output transistor is greater than the size of the fourth output transistor.

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