Differential content addressable memory array and sensing circuit

Abstract

Embodiments of the present disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learned storage memory. The analog output of the differentiable CAM can provide input to a learning algorithm that can compute gradients in comparison to historical values and reduce data inaccuracies and power consumption.

Description

TECHNICAL FIELD

[0001] The present disclosure generally designs a differentiable content addressable memory. BACKGROUND

[0002] A content addressable memory (CAM) is a type of computing memory in which stored data is accessed not by its location but by its content. A word or "tag" is input to the CAM, and the CAM searches its content for the tag. When found, the CAM returns the address of the location where the found content resides. CAMs are powerful, efficient, and fast. However, CAMs are also relatively large, consume a large amount of power, and are relatively expensive. These drawbacks limit their applicability, making them only useful in applications where their power, efficiency, and speed are all sufficient to outweigh their size, cost, and power consumption. SUMMARY

[0003] According to an aspect of the present disclosure, a differentiable content addressable memory (dCAM) array is provided, comprising: a plurality of rows and a plurality of columns of dCAM cells, wherein each row of dCAM cells comprises a high match line and a low match line; a sense circuit electrically connected to the high match line and the low match line, wherein the sense circuit comprises: a transimpedance amplifier (TIA) configured to sense a match line current on the low match line, and an analog-to-digital converter (ADC) configured to sense an output voltage of the TIA and a match line voltage of the high match line; and a digital-to-analog converter (DAC) electrically connected to each column of dCAM cells.

[0004] According to another aspect of the present disclosure, a sense circuit is provided, comprising: a training component comprising: an analog-to-digital converter (ADC) electrically connected to a transimpedance amplifier (TIA), wherein the ADC is electrically connected to a first match line, wherein the TIA is electrically connected to a second match line, wherein the TIA is configured to sense a current of the second match line and return an output voltage to the ADC, and wherein the ADC is configured to sense the output voltage of the TIA and a first match line voltage of the first match line; and an operational component comprising: a sense amplifier electrically connected to the first match line, wherein the sense amplifier is configured to sense the first match line voltage and a sense voltage during a training operation.

[0005] According to another aspect of the disclosure, a method for training a differential content addressable memory, dCAM, model is provided, comprising: sensing, by a transimpedance amplifier, TIA, a current of a second match line of a sensing circuit, the sensing circuit comprising an analog-to-digital converter, ADC, electrically connected to the TIA, wherein the ADC is electrically connected to a first match line and the TIA is electrically connected to the second match line; converting, by the TIA, the current to an output voltage; sensing, by the ADC, the output voltage and a first match line voltage of the first match line from the TIA; sensing, by a sense amplifier of the sensing circuit, the first match line voltage and a sense voltage; and training the dCAM model based on the output voltage and the sense voltage. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure is described in detail with reference to one or more various embodiments. The drawings are provided for purposes of illustration only and merely depict typical or example embodiments.

[0007] Figure 1 An analog content addressable memory (“analog CAM”) according to example embodiments described herein is conceptually depicted.

[0008] Figure 2 A selected portion of an analog cell array of an aCAM according to example embodiments described herein is illustrated.

[0009] Figure 3 A resistive differential according to example embodiments described herein is conceptually illustrated.

[0010] Figure 4 Electronic circuitry implementing an aCAM cell according to example embodiments described herein is depicted.

[0011] Figure 5 Electronic circuitry implementing an aCAM cell according to example embodiments described herein is depicted.

[0012] Figure 6 Electronic circuitry implementing an aCAM cell according to example embodiments described herein is depicted.

[0013] Figure 7 A search operation on an aCAM cell according to example embodiments described herein is depicted.

[0014] Figure 8 A high-level implementation of a memristor-based aCAM according to example embodiments described herein is shown.

[0015] Figure 9 A data structure for encoding values with an aCAM according to example embodiments described herein is illustrated.

[0016] Figure 10 A data structure for encoding values with aCAM is illustrated in accordance with example embodiments described herein.

[0017] Figure 11 A data structure for encoding values with aCAM is illustrated in accordance with example embodiments described herein.

[0018] Figure 12 A target analog voltage range is illustrated in accordance with example embodiments described herein.

[0019] Figure 13 A flow diagram depicting converting a decision tree to a table structure is illustrated in accordance with example embodiments described herein.

[0020] Figure 14 Encoding of a node chain set is illustrated in accordance with example embodiments described herein.

[0021] Figure 15 An electronic circuit for implementing a differentiable CAM cell that can be used to implement any of the CAM cells described herein is depicted.

[0022] Figure 16 A selected portion of a cell array of a differentiable CAM cell is illustrated in accordance with example embodiments described herein.

[0023] Figure 17 A sense amplifier block of a differentiable CAM cell is illustrated in accordance with example embodiments described herein.

[0024] Figure 18 An overview of an illustrative learn-to-store (L2S) process implemented by a differentiable CAM array is provided in accordance with example embodiments described herein.

[0025] Figure 19 An illustrative learn-to-store (LS2) process implemented by a differentiable CAM array is provided in accordance with example embodiments described herein.

[0026] Figure 20 Resilience to memristor noise comparisons is illustrated in accordance with example embodiments described herein.

[0027] Figure 21 A set of executable instructions stored in a machine-readable storage medium that, when executed, cause one or more hardware processors to perform an illustrative method for providing a differentiable CAM that improves upon analog CAM systems by implementing an analog input analog storage and analog output learning memory is depicted.

[0028] Figure 22 are example computing components that can be used in the example embodiments of the present application to implement various features.

[0029] The accompanying drawings are not exclusively exhaustive and do not restrict the present disclosure to the precise form disclosed. DETAILED DESCRIPTION

[0030] Content addressable memory ("CAM") is hardware that compares an input pattern to its stored data. The memory storing data in a CAM also performs search operations at the same location, eliminating expensive data transfers between different cells in conventional hardware. During a search, all memory cells operate in parallel, which results in a huge throughput for applications such as real-time network traffic monitoring, access control lists ("ACLs"), associative memories, etc.

[0031] CAMs can be implemented in technologies that allow the CAM to retain its contents in the event of power loss or the power otherwise being removed. Thus, data stored in a CAM can persist and can act as a so-called "non-volatile memory." These technologies include, for example, resistive switching memory (i.e., memristors), phase change memory, magnetoresistive memory, ferroelectric memory, some other resistive random access memory device, or a combination of these technologies.

[0032] CAMs can be classified as "binary" or "ternary." Binary CAMs ("BCAMs") operate on input patterns containing binary bits of zero and one. Ternary CAMs ("TCAMs") operate on (and store data for) input patterns containing not only binary bits of zero and one, but also "X" values. An "X" is sometimes referred to as a "wildcard" or "wildcard." In a search of input patterns in a TCAM, an "X" will return a match to either a zero bit or a one bit. Thus, a search for the input pattern "10X1" will return a match to both "1001" and "1011." Note that both BCAMs and TCAMS use and operate on binary values of zero and one. CAMs are digital in that data is stored in the CAM as binary values in memory (e.g., SRAM, memristors, etc.) and input patterns are represented by zeros and ones. Each memory cell in a CAM handles one value (0 / 1 or 0 / 1 / X) at a time, which limits memory density and power efficiency.

[0033] The present disclosure provides an analog CAM ("aCAM") circuit that searches for a multi-level voltage and stores an analog value in a non-volatile memory (e.g., a memristor). One analog cell can implement equivalent functionality to multiple digital CAM cells, resulting in significant advantages in area and power savings when implementing certain CAM-based functions. The aCAM circuit can be driven with standard multi-level digital values or directly with an analog signal, resulting in additional potential for increased functionality while eliminating the need for expensive analog-to-digital conversion. More particularly, when an analog input voltage matches a target analog voltage range defined by the aCAM cell, the aCAM cell outputs a match.

[0034] In some examples, the aCAM can be programmed to match all values between a "high value" and a "low value" or within a target analog voltage range, where the range includes non-binary values. These high and low values are set by programming the memristor and are therefore referred to herein as "R 高 " and "R 低 ", respectively. R 高 and R 低 set the bounds of the range of values that can be stored in the cell, such that the cell can store an analog value. The memory cell in the aCAM can store any value between the value defined by R 高 and the value defined by R 低 . As in a ternary CAM, if R 高 = R 最大 , where R 最大 is the maximum resistance of the memristor, and R 低 = R 最小 , where R 最小 is the minimum resistance of the memristor, then the stored value is "X". The number of equivalent digital cells or bits that can be stored in an analog CAM cell depends on the number of states that the programmable resistor can be programmed to. To be able to encode n bits of equivalent content (i.e., n binary CAM / TCAM cells), the programmable resistor has 2n+1 states.

[0035] A memristor-based aCAM can search for an analog voltage and store an analog value (or a digital value) as falling within R 低 and R 高values between. One example of an aCAM includes a plurality of cells arranged in rows and columns. Each cell performs two analog comparisons: a "greater than" and a "less than" performed simultaneously on a searched data line (DL) voltage, with significantly reduced processing time and energy consumption compared to its digital counterpart. In various examples, the aCAM can be driven with standard multi-level digital values or directly with analog signals. This provides additional potential for increased functionality when eliminating the need for expensive analog-to-digital conversion. The significant power savings of the proposed memristor aCAM enables CAM to be applied to more general-purpose computing and other novel application scenarios.

[0036] In structure, each memory cell of an aCAM can include a "high side" that sets a high value and a "low side" that sets a low value. In some examples, each side of the cell includes a memristor and a pair of transistors. The memristor and one of the transistors form a voltage divider and the memristor is programmed to define R 高 or R 低 and thus a high or low value. The second transistor provides a threshold function to determine from the voltage divider whether the searched data (in the case of the high side) is below a high threshold or (in the case of the low side) is below a low threshold. If there is a match, the match is indicated on a match line (ML) because neither transistor activates to discharge or pull down the match line (ML). The aCAM includes an array of such cells, a search data register into which an input pattern is loaded, and an encoder that produces an encoding of the match location from the match line (ML).

[0037] However, it is noted that the structures shown herein that can implement aCAM cells are merely illustrative devices that can implement aCAM cells. Those skilled in the art having the benefit of the present disclosure can implement other alternative structures that can perform the disclosed functions of aCAM cells. Accordingly, the subject matter claimed below is not limited to just these devices disclosed herein, but rather to equivalents that perform the disclosed functions.

[0038] More particularly, in some examples, an aCAM cell includes a high side and a low side. The high side encodes an upper limit of a range of values and includes a first voltage divider formed by a first programmable resistor and a first electronically controlled variable resistor. The low side encodes a lower limit of the range of values and includes a second voltage divider formed by a second programmable resistor and a second electronically controlled variable resistor.

[0039] In some examples, conventional programming of each aCAM cell can be affected by parasitic capacitance on a match line (ML) that causes total capacitance to discharge during a miss. Given a vector of input values on a data line (DL), an input value close to a stored threshold can partially activate a discharge transistor to contribute to total leakage that can discharge the match line (ML). Thus, to improve programming of target analog voltage ranges in aCAMs and increase the usability of aCAMs, the contribution of each cell can be considered along with the total match line (ML) capacitance. Further, in some configurations, programming analog conductance values into analog CAMs can be challenging due to non-idealities of the circuit and memory device (e.g., parasitic resistance / capacitance due to interconnects, electronic noise in the SA or pre-charge circuit, and / or non-linearity of the memristor resistance). These challenges can hinder the use of large aCAM arrays and limit the performance of smaller arrays. For example, given a search target, non-idealities can create errors in the native 1 : 1 mapping of stored values. However, during conventional aCAM programming operations, the voltage divider at the input of the analog CAM causes large power consumption, which limits the scalability of the analog CAM to larger process node environments. To reduce operating power, the analog CAM can operate in sub-threshold transistor conduction mode. However, operating conventional aCAMs in sub-threshold transistor conduction mode can incur large operating errors due to transistor process variations at scaled process nodes. Thus, there is a need in the art for a differential CAM that achieves low-power analog CAM operations with higher operating precision.

[0040] Embodiments of the present disclosure provide a system, method, or computer readable medium for a differentiable CAM that improves upon analog CAM systems by implementing an analog input, analog storage, and analog output learning memory. The analog output of the differentiable CAM can provide input to a learning algorithm that can compute gradients and account for non-idealities of the circuit / device described herein. The learning algorithm can learn analog values to store within the differentiable CAM to optimize an operational objective of a desired task. The operational objective can include, for example, maximum operational accuracy of decision tree inference or minimizing power consumption. The differentiable CAM circuit block can be paired with a neural network accelerator and can be end-to-end distinguishable, which can help provide a new learning memory element in the field of artificial intelligence (AI) accelerators.

[0041] The circuit can include an analog content addressable memory (aCAM) array with extra match lines for sensing discharge current, in some instances corresponding to the "differential CAM" label; a digital-to-analog converter (DAC) circuit block; a pre-charge circuit block (PC); a program circuit block (PM); a sense amplifier circuit block; and a digital signal processing (DSP) unit that controls the system.

[0042] These systems can provide systems, methods, and computer readable media for encoding logical rules, such as domain dependent logical rule sets, in aCAM arrays. Specifically, these systems can provide methods for enabling fast, parallel search of encoded rules; storage and search of flexible parameter values; storage and search of analog value ranges; and fuzzy matching of stored values or stored value ranges. Turning now to the figures, the aCAMs disclosed herein can be used in digital or analog applications to perform traditional CAM functions and operations.

[0043] Figure 1 Analog content addressable memory ("aCAM") according to example embodiments described herein is conceptually depicted. In this illustration, aCAM 100 is used in a digital application in which the input search pattern and the values stored in aCAM 100 are digital. aCAM 100 can include search data register 105, analog cell array 110, encoder 115, plurality of analog cells 120, plurality of search lines 125, and match line 130.

[0044] Analog cell array 110 stores W "memory words" 0 through W 1. Each memory word is a pattern of values, at least some of which can be analog values as described below. Search data register 105, in use, can be loaded with an analog or binary input pattern that can be searched for among the contents of analog cell array 110. Figure 1 The example operates on a binary input pattern as indicated by the "n bits" going to the data line register. Thus, instead of storing two bits of data in two columns (as in a digital CAM), one column of aCAM cells can encode four analog values. Examples of operating on analog search patterns are further discussed herein.

[0045] Analog cell array 110 includes a plurality of analog cells 120 (only one indicated) arranged in rows and columns, as in Figure 2The search data register 105 is loaded with the analog input pattern shown in the example and discussed further below. During the search, the analog input pattern is loaded into the search data register 105 and passed to the analog cell array 110 via a plurality of search lines 125. Some examples can also use data lines in addition to or instead of search lines. Each cell 120 then indicates whether the value of the analog input pattern matches the range of values contained in the cell 120, where the range of values includes non-binary values.

[0046] The indication of whether the cells contain a match is passed to the encoder 115 via a plurality of match lines 130. Each aCAM memory array includes a plurality of match lines 130 electrically connected to each respective row of aCAM cells. A match is found if the searched word (e.g., search data including a variable pattern) matches a stored word within the row. For example, in one embodiment, the aCAM returns a match on the match line for a given row when all of the values stored in each aCAM cell on the row equal the search data applied as input to the search lines. Thus, when the search data matches the stored word, the match line returns an output indicating that a match exists. For example, in one embodiment, if the search data matches the values stored in the row, the match line for the row will return a value associated with a true condition (e.g., the match line returns TRUE or a high value of 1). If the search data does not match the values stored in each row, the match line for the row will return a value associated with a false condition (e.g., the match line returns FALSE or a low value of 0). In one embodiment, when a mismatch is found, the voltage of the match line is precharged to a high voltage level (e.g., a voltage level of approximately 1 V, 2 V, or 3 V) and discharged to a low voltage level (e.g., a voltage level of approximately 0 V or 0.5 V). If a match is found, the high voltage level is maintained.

[0047] The encoder 115 is a priority encoder that returns the location of the match to the analog cell array 110. Note that the encoder 115 can be omitted in some examples, particularly in examples where multiple match locations are identified and desired. For example, because “wildcard” values can be included in the input pattern, multiple matches among W stored words can be found. Some examples can desire to identify more than one or even all of the match locations, and these examples will omit the encoder 115.

[0048] Figure 2A selected portion of an analog unit array of an aCAM is illustrated in accordance with example embodiments described herein. In this example, a portion of an aCAM 100 is provided, including a selected portion of an analog unit array 200. The aCAM units 205 are arranged in rows 210 and columns 215 and are each individually searchable via data lines DL1, DL2. When a match is found from data on the data lines DL1 and DL2, the data stored in the row as programmed values of M1 and M2 for each aCAM unit is indicated via match lines ML1, ML2. As will be appreciated by those of ordinary skill having the benefit of the present disclosure, the analog unit array 200 can be larger than the 2x2 array, as illustrated in Figure 2 . The exact size can be implementation specific. The 2x2 portion is shown for illustrative purposes and is not limiting. Each aCAM unit 205 includes two memristors M1, M2 (not shown individually) for defining a range of values stored in the respective aCAM unit 205.

[0049] Figure 3 The resistance amount differential that can be used in some examples to set the stored analog value or range of aCAM units 205 in Figure 2 is conceptually illustrated. The total range of resistance amounts R that can be implemented by both memristors M1, M2 is defined by a maximum resistance amount R 最大 and a minimum resistance amount R 最小 . The resistance amount range R 范围 is defined by R 高 and R 低 . R 高 is determined by programming a value in M1 and R 低 is determined by programming a value in M2. When storing an analog value, the analog number is encoded in the cell via two resistance amount thresholds, a high resistance amount threshold and a low resistance amount threshold at which the analog value (or range value) of the cell lies. The multiple electronic circuits by which the aCAM units 205 can be implemented will be discussed further below.

[0050] In some examples, more than three levels can be programmed in a content addressable memory. In a memristor CAM, information can ultimately map to resistance amount levels. The resistance amount levels include all resistance amount levels needed for CAM operations. For example, there are 2 低 +1 different resistance amount levels between R 高 and R n . That is, R 范围 = R 高 R 低 and includes 2 n +1 different resistance amount levels, each different resistance amount level representing a different value. For example, there are 2 高≠ R 低 and R 高 ≠ R 低 , then the aCAM cell 205 stores all levels between R 低 and R 高 . For another example, if R 高 = R 最大 and R 低 = R 最小 , then the aCAM cell 205 stores X = "don't care" value. For yet another example, if R 高 = resistance amount R1 and R 低 = R1 wherein, = (R 最大 R 最小 ) / (2 n ), then the aCAM cell 205 stores a single level R1.

[0051] Figure 4 depicts an electronic circuit implementing an aCAM cell 400, which can be used to implement the aCAM cell 205 of Figure 2 . In some examples, the aCAM cell 400 includes a "high side" 403 and a "low side" 406. These "high side" and "low side" can be values relative to each other, at least in part because the memristor (M1) and the memristor (M2) are programmed to determine values of R 高 and R 低 , respectively.

[0052] The high side 403 includes a first transistor (T1) and a first memristor (M1). The first memristor (M1) in combination with the first transistor (T1) defines a first voltage divider 409 for a voltage applied on the search line. When programmed, the memristor (M1) defines a high value R 范围 of a range of values R 高 . The high side 403 also includes a second transistor that, in use, indicates whether the searched value matches the high value R 高 , as discussed further below. The low side 406 includes a third transistor (T3) and a second memristor (M2). The second memristor (M2) in combination with the third transistor (T3) defines a second voltage divider 412. When programmed, the memristor (M2) defines a low value R 范围 of a range of values R 低 . The low side 406 also includes a fourth transistor (T4) that, in use, indicates whether the searched value matches the low value R 低 .

[0053] The aCAM cell 400 also includes a match line (ML), a word line WL used as a ground, a first search line SL P , a second search line SL N , and a data line DL P , DL N . As described above, the memristor-transistor pairs M1 / T1 and M2 / T3 define respective voltage dividers 409, 412. When the memristors M1, M2 of the voltage dividers 409, 412 are programmed, the memristors M1, M2 are used to encode R 高 and R 低 . The searched data can be matched to the stored data based on the function of the voltage dividers (e.g., M1 / M2 values and transistor characteristics). Thus, in this example, in each memristor-transistor pair M1 / T1 and M2 / T3, the analog search can be implemented as the gate voltage of the transistor to form a variable resistance voltage divider with the memristor programmed to analog (stored) values to represent an analog number or range.

[0054] In the high side 403, where R 高 is programmed, the V P voltage on DL 搜索 should be a voltage low enough so that the voltage at gate G1 (formed by the voltage divider between T1 and M1) will not turn on the T2 pull down transistor. If the V P voltage on DL 搜索 is too low (indicating a search value higher than the limit of R 高 ), then T1 will have a very low resistance amount. If T1 has a very low resistance amount, then the voltage applied to gate G1 will be similar to the search voltage on SL P (and thus quite high), turning on T2 and discharging the pre-charge voltage on ML. Discharging the pre-charge voltage indicates a mismatch.

[0055] With respect to the low side 406, when R 低 is programmed, the V N voltage on DL 搜索 should be higher than the threshold voltage at gate G2 to make the observed voltage at gate G2 a low voltage value, preventing the pull down transistor T4 from turning on. For example, in one embodiment, DL N must be a voltage high enough (e.g., a voltage level of about 1 V, about 2 V, about 3 V) so that the voltage at G2 (formed by the voltage divider between M2 and T3) will result in a low voltage (e.g., a voltage level of about 0 V or about 0.5 V) that will not turn on the pull down transistor T4. If DL N is too low, then T3 can be a too high resistance amount, and V SLn and V G2The voltage mismatch causes discharge, similar to what was described above. In other words, in DL... N In certain cases where the voltage is low, the voltage at G2 will be close to that at SL. N Voltage. In this case, especially compared to the resistance of M2, transistor T3 has a very high resistance. Therefore, the voltage divider from M2 and T3 will cause the voltage observed at G2 (e.g., the midpoint of the voltage divider) to be close to that at SL. N The voltage observed at T3 (because T3 is a significantly larger resistance, therefore a larger proportion of the total voltage SL is applied across M2 and T3 in series) N (Will descend across T3). Additionally, as in Figure 4 As further seen, this example uses a method that inversely maps the desired analog search value to the low and high gate voltages of lines T1 and T3. Therefore, for example: SL P =SL N = 0.8 V, DL P = 0 V, DL N = 1.5 V, M1 = 10 And M2 = 10 k .

[0056] Note that transistors T1 through T4 are implemented using metal-oxide-semiconductor field-effect transistors (“MOSFETs”). In one embodiment, T1 is a positive or “p” MOSFET (e.g., a PMOS transistor), and T3 is a negative or “n” MOSFET (e.g., an NMOS transistor). Using both PMOS and NMOS transistors in a CMOS integrated circuit allows the CMOS transistor to utilize the characteristics of both PMOS and NMOS transistors. Therefore, compared to the example where both T1 and T3 are “n” MOSFETs and the memristor / transistor pair is reversed, a wider array of analog levels is allowed. These and other advantages arising from the circuit design will become apparent to those skilled in the art who possess the benefits of this disclosure.

[0057] Various tuning knobs can be implemented in the aCAM 400 to adjust unit performance, including DL. P DL N SL P SL N The voltage on the transistors and the number of levels / ranges of M1 and M2. The sources of the pull-down transistors T1 and T2, which are ground (GND), can also be changed to globally non-zero voltage values ​​to help tune for near-matching conditions. Other tuning knobs or adjustment sources will become apparent to those skilled in the art who possess the benefits of this disclosure.

[0058] Figure 5An electronic circuit implementing aCAM cell 500 is depicted that can be used to implement aCAM cell 205 of Figure 2 The aCAM cell 500 includes a high side 503 and a low side 506, at least in part because the memristor (Ml) and the memristor (M2) are programmed to determine the values of R 高 and R 低 respectively.

[0059] The high side 503 can include a first transistor (Tl) and a first memristor (Ml). The first memristor (Ml) in combination with the first transistor (Tl) defines a first voltage divider 509 and, when programmed accordingly, a high value R 范围 of the range of values R 高 . The high side 503 also includes a second transistor that, in use, indicates whether a searched for value matches the high value R 高 , as discussed further herein.

[0060] The low side 506 includes a third transistor (T3) and a second memristor (M2). The second memristor (M2) in combination with the third transistor (T3) defines a second voltage divider 512. When the second memristor (M2) is programmed, the memristor (M2) defines a low value R 范围 of the range of values R 低 . The low side 506 also includes a fourth transistor (T4) that, in use, indicates whether a searched for value matches the low value R 低 .

[0061] The aCAM cell 500 also includes a match line (ML), a word line (WL) that serves as ground, a search line (SL), and data lines DL N (H), DL N (L). As described herein, the memristor-transistor pairs Ml / Tl and M2 / T3 define respective voltage dividers 509, 512. When the memristors Ml, M2 are programmed, the voltage dividers 509, 512 are used to encode R 高 and R 低 . Thus, in this example, in each of the memristor-transistor pairs Ml / Tl and M2 / T3, an analog search is implemented by determining the gate voltage of the voltage divider transistor to form a variable resistance voltage divider with a memristor programmed to analog (store) a value.

[0062] In the high side 503, programming R 高 into Ml, V N on the data line (DL) 搜索 (H) can be low enough such that the voltage at G1 (e.g., formed by the voltage divider between Tl and Ml) does not turn on the T2 pull down transistor. If the data line (DL)N (H) Too high (e.g., indicating a value higher than R) 高 If the limit is the search value, then T1 is a very low resistance, and the voltage at G1 can be similar to the search voltage on the search line (SL), thus causing a mismatch and discharging through T2.

[0063] In R 低 In the low-side 506 where programming is performed, the data line DL N V on (L) 搜索 It can be high enough that the voltage at G2 (e.g., formed by the voltage divider between M2 and T3) will not turn on the T4 pull-down transistor. If the data line DL N If (L) is too low, then T3 may have too high a resistance and cause a voltage at G2—the search line (SL) search voltage, which causes a mismatch and discharges through T4.

[0064] The high-side 503 and low-side 506 can share a search line (SL). In some examples, the search line (SL) can be split into two search lines to independently control the drain voltage on the two search sides (e.g., high-side 503 and low-side 506).

[0065] Figure 6 The electronic circuitry for implementing the aCAM unit 600 is depicted; in some examples, this aCAM unit can be used to implement... Figure 2 The aCAM unit 205. At least based on memristors (M1) and (M2), it is programmed to determine R respectively. 高 and R 低 The value of aCAM unit 600 includes a high side 603 and a low side 606.

[0066] The high-side 603 includes a first transistor (T1) and a first memristor (M1). The first memristor (M1), in conjunction with the first transistor (T1), defines a first voltage divider 609, and when programmed, defines a value range R. 范围 High value R 高 The high-side 603 also includes a second transistor that, in use, indicates whether the searched value matches the high value R. 高 Matching, as discussed further in this article.

[0067] The low-side 606 includes a third transistor (T3) and a second memristor (M2). The second memristor (M2), in conjunction with the third transistor (T3), defines a second voltage divider 612. When the second memristor (M2) is programmed, the memristor (M2) defines a value range R. 范围 low value R 低 The low-side 606 also includes another transistor T6, which, in use, indicates whether the searched value matches the low value R. 低Matched.

[0068] Note that, in contrast to the example of Figure 6 Figure 4 The examples shown in FIG. 6 and described herein can use different encoding of the input voltage on the DL P and DL N In the example of FIG. 6, the inputs can be tied together so that T1 / M1 and T3 / M2 are equivalent, and T4 / T5 can form an inverter. Thus, the left and right sides can independently define low and high sides. The T4 / T5 inverter is illustrated in the low side 606 in the illustrated example, and can be implemented in the high side 603 in other examples. Figure 6

[0069] The aCAM cell 600 also includes a match line (ML), search lines (SL HI ), (SL LO ), and data lines (DL), (DL1). As described above, the memristor-transistor pairs M1 / T1 and M2 / T3 define respective voltage dividers 609, 612. When the memristors M1, M2 are programmed, the voltage dividers 609, 612 are used to encode R 高 and R 低 . Thus, in this example, in each memristor-transistor pair M1 / T1 and M2 / T3, an analog search is implemented as the gate voltage of the transistor to form a variable resistance voltage divider with a memristor programmed to an analog (stored) value.

[0070] More particularly, the first memristor (M1) and the first transistor (T1) form a voltage divider 609, where M1 is a memristor with a tunable non-volatile resistance quantity and T1 is a transistor whose resistance quantity increases with the input voltage on the data line (DL). Thus, there is a threshold voltage dependent on the M1 resistance quantity, below which the pull-down transistor T2 turns on, which pulls down the match line (ML), resulting in a "no match" result, when the data line (DL) input voltage is less than the threshold. Similarly, the memristor (M2) and transistor T3 form another voltage divider 612, and the internal voltage node is inverted by transistors T4, T5 before being applied to another pull-down transistor T6. Thus, with the appropriate programmed resistance quantities in the memristors M1, M2, the aCAM cell 600 keeps the match line (ML) high when the voltage on the data line (DL) is within a certain range defined by the M1 and M2 resistance quantities.

[0071] Still referring to Figure 6 , the search result is thus sensed as the voltage level on the match line (ML), which is pulled down when the gate voltage of the pull-down transistors T1, T3 exceeds their threshold voltage (V th ). In some examples, the voltage (V​​G1 ) as V DL decreases. Thus, there is a lower limit voltage (V lo ) that can be configured by the corresponding memristor conductance. When V DL is less than V lo , V G1 is greater than the V th of the pull-down transistor, thus causing the match line (ML) to be pulled down for a “no match” result. Similarly, the voltage (V G2 ) on G2 increases as V DL increases, and thus the upper limit voltage is configured by another memristor conductance in the same aCAM cell 600. The pre-charge of the match line (ML) is initiated by a pre-charge peripheral not shown in FIG. 6. The data line (DL) is asserted in conjunction with the match line (ML) pre-charge while SL Figure 6 remains low. HI

[0072] The search can be initiated by asserting SL HI . As an illustrative example, when the voltage on the data line (DL) falls within a predefined range defined by the memristor conductance given by G(M1) and G(M2) (where conductance is the inverse of resistance), the search result sensed from the match line (ML) after initiating the search 10 ns can output a match. In the case of FIG. 6, the gate voltage VG1 at G1 of the pull-down transistor T2 decreases below its threshold voltage as the data line (DL) voltage increases. In the case of FIG. 7, the gate voltage VG2 at G2 of the pull-down transistor T6 increases above its threshold voltage as the data line (DL) voltage increases. The cutoff data line (DL) voltage for the upper and lower limits of the match search increases as the corresponding memristor conductance increases. Figure 6 Figure 6 The relationship between the search voltage range and the memristor conductance can be better understood by the voltage divider effect of the series connected transistors and memristors M1 / T1 and M2 / T3 from FIG. 6. During operation, the transistors (T1), (T2) can operate in a triode mode as the voltage drop across the transistor channel can be fairly small. Under this condition, the match line can be pulled down (i.e., no match) when V DL follows the equation:

[0073] Figure 6

[0074]

[0075] where V TH and V TH,ML are the threshold voltages of the transistors in the voltage divider and the transistor discharging or pulling down the ML, respectively, and β is a constant factor. G M1 ​​​​is the memristor conductance magnitude, according to which the memristor conductance magnitude is linearly related to the search voltage range on DL.

[0076] Returning to Figure 6 The aCAM unit 600 will output a match result when

[0077]

[0078] where, in Figure 6 , f(G M1 ) and f(G M2 ) are the voltage at G1, the voltage at G2, respectively. If the unit takes DL as input and G1 as output, then the unit is an inverter with a tunable parameter defined by the M1 resistance magnitude.

[0079]

[0080] Assume a field effect transistor (FET) is working in triode mode:

[0081]

[0082] Assume a field effect transistor (FET) is working in saturation mode:

[0083]

[0084] Figure 7 A search operation on an aCAM unit is depicted in accordance with example embodiments described herein. In this illustration, the search input is an analog value rather than zero and one. Note that there can not be registers for the search data. Since the values can be continuous, to avoid ambiguity, the stored values in the aCAM 700 can represent a range rather than a specific value.

[0085] Similar to a digital CAM word, an aCAM word can return a "match" result when all input values fall within the range stored in the analog memristor (specifically, memristor) as the resistance magnitude (or equivalently conductance magnitude) value of the word line of the analog CAM unit. In some examples, the aCAM 700 implements a similar function to a TCAM, where the TCAM stores an equivalent range from zero to one, while the aCAM stores any portion of the full range of analog signals. A wildcard or "X" value that matches all inputs can be stored when the resistance magnitudes of the two memristors map to the lower and upper bounds of the input voltage range, respectively.

[0086] In some examples, the analog search pattern is directly input to the aCAM 700 via multiple inputs 710. In some examples, the analog search pattern can be input to a search register (not shown) via input 710. Although the search register is typically used with digital binary values ​​(e.g., Figure 1 However, these search registers can be implemented in the aCAM 700. However, search registers that handle analog input values ​​can be implemented using, for example, sample / hold circuitry. Therefore, some examples (not shown) can provide input analog search values ​​via one or more search registers.

[0087] Figure 8 The following is illustrated based on one or more examples. Figure 7 An advanced implementation of the memristor-based aCAM 700. Figure 8 In the example shown in the figure, the following is used Figure 6 Electronic circuitry is used to implement the aCAM cells (e.g., as described herein, aCAM cells 600 are arranged in rows and columns, but...). Figure 8 Only a single row 800 is shown in the diagram. For each row 800, the aCAM unit 600 (illustrated as the first aCAM unit 600A, the second aCAM unit 600B, and the third aCAM unit 600C) also includes data lines (DL1 to DL2). n The CAM includes a pre-charged peripheral 810 that charges the match line (ML) in the enable word to a high logic level before a search. The match line (ML) remains at a high logic level while all inputs are within the range defined by the memristor resistance in each CAM unit 600. The matching result can be read out by sensing the peripheral 815.

[0088] Each example disclosed herein includes at least two programmable memristors. The memristors M1 and M2 in the aCAM unit 600 can be programmed prior to the search operation. For example, in Figure 6 As shown in the diagram, data lines DL1 and DL2 select the memristor device M1 or M2 to be programmed, and the search line SL... HI and SL LO A programming voltage is applied to set up the device (i.e., program the device from a low conductivity state to a high conductivity state) or reset it. Analog voltages can be applied to data lines DL1 and DL2 to set the compliance current during the setup operation for better multi-level tunability. Where the programmed memristor conductance needs to be verified after the write operation, it can be verified across SL... HI and SL LOThe conductance amount of a given memristor is read out by current when a read voltage is applied, where the data line selection device. Table 1 summarizes the detailed voltage signals as used in various operations.

[0089]

[0090] The aCAMs disclosed herein can permit tri-state like operations. For example, as discussed herein, aCAM cells can store and operate on a range of values. In encoding TCAMs for a large portion of the desired data to be stored and matched, it is often possible to implement "X" values from right (least significant bit) to left (most significant bit). "Wild card" values can not be randomly distributed in 8-bit / 16-bit objects. Thus, for example, in a four-bit object, X can not be implemented as 1001, 100X, 10XX, 1XXX to 1X1X.

[0091] For example, assume a two-bit object using four levels of memristor resistance or conductance state - 00, 01, 10, 11. Table 2 sets forth possible compression using aCAM cells as discussed herein. Note that in this art, X1 and X0 can not be suitable for compression.

[0092]

[0093] Data compression ratios can be matched to the stored data properties. For example, to compress in a four-bit object, four-level aCAM cells can be used. The number of analog bits stored per cell can be based on the compression requirements and the spacing of "X" bits or "wild card" bits. This can be done dynamically since the same circuitry can be used to encode four levels, eight levels, etc.

[0094] For another example, assume a four-bit object that produces sixteen levels of memristor state. Introducing "X" bits or "wild card" bits from the right hand side, three Xs can be introduced for the three rightmost bits. Table 3 sets forth possible compression using aCAM cells of the present disclosure. Note that in this art, X000 to X111 can not be suitable for compression.

[0095]

[0096]

[0097] As described above, a TCAM matches a contiguous input range when "X" bits are implemented from the least significant bit to the most significant bit. For example, 10XX represents a match from 1000 to 1011 (or decimal numbers 8 to 11), which can be represented by a 4-bit equivalent analog CAM cell. On the other hand, an analog CAM also permits searching over any range in the space of 4-bit binary, and some ranges cannot be represented by one TCAM word (e.g., 0010 to 1110 or decimal numbers 2 to 14).

[0098] Note that the discussion associated with Tables 2 and 3 discusses the functionality of aCAM from the perspective of binary values. For example, the aCAMs disclosed herein can perform digital TCAM in known manners. However, as should be apparent from the disclosure herein, the aCAMs can also store and operate on analog values, where the compression will operate in a similar manner to that discussed with respect to Tables 2 and 3.

[0099] Figure 4 to Figure 6 Each example of an aCAM memory cell in FIG. 1 can include a high side and a low side that are respectively set with an upper and lower limit of a range of values. Each of the high side and the low side includes a first and second voltage divider, respectively. In each of these voltage dividers, Tl and T3 are variable resistors, and Ml and M2 are programmable resistors. The variable resistors (Tl, T3) are electronically controlled by a search line or data line voltage.

[0100] For example, the programmable resistors can be metal oxide memristor devices, as is the case in the illustrated example. Other examples can instead use phase change memory ("PCM") devices, spin-torque transfer ("STT") devices, ferroelectric random access memory ("FeRAM") devices, or other resistive memory devices with programmable resistance. In the illustrated example, the variable resistors are complementary metal oxide semiconductor ("CMOS") transistors. Other examples can instead use ferroelectric transistors or other three-terminal electronic nonlinear devices (i.e., a device resistance that changes with an applied voltage).

[0101] Further, the examples discussed herein present only illustrative means by which upper and lower limits of a range of values in an aCAM memory cell can be set. Those skilled in the art having the benefit of the present disclosure can appreciate that other means by which this setting of limits can be accomplished. Accordingly, the subject matter claimed below encompasses means substantially equivalent to those explicitly disclosed herein that perform this function.

[0102] Throughout this disclosure, the term "match" is used to describe the context in which the stored content matches the search portion of the input pattern. What constitutes a "match" will be implementation specific. Thus, for example, in the operation of digital binary inputs, a "match" will be the case where the stored content is identical to the search input portion or is a "wildcard" bit. In the operation of analog inputs, a "match" will be the case where the search input is within the range of values defined by "high" and "low" values as described above, or is a "wildcard" bit. In the disclosed examples, a match can be defined as maintaining its pre-charge (high value) ML voltage, as well as a pattern match between the searched data and the stored data.

[0103] The aCAMs disclosed herein can significantly increase storage density relative to SRAM CAMs, as one aCAM cell utilizes only six transistors to search and store a multi-bit signal, while a SRAM CAM cell utilizes 16 transistors to search a single bit. Since energy consumption in the search operation of a CAM is primarily to charge parasitic capacitors, the reduction in chip area results in a significant decrease in the energy cost to accomplish a particular task. The analog processing capability also opens the possibility of directly handling analog signals acquired from the Internet of Things, such as sensors. The output of an aCAM is digital, which can be directly processed with digital logic, thus completely eliminating the cost of expensive analog-to-digital conversion. Furthermore, the functionality of an aCAM is fundamentally different from a digital CAM, which can enable new applications for fuzzy logic, analog computation, probabilistic computation, etc.

[0104] According to example embodiments, any of the aCAM structures disclosed in co-pending and co-owned U.S. Application Serial Nos. 16 / 274,379, 16 / 744,136, 16 / 526,455, and 17 / 514,847 can be incorporated by reference for any purpose and employed herein. Using the aCAM structures discussed herein, various programming (e.g., encoding, lookup, searching, storing, etc.) can be implemented.

[0105] Each aCAM memory array can implement various in-memory computing methods. For example, in one embodiment, as described above, the aCAM memory array can implement an ensemble method including a tree-based regression model (e.g., a random forest model). As further explained in Figure 6 the tree-based regression model can be used to perform various computations.

[0106] Figure 9is a flowchart depicting converting a first data structure representing a set of logical rules to a second data structure representing the logical rules and encoding values of the second data structure in an aCAM according to example embodiments of the present application. In example embodiments, the first data structure can be a decision tree 902. The decision tree 902 can include a set of decision nodes including a root node 904, various intermediate nodes (e.g., intermediate node 906), and various leaf nodes (e.g., leaf node 908) representing the end of the decision tree 902. It should be understood that the decision tree 902 is merely an illustrative implementation of a data structure, and other data structures including but not limited to arrays, lists, hash-based structures, graphs, and the like are contemplated.

[0107] The decision tree 902 can include a plurality of root-to-leaf paths. Each root-to-leaf path represents a traversal of a series of nodes in the decision tree 902 beginning at the root node 904, passing through various intermediate nodes, and ending at a given leaf node. In example embodiments, each decision node traversed in a given root-to-leaf path represents a respective evaluatable condition involving a corresponding feature of the feature vector 900. As such, each root-to-leaf path represents a series of evaluatable conditions representing a logical rule that can be evaluated against an input feature vector.

[0108] In the example root-to-leaf path 910 shown in Figure 9 In the example root-to-leaf path 910 shown in

[0109] In the example root-to-leaf path 910, the result of the determination at the root node 904 is illustratively depicted as the result "b," which indicates that the condition evaluated at the root node 904 involving feature fl is not satisfied. Based on this result, the root-to-leaf path 910 transitions from the root node 904 to the intermediate node 906. A transition within a root-to-leaf path from a first node to a second node is denoted as a combination of the condition evaluated at the first node and the result of that evaluation. For example, the transition from the root node 904 to the intermediate node 906 in the example root-to-leaf path 910 is denoted as fl conditionib. Using this convention, the example root-to-leaf path 910 can be represented by the following node transitions: fl conditionibto f3 conditionibto f2 condition2ato class 2. Each other root-to-leaf path in the decision tree 902 can be similarly represented as a series of node transitions denoting the condition evaluated at each node and the result of that evaluation.

[0110] In example embodiments, the information contained in the decision tree 902 can be converted to an alternative representation, such as a table representation. In particular, each root-to-leaf path in the decision tree 902 can be represented as a corresponding column in a table representation, which is referred to herein as a "node chain" and is illustrated in FIG. 10. For example, an integrated tree-based model (e.g., a random forest model) can be re-formulated for an aCAM implementation by re-formulating the decision tree to represent each root-to-leaf path as a chain of nodes, combining multiple thresholds for a single feature into one node, adding "wildcard" nodes in the chain for features that are not evaluated, and rotating (i.e., matrix transforming) the representation and mapping each chain to each row in an aCAM array such that the columns are feature vectors. Figure 10 In example embodiments, the information contained in the decision tree 902 can be converted to an alternative representation, such as a table representation. In particular, each root-to-leaf path in the decision tree 902 can be represented as a corresponding column in a table representation, which is referred to herein as a "node chain" and is illustrated in FIG. 10. For example, an integrated tree-based model (e.g., a random forest model) can be re-formulated for an aCAM implementation by re-formulating the decision tree to represent each root-to-leaf path as a chain of nodes, combining multiple thresholds for a single feature into one node, adding "wildcard" nodes in the chain for features that are not evaluated, and rotating (i.e., matrix transforming) the representation and mapping each chain to each row in an aCAM array such that the columns are feature vectors.

[0111] For example, Figure 9 The example root-to-leaf path 910 illustrated in FIG. 10 can be converted to a node chain 1012. Each node in the node chain 1012 can correspond to one or more node transitions in the corresponding root-to-leaf path 910. More specifically, each node in the node chain 1012 corresponds to a respective feature in the feature vector 900. Since the feature vector 900 is illustratively depicted as including four features (fl, f2, f3, f4), each node chain can include four nodes corresponding to the four features and a node representing the leaf node of the corresponding root-to-leaf path. It should be appreciated that the feature vector 900 can contain any number of features, in which case the corresponding node chain can include a corresponding number of nodes and a leaf node. In some example embodiments, the leaf node can also correspond to a feature (e.g., an optimization parameter) that forms part of the feature vector 900.

[0112] In example embodiments, certain root-to-leaf paths can not include an evaluatable condition for one or more features. For example, root-to-leaf path 910 does not include an evaluatable condition for feature f4. For any such features that do not have at least one associated evaluatable condition in a root-to-leaf path, a "wildcard" value can be used to represent the node in the node chain for that root-to-leaf path that corresponds to that feature. For example, for root-to-leaf path 910, a "wildcard" value is used for the node in node chain 1012 that corresponds to feature f4. This means that, when node chain 1012 is encoded in the aCAM and evaluated against, any value specified for feature f4 in a search query will result in a match for feature f4.

[0113] Additionally, in conjunction with converting the representation of the domain logic rule set from decision tree 902 to a table representation, nodes within a given root-to-leaf path can be merged and / or reordered when determining the sequence of corresponding nodes in the node chain representing the root-to-leaf path. For example, in the sequence of nodes traversed as part of root-to-leaf path 910, the evaluatable condition involving feature f3 occurs before the evaluatable condition involving feature f2. However, prior to encoding node chain 1012 in the aCAM, the sequence of evaluatable conditions represented by root-to-leaf path 910 can be reordered to ensure that the sequence of evaluatable conditions in corresponding node chain 1012 matches the sequence of features in feature vector 900. This reordering can occur for each root-to-leaf path in decision tree 902 as part of converting the root-to-leaf paths to corresponding node chains in the table representation as necessary.

[0114] More specifically, each node chain in the table representation (e.g., each column in the table) can begin with the node in the corresponding root-to-leaf path representing the evaluatable condition involving feature f1, followed by the evaluatable condition involving feature f2, and so on until the penultimate node in the node chain is the evaluatable condition involving the last feature f n in the feature vector (e.g., feature f4 in feature vector 900), where the final node is the appropriate leaf node (alternatively, each leaf node can correspond to the last feature in the feature vector). n

[0115] ​In some examples, if a given root-to-leaf path does not include an evaluatable condition for a particular feature, a "wildcard" value can be associated with the corresponding node in the node chain. This can ensure that each node chain in the table representation includes the same number of nodes, regardless of which features are evaluated in the corresponding root-to-leaf path. Thus, the node transitions of the example root-to-leaf path 910 (e.g., f 1 condition 1 b to f 3 condition 1 b to f 2 condition 2a to class 2) can be reordered when represented as the node chain 1012 to place the node for f 2 condition 2a in front of the node for f 3 condition 1 b. Additionally, since the root-to-leaf path 910 does not include an evaluatable condition involving feature f 4, a "wildcard" value can be used for the node in the node chain 1012 corresponding to feature f 4. The sequence of nodes in the node chain 1012 can then become: f 1 condition 1 b to f 2 condition 2a to f 3 condition 1 b to class 2.

[0116] In some example embodiments, converting root-to-leaf paths to corresponding node chains can include merging two or more node transitions in a path into a single node in a node chain. For example, consider a root-to-leaf path in the decision tree 902 that includes the following node transitions: f 1 condition 1 a -> f 4 condition 1 b to f 1 condition 2a to class 2. In this example path, two node transitions occur as a result of evaluating conditions involving feature f 1. As such, the two node transitions can be merged into a single node in the corresponding node chain 1014 associated with feature f 1 (represented as f 1 condition 1 a + 2a). For example, if f 1 condition 1 a represents f 1 > x 1 and if f 1 condition 2a represents f 1 < x 2, the result of the merge (i.e., x 1 < f 1 < x 2) can be represented in the first node of the node chain 1014 (e.g., the node associated with feature f 1). Merging multiple node transitions involving a particular feature variable into a single merged node for that feature variable can increase memory density and reduce the amount of area needed when encoding the set of logical rules represented by the decision tree 902 into an aCAM.

[0117] Converting the example root-to-leaf path involving the sequence of node transitions identified above to a node chain 1014 involves all types of data manipulation described above, specifically, merging node transitions (combining fl condition la with fl condition 2a); reordering node transitions (moving f4 condition lb to a position in node chain 1014 that is after the nodes corresponding to features fl, f2, and f3); and inserting "wildcard" values for particular nodes in node chain 1014 (that do not have an evaluatable condition in the corresponding root-to-leaf path) (the "wildcard" values for features f2 and f3). After each of these manipulations is performed, node chain 1014 results in the following sequence of nodes: fl 1 condition la+2a to f4 condition lb to category 2. In example embodiments, all of the set of root-to-leaf paths represented in decision tree 902 can be converted to a corresponding set of node chains according to the method described above.

[0118] Once the conversion process is complete and a tabular representation of the domain logic rules is generated, each node chain in the tabular representation can be rotated and mapped to a corresponding row of aCAM 1116 in Figure 11 In some example embodiments, the sequence of node chains in the tabular representation can be dictated by a convention that defines an order in which to traverse decision tree 902 to cover all of the root-to-leaf paths represented in decision tree 902. Further, in some example embodiments, the sequence of node chains in the tabular representation can be mapped and encoded to rows of aCAM 1116 in the same sequence. In other example embodiments, the ordering of node chains can be irrelevant, so long as each root-to-leaf node in decision tree 902 is converted to a respective corresponding node chain and each node chain is mapped to and encoded in a corresponding row of aCAM 1116.

[0119] As shown in Figure 11 More specifically, each value represented in each node of node chain 1012 can be stored using a respective corresponding one or more cells of aCAM 1116 in row N-1. For example, each other node chain, such as node chain 1014, can be similarly mapped to and encoded in a corresponding row of aCAM 1116 (not shown).

[0120] In some example embodiments, in fact, the values represented in the nodes of the node chain 1012 can be value ranges. As previously described, the aCAM 1116 provides the ability to store and encode such value ranges. The number of aCAM cells needed to encode the values / value ranges corresponding to a particular feature (e.g., feature fl) across all node chains (i.e., the number of CAM cell columns corresponding to feature fl) can depend on the level of precision needed to encode such values / value ranges. For features in the feature vector 900 that are categorical variables that can only have a finite number of discrete values (e.g., a set of all origin or destination “airports”), a single column of aCAM cells can be sufficient to represent all stored values of the feature across the domain logic rule set. On the other hand, for features corresponding to numerical variables that can have a large number of possible values (e.g., a continuous value range), multiple columns of aCAM cells can be needed to provide the bit precision needed to store such values.

[0121] In some example embodiments, in fact, the output parameters of each node chain (domain logic rule) encoded in the aCAM 1116 can be stored in a memory array separate from the aCAM 1116. For example, as illustratively shown in Figure 9 each leaf node of the decision tree 902 can represent a classification output that can be stored in a random access memory (RAM) 1118 separate from the aCAM 1116. This can then allow for multiple matches to be returned for a search query. In example embodiments, a search query can be in the format of the feature vector 900 and can specify discrete values, value ranges, or a “wildcard” value for each search variable (i.e., each feature in the feature vector 900). The search query can then be searched in parallel against each row in the aCAM to determine whether the search query matches the stored values in any such row. Each row of the aCAM 1116 can represent a stored word that corresponds to a particular node chain, and thus a particular root-to-leaf path in the decision tree 902. In some example embodiments, the stored word can only include those values stored in the particular row of the aCAM 1116. In other example embodiments, the stored word can include the values of the particular aCAM row and the corresponding values of the output parameters (e.g., classification output values) stored in the RAM 1118.

[0122] In some example embodiments, the output parameter (e.g., the classification output represented by a leaf node of decision tree 902) can be a parameter that the user seeks to optimize. For example, the search query can specify a maximum allowable value or a minimum allowable value for the optimization parameter, in which case any row in aCAM 1116 that matches each of the constraint and / or flexible parameter values specified in the search query and that satisfies the value specified for the optimization parameter can be returned as a matching result. More specifically, the address of any such matching row in aCAM 1116 can be returned as a search result. Optionally, the corresponding value of the optimization parameter stored in RAM 1118 (or the memory address of the corresponding value in RAM 1118) can also be returned.

[0123] In other example embodiments, rather than searching for stored rows in aCAM 1116 that correspond to output parameter values that are below or above a specified value as part of an optimization process, the search query can specify a value of the output parameter that needs to be matched exactly among the values of the output parameter stored in RAM 118. For example, in such example embodiments, a search query can yield a match only if: (1) all other search parameter values specified in the search query match the corresponding stored values in a given row of aCAM 1116; and (2) the output parameter value specified in the search query exactly matches the value stored in RAM 1118 corresponding to that row in aCAM 1116. Thus, in such example embodiments, a search query that includes the search variable values satisfying the first four nodes of node chain 1012 but that specifies “category 3” for the output parameter value would not yield a match at stored word N-1.

[0124] In still other example embodiments, the search query can specify an exclusive value for the output parameter. For example, in Figure 9 , the search query can specify “category 2” as an exclusive value for the output parameter. Such an example search query would then yield a matching result for any row in aCAM 1116, and thus for any node chain in the table representation and corresponding root-to-leaf path in decision tree 902, that matches each of the other constraint parameters in the search query and that corresponds to a stored output parameter value other than “category 2.” This can represent a mechanism for optimizing the output parameter by specifying a value to be excluded from the match, rather than by iterative adjustment of the optimization parameter.

[0125] Figure 12 FIGURE 3 illustrates a target analog voltage range according to example embodiments described herein. As illustrated, an aCAM cell can tune the respective conductance amounts of G M1 and the respective conductance amounts of G M2to obtain an analog voltage range bounded by a lower voltage limit f ( G M1 ) and an upper voltage limit f ( G M2 ) to store the analog value range.

[0126] In some examples, the aCAM cell can search an input value (e.g., a discrete numerical value) against the analog value range 1208 stored in the aCAM cell. This in turn involves determining whether the data line voltage V DL corresponding to the search input value is within an analog voltage range bounded by a lower voltage limit f ( G M1 ) and an upper voltage limit f ( G M2 ) based on whether the match line connected to the aCAM cell is held at a high voltage (high logic level) or discharged to a low voltage (low logic level). The stored value range can be the same as the match value range.

[0127] In some examples, a fuzzy search is supported. In these examples, the aCAM cell can search an input value range against the stored value range and output a match even if the search input range does not correspond exactly to the stored range. As previously described, the aCAM cell can store the analog value range by tuning the respective conductance G M1 of memristor Ml G M2 and the respective conductance f ( G M1 ) of memristor M2 to obtain an analog voltage range bounded by a lower voltage limit f ( G M2 ) and an upper voltage limit. The aCAM cell can additionally provide a fuzzy search capability, extending the match range 1206 of the aCAM cell beyond the stored analog range 1202 to also include a fuzzy match range 1204. In this way, the aCAM cell can output a match even if the input search range of values does not fall entirely within the stored analog range 1202, as long as the input search range falls within the larger match range that also includes the fuzzy match range 1204. The fuzzy match range 1204 can be appended to one or both ends of the stored analog range 1202 to produce the match range 1206. In example embodiments, the fuzzy match range 1204 can be bounded by a lower voltage limit f ( G M1 ) and an upper voltage limitf G M2 ) to capture.

[0128] As an illustrative example, range or range matching can be applied to avoid competitive parallel writes to overlapping regions in connection with updates to fabric-attached storage. For example, if the regions under development are tracked, incoming requests can be checked against outstanding requests, and if a range is found between the new request and an outstanding request, the new request can be queued until the outstanding request completes. It should be understood that the above example application scenario for range searching and matching is merely illustrative and is not exhaustive.

[0129] Figure 13 FIGURE 13 illustrates a flow diagram depicting converting a decision tree to a table structure, in accordance with example embodiments described herein. In this illustration, the flow can depict converting an example decision tree 1302 including a set of decision nodes corresponding to evaluatable conditions representing a set of logical rules to a table structure in which each logical rule is represented as a chain of nodes in the table structure, in accordance with example embodiments of the present disclosure. The decision tree 1302 can correspond to one example implementation of the decision tree 902 in FIGURE 9. Figure 9 Similarly, the feature vector 1300 can correspond to one particular example of the generalized feature vector 900 in FIGURE 8. Figure 9

[0130] The feature vector 1300 can represent a search query specifying values 0.3, 0.0, 0.5, and 0.75 for search variables f1, f2, f3, and f4, respectively. In other example embodiments, the values 0.3, 0.0, 0.5, and 0.75 can represent input voltages, each of which maps to a particular search input value. In such example embodiments, the evaluatable conditions within the root-to-leaf path of the decision tree 1302 can ultimately be converted to a chain of node representations and encoded in the aCAM 1412 in FIGURE 14. Figure 14 These node chain representations can reflect a comparison of the input data line voltage to a stored analog voltage range having a lower voltage limit and an upper voltage limit defined by the conductance quantization of the memristor within the cell of the aCAM encoding the voltage range.

[0131] The root-to-leaf path 1304 can be Figure 9 ​​An example representation of the root-to-leaf path 910 is shown below. The root-to-leaf path 1304 may include the same series of node transitions as the root-to-leaf path 910, specifically, f1 condition 1b -> f3 condition 1b -> f2 condition 2a -> category 2. Relative to the specific evaluable condition encoded in the decision tree 1302, this series of node transitions in the root-to-leaf path 1304 becomes: f1 ≥ 0.2 -> f3 < 0.7 -> f2 < 0.8 -> category 2.

[0132] As previously referenced Figure 9 As described in decision tree 902, each decision node (except for leaf nodes) in decision tree 1302 is associated with an evaluable condition that can cause either result "a" or result "b". Result "a" indicates that the evaluable condition is met (corresponding to the left branch extending from the decision node). Result "b" indicates that the evaluable condition is not met (corresponding to the right branch extending from the decision node). Therefore, taking the evaluable condition (f1 < 0.2) of the root node of decision tree 1302 as an example, result "a" is f1 < 0.2 and result "b" is the result that the condition is not met, i.e., f1 ≥ 0.2.

[0133] In some examples, the decision tree 1302 can be converted into a tabular representation. For example, this involves converting each root-to-leaf path in the decision tree 1302 into a corresponding chain of nodes in the tabular representation. Converting a root-to-leaf path into a corresponding chain of nodes may include: merging two or more nodes from a root-to-leaf path into a single node in the chain; reordering the nodes in the root-to-leaf path to produce a sequence of nodes in the corresponding chain that are identical to the sequence of features / search variables in the feature vector 1300; and / or generating nodes in the chain that correspond to “wildcard” values ​​of features not evaluated in the root-to-leaf path.

[0134] For example, converting the root-to-leaf path 1304 to the node chain 1306 involves reordering the node transitions of the root-to-leaf path 1304 to order the node representing the result of evaluating the condition for f2 in the node chain 1306 before the node representing the result of evaluating the condition for f3. Converting the root-to-leaf path 1304 to the node chain 1306 also includes associating a "wildcard" value with the node corresponding to feature f4, as this feature is not evaluated in the root-to-leaf path 1304. An example of merging node transitions of root-to-leaf paths is shown with respect to the node chain 1310. In particular, the node chain 1310 represents a root-to-leaf path in the decision tree 1302 given by the following node transitions: fl < 0.2 -> f4 < 0.75 -> fl > 0.1 -> class 0. The results of evaluating the two conditions involving feature fl can then be merged into a single node in the node chain 1310 representing the simulated range 0.1 < fl < 0.2. Converting the corresponding root-to-leaf path to the node chain 1310 can also include reordering the node transitions involving feature f4 and associating a "wildcard" value with feature f3.

[0135] In example embodiments, each root-to-leaf path traversable in the decision tree 1302 can be converted to a respective corresponding node chain in the table representation. In some embodiments, the decision tree 1302 can be systematically traversed according to a predetermined traversal scheme to identify each root-to-leaf path, and the node chains can be generated and stored in the table representation in the same sequence as the root-to-leaf paths are traversed. For example, a first root-to-leaf path identified in the decision tree 1302 can be given by a series of node transitions representing the result "a" at each node between the root node and the second-to-last node of the root-to-leaf path, specifically the following series of result transitions: fl < 0.2 to f4 > 0.75 to f2 < 0.8 -> class 0. This first root-to-leaf path traversal can then be converted to the first node chain 1308 in the table representation. In other example embodiments, the sequence of node chains in the table representation can not correspond exactly to the order in which root-to-leaf paths are traversed in the decision tree 1302, so long as each root-to-leaf path in the decision tree 1302 is converted to a corresponding node chain in the table representation.

[0136] Figure 14 Encoding of a set of node chains according to example embodiments described herein is illustrated. The encoding can be with respect to a table representation of a decision tree, such as the table representation 1306 of the decision tree 1302. Figure 13The node chains depicted in the middle correspond to, and are depicted in, the aCAM 1412. The aCAM 1412 can include multiple rows and multiple columns of cells. In this illustration, the aCAM 1412 includes four columns of cells, where each column corresponds to a respective feature / search variable, and eight rows of cells, where each row corresponds to a respective node chain, which in turn corresponds to a respective node-to-leaf path in the decision tree 1302. In example embodiments, each node chain can be rotated and encoded in the cells of the corresponding row of the aCAM 1412. As previously described, each root-to-leaf path, and thus each corresponding node chain, represents a series of evaluatable conditions that make up a logical rule, such as a domain-related logical rule. After the domain logical rules embodied by the node chains are encoded in the aCAM 1412, a search query containing a search variable input set (e.g., the feature vector 1300) matches the encoded rules if the search variable input satisfies the respective evaluatable conditions to which it corresponds.

[0137] In example embodiments, when each row of the aCAM 1412 is a storage word representing an encoded domain logical rule, each column of the aCAM 1412 includes a set of cells that store values or value ranges associated with evaluatable conditions that involve the same feature / search variable across the set of domain logical rules. For example, the cells in the first column of the aCAM 1412 together store all of the analog value ranges associated with evaluatable conditions that involve feature fl across the set of node chains, i.e., the set of domain logical rules. Similarly, the cells of the second column of the aCAM 1412 store all of the analog value ranges associated with evaluatable conditions that involve feature f2 across the set of node chains, the cells of the third column of the aCAM 1412 store all of the analog value ranges associated with evaluatable conditions that involve feature f3 across the set of node chains, etc. It should be understood that when the conversion of the path to node chains is at least partially complete, the node transitions of the root-to-leaf path are reordered to ensure that the proper values are stored in the correct aCAM cells so that search queries can be searched efficiently and matched in parallel with each storage word in the aCAM 1412, i.e., each row.

[0138] In Figure 14 Encoding some example node chains in the aCAM 1412 is illustratively shown in the middle. As previously described, each node chain includes a series of nodes that correspond to a series of evaluatable conditions that represent a particular root-to-leaf path in the decision tree 1302. The example node chain 1308, which includes the following sequence of nodes: fl < 0.2 -> f2 < 0.8 -> * -> f4 > 0.75 -> class 0, is encoded in the first row 1422 of the aCAM 1412. Similarly, the example node chains 1310, 1306 are encoded in rows 1424, 1426 of the aCAM 1412, respectively.

[0139] As an example with node chain 1306, a range of analog values given by f1 > 0.2 is encoded in a corresponding cell of a first column of aCAM 1412. In particular, this range of analog values can be encoded by tuning the conductance amounts of the memristors of the aCAM cell to establish a range of matching voltages for that aCAM cell that represents the range of analog values. The range of matching voltages can be bounded by a lower voltage limit that is a function of the respective conductance amount of a memristor (M1) in the aCAM cell and maps to a value of 0.2 (or is a value of 0.2), and an upper voltage limit that is a function of the respective conductance amount of a memristor (M2) in the aCAM cell. G M1 G M2 The conductance amounts of the memristors in the aCAM cell can be tuned so that the upper voltage limit given by G M2 f G M2 is higher than a maximum line voltage that can be applied to a data line 1414 that is connected to each cell in the first column of aCAM 1412. In this way, any search input value that is greater than or equal to 0.2 for feature f1 (or maps to a data line voltage that is greater than or equal to 0.2) will result in a match for that aCAM cell.

[0140] As another non-limiting example, a second evaluable condition f2 < 0.8 in node chain 1306 is encoded in a corresponding cell of a second column of aCAM 1412. This range of analog values can be encoded by tuning the conductance amounts of the memristors of the aCAM cell to establish a range of matching voltages that is bounded by a lower voltage limit and an upper voltage limit, where the upper voltage limit is a function of the respective conductance amount of a memristor (M2) in the aCAM cell and maps to a value of 0.8 (or is a value of 0.8). G M2 G M1 The conductance amounts of the memristors in the aCAM cell can be tuned so that the lower voltage limit given by f G M1 is lower than a minimum line voltage that can be applied to a data line that is connected to each cell in the second column of aCAM 1412. In this way, any search input value that is less than 0.8 for feature f2 will result in a match for that aCAM cell.

[0141] ​​​​​Additionally, various "wildcard" values in various node chains can be encoded in corresponding cells of aCAM 400. For example, encoding node chain 1306 in row 1426 of aCAM 1412 includes encoding a "wildcard" value corresponding to feature f4 (for which there is no corresponding evaluatable condition in node chain 1306) in aCAM cell in the fourth column of aCAM 1412. In example embodiments, the "wildcard" value is encoded in aCAM cell by tuning the respective conductance of memristor Ml G M1 and the respective conductance of memristor M2 G M2 to establish a matching voltage range bounded by a lower voltage limit f ( G M1 )<V DL,min and an upper voltage limit f ( G M2 )>V DL,max for the aCAM cell. In this way, any data line voltage supplied to the aCAM cell (which must be between V DL,min and V DL,max ) will necessarily fall between the lower voltage limit and the upper voltage limit. Thus, any input search value will result in a match for the aCAM cell encoding the "wildcard" value.

[0142] In some example embodiments, the final nodes in the node chains (which represent the leaf nodes in decision tree 1302) can be stored in a memory array such as RAM 1420 separate from aCAM 1412. This can allow multiple matching results to be returned for a search query seeking to optimize a particular feature / parameter / variable (e.g., the parameter represented by the last node in each node chain). For example, the "category" parameter values stored in RAM 1420 can represent different connection times in the aforementioned flight travel search application scenario or different product costs in the aforementioned product search scenario. In some example embodiments, the analog, range, and / or fuzzy search capabilities of aCAM 1412 can be used to search a domain- dependent logic rule set for a certain optimization criterion. That is, various search capabilities of aCAM 1412 can be leveraged to find rules (e.g., stored words in aCAM 1412) that include a set of constrained variables and optionally one or more free (i.e., "wildcard") variables and that produce a minimum, maximum, or other optimization value for another variable / parameter.

[0143] In example embodiments, a search query represented by feature vector 1300 (<0.3, 0.0, 0.5, 0.75>) can be provided as input to aCAM 1412. To facilitate explanation, the following description of the search and process of matching the query to the stored contents of aCAM 1412 assumes that the values of feature vector 1300 represent input data line voltages that map to corresponding search variable values specified in the search query, and further assumes that the numerical values compared to the feature vector values as part of the example evaluatable condition are the lower voltage limit and upper voltage limit of a stored analog voltage range representing the evaluatable condition. While example feature vector 1300 includes only discrete values, it should be understood that an input search variable can be an analog value range, in which case the value in feature vector 1300 corresponding to that input search variable can be an analog voltage range that maps to the analog value range.

[0144] In example embodiments, aCAM 1412 can reside within a computing device. A processor of the computing device can execute machine executable instructions to cause low latency, parallel searching of aCAM 1412 to be performed based on a search query. The parallel search can include searching input feature vector 1300 in parallel for each row in aCAM 1412. In example embodiments, searching input feature vector 1300 for a given aCAM row includes comparing the value specified for each feature to the stored value or value range in the corresponding cell of the aCAM row. If (for example, and only if) each feature value is equal to the stored value or within the stored value range of the corresponding aCAM cell, then the aCAM outputs a match for the stored word represented by that aCAM row. A match for a given stored word can be output if the voltage on the corresponding match line corresponds to a high logic level (which can be represented by a low voltage or a high voltage on the match line depending on the implementation). The match for a particular stored word indicates that feature vector 1300 satisfies the evaluatable condition associated with the domain logic rule represented by that stored word. On the other hand, if at least one feature value is not equal to the stored value or within the stored analog value range of the corresponding aCAM cell, then that cell can discharge the match line, indicating no match for that stored word.

[0145] For example, comparing the input feature vector 1300 (e.g., <0.3, 0.0, 0.5, 0.75>) to the stored word encoded at row 1426 of aCAM 1412 results in a match because each input search value in feature vector 1300 satisfies the condition embodied in the corresponding cell of aCAM row 1426. More specifically, if the input search value for fl falls within the range of analog values represented in the first aCAM cell that represents an evaluatable condition and is stored in aCAM row 1426, then the input search value satisfies the evaluatable condition (fl > 0.2) embodied in the first aCAM cell in aCAM row 1426. In example embodiments, a match occurs with respect to the evaluatable condition fl > 0.2 if the data line voltage to which the input search variable value specified for feature fl maps is within the stored analog voltage range bounded by a lower voltage limit of 0.2 and an upper voltage limit that is greater than the maximum data line voltage. Thus, as long as the voltage applied on the data line is at least 0.2 or greater, the aCAM cell does not discharge the match line, thereby indicating a match with respect to that aCAM cell. The other aCAM cells of row 1426 also indicate a match (i.e., do not discharge the match line) because f2 = 0.0 < 0.2; f3 = 0.5 < 0.7; and f4 = 0.75 is between 0 and 1. In fact, the aCAM cell corresponding to feature f4 in aCAM row 1426 always outputs a match because that aCAM cell stores a "wildcard" value in the form of an analog voltage range that encompasses any possible data line voltage that can be applied. Since each aCAM cell in aCAM row 1426 matches the corresponding feature value in feature vector 1300, none of the aCAM cells in aCAM row 1426 discharge the match line 1418, thereby maintaining the match line 1418 at a high logic level that indicates a match result.

[0146] In example embodiments, the address of the stored word at aCAM row 1426 in aCAM 1412 can be returned. In some example embodiments, the "category" variable can be a parameter that the user seeks to optimize, in which case the stored word at aCAM row 1426 will only be returned as a match result for feature vector 1300 if the corresponding value of the category parameter (i.e., category 2) satisfies the value of the optimization parameter specified in the search query. For example, if the category parameter represents the total product cost that the user seeks to minimize in a product search application scenario, then the combination of product parameters represented by aCAM row 1426 will be returned as a match result if the corresponding values stored for the total product cost parameter are less than the maximum allowable value specified in the search query.

[0147] In some examples, the feature vector 1300 produces a match result for only the storage word at aCAM row 1426 and can produce mismatches for each other storage word. For example, aCAM cells producing a match for the corresponding feature value in the feature vector 1300 are depicted with shading. In this example, aCAM row 1426 is the only storage word for each aCAM cell in row 1426 shown with shading, indicating a match. For each other storage word in aCAM 1412, at least one feature value specified in feature vector 1300 does not produce a match for the corresponding aCAM cell. For example, feature vector 1300 produces a match for aCAM cells in the second, third, and fourth columns of aCAM 1412. However, feature vector 1300 produces a mismatch for feature fl. In particular, the range of analog voltages encoded in the first aCAM cell of row 1422 bounded by lower limit 0 and upper limit 0.2 does not include fl = 0.3. This causes the pull-down transistor of the aCAM cell to turn on and discharge match line 1416, indicating a mismatch for the storage word at row 1422. Each other storage word in aCAM 1412 (other than the storage word at row 1426) produces a mismatch for the feature vector, including the storage word at row 1424 producing a match for the stored "wildcard" values of features f2 and f3, but producing mismatches for the stored ranges of analog values of features fl and f4.

[0148] Figure 15 An electronic circuit implementing a differentiable CAM cell 1500 is depicted, which can be used to implement any of the CAM cells described herein. In this illustration, differentiable CAM cell 1500 can be similar to aCAM cell 205 of Figure 2 or differentiable CAM cell 1605 of Figure 16 Differentiable CAM cell 1500 includes a high side 1503 and a low side 1506, at least in part because memristor (Ml) and memristor (M2) are programmed to determine values of R 高 and R 低 respectively.

[0149] High side 1503 can include a first transistor (Tl) and a first memristor (Ml). First memristor (Ml) bounds a first voltage divider 1509 with first transistor (Tl) and, when programmed accordingly, bounds a high value R 范围 of a range of values R 高 Low side 1506 includes a second transistor (T2) and a second memristor (M2). Second memristor (M2) bounds a second voltage divider 1511 with second transistor (T2) and, when programmed accordingly, bounds a low value R 高 of a range of values R

[0150] The low side 1506 includes a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), and a second memristor (M2). The second memristor (M2) in combination with the transistors (T3), (T4), (T5) defines a second voltage divider 1512. When the second memristor (M2) is programmed, the memristor (M2) defines a low value R 范围 . 低 .

[0151] The differentiable CAM cell 1500 also includes two match lines (MLhi 1511 and Mllo 1510), two search lines (SLhi and SLlo), and an analog data line aDL. As described herein, the memristor-transistor pairs M1 / T1 and M2 / T3 define respective voltage dividers 1509, 1512. When the memristors M1, M2 are programmed, the voltage dividers 1509, 1512 are used to encode R 高 and R 低 . Thus, in this example, in each of the memristor-transistor pairs M1 / T1 and M2 / T3, an analog search is implemented by determining the gate voltage of the voltage divider transistor to form a variable resistance voltage divider with a memristor programmed to an analog (stored) value.

[0152] The second transistor (T2) and the sixth transistor (T6) are attached to the two match lines (MLhi 1511, MLlo 1510), which allows for a threshold voltage to exist within a range of values. When the aggregate data line (aDL) input voltage is outside the threshold range, the pull-down transistor T2 turns on, which pulls down the match line (ML), resulting in a "mismatch" result outside the threshold range. Similarly, the memristor (M2) and transistor T3 form another voltage divider 1512. The internal voltage node is inverted by transistors T4, T5 before being applied to another pull-down transistor T6. Thus, with the appropriate programmed resistance amounts in the memristors M1, M2, the differentiable CAM cell 1500 will hold the match line between the threshold range when the voltage on the aggregate data line (aDL) is within a certain range defined by the M1 and M2 resistance amounts. As such, the differentiable CAM cell 1500 can sense the discharge current through T2 and T6. Moreover, because of the analog operation of the cell, the transition between match and mismatch is smooth. In traditional aCAM operation, a sense amplifier is utilized to improve the transition between match and mismatch. However, the differentiable CAM (dCAM) operation allows the sense block to sense the voltage on the analog data line (aDL) and the difference between a strong match and a mismatch.

[0153] Figure 16 A selected portion of a cell array of a differentiable CAM cell is illustrated in accordance with example embodiments described herein. In this example, Figure 1 a portion of the aCAM 100 is provided withFigure 15 The plurality of differentiable CAM cells 1500 are arranged as a dCAM 1605 in a cell array 1600.

[0154] The differentiable CAM cells 1605 are arranged in rows 1610 and columns 1615 and each can be accessed via data lines aDL0, aDL1,..., aDL w The individual search, where "w" is the width of the array. The data in the row passed through the programmed values of Ml and M2 of each differentiable CAM cell on each aDL is indicated in the match line MLlo 1510 and MLhi 1511 threshold range. As will be appreciated by those of ordinary skill having the benefit of the present disclosure, the cell array 1600 can be larger than the 3x3 array as illustrated in Figure 16 . The exact size can be implementation specific. The 3x3 portion is shown for illustrative purposes and is not limiting. Each differentiable CAM cell 1605 includes two memristors Ml, M2 (not shown individually) for defining a range of values stored in the respective differentiable CAM cell 1605.

[0155] The sense circuit block 1620 can sense the analog values from the differentiable CAM cells 1605 of each row 1610 of the array. The sense circuit block 1620 includes a sense amplifier 1710 as seen in Figure 17

[0156] An illustrative sense circuit block 1620 is provided in Figure 17 . In this example, the sense circuit block 1620 can include a training component and an operational component. The training component includes an analog-to-digital converter (ADC) 1720 and a transimpedance amplifier (TIA) 1730. The operational component includes the sense amplifier 1710. The training component can be performed prior to the operational component to train the model and tune the pattern of appropriate weights of the learning algorithm. The ADC 1720 can sense the output voltage and of the TIA 1730. The TIA 1730 can convert the current I_ML to a voltage. The TIA 1730 output is connected to the ADC 1720 input to convert the sensed current to the digital domain.

[0157] During training, the analog output is used to sense the distance of the input from each stored word. The analog output is then compared to the desired output and using the analog output, how to update the stored words in the differentiable CAM array is determined. The ADC 1720 and TIA 1730 can be turned off and the sense amplifier 1710 can be connected to to compare to the and obtain a digital / binary output. ​

[0158] During operation, the sense amplifier 1710 converts the analog output voltage V_ML_hi of a differentiable CAM row to a binary match / no-match signal by comparing it to the threshold voltage V_th shown in Figure 16 The sense amplifier 1710 converts the analog output voltage to a binary match / no-match signal by comparing it to the threshold voltage V_th shown in

[0159] Figure 18 An overview of an illustrative learning-to-storage (L2S) process implemented by a differentiable CAM array according to example embodiments described herein is provided. Here, the process includes generating an L2S dataset, generating a differentiable (Diff) CAM post-layout model, and programming final conductance quantities G to hardware to perform final testing.

[0160] At block 1830, an L2S dataset can be generated. A dataset of learning values can be generated from the thresholds, and the dataset can be provided to a differentiable CAM (dCAM) to learn the thresholds as patterns to storage. After the learning values are provided to the differentiable CAM, the L2S dataset can be generated using the thresholds as patterns.

[0161] At block 1840, a differentiable CAM post-layout model is generated by an L2S operation. In one embodiment, the post-layout model includes a pyTorch model of the differentiable CAM generated by the L2S operation. In this embodiment, the L2S operation optimizes a cross-entropy loss function using the following equation.

[0162]

[0163] H corresponds to the number of rows in the CAM. represents a target row (e.g., row 5) in which a pattern is stored. may be a target for storing a pattern in row 5 of a CAM array having rows. The SoftMax function:

[0164]

[0165] is determined as a function of V ML,hi according to the following equation:

[0166] if ， where ,

[0167] if​

[0168] At each epoch, the model can return the conductance amounts to be programmed in the CAM memristors updated to minimize the loss. The model can maximize the ML voltage for the row that should store a given pattern and minimize the ML voltage elsewhere. At the end of the L2S operation, the final conductance amounts G can be used to test the system's DT inference accuracy. The testing process can provide unseen data from the test dataset (e.g., as search vectors) and record the predicted class corresponding to the match of the row.

[0169] At block 1850, the resulting G is programmed to the hardware to perform a final test. Various issues can be addressed. For example, while traditional aCAMs (compared to TCAMs) are very powerful due to the compression of multi-bit representations and the possibility of releasing new applications (such as tree-based machine learning, etc.), some inference calculations can be inaccurate. Given the loss function above, the differentiable CAM can learn the conductance amount values to store in the CAM, which can recover the inference accuracy of the software equivalent.

[0170] Figure 19 An illustrative learn-to-store (LS2) process implemented by a differentiable CAM array is provided in accordance with example embodiments described herein. At block 1910, a dataset can be received. The dataset can include various types of data, including tabular data (e.g., iris, etc.) or image data (e.g., digits, etc.). At block 1920, a model can be trained. The model can correspond to a decision tree (DT) and the training can use a software machine learning library of one or more programming languages (e.g., SKLearn or scikit-learn). Training the model can generate weights, biases, thresholds, or other programmable values and learned values for the model. Further, thresholds can be extracted from the trained model.

[0171] At block 1930, a learn-to-store (L2S) dataset can be generated. A dataset of learned values can be generated based on the thresholds and provided to a differentiable CAM (dCAM) to learn the thresholds as patterns (i.e., if the thresholds must be learned from 0 to 0.5 into the dCAM). Thus, after the learned values are provided to the differentiable CAM, the L2S dataset can be generated using the thresholds as patterns. For example, the differentiable CAM can be provided with thresholds between zero and five.

[0172] At block 1940, a differentiable CAM layout post-model can be generated from the live of block 1840. At each epoch, the model can return the conductance amounts to be programmed in the CAM memristors The update is to minimize the loss. In some examples, the goal of this process can be to minimize the error in performing a search operation. This can maximize the ML voltage of the row that should store a given pattern and minimize the ML voltage elsewhere.

[0173] At the end of the L2S operation, the final conductance quantities G can be used to test the DT inference accuracy of the system. The testing process can provide unseen data from the test dataset (e.g., as search vectors) and record the predicted class corresponding to the match of the row.

[0174] At block 1950, the final conductance quantities G generated by the L2S operation are programmed into hardware to perform a final test. In addition to the example problem addressed at block 1850, the processes discussed herein can improve the aCAM programming process. For example, the programming can operate the aCAM in an array configuration, increase the number of bits per cell, and / or increase the maximum array width (columns). The algorithms discussed herein can be parasitic-aware and maximize the number of elements that can be stored for a given array width. The capacitance on the ML can be increased by directly sensing this capacitance. Additionally, the programming allows for writing the fuzzy threshold for tree-based machine learning applications.

[0175] Figure 20 Adaptation to memristor noise comparisons is illustrated in accordance with example embodiments described herein. In these illustrations, the memristor has programmed variations (as shown in graph 2010) and read noise (as shown in graph 2040) that can affect accuracy if inaccuracy is not accounted for in programming. Graph 2010 illustrates the write variability of each memristor. The plots in graph 2010 represent the cumulative distribution function of the actual conductance quantities of a plurality of memristors programmed to have 16 different states. Each vertical line represents a different state.

[0176] By using L2S with the differentiable CAM described herein, the processes performed can not lose accuracy in determining the inference of a decision tree (DT) with the variations in the memristor programming. These processes can not lose accuracy because the training operation of the memristor conductance quantities takes into account their variations as shown in graph 2020.

[0177] As seen in graphs 2020 and 240, the percentage of average error is plotted along the read noise. The error is determined according to the following equation :

[0178]

[0179] where, is the inference accuracy, and This refers to the hardware inference accuracy obtained using differentiable CAM. In some examples, the subthreshold operation of a transistor (e.g., current output) can be highly sensitive to process variations because the current is related to the threshold voltage. It exhibits an exponential relationship. In some examples, Variations can reach 20% in contemporary process nodes and can produce exponential variations in subthreshold currents. These correlations can significantly impact analog CAM operation (because matched / mismatched operation is highly influenced by the discharge current through the divider between each cell and the memristor and transistor conductance). L2S operation provides the ability to train stored values ​​while taking into account specific process variations present in the circuit, thus enabling analog CAM operation that adapts to process variations. The ability to extend analog CAM operation to the subthreshold range can correspond to reducing the ISO accuracy of power consumption on SLs (e.g., dividers M1-T1, M2-T3) by training analog CAM conductances using L2S.

[0180] In some examples, differentiable CAMs can advantageously provide a learning memory where L2S processes can be implemented. Using this approach, the accuracy of the simulated CAM is improved. This improvement in CAM accuracy can be at least partially demonstrated by achieving the software equivalent accuracy of DT inference. Furthermore, differentiable CAMs can adapt to memristor programming variations and read noise, and allow the use of input transistors T1 and T3 in the subthreshold range, resulting in a reduction in SL power consumption (e.g., a threefold reduction). Figure 20 As further seen in Figure 2030, the read variability of each memristor is illustrated. Here, multiple memristors are programmed to random simulated states and are then read multiple times over time.

[0181] Figure 21 A computing unit 2100 is described, comprising one or more hardware processors 2102 and a machine-readable storage medium 2104, the machine-readable storage medium storing, when executed, a set of machine-readable / machine-executable instructions that causes the hardware processors 2102 to execute illustrative methods for providing differentiable CAM, which improves an analog CAM system by implementing analog input analog storage and analog output learning memory.

[0182] For example, the computing component 2100 may be Figure 22 The computer system 2200 depicted herein. The hardware processor 2102 may include, for example... Figure 22 The processor(s) 2204 depicted herein or any other processing unit described herein. The machine-readable storage medium 2104 may include main memory 2206, read-only memory (ROM) 2112, storage device 2214, and / or any other suitable machine-readable storage medium described herein.

[0183] At block 2106, hardware processor(s) 2102 can execute machine readable / machine executable instructions stored in machine readable storage medium 2104 to compute a threshold sufficient to turn on a sense amplifier (SA) and discharge a match line (ML) of a cell connected to the aCAM.

[0184] At block 2108, hardware processor(s) 2102 can execute machine readable / machine executable instructions stored in machine readable storage medium 2104 to program a match line (ML) value. For example, based on computing the threshold current, these instructions can program the match threshold by setting the memristor conductance amount in association with a target analog voltage range applied to a data line (DL) input.

[0185] Figure 22 A block diagram of an example computer system 2200 in which various embodiments described herein can be implemented is depicted. Computer system 2200 includes a bus 2202 or other communication mechanism for communicating information, and one or more hardware processors 2204 coupled with bus 2202 for processing information. Hardware processor(s) 2204 can be, for example, one or more general purpose microprocessors.

[0186] Computer system 2200 also includes a main memory 2206, such as a random access memory (RAM), cache and / or other dynamic storage devices, coupled to bus 2202 for storing information and instructions to be executed by processor(s) 2204. Main memory 2206 also can be used for storing temporary variables or other intermediate information during execution of instructions to be executed by processor(s) 2204. Such instructions can be stored in a memory storage medium accessible to processor(s) 2204, when executed, to cause computer system 2200 to perform operations specified by the instructions.

[0187] Computer system 2200 additionally includes hardware accelerator 2208. Hardware accelerator 2208 may be configured to execute instructions (i.e., programming code or software code) stored in main memory 2206, read-only memory (ROM), and / or storage device 2214 to encode a set of logical rules embodied in a data structure (e.g., decision tree 902) into a CAM array 2210. In an example implementation, exemplary hardware accelerator 2208 may include multiple integrated circuits, which may further include application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other very large-scale integrated circuits (VLSIs). The integrated circuits of exemplary hardware accelerator 2208 may be specifically optimized to perform a discrete subset of computer processing operations in an accelerated manner, or to execute a discrete subset of computer-executable instructions. For example, hardware accelerator 2208 may be configured or manufactured to implement a set of logical rules embodied in a data structure such as decision tree 902 on aCAM array 2210.

[0188] aCAM array 2210 may include non-volatile memory constructed using techniques including, for example, resistive random access memory (i.e., memristors), phase-change memory, magnetoresistive memory, ferroelectric memory, some other resistive random access memory device (Re-RAM), or combinations of these techniques. More generally, aCAM array 2210 may be implemented using techniques that allow aCAM array 2210 to retain its contents even when power is lost or otherwise removed. Therefore, data in aCAM array 2210 is "persistent," and aCAM array 2210 can act as a so-called "non-volatile memory."

[0189] Computer system 2200 also includes read-only memory (ROM) 2212 or other static storage devices coupled to bus 2202 for storing static information and instructions of processor 2204. Storage devices 2214, such as disks, optical discs, or USB thumb drives (flash drives), are provided and coupled to bus 2202 for storing information and instructions.

[0190] Computer system 2200 can be coupled to display 2216, such as a liquid crystal display (LCD) (or touchscreen), via bus 2202 to display information to the computer user. Input device 2218, including alphanumeric keys and other keys, is coupled to bus 2202 to transmit information and command selections to processor 2204. Another type of user input device is cursor control 2220, such as a mouse, trackball, or cursor arrow keys, to transmit directional information and command selections to processor 2204 and control cursor movement on display 2216. In some embodiments, the same directional information and command selections as those of the cursor control can be implemented via receiving touch on the touchscreen without a cursor.

[0191] Computer system 2200 can include a user interface module for implementing a GUI that can be stored in a mass storage device as executable software code that is executed by the computing device(s). This and other modules can include, by way of example, components, such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables.

[0192] Generally, the words "component," "engine," "system," "database," "data store," and the like, as used herein, can refer to logic either in hardware or firmware or software implementing the logic. The software implementing the logic can be written in an interpreted language or a compiled language, and can be executed by a computer using a virtual machine or by a central processing unit. A component can be compiled and linked into an executable program, installed in a dynamically linked library, or can be written in an interpreted language such as BASIC, Perl, or Python. It will be appreciated that software components can be callable from other components or from themselves, and / or can be invoked in response to detected events or interrupts. Software components configured for execution on the computing device can be provided on a computer readable medium, such as a compact disc, digital video disc, flash drive, magnetic disc, or any other tangible medium, or as a digital download (and can be originally stored in an electronically readable medium such as a memory before being stored on a tangible medium or downloaded). Such software code can be stored and / or transmitted using a storage medium, such as a magnetic floppy or hard disk, an optical disk (e.g., a compact disc or a Blu-ray disc), a flash drive, a memory stick, or a magnetic tape. Further, it will be appreciated that storage media can be embodied in a computer readable medium, which include both volatile and nonvolatile media, removable and nonremovable media used in the operation and / or management of the computing device. A computer readable medium can include an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system, apparatus, or device.

[0193] Computer system 2200 can implement the techniques described herein using customized hard-wired logic, one or more ASICs or FPGAs, firmware and / or program logic which in combination with the computer system causes or programs computer system 2200 to be a special-purpose machine. According to one embodiment, the techniques herein are performed by computer system 2200 in response to the one or more processors 2204 executing one or more sequences of instructions contained in main memory 2206. Such instructions can be read into main memory 2206 from another storage medium, such as storage device 2214. Execution of the sequences of instructions contained in main memory 2206 causes the one or more processors 2204 to perform the process steps described herein. In alternative embodiments, hard-wired circuitry can be used in place of or in combination with software instructions.

[0194] The term "non-transitory medium" and similar terms as used herein (e.g., machine-readable storage medium) refer to any medium that stores the data and / or instructions that cause a machine to operate in a specific fashion. Such non-transitory media can include non-volatile media and / or volatile media. Non-volatile media includes, for example, optical or magnetic disks, such as storage device 2214. Volatile media includes dynamic memory, such as main memory 2206. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid-state drive, magnetic tape, or any other magnetic data storage medium, a CD-ROM, any other optical data storage medium, any physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH- EPROM, NVRAM, any other memory chip or cartridge, and networks or networking links that are used to transfer data to and from a computer system 2200.

[0195] Non-transitory media is distinct from, but can be used in combination with, transmission media. Transmission media participate in transferring information between non-transitory media. For example, transmission media includes coaxial cables, copper wire, and optical fibers, including wires that comprise bus 2202. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency and infrared data communications.

[0196] Computer system 2200 also includes a communication interface 2222 coupled to bus 2202. Communication interface 2222 provides a two-way data communication coupling to one or more network links that are connected to one or more local networks. For example, communication interface 2222 can be an integrated services digital network (ISDN) card, cable modem, satellite modem, or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, communication interface 2222 can be a local area network (LAN) card to provide a data communication connection to a compatible LAN (or WAN component to communicate with a WAN). Wireless links can also be implemented. In any such implementation, communication interface 2222 sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

[0197] Network links typically provide data communication through one or more networks to other data devices. For example, a network link can provide a connection through a local network to a host computer or to data equipment operated by an Internet Service Provider (ISP) to other data devices operated by customers to the ISP. The ISP in turn provides data communication services through the world wide packet data communication network now commonly referred to as the "Internet." Local networks and the Internet both use electrical, electromagnetic, or optical signals that carry digital data streams. The signals through the various networks and the signals on network links and through communication interface 2222, which carry the digital data to and from computer system 2200, are example forms of transmission media.

[0198] Computer system 2200 can send messages and receive data, including program code, through the network(s), network link(s), and communication interface(s) 2222. In the Internet example, a server might transmit a requested code for an application program through the Internet, ISP, local network and communication interface 2222. The received code can be executed by processor 2204 as it is received, and / or stored in storage device 2214, or other non-volatile storage for later execution.

[0199] Each of the processes, methods, and algorithms described in the preceding sections can be embodied in, and fully or partially automated by, code components of one or more computer systems or computer processors that execute the code components, and by other mechanisms that are separate from and / or that operate in conjunction with one or more computer systems or computer processors that execute the code components. The one or more computer systems or computer processors can also operate to support performance of the relevant operations in a "cloud computing" environment or as a "software as a service" (SaaS). The various features and processes described above can be used independently of one another or can be combined in various ways. Different combinations and sub-combinations of the features and processes can be made. Certain features and processes can be omitted, or other

[0200] As used herein, a circuit can be implemented using any form of hardware, software or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FPGAs, logical components, software routines or other mechanisms might be implemented to make up a circuit. In implementation, the various circuits described herein might be implemented within one or more circuits, and might be shared among one or more circuits. Even though various features or elements of the described product might be described and claimed as separate circuits or components, these features or elements might be shared among one or more common circuits, and such description or claim should not be understood as requiring or implying that separate circuits or components are necessarily related to the efficient implementation of the described product. No element, component or

[0201] As used herein, the term "or" can be construed in either an inclusive or exclusive sense. Furthermore, as used herein, a singular resource, operation, or structure can be described as being "adapted" or "configured" to perform a certain action or function, or to achieve certain results. Unless specifically stated, or as understood by one of ordinary skill in the art from the context, the description herein of performing an action or a function, or achieving certain results, can take place in one implementation at a different time, or in a different space than other implementations. Unless specifically stated, or as understood by one of ordinary skill in the art from the context, the description herein of a feature, structure, or means can be interpreted to mean that the feature, structure, or means is an example of the feature, structure, or means that can be used, even if that specific feature, structure, or means is not explicitly described herein.

[0202] Unless specifically stated otherwise, and as can be apparent from the context, discussions utilizing terms such as "processing," "computing," "calculating," "determining," "displaying," or the like, can refer to actions or processes of a machine that manipulates or transforms data represented as physical electronic or magnetic quantities within memories, registers, or other information storage devices. Unless specifically stated otherwise, and as can be apparent from the context, the foregoing can collectively be construed as either singular or plural acts, and can include an undesired state as being either an included state or a process that is at least a part of an overarching process. Examples of states and processes can include an action, a finding, a transaction, a result, a state, a process, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a result, a

Claims

1. A differential content addressable memory (dCAM) array, comprising: a plurality of rows and a plurality of columns of dCAM cells, wherein each row of dCAM cells comprises a high match line and a low match line; a sense circuit electrically connected to the high match line and the low match line, wherein the sense circuit comprises: a transimpedance amplifier (TIA) configured to sense a match line current on the low match line, and an analog-to-digital converter (ADC) configured to sense an output voltage of the TIA and a match line voltage of the high match line; and a digital-to-analog converter (DAC) electrically connected to each column of dCAM cells.

2. The dCAM array of claim 1, wherein, the DAC is configured to apply an aggregate data line input voltage to each column of dCAM cells.

3. The dCAM array of claim 1, wherein, the sense circuit is configured to sense the match line voltage, the match line current, and a sense voltage.

4. The dCAM array of claim 1, further comprising: a plurality of transistors comprising a first transistor and a second transistor electrically connected to the high match line and the low match line, wherein the TIA is configured to sense a discharge current through the first transistor and the second transistor via the match line current on the low match line.

5. The dCAM array of claim 4, further comprising: an aggregate data line electrically connected to a third transistor and a fourth transistor, wherein a drain of the third transistor is electrically connected to a gate of the first transistor, wherein a drain of the fourth transistor is electrically connected to a gate of a fifth transistor and the drain of the fourth transistor is electrically connected to a gate of a sixth transistor, and wherein a source of the sixth transistor and a drain of the fifth transistor are coupled to a gate of the second transistor.

6. The dCAM array of claim 5, wherein, the third transistor and the fourth transistor are electrically connected to a high search line and a low search line.

7. The dCAM array of claim 6, wherein, the fifth transistor is electrically connected to the low search line and the sixth transistor is electrically connected to the high search line.

8. The dCAM array of claim 7, wherein, the drain of the fifth transistor is electrically connected to the drain of the sixth transistor.

9. The dCAM array of claim 7, wherein, the sense circuit further comprises: a sense amplifier electrically connected to the high match line, wherein the sense amplifier is configured to sense the match line voltage of the high match line and a sense voltage.

10. The dCAM array of claim 9, wherein, the TIA and the ADC are configurable to be turned off during a training operation, and wherein the sense amplifier is further configured to sense the match line voltage on the high match line once the TIA and the ADC are turned off.

11. A sense circuit, comprising: a training component comprising: an analog-to-digital converter (ADC) electrically connected to a transimpedance amplifier (TIA), wherein the ADC is electrically connected to a first match line, wherein the TIA is electrically connected to a second match line, wherein the TIA is configured to sense a current of the second match line and return an output voltage to the ADC, and wherein the ADC is configured to sense the output voltage of the TIA and a first match line voltage of the first match line; and an operational component comprising: a sense amplifier electrically connected to the first match line, wherein the sense amplifier is configured to sense the first match line voltage and a sense voltage during a training operation.

12. The sensing circuit of claim 11, wherein, the TIA and the ADC are configurable to be turned off during the training operation.

13. The sensing circuit of claim 12, wherein, the sense amplifier is further configured to sense the first match line voltage once the TIA and the ADC are turned off.

14. The sensing circuit of claim 13, wherein, the sense amplifier is further configured to compare the first match line voltage to the sense voltage to determine a binary output value.

15. The sensing circuit of claim 11, wherein, the ADC is configured to learn a pattern using the output voltage and the first match line voltage.

16. A method for training a differential content addressable memory (dCAM) model, comprising: sensing, by a transimpedance amplifier (TIA), a current of a second match line of a sensing circuit, the sensing circuit comprising an analog-to-digital converter (ADC) electrically connected to the TIA, wherein the ADC is electrically connected to a first match line and the TIA is electrically connected to the second match line; converting, by the TIA, the current to an output voltage; sensing, by the ADC, the output voltage and a first match line voltage of the first match line from the TIA; sensing, by a sense amplifier of the sensing circuit, the first match line voltage and a sense voltage; and training the dCAM model based on the output voltage and the sense voltage.

17. The method of claim 16, further comprising: turning off the TIA and the ADC during a training.

18. The method of claim 17, wherein, sensing, by the sense amplifier, the first match line voltage once the TIA and the ADC are turned off.

19. The method of claim 18, further comprising: comparing, at the sense amplifier, the first match line voltage to the sense voltage; and determining a binary output value based on the comparison.

20. The method of claim 16, further comprising: learning, by the ADC, a pattern from the output voltage and the first match line voltage.

Images