Display panel, manufacturing method thereof, and display device

Abstract

Provided are a display panel and a manufacturing method therefor, and a display device. The display panel comprises a substrate (BP), a driving layer (CL) and a light-emitting layer (EE); the driving layer (CL) comprises a plurality of groups of pixel circuits (PDCA), a source-drain metal layer (SD) of the driving layer (CL) comprises an auxiliary electrode (PA), and the auxiliary electrode (PA) is located on one side of one group of pixel circuits (PDCA); and the light-emitting layer (EE) comprises a light-emitting device and a transfer structure (PAS), a second electrode (COM) of the light-emitting device covers at least part of the transfer structure (PAS) and is connected to the auxiliary electrode (PA). The setting of the auxiliary electrode (PA) can effectively improve the potential uniformity of the second electrode (COM); and because the light-emitting functional layer (EL) simultaneously covers the first electrode (An) and the transfer structure (PAS), the manufacturing process is simplified relative to a patterned light-emitting functional layer (EL).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] With the rapid development of display panels, users have increasingly higher requirements for the display quality. A display panel includes multiple light-emitting devices to display images by emitting light. Each light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode stacked sequentially, with multiple light-emitting devices sharing the second electrode. During the control of image display, the voltage drop across the second electrode causes uneven distribution of light points on the electrode, resulting in varying brightness among the multiple light-emitting devices and thus uneven brightness of the displayed image.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a display panel, a method for manufacturing the same, and a display device.

[0005] According to a first aspect of this disclosure, a display panel is provided, comprising:

[0006] substrate;

[0007] A driving layer is located on one side of the substrate and includes multiple sets of pixel circuits distributed along the row direction. The driving layer includes a source / drain metal layer, and the source / drain metal layer includes an auxiliary electrode that corresponds one-to-one with at least one set of the pixel circuits, and one of the auxiliary electrodes is located on one side of the corresponding set of pixel circuits.

[0008] A light-emitting layer is located on the side of the driving layer facing away from the substrate. The light-emitting layer includes light-emitting devices and a transition structure distributed at intervals. The orthographic projections of the transition structure and the auxiliary electrode on the substrate have overlapping areas. The light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode distributed sequentially in a direction away from the substrate. The first electrode is connected to a pixel circuit. The light-emitting functional layer covers the first electrode and the transition structure, and forms a break at at least a portion of the edge of the transition structure. The second electrode covers the light-emitting functional layer and the exposed portion of the transition structure at the break in the light-emitting functional layer, and is connected to the auxiliary electrode.

[0009] According to any of the display panels described in this disclosure, the driving layer has an opening facing the light-emitting layer, and at least a portion of the edge of the transition structure is orthogonally projected onto the substrate within the orthogonal projection of the opening onto the substrate.

[0010] The auxiliary electrode includes an exposed portion at the opening, the light-emitting functional layer includes a covering portion and a partition portion, the covering portion and the partition portion form a discontinuity at at least a portion of the edge of the transition structure, the covering portion covers the first electrode and the transition structure, the partition portion is located inside the opening, and at least a portion of the edge of the orthographic projection of the exposed portion of the auxiliary electrode on the substrate extends beyond the orthographic projection of the partition portion on the substrate.

[0011] The second electrode covers the side of the adapter structure and the portion of the exposed portion not covered by the partition portion, and the portion of the second electrode covering the light-emitting functional layer and the portion covering the exposed portion are continuous.

[0012] According to any of the display panels described in this disclosure, the transition structure has an opening, and at least a portion of the opening edge of the transition structure is projected onto the substrate in the orthographic projection of the opening onto the substrate.

[0013] According to any of the display panels described in this disclosure, the opening of the transition structure coincides with the center line of the opening of the driving layer, and the opening size of the opening is smaller than the opening size of the opening.

[0014] According to any of the display panels described in this disclosure, the edge of the transition structure extends into the area corresponding to the opening by a length greater than or equal to 0.8 micrometers and less than or equal to 1.2 micrometers.

[0015] According to any of the display panels described in this disclosure, the transition structure includes a first conductive layer, a metal layer, and a second conductive layer sequentially distributed along a direction away from the substrate.

[0016] At least a portion of the edge of at least one of the structural layers, the first conductive layer, the metal layer, and the second conductive layer, is projected onto the substrate within the orthogonal projection of the opening onto the substrate, and the orthogonal projections of the remaining structural layers onto the substrate and the orthogonal projections of the opening onto the substrate do not overlap.

[0017] According to any of the display panels described in this disclosure, the first conductive layer, the metal layer, and the second conductive layer all have openings;

[0018] The opening edges of the first conductive layer and the metal layer are flush with the hole wall of the opening, and at least a portion of the opening edge of the second conductive layer is projected onto the substrate within the projection of the opening onto the substrate.

[0019] According to any of the display panels described in this disclosure, the adapter structure is connected to the auxiliary electrode via a via.

[0020] According to any of the display panels described in this disclosure, the transition structure includes a first conductive layer, a third conductive layer, a metal layer, and a second conductive layer sequentially distributed along a direction away from the substrate.

[0021] The first conductive layer is connected to the auxiliary electrode through a via. The material of the third conductive layer is an inorganic material. The orthographic projection of the metal layer on the substrate is located within the orthographic projection of the third conductive layer on the substrate, and at least a portion of the edge of the second conductive layer extends beyond the edge of the metal layer.

[0022] The light-emitting functional layer covers the first electrode, the second conductive layer, and the third conductive layer, and the light-emitting functional layer forms a break at the edge of the second conductive layer to expose at least a portion of the third conductive layer and / or the side of the metal layer. The second electrode also covers the portion of the third conductive layer not covered by the light-emitting functional layer and / or the side of the metal layer.

[0023] According to any of the display panels described in this disclosure, the edge of the orthographic projection of the metal layer on the substrate is located within the orthographic projection of the second conductive layer on the substrate.

[0024] According to any of the display panels described in this disclosure, the source / drain metal layer includes a plurality of power lines corresponding one-to-one with the plurality of pixel circuits, one power line being connected to a corresponding group of pixel circuits, and one power line being located on the side of the corresponding group of pixel circuits away from the auxiliary electrode.

[0025] According to any of the display panels described in this disclosure, the auxiliary electrode has an extension on the side opposite to the corresponding power line, the adapter structure and the extension have overlapping areas in their orthogonal projections on the substrate, and the second electrode covers the adapter structure and is connected to the extension.

[0026] According to any of the display panels described in this disclosure, the pixel circuit includes a first transistor, a second transistor, a third transistor, and a storage capacitor;

[0027] The control electrode of the first transistor is connected to the first plate of the storage capacitor and the first electrode of the second transistor. The first electrode of the first transistor is used to load a power signal. The second electrode of the first transistor is connected to the second plate of the storage capacitor and the first electrode of the third transistor, and is also connected to a first electrode.

[0028] The control electrode of the second transistor is used to load the first scan signal, and the second electrode of the second transistor is used to load the data signal;

[0029] The control electrode of the third transistor is used to load the second scan signal, and the second electrode of the third transistor is used to load the sensing signal.

[0030] According to any of the display panels described in this disclosure, the driving layer includes:

[0031] A shielding layer is located on one side of the substrate and includes a shielding sheet;

[0032] A semiconductor layer is located on the side of the shielding layer away from the substrate, and includes active portions of the first transistor, the second transistor, and the third transistor. The active portion includes a channel region and two connection portions located on both sides of the channel region.

[0033] A gate metal layer is located on the side of the semiconductor layer away from the substrate, and includes a first scan line, a second scan line and a second electrode of the storage capacitor. The first scan line loads the first scan signal at the control electrode of the second transistor, and the second scan line loads the second scan signal at the control electrode of the third transistor.

[0034] The source and drain metal layers are located on the side of the gate metal layer away from the substrate, and also include power lines, data lines, sensing lines and the first plate of the storage capacitor. The power lines load the power signal at the first electrode of the first transistor, the data lines load the data signal at the second electrode of the second transistor, the sensing lines load the sensing signal at the second electrode of the third transistor, and the first plate of the storage capacitor is directly opposite to the shielding sheet and connected through a via.

[0035] A planarization layer is located on the side of the source / drain metal layer opposite to the substrate, and at least covers the power line, the data line, the sensing line, the first plate of the storage capacitor, and the auxiliary electrode.

[0036] According to any of the display panels described in this disclosure, a group of pixel circuits includes a plurality of circuit units distributed in a column direction, and one circuit unit includes four pixel circuits distributed in two rows and two columns. For one circuit unit:

[0037] The power line and the auxiliary electrode both extend along the column direction and are distributed along the row direction. The power line applies a power signal to the first electrode of the first transistor of the four pixel circuits.

[0038] The four shielding plates are located between the power line and the auxiliary electrode, and the orthographic projections of the first plate and the second plate of each storage capacitor on the substrate are all located within the orthographic projections of the shielding plates of the same pixel circuit on the substrate.

[0039] Both the first scan line and the second scan line extend along the row direction and are located between the two blocking plates along the column direction. The first scan line is loaded with a first scan signal at the control electrode of the second transistor of the four pixel circuits, and the second scan line is loaded with a second scan signal at the control electrode of the third transistor of the four pixel circuits.

[0040] The data lines extend along the column direction, and each of the two shielding plates along the row direction has a data line on both sides. The four data lines are located between the power line and the auxiliary electrode, and a data line loads a data signal on the second electrode of the second transistor of the pixel circuit.

[0041] The sensing line extends along the column direction and is located between the two blocking plates along the row direction. The sensing line is the second electrode of the third transistor of the four pixel circuits that loads the sensing signal.

[0042] According to a second aspect of this disclosure, a method for manufacturing a display panel is provided, the method comprising:

[0043] Provide a substrate;

[0044] A driving layer is fabricated on one side of the substrate. The driving layer includes multiple sets of pixel circuits distributed along the row direction. The driving layer includes a source / drain metal layer. The source / drain metal layer includes auxiliary electrodes that correspond one-to-one with at least one set of the pixel circuits, and one of the auxiliary electrodes is located on one side of the corresponding set of pixel circuits.

[0045] A first electrode layer is fabricated on the side of the driving layer opposite to the substrate. The first electrode layer includes first electrodes and a transition structure distributed at intervals. A first electrode is connected to a pixel circuit. The orthographic projections of the transition structure and the auxiliary electrode on the substrate have overlapping areas.

[0046] The adapter structure and the driving layer are etched to form an opening in the driving layer that faces the first electrode layer and exposes the auxiliary electrode. At least a portion of the edge of the adapter structure is projected onto the substrate in the orthographic projection of the opening onto the substrate.

[0047] A light-emitting functional layer is formed on the side of the first electrode layer away from the substrate. The light-emitting functional layer includes a covering portion and a partition portion. The covering portion covers the first electrode and the transition structure. The partition portion is located in the opening. The covering portion and the partition portion form a break at at least a portion of the edge of the transition structure. At least a portion of the edge of the orthographic projection of the exposed portion of the auxiliary electrode on the substrate extends beyond the orthographic projection of the partition portion on the substrate.

[0048] A second electrode is fabricated on the side of the light-emitting functional layer away from the substrate. The second electrode covers the light-emitting functional layer and the portion of the exposed portion of the auxiliary electrode that is not covered by the partition portion.

[0049] According to a third aspect of this disclosure, a method for manufacturing a display panel is provided, the method comprising:

[0050] Provide a substrate;

[0051] A driving layer is fabricated on one side of the substrate. The driving layer includes multiple sets of pixel circuits distributed along the row direction. The driving layer includes a source / drain metal layer. The source / drain metal layer includes auxiliary electrodes that correspond one-to-one with at least one set of the pixel circuits, and one of the auxiliary electrodes is located on one side of the corresponding set of pixel circuits.

[0052] A first electrode layer is fabricated on the side of the driving layer away from the substrate. The first electrode layer includes first electrodes spaced apart and a transition structure. One of the first electrodes is connected to a pixel circuit. The transition structure includes a first conductive layer, a third conductive layer, a metal layer, and a second conductive layer distributed sequentially along the direction away from the substrate. The material of the third conductive layer is an inorganic material. The orthographic projection of the metal layer on the substrate is located within the orthographic projection of the third conductive layer on the substrate, and at least a portion of the edge of the second conductive layer extends beyond the edge of the metal layer.

[0053] A light-emitting functional layer is formed on the side of the first electrode layer away from the substrate. The light-emitting functional layer covers the first electrode, the second conductive layer, and the third conductive layer. The light-emitting functional layer forms a break at the edge of the second conductive layer to expose at least a portion of the second conductive layer and / or the side of the metal layer.

[0054] A second electrode is fabricated on the side of the light-emitting functional layer away from the substrate. The second electrode covers the light-emitting functional layer, as well as the portion of the second conductive layer not covered by the light-emitting functional layer and / or the side of the metal layer.

[0055] According to a fourth aspect of this disclosure, a display device is provided, including the display panel described in the first aspect above.

[0056] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0057] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0058] Figure 1 This is a cross-sectional structural diagram of a display panel provided for an embodiment of the present disclosure.

[0059] Figure 2 This is a cross-sectional structural diagram of another display panel provided in an embodiment of the present disclosure.

[0060] Figure 3 This is a schematic diagram of a driver layer provided for an embodiment of the present disclosure.

[0061] Figure 4 This is a schematic diagram of a source / drain metal layer provided for an embodiment of this disclosure.

[0062] Figure 5 This is a schematic diagram of another driver layer provided in an embodiment of the present disclosure.

[0063] Figure 6 This is a schematic diagram of a pixel circuit provided for an embodiment of the present disclosure.

[0064] Figure 7 This is a schematic diagram of a shielding layer provided for an embodiment of the present disclosure.

[0065] Figure 8 This is a schematic diagram of a semiconductor layer provided for an embodiment of the present disclosure.

[0066] Figure 9 This is a schematic diagram of a gate metal layer provided for an embodiment of the present disclosure.

[0067] Figure 10 This is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0068] Figure 11 This is a schematic flowchart illustrating another method for manufacturing a display panel according to an embodiment of the present disclosure. Detailed Implementation

[0069] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0070] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0071] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0072] A transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain electrode) and the source electrode (source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. The channel region is the area through which the current primarily flows.

[0073] The first electrode involved in this disclosure can be a drain electrode and the second electrode can be a source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "first electrode" and the "second electrode" can be interchanged.

[0074] This disclosure provides a display panel, such as... Figure 1 or Figure 2As shown, the display panel includes a substrate BP, a driving layer CL, and a light-emitting layer EE. The driving layer CL is located on one side of the substrate BP, and the light-emitting layer EE is located on the side of the driving layer CL opposite to the substrate BP. The driving layer CL includes multiple pixel circuits PDCA, and the light-emitting layer EE includes multiple light-emitting devices arranged in an array. Each pixel circuit PDCA corresponds one-to-one with a light-emitting device, and each light-emitting device is connected to a corresponding pixel circuit PDCA. In this way, the corresponding light-emitting device can be controlled to emit light under the drive of the pixel circuit PDCA, thereby realizing the display of the image on the display panel.

[0075] The substrate BP can be made of either inorganic or organic materials. For example, in some embodiments, the substrate BP can be made of glass materials such as soda-lime glass, quartz glass, or sapphire glass, or metal materials such as stainless steel, aluminum, or nickel. In other embodiments, the substrate BP can be made of polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or combinations thereof.

[0076] Optionally, the substrate BP can be a single-layer material or a composite of multiple materials. For example, in some embodiments, the substrate BP includes a base film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked sequentially.

[0077] In this embodiment of the disclosure, a pixel circuit PDCA may include multiple transistors and a storage capacitor CP.

[0078] The transistor can be a thin-film transistor (TFT), which can be selected from top-gate TFT, bottom-gate TFT, or dual-gate TFT; the storage capacitor CP can be a bipolar capacitor or a tripolar capacitor. The active layer material of the TFT can be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, or other types of semiconductor material; the TFT can be an N-type TFT or a P-type TFT.

[0079] It is understood that among the multiple transistors included in a pixel circuit PDCA, any two transistors may be of the same or different types. For example, in some embodiments, some transistors in a pixel circuit PDCA may be N-type transistors and some may be P-type transistors. Further exemplarily, in other embodiments, the active layer material of some transistors in a pixel circuit PDCA may be low-temperature polycrystalline silicon semiconductor material, and the active layer material of some transistors may be metal-oxide-semiconductor material.

[0080] In the embodiments of this disclosure, such as Figure 1 or Figure 2 As shown, the driving layer CL includes an insulating buffer layer BUF, a transistor layer, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN, which are sequentially distributed in the direction away from the substrate BP. The transistor layer includes a semiconductor layer ACT, a gate insulating layer GI, and a gate metal layer Ga, which are stacked between the substrate BP and the interlayer dielectric layer ILD. The positional relationship of the various film layers included in the transistor layer can be determined according to the film layer structure of the thin-film transistor.

[0081] In some embodiments, the insulating buffer layer BUF can be made of inorganic insulating materials such as silicon oxide and silicon nitride. The insulating buffer layer BUF can be a single inorganic material layer or multiple stacked inorganic material layers. The semiconductor layer ACT can be used to form the active portions of each transistor included in the pixel circuit PDCA. Each active portion includes a channel region and two connection portions (i.e., source and drain) located on both sides of the channel region. The channel region can maintain semiconductor characteristics, and the semiconductor material corresponding to the two connection portions is partially or completely conductive. The gate metal layer Ga can be used to form gate metal layer traces such as scan lines, and can also be used to form the second electrode plate CP2 of the storage capacitor CP. The source-drain metal layer SD can be used to form source-drain metal layer traces such as power lines VDD, data lines DA, sensing lines SE, and connection lines, and can also be used to form the first electrode plate CP1 for forming the storage capacitor CP. The planarization layer PLN has multiple first vias. Multiple pixel circuits PDCA, multiple first vias, and multiple light-emitting devices correspond one-to-one. The first electrode An of a light-emitting device is connected to the corresponding pixel circuit PDCA through the corresponding first via.

[0082] In some implementations, such as Figure 1 or Figure 2 As shown, the transistor layer includes a semiconductor layer ACT, a gate insulating layer GI, and a gate metal layer Ga sequentially stacked in a direction away from the substrate BP, thus forming a top-gate thin-film transistor. In other embodiments, the transistor layer includes a gate metal layer Ga, a gate insulating layer GI, and a semiconductor layer ACT sequentially stacked in a direction away from the substrate BP, thus forming a bottom-gate thin-film transistor.

[0083] In some embodiments, the semiconductor layer ACT can be a single semiconductor layer ACT or two semiconductor layers ACT. For example, the semiconductor layer ACT includes a low-temperature polycrystalline silicon semiconductor layer ACT. The gate metal layer Ga can be a single gate metal layer Ga, or two or three gate metal layers Ga. For example, the gate metal layer Ga includes a single gate metal layer Ga.

[0084] It is understood that when the gate metal layer Ga or the semiconductor layer ACT has a multilayer structure, the gate insulating layer GI in the transistor layer can be adaptively increased or decreased. For example, in some embodiments, the transistor layer included in the driving layer CL includes a low-temperature polycrystalline silicon semiconductor layer, a gate insulating layer GI, and a gate metal layer Ga, which are sequentially stacked on the substrate BP.

[0085] In some implementations, the source / drain metal layer SD can be a single source / drain metal layer SD, or it can be two or three source / drain metal layer SDs. For example, the source / drain metal layer SD included in the driver layer CL includes a single source / drain metal layer SD.

[0086] Optionally, such as Figure 1 or Figure 2 As shown, the driving layer CL also includes a passivation layer PVX disposed between the source / drain metal layer SD and the planarization layer PLN, so as to protect the source / drain metal layer SD through the setting of the passivation layer PVX.

[0087] Optionally, such as Figure 1 or Figure 2 As shown, the driving layer CL also includes a shielding layer BSM disposed between the insulating buffer layer BUF and the substrate BP. The shielding layer BSM can overlap with at least part of the channel region of the transistor to shield the light shining on the transistor, thereby stabilizing the electrical characteristics of the transistor.

[0088] In this embodiment of the disclosure, the light-emitting device can be an organic light-emitting diode, a micro light-emitting diode, a quantum dot-organic light-emitting diode, a quantum dot light-emitting diode, or other types of light-emitting devices.

[0089] For example, in some embodiments, the light-emitting device is an organic light-emitting diode (OLED), and the display panel is an OLED display panel. Below, taking an organic light-emitting diode as an example, a feasible structure of the light-emitting device is described exemplarily.

[0090] Optionally, such as Figure 1 or Figure 2As shown, the light-emitting layer EE also includes a pixel definition layer PDL disposed on the side of the driving layer CL facing away from the substrate BP. The pixel definition layer PDL has pixel openings corresponding to a plurality of light-emitting devices. The light-emitting devices include a first electrode An, a light-emitting functional layer EL, and a second electrode COM, which are sequentially stacked along the direction facing away from the substrate BP. The first electrode An is connected to a pixel circuit PDCA through a via. The first electrode An includes an exposed area at the corresponding pixel opening and an area covered by the pixel definition layer PDL. The exposed area of ​​the first electrode An forms the light-emitting area of ​​the corresponding light-emitting device.

[0091] The light-emitting functional layer EL may include an organic electroluminescent material layer, and may include one or more of the following: a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer.

[0092] In some embodiments, the display panel may further include a thin-film encapsulation layer. The thin-film encapsulation layer is disposed on the side of the light-emitting layer EE facing away from the substrate BP, and may include alternately stacked inorganic and organic encapsulation layers. The inorganic encapsulation layer effectively blocks external moisture and oxygen, preventing water and oxygen from invading the organic light-emitting functional layer EL and causing material degradation. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers.

[0093] The display panel has a display area and a peripheral area surrounding the display area. The edge of the inorganic encapsulation layer may be located in the peripheral area, and the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. For example, the thin-film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the light-emitting layer EE facing away from the substrate BP.

[0094] In some embodiments, the display panel may further include a touch function layer disposed on the side of the thin film encapsulation layer opposite to the substrate BP, for realizing touch operation of the display panel.

[0095] In the embodiments of this disclosure, such as Figure 1 or Figure 2 As shown, the light-emitting device includes a first electrode An, a light-emitting functional layer EL, and a second electrode COM, which are sequentially distributed along the direction away from the substrate BP. For a top-emitting light-emitting device, taking the second electrode COM as the cathode as an example, in order to ensure the light-emitting effect of the device, the second electrode COM needs to be made of a material with high transmittance, low resistance, and low work function matching.

[0096] In related technologies, commonly used materials for the second electrode COM include IZO and Mg / Ag alloys. While these materials have good transmittance, they also have relatively high resistance, resulting in a large voltage drop across the second electrode COM, meaning the potential of the second electrodes COM in multiple light-emitting devices is uneven. To ensure good transmittance while minimizing voltage drop, auxiliary electrodes PA are typically fabricated concurrently with the first electrode An, spaced apart from it. The second electrode COM is then connected to the auxiliary electrodes PA. This increases the effective area of ​​the second electrode COM, thereby reducing the voltage drop.

[0097] In the embodiments of this disclosure, such as Figure 3 and Figure 4 As shown, the driving layer CL includes multiple sets of pixel circuits PDCA distributed along the row direction. The driving layer CL includes a source / drain metal layer SD, and the source / drain metal layer SD includes an auxiliary electrode PA corresponding to at least one set of pixel circuits PDCA, with one auxiliary electrode PA located on one side of the corresponding set of pixel circuits PDCA; as shown Figure 1 or Figure 2 As shown, the light-emitting layer EE includes light-emitting devices and a transition structure PAS spaced apart. The orthogonal projections of the transition structure PAS and the auxiliary electrode PA on the substrate BP have overlapping areas. The light-emitting functional layer EL of the light-emitting device simultaneously covers the first electrode An and the transition structure PAS, and a discontinuity is formed at at least a portion of the edge of the transition structure PAS. The second electrode COM of the light-emitting device covers the simultaneously light-emitting functional layer EL and the exposed portion of the transition structure PAS at the discontinuity of the light-emitting functional layer EL, and is connected to the auxiliary electrode PA.

[0098] Thus, by setting the auxiliary electrode PA in the source / drain metal layer SD and connecting the second electrode COM to the auxiliary electrode PA, the voltage drop of the second electrode COM can be effectively reduced, thereby effectively improving the potential uniformity of the second electrode COM of multiple light-emitting devices, and ensuring the brightness uniformity when the display panel displays images. Furthermore, for the auxiliary electrode PA set in the source / drain metal layer SD, the auxiliary electrode PA can be set to extend in the column direction to effectively increase the area of ​​the auxiliary electrode PA projected onto the substrate BP, thereby further reducing the voltage drop of the second electrode COM. Moreover, by setting the transition structure PAS, the problem of the second electrode COM being discontinuous around the light-emitting device is avoided, and when the light-emitting device is subsequently encapsulated by the encapsulation layer, the problem of the organic film layer included in the encapsulation layer being discontinuous around the light-emitting device is also avoided. In terms of manufacturing process, since the light-emitting functional layer EL can simultaneously cover the first electrode An and the transition structure PAS, the manufacturing process is simplified compared to the patterned light-emitting functional layer EL.

[0099] In this embodiment, for multiple sets of pixel circuit PDCA, each set of pixel circuit PDCA in a partial set of pixel circuit PDCA may have a corresponding auxiliary electrode PA, or each set of pixel circuit PDCA in multiple sets of pixel circuit PDCA may have a corresponding auxiliary electrode PA. This embodiment does not limit this.

[0100] In one embodiment, such as Figure 1 As shown, the driving layer CL has an opening CL1 facing the light-emitting layer EE. The orthographic projection of at least a portion of the edge of the transition structure PAS onto the substrate BP lies within the orthographic projection of the opening CL1 onto the substrate BP. The auxiliary electrode PA includes an exposed portion PA1 at the opening CL1. The light-emitting functional layer EL includes a covering portion and a partition portion. The covering portion and the partition portion form a discontinuity at at least a portion of the edge of the transition structure PAS. The covering portion covers the first electrode An and the transition structure PAS. The partition portion lies within the opening CL1, and at least a portion of the edge of the orthographic projection of the exposed portion PA1 of the auxiliary electrode PA extends beyond the orthographic projection of the partition portion onto the substrate BP. The second electrode COM covers the side of the transition structure PAS and the portion of the exposed portion PA1 not covered by the partition portion. The portion of the second electrode COM covering the light-emitting functional layer EL and the portion covering the exposed portion PA1 are continuous.

[0101] Thus, the second electrode COM covers a portion of the exposed portion PA1 of the auxiliary electrode PA, thereby achieving the connection between the second electrode COM and the auxiliary electrode PA. For the transition structure PAS, it is only necessary to ensure that the orthographic projection of at least a portion of the edge of the transition structure PAS on the substrate BP is within the orthographic projection of the opening CL1 on the substrate BP, thereby avoiding the situation where the thickness of the transition structure PAS is large, and thus reducing the possibility of bulging during the manufacturing of the transition structure PAS; in addition, when etching the first electrode An of multiple light-emitting devices, the transition structure PAS can be etched simultaneously, thereby eliminating the need to manufacture the transition structure PAS separately and simplifying the manufacturing process.

[0102] During the manufacturing process of the light-emitting layer EE, when the driving layer CL has an opening CL1 and the orthographic projection of at least a portion of the edge of the transition structure PAS onto the substrate BP is located within the orthographic projection of the opening CL1 onto the substrate BP, when manufacturing the light-emitting functional layer EL, the light-emitting functional layer EL can form a discontinuity at at least a portion of the edge of the transition structure PAS, that is, there is a discontinuity between the aforementioned covering portion and the partition portion, so as to ensure that after the light-emitting functional layer EL is formed, a portion of the exposed portion PA1 of the auxiliary electrode PA is still not covered by the light-emitting functional layer EL, so that when the second electrode COM is manufactured, the second electrode COM can cover the portion of the exposed portion PA1 of the auxiliary electrode PA that is not covered by the light-emitting functional layer EL, thereby realizing the connection between the second electrode COM and the auxiliary electrode PA.

[0103] The edge of the transition structure PAS includes at least an outer peripheral edge, which can be specifically determined according to the shape of the transition structure PAS. For example, the transition structure PAS has a notch or an opening PAS1. In this case, the edge of the transition structure PAS includes an outer peripheral edge and a notch edge or an opening edge. For the outer peripheral edge of the transition structure PAS, only a portion of the outer peripheral edge can have its orthographic projection on the substrate BP located within the orthographic projection of the opening CL1 on the substrate BP. For the notch edge and opening edge of the transition structure PAS, taking the opening edge as an example, either a portion of the opening edge of the transition structure PAS can have its orthographic projection on the substrate BP located within the orthographic projection of the opening CL1 on the substrate BP, or the entire opening edge can have its orthographic projection on the substrate BP located within the orthographic projection of the opening CL1 on the substrate BP. As long as the planarization layer PLN can support the transition structure PAS, this disclosure does not limit this.

[0104] Taking the opening edge of the transition structure PAS as an example, when the orthographic projection of the entire opening edge of the transition structure PAS on the substrate BP is located within the orthographic projection of the opening CL1 on the substrate BP, it can increase the probability of the light-emitting functional layer EL being discontinuous at the opening edge of the transition structure PAS, and ensure that the exposed part PA1 of the auxiliary electrode PA is not completely covered by the light-emitting functional layer EL.

[0105] Taking the PAS with an opening, such as the PAS1, as an example, Figure 1 As shown, the centerline of the opening PAS1 of the transition structure PAS coincides with the centerline of the opening CL1 of the driving layer CL, and the size of the opening PAS1 is smaller than the size of the opening CL1. That is, the orthographic projection of the entire opening edge of the transition structure PAS on the substrate BP lies within the orthographic projection of the opening CL1 on the substrate BP.

[0106] In conjunction with the above, the driving layer CL includes a planarization layer PLN located on the side of the source / drain metal layer SD facing away from the substrate BP. The planarization layer PLN has an opening CL1 to expose a portion of the auxiliary electrode PA. The planarization layer PLN may have one opening CL1 for exposing the auxiliary electrode PA, or it may have multiple openings CL1 for exposing the auxiliary electrode PA. This allows the second electrode COM to be connected to the auxiliary electrode PA at multiple locations, ensuring connection stability.

[0107] The opening CL1 on the planarization layer PLN can be etched according to the position of the transition structure PAS after the transition structure PAS is formed, so as to ensure that at least part of the edge of the transition structure PAS is orthogonally projected on the substrate BP within the orthogonal projection of the opening CL1 on the substrate BP.

[0108] When an opening CL1 is provided on the planarization layer PLN, in order to ensure that the light-emitting functional layer EL can form a discontinuity at the edge of the transition structure PAS, and that the light-emitting functional layer EL does not completely cover the exposed portion PA1 of the auxiliary electrode PA, the length of the edge of the transition structure PAS extending into the region corresponding to the opening CL1 is greater than or equal to 0.8 micrometers and less than or equal to 1.2 micrometers. That is, the radial dimension of the overlapping region of the opening CL1 on the transition structure PAS and the driving layer CL projected onto the substrate BP is greater than or equal to 0.8 micrometers and less than or equal to 1.2 micrometers.

[0109] In this embodiment of the disclosure, the transition structure PAS can be a single-layer structure or a multi-layer structure. When the transition structure PAS is a single-layer structure, the material of the transition structure PAS can be ITO or other conductive materials; when the transition structure PAS is a multi-layer structure, for example, such as... Figure 1 As shown, the transition structure PAS includes a first conductive layer PASa, a metal layer PASb, and a second conductive layer PASc, which are sequentially distributed along the direction away from the substrate BP.

[0110] In this configuration, the orthographic projection of at least a portion of the edge of at least one of the structural layers PASa, PASb, and PASc onto the substrate BP lies within the orthographic projection of the opening CL1 onto the substrate BP, and there is no overlap between the orthographic projection of the remaining structural layers onto the substrate BP and the orthographic projection of the opening CL1 onto the substrate BP. Thus, during the subsequent fabrication of the light-emitting functional layer EL, a break can be formed at this at least portion of the edge.

[0111] The edge of any structural layer can be the outer peripheral edge described above, or the notch edge or opening edge of the transition structure PAS described above. For example, such as Figure 1 As shown, the first conductive layer PASa, the metal layer PASb, and the second conductive layer PASc all have an opening PAS1. The opening edges of the first conductive layer PASa and the metal layer PASb are flush with the hole wall of the opening CL1. At least a portion of the opening edge of the second conductive layer PASc is projected onto the substrate BP in the orthogonal projection of the opening CL1 onto the substrate BP.

[0112] The materials for the first conductive layer PASa and the second conductive layer PASc can both be ITO, etc., while the materials for the metal layer PASb can be Al, Al alloy, Ag, etc. The thickness of the metal layer PASb is greater than or equal to 30 nanometers and less than or equal to 150 nanometers, and the thickness of the second conductive layer PASc is greater than or equal to 10 nanometers and less than or equal to 140 nanometers.

[0113] In another embodiment, such as Figure 2As shown, the adapter structure PAS is connected to the auxiliary electrode PA via a via. Thus, with the second electrode COM covering at least a portion of the adapter structure PAS, the connection between the second electrode COM and the auxiliary electrode PA is achieved.

[0114] In this case, to ensure that the second electrode COM covers at least a portion of the transition structure PAS, in some embodiments, the transition structure PAS includes a first conductive layer PASa, a metal layer PASb, and a second conductive layer PASc sequentially distributed along a direction away from the substrate BP. The first conductive layer PASa is connected to the auxiliary electrode PA through a via, the orthographic projection of the metal layer PASb onto the substrate BP lies within the orthographic projection of the first conductive layer PASa onto the substrate BP, and at least a portion of the edge of the second conductive layer PASc extends beyond the edge of the metal layer PASb. Thus, an "I"-shaped structure is formed by the first conductive layer PASa, the metal layer PASb, and the second conductive layer PASc.

[0115] The light-emitting functional layer EL covers the first electrode An, the second conductive layer PASc, and the first conductive layer PASa. The light-emitting functional layer EL forms a discontinuity under the action of the "I"-shaped transition structure PAS, specifically at the edge of the second conductive layer PASc, exposing at least a portion of the first conductive layer PASa and / or the side surface of the metal layer. The second electrode COM covers not only the light-emitting functional layer EL but also the portion of the first conductive layer PASa not covered by the light-emitting functional layer EL and / or the side surface of the metal layer. Thus, the second electrode COM achieves at least partial coverage of the transition structure PAS.

[0116] In other implementations, such as Figure 2 As shown, the transition structure PAS includes a first conductive layer PASa, a third conductive layer PASd, a metal layer PASb, and a second conductive layer PASc, sequentially distributed along a direction away from the substrate BP. The first conductive layer PASa is connected to the auxiliary electrode PA through a via. The third conductive layer PASd is made of an inorganic material. The orthographic projection of the metal layer PASb onto the substrate BP lies within the orthographic projection of the third conductive layer PASd onto the substrate BP, and at least a portion of the edge of the second conductive layer PASc extends beyond the edge of the metal layer PASb. Thus, the third conductive layer PASd, the metal layer PASb, and the second conductive layer PASc form an "I"-shaped structure.

[0117] Continue as Figure 2As shown, the light-emitting functional layer EL covers the first electrode An, the second conductive layer PASc, and the third conductive layer PASd. The light-emitting functional layer EL forms a discontinuity under the action of the "I"-shaped transition structure PAS, specifically at the edge of the second conductive layer PASc, exposing at least a portion of the third conductive layer PASd and / or the side surface of the metal layer PASb. The second electrode COM, in addition to covering the light-emitting functional layer EL, also covers the portion of the third conductive layer PASd not covered by the light-emitting functional layer EL and / or the side surface of the metal layer PASb. Thus, the second electrode COM achieves at least partial coverage of the transition structure PAS.

[0118] In both of the above embodiments, a portion of the edge of the second conductive layer PASc may extend beyond the edge of the metal layer PASb, or all the edges of the second conductive layer PASc may extend beyond the edge of the metal layer PASb. That is, the edge of the orthographic projection of the metal layer PASb onto the substrate BP lies within the orthographic projection of the second conductive layer PASc onto the substrate BP. When the edge of the orthographic projection of the metal layer PASb onto the substrate BP lies within the orthographic projection of the second conductive layer PASc onto the substrate BP, the probability of a break in the light-emitting functional layer EL at the edge of the second conductive layer PASc can be increased, and it can be ensured that the first conductive layer PASa or the third conductive layer PASd is not completely covered by the light-emitting functional layer EL.

[0119] For a transition structure PAS comprising a first conductive layer PASa, a metal layer PASb, and a second conductive layer PASc, the patterned first conductive layer PASa is fabricated first to facilitate inspection of the previously fabricated film structure. After inspection, the entire metal layer PASb and the second conductive layer PASc are fabricated, and then etched to obtain an "I"-shaped transition structure PAS. Because the entire metal layer PASb is in direct contact with the planarization layer PLN (organic material layer) during fabrication, bulging is prone to occur in the metal layer PASb, meaning the fabricated transition structure PAS is susceptible to bulging.

[0120] For the transition structure PAS, which includes a first conductive layer PASa, a third conductive layer PASd, a metal layer PASb, and a second conductive layer PASc, after obtaining the patterned first conductive layer PASa during the fabrication of the transition structure PAS, the third conductive layer PASd, the metal layer PASb, and the second conductive layer PASc can be fabricated simultaneously. Then, the third conductive layer PASd, the metal layer PASb, and the second conductive layer PASc are etched to obtain an "I"-shaped transition structure PAS. Because the entire third conductive layer PASd is fabricated first, and the third conductive layer PASd is an inorganic material layer, contact between the metal layer PASb and the planarization layer PLN (organic material layer) is avoided, thus preventing bulging of the metal layer PASb, and consequently, preventing bulging in the transition structure PAS.

[0121] In the embodiments of this disclosure, such as Figure 3 and Figure 4 As shown, the source / drain metal layer SD includes multiple power lines VDD corresponding to multiple sets of pixel circuits PDCA. Each power line VDD is connected to a corresponding set of pixel circuits PDCA, and the power line VDD is located on the side of the corresponding set of pixel circuits PDCA away from the auxiliary electrode PA.

[0122] Thus, for a single pixel circuit PDCA, the power line VDD and the auxiliary electrode PA are positioned on opposite sides along the row direction to increase the distance between them, thereby avoiding mutual interference. For multiple pixel circuit PDCAs, to avoid the power line VDD and auxiliary electrode PA being too close, the routing area between adjacent pixel circuit PDCAs includes either the power line VDD or the auxiliary electrode PA. For example, such as... Figure 5 As shown, the routing area between two adjacent sets of pixel circuits PDCA includes only the auxiliary electrode PA; or the routing area between two adjacent sets of pixel circuits PDCA includes both the power line VDD and the auxiliary electrode PA, and the distance between the power line VDD and the auxiliary electrode PA in the row direction is greater than a reference distance. This reduces the interference that the power line VDD corresponding to one set of pixel circuits PDCA may cause to the auxiliary electrode PA corresponding to the adjacent set of pixel circuits PDCA, thereby ensuring the effectiveness of the auxiliary electrode PA setting (i.e., effectively reducing the voltage drop of the second electrode COM). Where the routing area includes both the power line VDD and the auxiliary electrode PA, the distance between the power line VDD and the auxiliary electrode PA in the row direction can be determined based on specific experiments, and this embodiment does not limit this.

[0123] Among them, such as Figure 3 or Figure 4As shown, the auxiliary electrode PA has an extension PA1 on the side opposite to the corresponding power line VDD. The orthographic projections of the transition structure PAS and the extension PA1 on the substrate BP overlap. The second electrode COM covers at least a portion of the transition structure PAS and is connected to the extension PA1. The extension PA1 can be one or more. For example, as... Figure 3 or Figure 4 As shown, the auxiliary electrode PA has four extensions PA1, and the second electrode COM is connected to the four extensions PA1 to ensure the stability of the connection between the second electrode COM and the auxiliary electrode PA.

[0124] In this embodiment, the pixel circuit PDCA can be a 3T1C, 4T1C, or other circuits, as long as it can drive the light-emitting device to emit light. The structure of the driving layer CL will be explained in detail below using 3T1C as an example.

[0125] like Figure 6 As shown, the pixel circuit PDCA includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor CP. The control electrode of the first transistor T1 is connected to the first plate CP1 of the storage capacitor CP and the first electrode of the second transistor T2. The first electrode of the first transistor T1 is used to load a power signal. The second electrode of the first transistor T1 is connected to the second plate CP2 of the storage capacitor CP and the first electrode of the third transistor T3, and is also connected to a first electrode An. The control electrode of the second transistor T2 is used to load a first scan signal, and the second electrode of the second transistor T2 is used to load a data signal. The control electrode of the third transistor T3 is used to load a second scan signal, and the second electrode of the third transistor T3 is used to load a sensing signal.

[0126] like Figure 1 or Figure 2 As shown, the driving layer CL includes a shielding layer BSM, an insulating buffer layer BUF, a semiconductor layer ACT, a gate insulating layer GI, a gate metal layer Ga, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN.

[0127] like Figure 1 or Figure 2 ,as well as Figure 4 , Figure 7 , Figure 8 and Figure 9As shown, the shielding layer BSM is located on one side of the substrate BP and includes a shielding sheet BSM1; the semiconductor layer ACT is located on the side of the shielding layer BSM away from the substrate BP and includes the active portions of the first transistor T1, the second transistor T2, and the third transistor T3. The active portions include a channel region and two connection portions located on both sides of the channel region; the gate metal layer Ga is located on the side of the semiconductor layer ACT away from the substrate BP and includes a first scan line G1, a second scan line G2, and the second electrode CP2 of the storage capacitor CP. The first scan line G1 loads a first scan signal at the control electrode of the second transistor T2, and the second scan line G2 loads a second scan signal at the control electrode of the third transistor T3; the source / drain metal layer SD... On the side of the gate metal layer Ga away from the substrate BP, there is also a power line VDD, a data line DA, a sensing line SE, and a first electrode CP1 of the storage capacitor CP. The power line VDD is loaded with a power signal at the first electrode of the first transistor T1, the data line DA is loaded with a data signal at the second electrode of the second transistor T2, the sensing line SE is loaded with a sensing signal at the second electrode of the third transistor T3, and the first electrode CP1 of the storage capacitor CP is directly opposite to the shielding sheet BSM1 and connected through a via. The planarization layer PLN is located on the side of the source / drain metal layer SD away from the substrate BP, and at least covers the power line VDD, the data line DA, the sensing line SE, the first electrode CP1 of the storage capacitor CP, and the auxiliary electrode PA.

[0128] A set of pixel circuits PDCA includes multiple circuit units PDCC distributed in the column direction. One circuit unit includes four pixel circuits PDCA arranged in two rows and two columns. For one circuit unit PDCC: as follows Figure 3 and Figure 4 As shown, the power line VDD and the auxiliary electrode PA both extend along the column direction and are distributed along the row direction. The power line VDD is charged with a power signal at the first electrode of the first transistor T1 of the four pixel circuits PDCA; as shown... Figure 3 and Figure 7 As shown, the four shielding plates BSM1 are located between the power line VDD and the auxiliary electrode PA, and as... Figure 3 , Figure 8 and Figure 9 As shown, the orthographic projections of the first plate CP1 and the second plate CP2 of the storage capacitor CP of each pixel circuit PDCA onto the substrate BP are all located within the orthographic projection of the shielding plate BSM1 of the same pixel circuit PDCA onto the substrate BP; as Figure 3 and Figure 9 As shown, both the first scan line G1 and the second scan line G2 extend along the row direction and are located between two blocking plates BSM1 along the column direction. The first scan line G1 is loaded with a first scan signal at the control electrode of the second transistor T2 of the four-pixel circuit PDCA, and the second scan line G2 is loaded with a second scan signal at the control electrode of the third transistor T3 of the four-pixel circuit PDCA. Figure 3and Figure 4 As shown, the data line DA extends along the column direction, and there is a data line DA on both sides of the two blocking plates BSM1 along the row direction. The four data lines DA are located between the power line VDD and the auxiliary electrode PA. A data signal is loaded onto the second electrode of the second transistor T2 in the pixel circuit PDCA on one data line DA; as shown... Figure 3 and Figure 4 As shown, the sensing line SE extends along the column direction and is located between two blocking plates BSM1 along the row direction. The sensing line SE is the second pole of the third transistor T3 of the four pixel circuit PDCA to load the sensing signal.

[0129] like Figure 7 As shown, the shielding layer BSM also includes a connecting piece BSM2, such as Figure 9 As shown, the gate metal layer Ga further includes a first horizontal segment L1 and a second horizontal segment L2, as well as a first vertical segment Y1 and a second vertical segment Y2; as Figure 4 As shown, the source / drain metal layer SD also includes multiple connection lines.

[0130] Among them, such as Figure 3 , Figure 4 , Figure 7 and Figure 9 As shown, the middle part of the connecting piece BSM2 overlaps with the sensing line SE of the source / drain metal layer SD and is connected through a via; the first horizontal segment L1 is connected to the first vertical segment Y1, and the first vertical segment Y1 overlaps with the power line VDD of the source / drain metal layer SD and is connected through a via; the second horizontal segment L2 is connected to the first scan line G1 through the connecting line LA; the second vertical segment Y2 overlaps with the auxiliary electrode PA of the source / drain metal layer SD and is connected through a via; the second scan line G2 includes a scan line body G21 extending in the row direction and a scan line branch G22, the scan line branch G22 is located on the side of the scan line body G21 away from the first scan line G1, and at least one end of the scan line branch G22 is connected to the scan line body G21.

[0131] In addition, the number of the first horizontal segment L1 and the first vertical segment Y1 is at least two, and the number of the second vertical segment Y2 can be one or more.

[0132] For a pixel circuit PDCA, such as Figure 3 and Figure 8As shown, the channel region of the first transistor T1 and the orthographic projection of the second plate CP2 of the storage capacitor CP on the substrate BP overlap. One connection portion of the first transistor T1 is connected to the first plate CP1 of the storage capacitor CP through a via, and the other connection portion of the first transistor T1 is connected to the first horizontal segment L1 through a connecting line LB. The channel region of the second transistor T2 and the orthographic projection of the second horizontal segment L2 on the substrate BP overlap. One connection portion of the second transistor T2 is connected to the data line DA through a connecting line LC, and the other connection portion of the second transistor T2 is connected to the second plate CP2 of the storage capacitor CP through a connecting line LD. The channel region of the third transistor T3 and the orthographic projection of the scan line body G21 or scan line branch G22 of the second scan line G2 on the substrate BP overlap. One connection portion of the third transistor T3 is connected to the first plate CP1 of the storage capacitor CP through a connecting line LE, and the other connection portion of the third transistor T3 is connected to the end of the connecting piece BSM2 through a connecting line LF.

[0133] For a circuit unit PDCC, such as Figure 3 and Figure 8 As shown, in the column direction, the active parts of the third transistor T3 of the two pixel circuits PDCA are an integral structure, that is, the two third transistors T3 share a connection part, and the shared connection part is used to connect to the end of the connecting piece BSM2; in the row direction, the first transistor T1 of the two pixel circuits PDCA is connected to the same first horizontal segment L1.

[0134] This disclosure also provides a method for manufacturing a display panel. This method is used to manufacture the display panel described in one embodiment of the above-described embodiments. Figure 10 As shown, the method includes the following steps S110 to S160.

[0135] Step S110: Provide a substrate.

[0136] Step S120: A driving layer is fabricated on one side of the substrate. The driving layer includes multiple sets of pixel circuits distributed along the row direction. The driving layer includes source and drain metal layers. The source and drain metal layers include auxiliary electrodes that correspond one-to-one with at least one set of pixel circuits, and an auxiliary electrode is located on one side of the corresponding set of pixel circuits.

[0137] Step S130: A first electrode layer is fabricated on the side of the driving layer away from the substrate. The first electrode layer includes first electrodes and a transition structure that are spaced apart. A first electrode is connected to a pixel circuit. The orthogonal projections of the transition structure and the auxiliary electrode on the substrate have overlapping areas.

[0138] Step S140: Etch the adapter structure and the driving layer to form an opening in the driving layer that faces the first electrode layer and exposes the auxiliary electrode. The orthographic projection of at least a portion of the edge of the adapter structure on the substrate is located within the orthographic projection of the opening on the substrate.

[0139] Step S150: A light-emitting functional layer is manufactured on the side of the first electrode layer away from the substrate. The light-emitting functional layer includes a covering portion and a partition portion. The covering portion covers the first electrode and the transition structure. The partition portion is located inside the opening. The covering portion and the partition portion form a break at at least a portion of the edge of the transition structure. At least a portion of the edge of the orthographic projection of the exposed portion of the auxiliary electrode on the substrate extends beyond the orthographic projection of the partition portion on the substrate.

[0140] Step S160: A second electrode is fabricated on the side of the light-emitting functional layer away from the substrate. The second electrode covers the portion of the light-emitting functional layer and the exposed portion of the auxiliary electrode that is not covered by the partition portion.

[0141] Taking a transition structure comprising a first conductive layer, a metal layer, and a second conductive layer as an example, the etching performed on the transition structure and the driving layer specifically includes: sequentially forming a full-length first conductive layer, a metal layer, and a second conductive layer on the side of the driving layer facing away from the substrate; etching the first conductive layer, the metal layer, and the second conductive layer such that at least a portion of the edge of the second conductive layer extends beyond the edge of the metal layer, and the edge of the metal layer is at least flush with the edge of the first conductive layer; etching the driving layer such that the driving layer has an opening facing the first electrode layer, and the edge of the first conductive layer is flush with the wall of the opening. This ensures that the orthographic projection of at least a portion of the edge of the transition structure onto the substrate lies within the orthographic projection of the opening onto the substrate.

[0142] In this embodiment, the second electrode covers a portion of the exposed portion of the auxiliary electrode to achieve connection between the second electrode and the auxiliary electrode, thereby effectively reducing the voltage drop of the second electrode and improving the potential uniformity of the second electrodes of multiple light-emitting devices, thus ensuring the uniformity of brightness when the display panel displays an image. Furthermore, for the auxiliary electrode disposed in the source / drain metal layer, the auxiliary electrode can be configured to extend in the column direction to effectively increase the area of ​​the orthographic projection of the auxiliary electrode onto the substrate, thereby further reducing the voltage drop of the second electrode. Moreover, for the transition structure, it is only necessary to ensure that the orthographic projection of at least a portion of the edges of the transition structure onto the substrate is within the orthographic projection of the opening onto the substrate, thereby avoiding a large thickness of the transition structure and reducing the possibility of bulging during the manufacturing of the transition structure; when etching the first electrodes of multiple light-emitting devices, the transition structure can be etched simultaneously, thus eliminating the need to manufacture the transition structure separately and simplifying the manufacturing process.

[0143] In this disclosure, another method for manufacturing a display panel is also provided, which is used to manufacture a display panel according to another embodiment of the above embodiments. For example... Figure 11 As shown, the method includes the following steps S210 to S260.

[0144] Step S210: Provide a substrate.

[0145] Step S220: A driving layer is fabricated on one side of the substrate. The driving layer includes multiple sets of pixel circuits distributed along the row direction. The driving layer includes source and drain metal layers. The source and drain metal layers include auxiliary electrodes that correspond one-to-one with at least one set of pixel circuits, and an auxiliary electrode is located on one side of the corresponding set of pixel circuits.

[0146] Step S230: A first electrode layer is fabricated on the side of the driving layer away from the substrate. The first electrode layer includes first electrodes and a transition structure distributed at intervals. A first electrode is connected to a pixel circuit. The transition structure includes a first conductive layer, a third conductive layer, a metal layer and a second conductive layer distributed sequentially along the direction away from the substrate. The material of the third conductive layer is an inorganic material. The orthographic projection of the metal layer on the substrate is located within the orthographic projection of the third conductive layer on the substrate, and at least a portion of the edge of the second conductive layer extends beyond the edge of the metal layer.

[0147] Step S240: A light-emitting functional layer is formed on the side of the first electrode layer away from the substrate. The light-emitting functional layer covers the first electrode, the second conductive layer, and the third conductive layer. The light-emitting functional layer forms a break at the edge of the second conductive layer to expose at least a portion of the second conductive layer and / or the side of the metal layer.

[0148] Step S250: A second electrode is fabricated on the side of the light-emitting functional layer away from the substrate. The second electrode covers the light-emitting functional layer, as well as the portion of the second conductive layer not covered by the light-emitting functional layer and / or the side of the metal layer.

[0149] Taking the transition structure comprising a first conductive layer, a third conductive layer, a metal layer, and a second conductive layer as an example, the transition structure is provided on the side of the driving layer away from the substrate. Specifically, it includes: forming a patterned first conductive layer on the driving layer, the first conductive layer being connected to an auxiliary electrode through a via; sequentially forming a full-layer third conductive layer, a metal layer, and a second conductive layer on the side of the first conductive layer away from the substrate; etching the third conductive layer, the metal layer, and the second conductive layer to form an "I"-shaped transition structure (the orthographic projection of the metal layer on the substrate is located within the orthographic projection of the third conductive layer on the substrate, and at least a portion of the edge of the second conductive layer extends beyond the edge of the metal layer).

[0150] In this embodiment, the transition structure and the auxiliary electrode are connected via vias. The second electrode covers a portion of the transition structure to achieve connection between the second electrode and the auxiliary electrode. This effectively reduces the voltage drop of the second electrode, thereby improving the potential uniformity of the second electrodes of multiple light-emitting devices and ensuring the brightness uniformity of the display panel when displaying images. Furthermore, for the auxiliary electrode disposed in the source / drain metal layer, it can be configured to extend in the column direction to effectively increase the area of ​​the auxiliary electrode's orthogonal projection onto the substrate, further reducing the voltage drop of the second electrode. Moreover, for the transition structure, a third conductive layer can isolate the metal layer from the planarization layer (organic material layer), thereby preventing bulging of the metal layer, and thus avoiding bulging of the transition structure, improving the yield of the display panel.

[0151] It should be noted that, although in Figure 10 and Figure 11 The steps of the method for manufacturing the display panel in this disclosure are described in a specific order; however, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0152] This disclosure also provides a display device including a display panel as described in the above embodiments. Thus, by using the display panel described in the above embodiments, the uniformity of brightness of the displayed image can be effectively improved, thereby enhancing the display effect.

[0153] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, wherein, include: substrate; A driving layer is located on one side of the substrate and includes multiple sets of pixel circuits distributed along the row direction. The driving layer includes a source / drain metal layer, and the source / drain metal layer includes an auxiliary electrode that corresponds one-to-one with at least one set of the pixel circuits, and one of the auxiliary electrodes is located on one side of the corresponding set of pixel circuits. A light-emitting layer is located on the side of the driving layer away from the substrate. The light-emitting layer includes light-emitting devices and a transition structure distributed at intervals. The orthographic projections of the transition structure and the auxiliary electrode on the substrate have an overlapping area. The light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode distributed sequentially in a direction away from the substrate. The first electrode is connected to a pixel circuit. The light-emitting functional layer covers the first electrode and the transition structure, and a break is formed at at least a portion of the edge of the transition structure. The second electrode covers the light-emitting functional layer and the exposed portion of the transition structure at the break in the light-emitting functional layer, and is connected to the auxiliary electrode. The driving layer has an opening facing the light-emitting layer, and at least a portion of the edge of the transition structure is projected onto the substrate within the projection of the opening onto the substrate; the auxiliary electrode includes an exposed portion at the opening, and the light-emitting functional layer includes a covering portion and a partition portion, the covering portion and the partition portion forming a discontinuity at at least a portion of the edge of the transition structure, the covering portion covering the first electrode and the transition structure, the partition portion being located within the opening, and at least a portion of the edge of the projection of the exposed portion of the auxiliary electrode onto the substrate extending beyond the projection of the partition portion onto the substrate; The second electrode covers the side of the transition structure and the portion of the exposed portion not covered by the partition portion, and the portion of the second electrode covering the light-emitting functional layer and the portion covering the exposed portion are continuous; The transition structure includes a first conductive layer, a metal layer, and a second conductive layer distributed sequentially along a direction away from the substrate. At least a portion of the edge of at least one of the structural layers, the first conductive layer, the metal layer, and the second conductive layer, is projected onto the substrate within the orthogonal projection of the opening onto the substrate, and the orthogonal projections of the remaining structural layers onto the substrate and the orthogonal projections of the opening onto the substrate do not overlap.

2. The display panel as claimed in claim 1, wherein, The adapter structure has an opening, and at least a portion of the opening edge of the adapter structure is projected onto the substrate in the orthographic projection of the opening onto the substrate.

3. The display panel as described in claim 2, wherein, The opening of the adapter structure coincides with the center line of the opening of the drive layer, and the opening size of the opening is smaller than the opening size of the opening.

4. The display panel as claimed in claim 1, wherein, The length of the edge of the adapter structure extending into the area corresponding to the opening is greater than or equal to 0.8 micrometers and less than or equal to 1.2 micrometers.

5. The display panel as claimed in claim 1, wherein, The first conductive layer, the metal layer, and the second conductive layer all have openings; The opening edges of the first conductive layer and the metal layer are flush with the hole wall of the opening, and at least a portion of the opening edge of the second conductive layer is projected onto the substrate within the projection of the opening onto the substrate.

6. The display panel as described in any one of claims 1-5, wherein, The source / drain metal layer includes multiple power lines corresponding one-to-one with the multiple sets of pixel circuits. Each power line is connected to a corresponding set of pixel circuits, and each power line is located on the side of the corresponding set of pixel circuits away from the auxiliary electrode.

7. The display panel as claimed in claim 6, wherein, The auxiliary electrode has an extension on the side opposite to the corresponding power line. The orthographic projections of the adapter structure and the extension on the substrate overlap. The second electrode covers the adapter structure and is connected to the extension.

8. The display panel as described in any one of claims 1-5, wherein, The pixel circuit includes a first transistor, a second transistor, a third transistor, and a storage capacitor; The control electrode of the first transistor is connected to the first plate of the storage capacitor and the first electrode of the second transistor. The first electrode of the first transistor is used to load a power signal. The second electrode of the first transistor is connected to the second plate of the storage capacitor and the first electrode of the third transistor, and is also connected to a first electrode. The control electrode of the second transistor is used to load the first scan signal, and the second electrode of the second transistor is used to load the data signal; The control electrode of the third transistor is used to load the second scan signal, and the second electrode of the third transistor is used to load the sensing signal.

9. The display panel as claimed in claim 8, wherein, The driving layer includes: A shielding layer is located on one side of the substrate and includes a shielding sheet; A semiconductor layer is located on the side of the shielding layer away from the substrate, and includes active portions of the first transistor, the second transistor, and the third transistor. The active portion includes a channel region and two connection portions located on both sides of the channel region. A gate metal layer is located on the side of the semiconductor layer away from the substrate, and includes a first scan line, a second scan line and a second electrode of the storage capacitor. The first scan line loads the first scan signal at the control electrode of the second transistor, and the second scan line loads the second scan signal at the control electrode of the third transistor. The source and drain metal layers are located on the side of the gate metal layer away from the substrate, and also include power lines, data lines, sensing lines and the first plate of the storage capacitor. The power lines load the power signal at the first electrode of the first transistor, the data lines load the data signal at the second electrode of the second transistor, the sensing lines load the sensing signal at the second electrode of the third transistor, and the first plate of the storage capacitor is directly opposite to the shielding sheet and connected through a via. A planarization layer is located on the side of the source / drain metal layer opposite to the substrate, and at least covers the power line, the data line, the sensing line, the first plate of the storage capacitor, and the auxiliary electrode.

10. The display panel as claimed in claim 9, wherein, A group of said pixel circuits includes a plurality of circuit units distributed in a column direction, and one said circuit unit includes four said pixel circuits distributed in two rows and two columns. For one said circuit unit: The power line and the auxiliary electrode both extend along the column direction and are distributed along the row direction. The power line applies a power signal to the first electrode of the first transistor of the four pixel circuits. The four shielding plates are located between the power line and the auxiliary electrode, and the orthographic projections of the first plate and the second plate of each storage capacitor on the substrate are all located within the orthographic projections of the shielding plates of the same pixel circuit on the substrate. Both the first scan line and the second scan line extend along the row direction and are located between the two blocking plates along the column direction. The first scan line is loaded with a first scan signal at the control electrode of the second transistor of the four pixel circuits, and the second scan line is loaded with a second scan signal at the control electrode of the third transistor of the four pixel circuits. The data lines extend along the column direction, and each of the two shielding plates along the row direction has a data line on both sides. The four data lines are located between the power line and the auxiliary electrode, and a data line loads a data signal on the second electrode of the second transistor of the pixel circuit. The sensing line extends along the column direction and is located between the two blocking plates along the row direction. The sensing line is the second electrode of the third transistor of the four pixel circuits that loads the sensing signal.

11. A display panel, wherein, include: substrate; A driving layer is located on one side of the substrate and includes multiple sets of pixel circuits distributed along the row direction. The driving layer includes a source / drain metal layer, and the source / drain metal layer includes an auxiliary electrode that corresponds one-to-one with at least one set of the pixel circuits, and one of the auxiliary electrodes is located on one side of the corresponding set of pixel circuits. A light-emitting layer is located on the side of the driving layer away from the substrate. The light-emitting layer includes light-emitting devices and a transition structure distributed at intervals. The orthographic projections of the transition structure and the auxiliary electrode on the substrate have an overlapping area. The light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode distributed sequentially in a direction away from the substrate. The first electrode is connected to a pixel circuit. The light-emitting functional layer covers the first electrode and the transition structure, and a break is formed at at least a portion of the edge of the transition structure. The second electrode covers the light-emitting functional layer and the exposed portion of the transition structure at the break in the light-emitting functional layer, and is connected to the auxiliary electrode. The adapter structure is connected to the auxiliary electrode through a via; the adapter structure includes a first conductive layer, a third conductive layer, a metal layer, and a second conductive layer distributed sequentially along a direction away from the substrate; The first conductive layer is connected to the auxiliary electrode through a via. The material of the third conductive layer is an inorganic material. The orthographic projection of the metal layer on the substrate is located within the orthographic projection of the third conductive layer on the substrate, and at least a portion of the edge of the second conductive layer extends beyond the edge of the metal layer. The light-emitting functional layer covers the first electrode, the second conductive layer, and the third conductive layer, and the light-emitting functional layer forms a break at the edge of the second conductive layer to expose at least a portion of the third conductive layer and / or the side of the metal layer. The second electrode also covers the portion of the third conductive layer not covered by the light-emitting functional layer and / or the side of the metal layer.

12. The display panel as claimed in claim 11, wherein, The edge of the orthographic projection of the metal layer on the substrate is located within the orthographic projection of the second conductive layer on the substrate.

13. The display panel as described in any one of claims 11-12, wherein, The source / drain metal layer includes multiple power lines corresponding one-to-one with the multiple sets of pixel circuits. Each power line is connected to a corresponding set of pixel circuits, and each power line is located on the side of the corresponding set of pixel circuits away from the auxiliary electrode.

14. The display panel as claimed in claim 13, wherein, The auxiliary electrode has an extension on the side opposite to the corresponding power line. The orthographic projections of the adapter structure and the extension on the substrate overlap. The second electrode covers the adapter structure and is connected to the extension.

15. The display panel as described in any one of claims 11-12, wherein, The pixel circuit includes a first transistor, a second transistor, a third transistor, and a storage capacitor; The control electrode of the first transistor is connected to the first plate of the storage capacitor and the first electrode of the second transistor. The first electrode of the first transistor is used to load a power signal. The second electrode of the first transistor is connected to the second plate of the storage capacitor and the first electrode of the third transistor, and is also connected to a first electrode. The control electrode of the second transistor is used to load the first scan signal, and the second electrode of the second transistor is used to load the data signal; The control electrode of the third transistor is used to load the second scan signal, and the second electrode of the third transistor is used to load the sensing signal.

16. The display panel as claimed in claim 15, wherein, The driving layer includes: A shielding layer is located on one side of the substrate and includes a shielding sheet; A semiconductor layer is located on the side of the shielding layer away from the substrate, and includes active portions of the first transistor, the second transistor, and the third transistor. The active portion includes a channel region and two connection portions located on both sides of the channel region. A gate metal layer is located on the side of the semiconductor layer away from the substrate, and includes a first scan line, a second scan line and a second electrode of the storage capacitor. The first scan line loads the first scan signal at the control electrode of the second transistor, and the second scan line loads the second scan signal at the control electrode of the third transistor. The source and drain metal layers are located on the side of the gate metal layer away from the substrate, and also include power lines, data lines, sensing lines and the first plate of the storage capacitor. The power lines load the power signal at the first electrode of the first transistor, the data lines load the data signal at the second electrode of the second transistor, the sensing lines load the sensing signal at the second electrode of the third transistor, and the first plate of the storage capacitor is directly opposite to the shielding sheet and connected through a via. A planarization layer is located on the side of the source / drain metal layer opposite to the substrate, and at least covers the power line, the data line, the sensing line, the first plate of the storage capacitor, and the auxiliary electrode.

17. The display panel as claimed in claim 16, wherein, A group of said pixel circuits includes a plurality of circuit units distributed in a column direction, and one said circuit unit includes four said pixel circuits distributed in two rows and two columns. For one said circuit unit: The power line and the auxiliary electrode both extend along the column direction and are distributed along the row direction. The power line applies a power signal to the first electrode of the first transistor of the four pixel circuits. The four shielding plates are located between the power line and the auxiliary electrode, and the orthographic projections of the first plate and the second plate of each storage capacitor on the substrate are all located within the orthographic projections of the shielding plates of the same pixel circuit on the substrate. Both the first scan line and the second scan line extend along the row direction and are located between the two blocking plates along the column direction. The first scan line is loaded with a first scan signal at the control electrode of the second transistor of the four pixel circuits, and the second scan line is loaded with a second scan signal at the control electrode of the third transistor of the four pixel circuits. The data lines extend along the column direction, and each of the two shielding plates along the row direction has a data line on both sides. The four data lines are located between the power line and the auxiliary electrode, and a data line loads a data signal on the second electrode of the second transistor of the pixel circuit. The sensing line extends along the column direction and is located between the two blocking plates along the row direction. The sensing line is the second electrode of the third transistor of the four pixel circuits that loads the sensing signal.

18. A method for manufacturing a display panel, wherein, The method includes: Provide a substrate; A driving layer is fabricated on one side of the substrate. The driving layer includes multiple sets of pixel circuits distributed along the row direction. The driving layer includes a source / drain metal layer. The source / drain metal layer includes auxiliary electrodes that correspond one-to-one with at least one set of the pixel circuits, and one of the auxiliary electrodes is located on one side of the corresponding set of pixel circuits. A first electrode layer is fabricated on the side of the driving layer away from the substrate. The first electrode layer includes first electrodes and a transition structure distributed at intervals. One of the first electrodes is connected to one of the pixel circuits. The orthographic projections of the transition structure and the auxiliary electrode on the substrate have an overlapping area. The transition structure includes a first conductive layer, a metal layer and a second conductive layer distributed sequentially along the direction away from the substrate. The adapter structure and the driving layer are etched to form an opening in the driving layer that faces the first electrode layer and exposes the auxiliary electrode. At least a portion of the edge of the adapter structure is projected onto the substrate in the orthogonal projection of the opening onto the substrate. The auxiliary electrode includes an exposed portion at the opening. At least a portion of the edge of at least one of the structural layers (the first conductive layer, the metal layer, and the second conductive layer) is projected onto the substrate in the orthogonal projection of the opening onto the substrate. The orthogonal projections of the remaining structural layers onto the substrate and the orthogonal projections of the opening onto the substrate do not overlap. A light-emitting functional layer is fabricated on the side of the first electrode layer facing away from the substrate. The light-emitting functional layer includes a covering portion and a partition portion. The covering portion covers the first electrode and the transition structure. The partition portion is located within the opening. The covering portion and the partition portion form a discontinuity at at least a portion of the edge of the transition structure. At least a portion of the edge of the orthographic projection of the exposed portion of the auxiliary electrode on the substrate extends beyond the orthographic projection of the partition portion on the substrate. A second electrode is fabricated on the side of the light-emitting functional layer away from the substrate. The second electrode covers the light-emitting functional layer and the portion of the exposed portion of the auxiliary electrode that is not covered by the partition portion. The second electrode covers the side of the transition structure and the portion of the exposed portion that is not covered by the partition portion. The portion of the second electrode covering the light-emitting functional layer and the portion covering the exposed portion are continuous.

19. A method for manufacturing a display panel, wherein, The method includes: Provide a substrate; A driving layer is fabricated on one side of the substrate. The driving layer includes multiple sets of pixel circuits distributed along the row direction. The driving layer includes a source / drain metal layer. The source / drain metal layer includes auxiliary electrodes that correspond one-to-one with at least one set of the pixel circuits, and one of the auxiliary electrodes is located on one side of the corresponding set of pixel circuits. A first electrode layer is fabricated on the side of the driving layer away from the substrate. The first electrode layer includes first electrodes spaced apart and a transition structure. One of the first electrodes is connected to a pixel circuit. The transition structure includes a first conductive layer, a third conductive layer, a metal layer, and a second conductive layer distributed sequentially along the direction away from the substrate. The material of the third conductive layer is an inorganic material. The orthographic projection of the metal layer on the substrate is located within the orthographic projection of the third conductive layer on the substrate, and at least a portion of the edge of the second conductive layer extends beyond the edge of the metal layer. A light-emitting functional layer is formed on the side of the first electrode layer away from the substrate. The light-emitting functional layer covers the first electrode, the second conductive layer, and the third conductive layer. The light-emitting functional layer forms a break at the edge of the second conductive layer to expose at least a portion of the second conductive layer and / or the side of the metal layer. A second electrode is fabricated on the side of the light-emitting functional layer away from the substrate. The second electrode covers the light-emitting functional layer, as well as the portion of the second conductive layer not covered by the light-emitting functional layer and / or the side of the metal layer.

20. A display device, wherein, Includes the display panel as described in any one of claims 1-17 above.

Images