Trench gate semiconductor device and manufacturing method

Abstract

The present invention discloses a trench gate semiconductor device, wherein the device unit includes: a trench gate, a source trench, and a first semiconductor epitaxial layer doped with a first conductivity type located between the source trench and the trench gate, forming a platform region. A channel region is formed in the platform region, and a source region is formed in a surface region of the channel region. The gate trench of the trench gate vertically passes through the channel region. The source trench is filled with a source lead metal. A bottom doped region heavily doped with a second conductivity type is self-alignedly formed in the bottom region of the source trench. The bottom doped region covers the bottom of the source lead metal and forms an ohmic contact. The side of the source lead metal contacts the channel region and the source region. In the vertical direction, the bottom surface of the gate trench is located within the depth range of the bottom doped region, and the bottom doped region forms an electric field shielding structure for the bottom region of the trench gate. The present invention also discloses a method for manufacturing a trench gate semiconductor device. The present invention can reduce the electric field strength in the bottom region of the trench gate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench gate semiconductor device; the present invention also relates to a method for manufacturing the trench gate semiconductor device. Background Art

[0002] Compared to Si, SiC has a wider bandgap and a higher critical breakdown field. Therefore, while maintaining the same withstand voltage, the drift region length of SiC devices can be significantly reduced, and the drift region doping concentration can be significantly increased. For this reason, SiC has recently garnered increasing attention.

[0003] An increasing number of devices have been introduced based on SiC materials. SiC MOSFETs are among the most important. Currently, SiC MOSFETs are primarily planar. Limited by the JFET effect in the channel and drift regions, their minimum unit cell size is difficult to reduce to 3μm or below.

[0004] Trench MOSFETs (i.e., MOSFETs with trench gates) eliminate the JFET effect, allowing for smaller cell sizes and improved performance. Furthermore, the oxide layer of SiC MOSFETs has a high defect density and low mobility. Using trench MOSFETs can achieve higher mobility by selecting the crystal orientation of the oxide layer. Therefore, trench SiC MOSFETs are the future trend. However, the biggest challenge facing trench SiC MOSFETs is reducing the electric field strength at the bottom of the trench. Only by reducing the electric field strength at the bottom of the trench gate can the gate dielectric layer, such as the gate oxide, be protected.

[0005] According to Gauss's theorem, the electric field strength of the device in the semiconductor and oxide layers conforms to the following formula:

[0006]

[0007] Among them, E semi is the critical electric field strength of the semiconductor device, ε semi and ε oxide are the dielectric constants of the semiconductor material and the oxide layer material, respectively. Because the critical electric field strength of Si and SiC differs by a factor of 10, for Si devices, in its gate dielectric layer, i.e., silicon dioxide, the electric field strength is unlikely to exceed 3×10 6 V*cm -1 For SiC devices, the dielectric constant of SiC (ε semi ) and the dielectric constant of silicon dioxide (ε oxide) is usually around 2.6. When the SiC at the interface of the SiC and the insulating layer corresponding to the gate dielectric layer reaches the critical electric field strength of 3e6 V / cm, the electric field strength in the insulating layer such as silicon dioxide can be as high as 9×10 6 V*cm -1 , which has reached or exceeded the critical electric field strength of silicon dioxide. That is, in Si devices, when the electric field strength in the Si material reaches the critical electric field strength, the electric field strength of the gate oxide remains low; however, in SiC devices, when the electric field strength in the SiC material reaches the critical electric field strength, the electric field strength of the gate oxide reaches or exceeds the critical electric field strength of the gate oxide, which will cause gate oxide breakdown and thus reliability issues. Therefore, for SiC MOSFETs, adopting appropriate device structure and design methods to reduce the electric field strength at the gate-oxide interface at the bottom of the trench gate during device breakdown is particularly important for device reliability. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a trench-gate semiconductor device that can shield the electric field strength at the bottom region of the trench gate, thereby reducing the electric field strength at the bottom region of the trench gate and improving device reliability. The device also has the advantages of being simple and easy to implement, and not requiring additional photomasks. To this end, the present invention also provides a method for manufacturing the trench-gate semiconductor device.

[0009] In order to solve the above technical problems, the device unit of the trench gate semiconductor device provided by the present invention includes:

[0010] A first semiconductor epitaxial layer doped with a first conductive type is provided, and a trench gate is formed in a selected area of ​​the first semiconductor epitaxial layer, wherein the trench gate includes a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench.

[0011] A source trench is formed in a selected region of the first semiconductor epitaxial layer, and the first semiconductor epitaxial layer between the source trench and the trench gate is a terrace region.

[0012] A channel region doped with the second conductivity type is formed in the terrace region, and a source region heavily doped with the first conductivity type is formed in a surface region of the channel region.

[0013] The gate trench passes through the channel region longitudinally, and a surface area of ​​a first side surface of the channel region covered by a side surface of the trench gate is used to form a channel.

[0014] The source trench is filled with a source lead-out metal.

[0015] A bottom doped region heavily doped with the second conductive type is self-alignedly formed in the bottom area of ​​the source trench, and the bottom doped region covers the bottom of the source lead-out metal and forms an ohmic contact. The side surface of the source lead-out metal contacts the second side surface of the channel region and the second side surface of the source region and is used to lead out the channel region and the source region.

[0016] In the vertical direction, the bottom surface of the gate trench is located within the depth range of the bottom doping region, and the bottom doping region forms an electric field shielding structure for the bottom area of ​​the trench gate, so as to reduce the electric field strength in the bottom area of ​​the trench gate.

[0017] A further improvement is that the depth of the channel region gradually increases from the first side surface to the second side surface of the channel region.

[0018] A further improvement is that the channel region is an inclined ion implantation region, and the channel region is formed by using inclined ion implantation after the source trench is opened. The inclined ion implantation is implanted into the platform region from the top surface of the platform region and the side of the source trench to form the channel region.

[0019] A further improvement is that the trench gate semiconductor device is a MOS transistor, and a drain region heavily doped with the first conductivity type is formed on the back side of the first semiconductor epitaxial layer; the drain region is composed of a thinned semiconductor substrate heavily doped with the first conductivity type or the drain region is composed of a back ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate.

[0020] Alternatively, the trench gate semiconductor device is an IGBT device, and a collector region heavily doped with the second conductivity type is formed on the back side of the first semiconductor epitaxial layer; the collector region is composed of a thinned semiconductor substrate heavily doped with the second conductivity type, or the collector region is composed of a back ion implantation region heavily doped with the second conductivity type formed in a thinned semiconductor substrate.

[0021] A further improvement is that when the trench gate semiconductor device is a MOS transistor, a buffer layer doped with a first conductive type is formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the semiconductor substrate, and the doping concentration of the buffer layer is greater than the doping concentration of the first semiconductor epitaxial layer and less than the doping concentration of the semiconductor substrate.

[0022] When the trench gate semiconductor device is an IGBT, a field stop layer doped with a first conductive type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the collector region, and the doping concentration of the field stop layer is greater than the doping concentration of the first semiconductor epitaxial layer and less than the doping concentration of the semiconductor substrate.

[0023] A further improvement is that the semiconductor device includes a plurality of the device units connected in parallel, and each of the device units is formed in a device unit region.

[0024] The transition region surrounds the peripheral side of the device unit region, and the termination region surrounds the peripheral side of the transition region.

[0025] A second trench is formed in the first semiconductor epitaxial layer in the transition region, and a plurality of third trenches are formed in the first semiconductor epitaxial layer in the termination region.

[0026] The second trench and each of the third trenches are formed simultaneously with the source trench.

[0027] A second well region is formed between the source trench and the second trench, between the second trench and the third trench, and between the third trenches. The second well region and the channel region have the same process structure and are formed simultaneously.

[0028] The second trench is filled with a first lead-out metal, and each of the second trenches is filled with a second lead-out metal. The first lead-out metal, the second lead-out metal, and the source lead-out metal have the same process structure and are formed simultaneously.

[0029] A second bottom doping region heavily doped with the second conductivity type is formed at the bottom of each of the second trenches and the third trench. The process structure of each of the second bottom doping regions is the same as that of the bottom doping region and is formed simultaneously.

[0030] The tops of the source lead-out metal and the first lead-out metal are both connected to the source formed by the front metal layer, and the second lead-out metal is floating.

[0031] A further improvement is that the width of the second trench is more than 10 times the width of the source trench; and the width of the third trench is greater than or equal to the width of the source trench.

[0032] The spacing between the second trenches or the third trenches is greater than or equal to the spacing between the source trenches.

[0033] The intervals between the second trenches or the third trenches are equal or gradually increase in a direction from the device cell region to the terminal region.

[0034] The number of the third trenches is set according to the operating voltage of the semiconductor device. The greater the operating voltage of the semiconductor device, the greater the number of the third trenches.

[0035] A further improvement is that the trench gate semiconductor device is a SiC device, and the material of the first semiconductor epitaxial layer is SiC; or, the trench gate semiconductor device is a silicon-based device, and the material of the first semiconductor epitaxial layer is silicon.

[0036] To solve the above technical problems, the present invention provides a method for manufacturing a trench gate semiconductor device, wherein the step of forming a device unit includes:

[0037] A first semiconductor epitaxial layer doped with a first conductive type is provided, and a trench gate is formed in a selected area of ​​the first semiconductor epitaxial layer. The trench gate includes a gate trench, a gate dielectric layer formed on an inner surface of the gate trench, and a gate conductive material layer filled in the gate trench.

[0038] A hard mask layer is formed on the surface of the first semiconductor epitaxial layer, and the hard mask layer is patterned and etched, wherein the opening area of ​​the hard mask layer is the formation area of ​​the source trench.

[0039] The first semiconductor epitaxial layer is etched using the hard mask layer as a mask to form a source trench; the first semiconductor epitaxial layer located between the source trench and the trench gate is a platform region.

[0040] Using the hard mask layer as a barrier layer, ion implantation of a second conductive type heavy doping is performed to self-align at the bottom area of ​​the source trench to form a bottom doping region. Outside the source trench, the implantation energy of the ion implantation in the bottom doping region is ensured not to pass through the hard mask layer.

[0041] Using the hard mask layer as a barrier layer, a second conductive type of ion implantation with an inclined angle is performed, and the ion implantation with an inclined angle is implanted into the platform area from the top surface of the platform area and the side of the source trench to form a channel area; the depth of the channel area gradually increases from the first side to the second side of the channel area; the gate trench longitudinally passes through the channel area, and the surface area of ​​the first side of the channel area covered by the side of the trench gate is used to form a channel.

[0042] The hard mask layer is removed, and a source lead metal is filled in the source trench.

[0043] A source region heavily doped with a first conductivity type is formed on a surface of the channel region of the terrace region.

[0044] The bottom doped region covers the bottom of the source lead-out metal and forms an ohmic contact. The side surface of the source lead-out metal contacts the second side surface of the channel region and the second side surface of the source region and is used to lead out the channel region and the source region.

[0045] In the vertical direction, the bottom surface of the gate trench is located within the depth range of the bottom doping region, and the bottom doping region forms an electric field shielding structure for the bottom area of ​​the trench gate, so as to reduce the electric field strength in the bottom area of ​​the trench gate.

[0046] A further improvement is that the trench gate semiconductor device is a MOS transistor, the first semiconductor epitaxial layer is formed on the surface of the semiconductor substrate, and after the front side process is completed, the following back side process is also included:

[0047] The semiconductor substrate is back-thinned.

[0048] The semiconductor substrate is heavily doped with the first conductivity type, and the drain region is formed by thinning the semiconductor substrate on the back side; or, the drain region is formed in the thinned semiconductor substrate by performing back ion implantation heavily doped with the first conductivity type.

[0049] Alternatively, the trench gate semiconductor device is an IGBT device, the first semiconductor epitaxial layer is formed on the surface of the semiconductor substrate, and after the front side process is completed, the following back side process is further included:

[0050] The back side of the semiconductor substrate is thinned; the semiconductor substrate is heavily doped with the second conductivity type, and the collector region is formed by the semiconductor substrate after the back side is thinned; or, back side ion implantation with heavy doping of the second conductivity type is performed to form a collector region in the thinned semiconductor substrate.

[0051] A further improvement is that when the trench gate semiconductor device is a MOS transistor, a buffer layer doped with a first conductive type is formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the semiconductor substrate, and the doping concentration of the buffer layer is greater than the doping concentration of the first semiconductor epitaxial layer and less than the doping concentration of the semiconductor substrate.

[0052] When the trench gate semiconductor device is an IGBT, a field stop layer doped with a first conductive type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the collector region, and the doping concentration of the field stop layer is greater than the doping concentration of the first semiconductor epitaxial layer and less than the doping concentration of the semiconductor substrate.

[0053] A further improvement is that the semiconductor device includes a plurality of the device units connected in parallel, and each of the device units is formed in a device unit region.

[0054] The transition region surrounds the peripheral side of the device unit region, and the termination region surrounds the peripheral side of the transition region.

[0055] A second trench is formed in the first semiconductor epitaxial layer in the transition region, and a plurality of third trenches are formed in the first semiconductor epitaxial layer in the termination region.

[0056] The second trench and each of the third trenches are formed simultaneously with the source trench.

[0057] A second well region is formed between the source trench and the second trench, between the second trench and the third trench, and between the third trenches. The second well region and the channel region have the same process structure and are formed simultaneously.

[0058] The second trench is filled with a first lead-out metal, and each of the second trenches is filled with a second lead-out metal. The first lead-out metal, the second lead-out metal, and the source lead-out metal have the same process structure and are formed simultaneously.

[0059] A second bottom doping region heavily doped with the second conductivity type is formed at the bottom of each of the second trenches and the third trench. The process structure of each of the second bottom doping regions is the same as that of the bottom doping region and is formed simultaneously.

[0060] The tops of the source lead-out metal and the first lead-out metal are both connected to the source formed by the front metal layer, and the second lead-out metal is floating.

[0061] A further improvement is that the width of the second trench is more than 10 times the width of the source trench; and the width of the third trench is greater than or equal to the width of the source trench.

[0062] The spacing between the second trenches or the third trenches is greater than or equal to the spacing between the source trenches.

[0063] The intervals between the second trenches or the third trenches are equal or gradually increase in a direction from the device cell region to the terminal region.

[0064] The number of the third trenches is set according to the operating voltage of the semiconductor device. The greater the operating voltage of the semiconductor device, the greater the number of the third trenches.

[0065] A further improvement is that the trench gate semiconductor device is a SiC device, and the material of the first semiconductor epitaxial layer is SiC; or, the trench gate semiconductor device is a silicon-based device, and the material of the first semiconductor epitaxial layer is silicon.

[0066] A further improvement is that the trench gate semiconductor device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench gate semiconductor device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0067] The present invention provides a source trench in a device unit of a trench-gate semiconductor device and self-aligns to form a bottom doped region heavily doped with a second conductivity type at the bottom of the source trench. The depth of the source trench is similar to or slightly deeper than that of the gate trench, so that the depth of the bottom surface of the gate trench is within the depth range of the bottom doped region. In this way, the bottom doped region can form an electric field shield for the bottom region of the trench gate, thereby reducing the electric field lines converging in the bottom region of the trench gate, especially at the bottom corners of the trench gate, when the device is reverse biased, thereby reducing the electric field strength in the bottom region of the trench gate and improving the reliability of the device. The present invention is particularly suitable for SiC devices and improves the reliability of SiC devices such as SiC MOSFET devices.

[0068] The source trench of the present invention is also used to fill metal to form a source lead-out metal for the lead-out channel region and the source region, while the bottom doped region can also serve as an ohmic contact region between the channel region and the source lead-out metal. Therefore, the present invention does not require the introduction of additional process structures, which is conducive to reducing the size of the device.

[0069] In addition, the channel region of the present invention can be formed by using ion implantation with an angle after the source trench is formed and before filling, and the bottom doping region can also be formed at the bottom of the source trench by self-alignment using vertical ion implantation after the source trench is formed. Therefore, the channel region and the bottom doping region of the present invention do not require the introduction of an additional photomask, are easy to implement, and have a simple process and low cost.

[0070] In addition, the tilted ion implantation can also gradually increase the depth of the channel region from the trench gate to the source trench, which is beneficial to reducing the JFET effect of the device.

[0071] The structure of the source trench, channel region and bottom doping region of the present invention can be applied to the transition region and the terminal region, so that the terminal structure does not require an additional photomask, which can reduce process costs; moreover, by adjusting the number of third trenches in the terminal region corresponding to the source trench, the voltage resistance performance of the device can be adjusted, making the applicability of the present invention better. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0073] Figure 1 1 is a schematic structural diagram of a device unit of a trench gate semiconductor device according to a first embodiment of the present invention;

[0074] Figure 2 1 is a schematic structural diagram of a terminal structure of a trench gate semiconductor device according to a first embodiment of the present invention;

[0075] Figure 3 1 is a schematic structural diagram of a device unit of a trench gate semiconductor device according to a second embodiment of the present invention;

[0076] Figure 4A 1 is a schematic diagram of a device structure when a bottom doped region is formed in a method for manufacturing a trench gate semiconductor device according to an embodiment of the present invention;

[0077] Figure 4B It is a schematic diagram of the device structure when forming a channel region in the method for manufacturing a trench gate semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0078] like Figure 1 FIG. 1 is a schematic structural diagram of a device unit of a trench gate semiconductor device according to a first embodiment of the present invention. The device unit of the trench gate semiconductor device according to the embodiment of the present invention includes:

[0079] A first semiconductor epitaxial layer 3 having a first conductive type doping structure is provided, and a trench gate is formed in a selected area of ​​the first semiconductor epitaxial layer 3. The trench gate includes a gate trench 10, a gate dielectric layer 4 formed on the inner surface of the gate trench 10, and a gate conductive material layer 5 filled in the gate trench 10.

[0080] The source trench 11 is formed in a selected region of the first semiconductor epitaxial layer 3 , and the first semiconductor epitaxial layer 3 between the source trench 11 and the trench gate is a terrace region.

[0081] A channel region 8 doped with the second conductivity type is formed in the terrace region, and a source region 9 heavily doped with the first conductivity type is formed in a surface region of the channel region 8 .

[0082] The gate trench 10 passes through the channel region 8 longitudinally, and the surface area of ​​the first side surface of the channel region 8 covered by the side surface of the trench gate is used to form a channel.

[0083] The first semiconductor epitaxial layer 3 at the bottom of the channel region 8 constitutes a drift region.

[0084] The source trench 11 is filled with a source lead-out metal 7 .

[0085] A bottom doped region 6 heavily doped with the second conductive type is self-alignedly formed in the bottom area of ​​the source trench 11, and the bottom doped region 6 covers the bottom of the source lead-out metal 7 and forms an ohmic contact. The side surface of the source lead-out metal 7 is in contact with the second side surface of the channel region 8 and the second side surface of the source region 9 and is used to lead out the channel region 8 and the source region 9.

[0086] In the vertical direction, the bottom surface of the gate trench 10 is located within the depth range of the bottom doping region 6. The bottom doping region 6 forms an electric field shielding structure for the bottom area of ​​the trench gate, which is used to reduce the electric field strength in the bottom area of ​​the trench gate. Figure 1 As shown, when the device is reverse biased, if the bottom doping region 6 is not provided, the electric lines will easily converge to the bottom of the gate trench 10, especially the bottom corner; whereas in the first embodiment of the present invention, since the bottom doping region 6 is provided, the bottom doping region 6 can deplete the drift region, and the bottom doping region 6 attracts most of the electric lines, so the electric lines converged to the bottom area of ​​the gate trench 10 can be shielded, thereby reducing the electric field strength in the bottom area of ​​the trench gate.

[0087] In the first embodiment of the present invention, the depth of the channel region 8 gradually increases from the first side to the second side of the channel region 8. This structural arrangement of the channel region 8 can reduce the JFET effect formed by the channel region 8 and the drift region; in the prior art, reducing the electric field strength at the bottom of the trench gate often introduces a severe JFET effect.

[0088] The channel region 8 is an inclined ion implantation region. The channel region 8 is formed by using tilted ion implantation after the source trench 11 is opened. The tilted ion implantation is performed from the top surface of the terrace region and the side of the source trench 11 into the terrace region to form the channel region 8. In this way, the channel region 8 does not require an additional photomask.

[0089] Likewise, the bottom doped region 6 is formed in a self-aligned manner at the bottom of the source trench 11 , so no additional photomask is required.

[0090] In the first embodiment of the present invention, the trench-gate semiconductor device is a MOS transistor, and a drain region heavily doped with the first conductivity type is formed on the back surface of the first semiconductor epitaxial layer 3; the drain region is formed from a thinned semiconductor substrate 1 heavily doped with the first conductivity type. In other embodiments, the drain region may also be formed from a back-side ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate 1.

[0091] When the trench-gate semiconductor device is a MOS transistor, a buffer layer 2 doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer 3 and the top surface of the semiconductor substrate 1. The doping concentration of the buffer layer 2 is greater than the doping concentration of the first semiconductor epitaxial layer 3 and less than the doping concentration of the semiconductor substrate 1. The buffer layer 2 is also an epitaxial layer, but its doping concentration is between that of the first semiconductor epitaxial layer 3 and the semiconductor substrate 1. This can reduce the impact of defects in the semiconductor substrate 1 on the first semiconductor epitaxial layer 3 and, therefore, the performance of the device.

[0092] like Figure 2 1 is a schematic structural diagram of the terminal structure of the trench gate semiconductor device according to the first embodiment of the present invention. In the first embodiment of the present invention, the semiconductor device includes a plurality of device units connected in parallel, and each of the device units is formed in a device unit region.

[0093] The transition region surrounds the peripheral side of the device unit region, and the termination region surrounds the peripheral side of the transition region.

[0094] Figure 2 In the figure, the right side of the dotted line AA is the device unit region, also known as the primitive cell region, the area between the dotted lines AA and BB is the transition region, and the left side of the dotted line BB is the terminal region. The terminal structure is located in the transition region and the terminal region.

[0095] A second trench 11 a is formed in the first semiconductor epitaxial layer 3 in the transition region, and a plurality of third trenches 11 b are formed in the first semiconductor epitaxial layer 3 in the termination region.

[0096] The second trench 11 a and each of the third trenches 11 b are formed simultaneously with the source trench 11 .

[0097] A second well region (not shown) is formed between the source trench 11 and the second trench 11 a , between the second trench 11 a and the third trench 11 b , and between the third trenches 11 b . The second well region and the channel region 8 have the same process structure and are formed simultaneously.

[0098] The second trench 11 a is filled with a first lead metal 7 a and each second trench 11 a is filled with a second lead metal 7 b . The first lead metal 7 a , the second lead metal 7 b and the source lead metal 7 have the same process structure and are formed simultaneously.

[0099] A second bottom doping region (not shown) heavily doped with the second conductivity type is formed at the bottom of each of the second trenches 11a and the third trenches 11b. The process structure of each of the second bottom doping regions is the same as that of the bottom doping region 6 and is formed simultaneously.

[0100] The tops of the source lead-out metal 7 and the first lead-out metal 7a are both connected to a source (not shown) formed by a front metal layer, and the second lead-out metal 7b is floating.

[0101] The front structure of the device also includes: an interlayer film and a front metal layer; the front metal layer is patterned to form a gate and the source; the gate contacts the gate conductive material layer through a contact hole passing through the interlayer film.

[0102] In some embodiments, the width of the second trench 11 a is more than 10 times the width of the source trench 11 ; and the width of the third trench 11 b is greater than or equal to the width of the source trench 11 .

[0103] The distance between the second trenches 11 a or the third trenches 11 b is greater than or equal to the distance between the source trenches 11 .

[0104] The intervals between the second trenches 11 a or the third trenches 11 b are equal, or the intervals between the second trenches 11 a or the third trenches 11 b gradually increase in a direction from the device cell region to the terminal region.

[0105] The number of the third trenches 11 b is set according to the operating voltage of the semiconductor device. The greater the operating voltage of the semiconductor device, the greater the number of the third trenches 11 b.

[0106] In the first embodiment of the present invention, the trench-gate semiconductor device is a SiC device, and the first semiconductor epitaxial layer 3 is made of SiC. Both the buffer layer 2 and the semiconductor substrate 1 are made of SiC. The structure of the first embodiment of the present invention is particularly suitable for SiC devices, and is used to reduce the electric field strength at the bottom of the trench gate in SiC devices, a technical problem that urgently needs to be addressed in SiC devices. In other embodiments, the trench-gate semiconductor device may be a silicon-based device, and the first semiconductor epitaxial layer 3 may be made of silicon.

[0107] In a first embodiment of the present invention, the trench-gate semiconductor device is an N-type device, i.e., an N-type SiC MOSFET, having an N-type first conductivity type and a P-type second conductivity type. In SiC devices, nitrogen is typically used as an N-type dopant impurity, and aluminum is typically used as a P-type dopant impurity. In other embodiments, the trench-gate semiconductor device may be a P-type device, having a P-type first conductivity type and an N-type second conductivity type.

[0108] In a first embodiment of the present invention, a source trench 11 is provided in a device unit of a trench-gate semiconductor device, and a bottom doped region 6 heavily doped with a second conductivity type is self-alignedly formed at the bottom of the source trench 11. The depth of the source trench 11 is similar to or slightly deeper than the depth of the gate trench 10, so that the depth of the bottom surface of the gate trench 10 is within the depth range of the bottom doped region 6. In this way, the bottom doped region 6 can form an electric field shielding for the bottom region of the trench gate, thereby reducing the electric lines of force converging in the bottom region of the trench gate, especially at the bottom corners of the trench gate, when the device is reverse biased, thereby reducing the electric field strength in the bottom region of the trench gate and improving the reliability of the device. The present invention is particularly suitable for use in SiC devices to improve the reliability of SiC devices such as SiC MOSFET devices.

[0109] The source trench 11 of the first embodiment of the present invention is also used to fill metal to form a source lead-out metal 7 that leads to the channel region 8 and the source region 9, while the bottom doped region 6 can also serve as an ohmic contact region between the channel region 8 and the source lead-out metal 7. Therefore, the first embodiment of the present invention does not require the introduction of additional process structures, which is conducive to reducing the size of the device.

[0110] In addition, the channel region 8 of the first embodiment of the present invention can be formed by using ion implantation with an inclined angle after the source trench 11 is formed and before filling, and the bottom doping region 6 can also be formed at the bottom of the source trench 11 by self-alignment using vertical ion implantation after the source trench 11 is formed. Therefore, the channel region 8 and the bottom doping region 6 of the first embodiment of the present invention do not require the introduction of an additional photomask, are easy to implement, and have a simple process and low cost.

[0111] The structure of the source trench 11, the channel region 8 and the bottom doping region 6 of the first embodiment of the present invention can be applied to the transition region and the terminal region, so that the terminal structure does not require an additional photomask, which can reduce the process cost; moreover, by adjusting the number of third trenches 11b in the terminal region corresponding to the source trench 11, the voltage resistance performance of the device can be adjusted, making the applicability of the present invention better.

[0112] A trench gate semiconductor device according to a second embodiment of the present invention:

[0113] The trench gate semiconductor device according to the second embodiment of the present invention can be obtained by transforming the trench gate semiconductor device according to the first embodiment of the present invention. In the trench gate semiconductor device according to the second embodiment of the present invention:

[0114] The trench-gate semiconductor device is an IGBT device. A collector region 11 heavily doped with the second conductivity type is formed on the back surface of the first semiconductor epitaxial layer 3. The collector region 11 is composed of a thinned semiconductor substrate heavily doped with the second conductivity type. For an N-type SiC device, the semiconductor substrate is a P+-doped SiC substrate. In some embodiments, the collector region 11 may be composed of a back-side ion-implanted region heavily doped with the second conductivity type formed in the thinned semiconductor substrate 1. For an N-type SiC device, the back-side ion-implanted impurity constituting the collector region 11 is aluminum.

[0115] A field stop layer 12 doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer 3 and the top surface of the collector region 11. The doping concentration of the field stop layer 12 is greater than the doping concentration of the first semiconductor epitaxial layer 3 and less than the doping concentration of the semiconductor substrate 1. The field stop layer 12 is primarily used to reduce the electric field strength in the drift region to zero.

[0116] like Figure 4A FIG. 1 is a schematic diagram of a device structure when a bottom doped region is formed in a method for manufacturing a trench gate semiconductor device according to an embodiment of the present invention; FIG. Figure 4B FIG. 1 is a schematic diagram of a device structure when a channel region is formed in a method for manufacturing a trench gate semiconductor device according to an embodiment of the present invention. In the method for manufacturing a trench gate semiconductor device according to an embodiment of the present invention, the steps of forming a device unit include:

[0117] like Figure 1 As shown, a first semiconductor epitaxial layer 3 doped with a first conductive type is provided, and a trench gate is formed in a selected area of ​​the first semiconductor epitaxial layer 3, wherein the trench gate includes a gate trench 10, a gate dielectric layer 4 formed on the inner surface of the gate trench 10, and a gate conductive material layer 5 filled in the gate trench 10.

[0118] like Figure 4A As shown, a hard mask layer 201 is formed on the surface of the first semiconductor epitaxial layer 3 , and the hard mask layer 201 is patterned and etched. The opening area of ​​the hard mask layer 201 is the formation area of ​​the source trench 11 .

[0119] like Figure 4A As shown, the first semiconductor epitaxial layer 3 is etched using the hard mask layer 201 as a mask to form a source trench 11; the first semiconductor epitaxial layer 3 located between the source trench 11 and the trench gate is a platform region.

[0120] like Figure 4AAs shown, with the hard mask layer 201 as a barrier layer, ion implantation of a second conductive type heavy doping as indicated by mark 202 is performed in a self-aligned manner at the bottom region of the source trench 11 to form a bottom doping region 6. Outside the source trench 11, the implantation energy of the ion implantation of the bottom doping region 6 is ensured not to pass through the hard mask layer 201. Figure 4A As shown, the ion implantation 202 is a vertical implantation.

[0121] like Figure 4B As shown, with the hard mask layer 201 serving as a barrier layer, angled ion implantation of the second conductivity type, as indicated by reference numeral 203, is performed. The angled ion implantation is performed from the top surface of the terrace region and the side surfaces of the source trench 11 into the terrace region to form a channel region 8. The depth of the channel region 8 gradually increases from the first side surface to the second side surface of the channel region 8. The gate trench 10 vertically penetrates the channel region 8, and the surface area of ​​the first side surface of the channel region 8 covered by the side surface of the trench gate is used to form the channel. This structural configuration of the channel region 8 can reduce the JFET effect formed by the channel region 8 and the drift region.

[0122] The hard mask layer 201 is removed, and the source trench 11 is filled with a source lead-out metal 7 .

[0123] A source region 9 heavily doped with the first conductivity type is formed on the surface of the channel region 8 in the terrace region.

[0124] The bottom doped region 6 covers the bottom of the source lead-out metal 7 and forms an ohmic contact. The side of the source lead-out metal 7 contacts the second side of the channel region 8 and the second side of the source region 9 and is used to lead out the channel region 8 and the source region 9.

[0125] In the vertical direction, the bottom surface of the gate trench 10 is located within the depth range of the bottom doping region 6. The bottom doping region 6 forms an electric field shielding structure for the bottom area of ​​the trench gate, so as to reduce the electric field strength in the bottom area of ​​the trench gate.

[0126] The method according to the embodiment of the present invention can manufacture the device according to the first embodiment of the present invention. The trench-gate semiconductor device is a MOS transistor. The first semiconductor epitaxial layer 3 is formed on the surface of the semiconductor substrate 1 .

[0127] A buffer layer 2 doped with a first conductive type is formed between the bottom surface of the first semiconductor epitaxial layer 3 and the top surface of the semiconductor substrate 1 . The doping concentration of the buffer layer 2 is greater than the doping concentration of the first semiconductor epitaxial layer 3 and less than the doping concentration of the semiconductor substrate 1 .

[0128] The following positive processes will be carried out afterwards:

[0129] An interlayer film, contact holes, and a front metal layer are formed, and the front metal layer is patterned to form a gate and source. The gate contacts the gate conductive material layer through a contact hole passing through the interlayer film. The source is connected to the source lead metal 7.

[0130] After the front side process is completed, the following back side processes are also included:

[0131] The semiconductor substrate 1 is back-thinned.

[0132] The semiconductor substrate 1 is heavily doped with the first conductivity type, and the drain region is formed by thinning the back side of the semiconductor substrate 1. In other embodiments, the method can also be: performing back ion implantation of heavily doped with the first conductivity type to form the drain region in the thinned semiconductor substrate 1.

[0133] The method of the embodiment of the present invention can also manufacture the device structure of the second embodiment of the present invention. In this case, the trench gate semiconductor device is an IGBT device, and the first semiconductor epitaxial layer 3 is formed on the surface of the semiconductor substrate.

[0134] A field stop layer 12 doped with a first conductive type is formed between the bottom surface of the first semiconductor epitaxial layer 3 and the top surface of the collector region 11 . The doping concentration of the field stop layer 12 is greater than the doping concentration of the first semiconductor epitaxial layer 3 and less than the doping concentration of the semiconductor substrate 1 .

[0135] After the front side process is completed, the following back side processes are also included:

[0136] The semiconductor substrate is back-thinned; the semiconductor substrate is heavily doped with the second conductivity type, and the collector region 11 is formed by the back-thinned semiconductor substrate 1. In other embodiments, the method can also be: back-side ion implantation with heavy doping of the second conductivity type is performed to form the collector region 11 in the thinned semiconductor substrate.

[0137] The semiconductor device includes a plurality of device units connected in parallel, and each of the device units is formed in a device unit region.

[0138] The transition region surrounds the peripheral side of the device unit region, and the termination region surrounds the peripheral side of the transition region.

[0139] A second trench 11 a is formed in the first semiconductor epitaxial layer 3 in the transition region, and a plurality of third trenches 11 b are formed in the first semiconductor epitaxial layer 3 in the termination region.

[0140] The second trench 11 a and each of the third trenches 11 b are formed simultaneously with the source trench 11 .

[0141] A second well region is formed between the source trench 11 and the second trench 11 a , between the second trench 11 a and the third trench 11 b , and between the third trenches 11 b . The second well region and the channel region 8 have the same process structure and are formed simultaneously.

[0142] The second trench 11 a is filled with a first lead metal 7 a and each second trench 11 a is filled with a second lead metal 7 b . The first lead metal 7 a , the second lead metal 7 b and the source lead metal 7 have the same process structure and are formed simultaneously.

[0143] A second bottom doping region heavily doped with the second conductivity type is formed at the bottom of each of the second trenches 11 a and the third trenches 11 b . The process structure of each of the second bottom doping regions is the same as that of the bottom doping region 6 and is formed simultaneously.

[0144] The tops of the source lead-out metal 7 and the first lead-out metal 7a are both connected to the source formed by the front metal layer, and the second lead-out metal 7b is floating.

[0145] The width of the second trench 11 a is more than 10 times the width of the source trench 11 ; the width of the third trench 11 b is greater than or equal to the width of the source trench 11 .

[0146] The distance between the second trenches 11 a or the third trenches 11 b is greater than or equal to the distance between the source trenches 11 .

[0147] The intervals between the second trenches 11 a or the third trenches 11 b are equal, or the intervals between the second trenches 11 a or the third trenches 11 b gradually increase in a direction from the device cell region to the terminal region.

[0148] The number of the third trenches 11 b is set according to the operating voltage of the semiconductor device. The greater the operating voltage of the semiconductor device, the greater the number of the third trenches 11 b.

[0149] In the first embodiment of the present invention, the trench-gate semiconductor device is a SiC device, and the material of the first semiconductor epitaxial layer 3 is SiC; the material of the buffer layer 2 and the semiconductor substrate 1 are both SiC. The first embodiment of the present invention, formed by the method of the present embodiment, is particularly suitable for SiC devices, and is used to reduce the electric field strength at the bottom of the trench gate in SiC devices, which is a technical problem that needs to be urgently addressed in SiC devices. In other embodiments, the trench-gate semiconductor device can also be a silicon-based device, and the material of the first semiconductor epitaxial layer 3 is silicon.

[0150] In the first embodiment of the present invention, the trench-gate semiconductor device formed by the method of the present embodiment is an N-type device, i.e., an N-type SiC MOSFET, having an N-type first conductivity type and a P-type second conductivity type. In SiC devices, nitrogen is typically used as an N-type dopant impurity, and aluminum is typically used as a P-type dopant impurity. In other embodiments, the trench-gate semiconductor device can also be a P-type device, having a P-type first conductivity type and an N-type second conductivity type.

[0151] The device of the first embodiment of the present invention is further described below with reference to specific parameters, taking N-type SiC MOSFET as an example:

[0152] The semiconductor substrate 1 is a SiC substrate. The substrate, or semiconductor substrate 1, serves as a support. It is desirable for the substrate to be as thin as possible and have a higher doping concentration, meaning a lower resistivity, as possible. Nitrogen is typically used for doping. This reduces the device's thermal resistance and substrate resistance. However, substrate thickness is limited by process capabilities, and substrate doping concentration is limited by material properties. Currently, SiC MOSFET substrates typically have a thickness of around 150μm and a resistivity of approximately 0.020Ω*cm.

[0153] The buffer layer 2 is set to have a thickness of usually 1 μm and a doping concentration of usually 1e18 cm -3 The buffer layer 2 is used to reduce the influence of substrate defects on device performance.

[0154] The first semiconductor epitaxial layer 3 is set as follows: The doping concentration and thickness of the epitaxial layer, i.e., the first semiconductor epitaxial layer 3, determine the breakdown voltage of the device. Generally, for a 650V SiC MOSFET, the thickness of the epitaxial layer is usually around 6μm, and the corresponding doping concentration is around 2e16cm -3 For a 1200V SiC MOSFET, the thickness of its epitaxial layer is usually around 11μm, and the corresponding doping concentration is around 1e16cm -3 For a 170V SiC MOSFET, the thickness of the epitaxial layer is usually around 16μm, and the corresponding doping concentration is around 7e17cm -3 nearby.

[0155] The gate dielectric layer 4 is configured as follows: an oxide layer is used; the mobility of the oxide layer has a great influence on the performance of the device; there are many methods to improve the mobility of the oxide layer; the most common method is annealing in an N2 environment. The oxide layer is currently made of SiO2, and its thickness is usually nearby.

[0156] The gate conductive material layer 5 is configured to be made of polysilicon gate material or metal. The gate conductive material layer 5 is formed by etching the gate trench and filling it with conductive material such as metal or polysilicon.

[0157] The bottom doping region 6 is configured to be heavily doped P-type and connected to the channel region 8. The bottom doping region 6 has two functions:

[0158] First, the doping concentration of the bottom doped region 6 can form a good ohmic contact with the source lead metal 7 .

[0159] Second, the bottom doped region 6 can play a shielding role, reducing the electric field intensity on the surface of the bottom area of ​​the trench gate. The bottom doped region 6 is usually implanted with Al ions.

[0160] The channel region 8 is configured as a P-type channel region, and the doping concentration of the channel region 8 determines the threshold voltage of the device.

[0161] The source region 9 is configured as a heavily doped N-type source region, which is connected to the source lead metal 7 through a side wall and further connected to the source composed of a front metal layer.

[0162] As can be seen from the above, one device unit includes two trenches, namely the gate trench 10 and the source trench 11. The dimensions of the two trenches are set as:

[0163] 1. The width of the gate trench 10 is 0.7 μm. The width of the gate trench 10 corresponds to Figure 1 a in Figure 1 Only half of the gate trench 10 is drawn in the device unit, ie, the primitive cell; the corresponding depth of the gate trench 10 is 1.0 μm.

[0164] 2. Platform (Mesa) area: The width of the mesa area is 0.5 μm. The reason why it can be chosen to be so small is that no additional metal contact holes are required at the Mesa. The source lead metal 7 is connected to the heavily doped source region 9 through the side wall.

[0165] 3. The width of the source trench 11 is 0.8 μm, and the corresponding depth is 1.2 μm. The depth of the source trench 11 is slightly deeper than the depth of the gate trench 10, which can better shield the electric field strength at the bottom of the gate and improve device reliability. In some embodiments, the corresponding pitch is 0.7 μm + 0.5 μm * 2 + 0.8 μm, for a total of 2.5 μm.

[0166] The first embodiment of the present invention has the following features:

[0167] 1. The bottom doped region 6 and the channel region 8 do not require an additional photomask.

[0168] 2. The terminal structure of the device is also formed simultaneously through the formation process of the bottom doped region 6 and the channel region 8.

[0169] Please combine Figure 4A As shown, after the source trench 11 is etched, the hard mask layer 201 remains, which also serves as a barrier for subsequent ion implantation. Because of the hard mask, no additional photolithography layer is required to form the bottom doped region 6 and the channel region 8.

[0170] The bottom doping region 6 is implanted with a high dose of Alμminμm to form a heavily doped P-type region. It is implanted vertically with no angle or a very small angle to prevent channeling effect. The typical implantation dose is 1e15cm -2 The typical value of the injection energy is 50 to 100 keV.

[0171] like Figure 4B As shown, the channel region 8 is implanted at an angle of 15 to 60 degrees, with a typical value of 30 degrees or even 45 degrees. The channel region 8 is used to form a channel, and the typical value of the implantation dose is 1e12 cm -2 ~1e13cm -2 The typical value of the injection energy is around 100 to 600 keV.

[0172] In the first embodiment of the present invention, the bottom doped region 6 and the channel region 8 are formed at one time, without the need for an additional photomask, thus reducing costs. More importantly, because the channel region 8 is implanted at an oblique angle, the doping concentration distribution of the channel region 8 is deep near the Source Trench and shallow near the gate trench 10. This distribution can reduce the JFET effect of the channel region 8 and the drift region. This is different from the traditional structure, which introduces a very serious JFET effect in order to reduce the electric field strength at the bottom of the trench gate. Because the channel region 8 is also implanted at the bottom of the Source Trench, this will also make the shielding effect better.

[0173] In the terminal structure of the first embodiment of the present invention, no additional photomask is required.

[0174] The terminal of the first embodiment of the present invention adopts a floating ring terminal structure. For a typical terminal structure, please refer to Figure 2 shown.

[0175] The terminal structure of the first embodiment of the present invention has the following characteristics:

[0176] 1. Use Source-Trench as the terminal structure, without adding additional photoresist.

[0177] 2. There is a relatively large source-trench trench, namely the second trench 11 a , in the transition region. The width of the second trench 11 a is at least 10 times that of the source cell region, namely the device unit region.

[0178] 3. The metal in the Source-Trench of the terminal region, namely the second lead-out metal, is floating. Only the first lead-out metal in the first second trench 11a in the transition region is connected to the source metal, and the rest are floating.

[0179] 4. The termination region is composed of multiple floating second-lead metals that fill the source-trench. The number of floating second-lead metals is closely related to the required breakdown voltage. Typically, for a 650V device, 15 floating second-lead metals are required; for a 1200V device, 30 floating second-lead metals are required.

[0180] 5. The spacing between source-trench in the transition and terminal regions is greater than that in the original cell region. Each source-trench can be equally spaced, such as 3 μm between source-trench. More preferably, the distance between source-trench increases gradually, with one approach being a linear increase.

[0181] 6. The width of the terminal source-trench, i.e., the source-trench in the transition region and the terminal region, can be the same as the source-trench width in the original cell region. However, it is more preferably greater than the source-trench width in the original cell region. In one embodiment, the width of the terminal source-trench is 1 μm.

[0182] The first embodiment of the present invention adopts a dual-trench design and dual P-type channel oblique-angle implantation technology to reduce the electric field strength at the bottom of the SiC MOSFET trench, reduce the JFET effect in the channel and drift regions, and improve device reliability. The P-type channel does not require an additional photomask, reducing production costs. In addition, the technology used in the first embodiment of the present invention is also suitable for improving the reliability of silicon devices and SiC IGBT products.

[0183] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A trench gate semiconductor device, characterized in that: The device unit includes: A first semiconductor epitaxial layer having a first conductivity type doping layer, wherein a trench gate is formed in a selected region of the first semiconductor epitaxial layer, the trench gate comprising a gate trench, a gate dielectric layer formed on an inner surface of the gate trench, and a gate conductive material layer filled in the gate trench; A source trench is formed in a selected region of the first semiconductor epitaxial layer, wherein the first semiconductor epitaxial layer between the source trench and the trench gate is a terrace region; A channel region doped with the second conductivity type is formed in the platform region, and a source region heavily doped with the first conductivity type is formed in a surface region of the channel region; The gate trench passes through the channel region longitudinally, and the surface area of ​​the first side surface of the channel region covered by the side surface of the trench gate is used to form a channel; The source trench is filled with a source lead-out metal; A bottom doped region heavily doped with the second conductivity type is self-alignedly formed in the bottom area of ​​the source trench, and the bottom doped region covers the bottom of the source lead-out metal and forms an ohmic contact, and the side surface of the source lead-out metal contacts the second side surface of the channel region and the second side surface of the source region and is used to lead out the channel region and the source region; In the vertical direction, the bottom surface of the gate trench is located within the depth range of the bottom doped region, and the bottom doped region forms an electric field shielding structure for the bottom area of ​​the trench gate, so as to reduce the electric field strength in the bottom area of ​​the trench gate; The depth of the channel region gradually increases from the first side to the second side of the channel region; The channel region is an inclined ion implantation region, and the channel region is formed by using an inclined ion implantation after the source trench is opened, and the inclined ion implantation is implanted into the platform region from the top surface of the platform region and the side of the source trench to form the channel region; The semiconductor device includes a plurality of device units connected in parallel, each of the device units being formed in a device unit region; The transition region surrounds the peripheral side of the device unit region, and the terminal region surrounds the peripheral side of the transition region; A second trench is formed in the first semiconductor epitaxial layer in the transition region and a plurality of third trenches are formed in the first semiconductor epitaxial layer in the termination region; The second trench and each of the third trenches are formed simultaneously with the source trench; A second well region is formed between the source trench and the second trench, between the second trench and the third trench, and between each of the third trenches, wherein the second well region and the channel region have the same process structure and are formed simultaneously; The second trench is filled with a first lead metal and each of the third trenches is filled with a second lead metal, wherein the first lead metal, the second lead metal and the source lead metal have the same process structure and are formed simultaneously; A second bottom doped region heavily doped with the second conductivity type is formed at the bottom of each of the second trenches and the third trench, and the process structure of each of the second bottom doped regions is the same as that of the first bottom doped region and is formed simultaneously; The tops of the source lead-out metal and the first lead-out metal are both connected to the source formed by the front metal layer, and the second lead-out metal is floating.

2. The trench gate semiconductor device according to claim 1, wherein: The trench gate semiconductor device is a MOS transistor, wherein a drain region heavily doped with the first conductivity type is formed on the back surface of the first semiconductor epitaxial layer; the drain region is composed of a thinned semiconductor substrate heavily doped with the first conductivity type, or the drain region is composed of a back ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate; Alternatively, the trench gate semiconductor device is an IGBT device, and a collector region heavily doped with the second conductivity type is formed on the back side of the first semiconductor epitaxial layer; the collector region is composed of a thinned semiconductor substrate heavily doped with the second conductivity type, or the collector region is composed of a back ion implantation region heavily doped with the second conductivity type formed in a thinned semiconductor substrate.

3. The trench gate semiconductor device according to claim 2, wherein: When the trench gate semiconductor device is a MOS transistor, a buffer layer doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the semiconductor substrate, and the doping concentration of the buffer layer is greater than the doping concentration of the first semiconductor epitaxial layer and less than the doping concentration of the semiconductor substrate; When the trench gate semiconductor device is an IGBT, a field stop layer doped with a first conductive type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the collector region, and the doping concentration of the field stop layer is greater than the doping concentration of the first semiconductor epitaxial layer and less than the doping concentration of the semiconductor substrate.

4. The trench gate semiconductor device according to claim 1, wherein: The width of the second trench is more than 10 times the width of the source trench; the width of the third trench is greater than or equal to the width of the source trench; The spacing between the third trenches is greater than or equal to the spacing between the source trenches; The spacings between the third trenches are equal or gradually increase in the direction from the device unit region to the terminal region; The number of the third trenches is set according to the operating voltage of the semiconductor device. The greater the operating voltage of the semiconductor device, the greater the number of the third trenches.

5. The trench gate semiconductor device according to any one of claims 1 to 4, wherein: The trench gate semiconductor device is a SiC device, and the material of the first semiconductor epitaxial layer is SiC; or, the trench gate semiconductor device is a silicon-based device, and the material of the first semiconductor epitaxial layer is silicon.

6. A method for manufacturing a trench gate semiconductor device, characterized in that: The steps for forming a device unit include: Providing a first semiconductor epitaxial layer doped with a first conductivity type, forming a trench gate in a selected region of the first semiconductor epitaxial layer, the trench gate comprising a gate trench, a gate dielectric layer formed on an inner surface of the gate trench, and a gate conductive material layer filled in the gate trench; forming a hard mask layer on the surface of the first semiconductor epitaxial layer, and performing patterned etching on the hard mask layer, wherein the opening area of ​​the hard mask layer is the formation area of ​​the source trench; The first semiconductor epitaxial layer is etched using the hard mask layer as a mask to form a source trench; the first semiconductor epitaxial layer located between the source trench and the trench gate is a terrace region; Using the hard mask layer as a barrier layer, ion implantation of a second conductive type heavy dopant is performed in a self-aligned manner at the bottom region of the source trench to form a bottom doped region. The ion implantation energy of the bottom doped region is ensured to not penetrate the hard mask layer outside the source trench. Using the hard mask layer as a barrier layer, performing tilted ion implantation of a second conductivity type, wherein the tilted ion implantation is performed from the top surface of the platform region and the side of the source trench into the platform region to form a channel region; the depth of the channel region gradually increases from the first side to the second side of the channel region; the gate trench longitudinally passes through the channel region, and the surface area of ​​the first side of the channel region covered by the side of the trench gate is used to form a channel; removing the hard mask layer and filling the source electrode lead-out metal in the source electrode trench; forming a heavily doped source region of the first conductivity type on a surface of the channel region of the platform region; The bottom doped region covers the bottom of the source lead-out metal and forms an ohmic contact, and the side surface of the source lead-out metal contacts the second side surface of the channel region and the second side surface of the source region and is used to lead out the channel region and the source region; In the vertical direction, the bottom surface of the gate trench is located within the depth range of the bottom doped region, and the bottom doped region forms an electric field shielding structure for the bottom area of ​​the trench gate, so as to reduce the electric field strength in the bottom area of ​​the trench gate; The semiconductor device includes a plurality of device units connected in parallel, each of the device units being formed in a device unit region; The transition region surrounds the peripheral side of the device unit region, and the terminal region surrounds the peripheral side of the transition region; A second trench is formed in the first semiconductor epitaxial layer in the transition region and a plurality of third trenches are formed in the first semiconductor epitaxial layer in the termination region; The second trench and each of the third trenches are formed simultaneously with the source trench; A second well region is formed between the source trench and the second trench, between the second trench and the third trench, and between each of the third trenches, wherein the second well region and the channel region have the same process structure and are formed simultaneously; The second trench is filled with a first lead metal and each of the third trenches is filled with a second lead metal, wherein the first lead metal, the second lead metal and the source lead metal have the same process structure and are formed simultaneously; A second bottom doped region heavily doped with the second conductivity type is formed at the bottom of each of the second trenches and the third trench, and the process structure of each of the second bottom doped regions is the same as that of the first bottom doped region and is formed simultaneously; The tops of the source lead-out metal and the first lead-out metal are both connected to the source formed by the front metal layer, and the second lead-out metal is floating.

7. The method for manufacturing a trench gate semiconductor device according to claim 6, wherein: The trench gate semiconductor device is a MOS transistor. The first semiconductor epitaxial layer is formed on the surface of the semiconductor substrate. After the front surface process is completed, the following back surface process is also included: performing backside thinning on the semiconductor substrate; The semiconductor substrate is heavily doped with the first conductivity type, and the drain region is formed by thinning the semiconductor substrate at the back side; or, the drain region is formed in the thinned semiconductor substrate by performing back ion implantation with heavy doping of the first conductivity type; Alternatively, the trench gate semiconductor device is an IGBT device, the first semiconductor epitaxial layer is formed on the surface of the semiconductor substrate, and after the front side process is completed, the following back side process is further included: The back side of the semiconductor substrate is thinned; the semiconductor substrate is heavily doped with the second conductivity type, and the collector region is formed by the semiconductor substrate after the back side is thinned; or, back side ion implantation with heavy doping of the second conductivity type is performed to form a collector region in the thinned semiconductor substrate.

8. The method for manufacturing a trench gate semiconductor device according to claim 7, wherein: When the trench gate semiconductor device is a MOS transistor, a buffer layer doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the semiconductor substrate, and the doping concentration of the buffer layer is greater than the doping concentration of the first semiconductor epitaxial layer and less than the doping concentration of the semiconductor substrate; When the trench gate semiconductor device is an IGBT, a field stop layer doped with a first conductive type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the collector region, and the doping concentration of the field stop layer is greater than the doping concentration of the first semiconductor epitaxial layer and less than the doping concentration of the semiconductor substrate.

9. The method for manufacturing a trench gate semiconductor device according to claim 6, wherein: The width of the second trench is more than 10 times the width of the source trench; the width of the third trench is greater than or equal to the width of the source trench; The spacing between the third trenches is greater than or equal to the spacing between the source trenches; The spacings between the third trenches are equal or gradually increase in the direction from the device unit region to the terminal region; The number of the third trenches is set according to the operating voltage of the semiconductor device. The greater the operating voltage of the semiconductor device, the greater the number of the third trenches.

10. The method for manufacturing a trench gate semiconductor device according to any one of claims 6 to 9, wherein: The trench gate semiconductor device is a SiC device, and the material of the first semiconductor epitaxial layer is SiC; or, the trench gate semiconductor device is a silicon-based device, and the material of the first semiconductor epitaxial layer is silicon.

11. The method for manufacturing a trench gate semiconductor device according to claim 10, wherein: The trench gate semiconductor device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the trench gate semiconductor device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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