Preparation method of heterojunction battery and heterojunction battery

Abstract

The present invention relates to the technical field of preparation of solar cells, and specifically provides a preparation method of a heterojunction battery and a heterojunction battery, wherein the preparation method of the heterojunction battery comprises: forming a patterned mask on the first surface and / or the second surface of a semiconductor substrate layer; performing a texturing treatment on the area of ​​the semiconductor substrate layer not covered by the patterned mask, removing the patterned mask, and making the first surface and / or the second surface of the semiconductor substrate layer a light surface in the area corresponding to the patterned mask; forming a photosensitive film layer on one side of the first surface and / or the second surface of the semiconductor substrate layer; processing the photosensitive film layer to form a grid line preformed layer; the grid line preformed layer comprises a conductive pattern area, and the projection of the conductive pattern area on the first surface and / or the second surface of the semiconductor substrate layer corresponds to the light surface; and forming a grid line electrode by electroplating in the corresponding conductive pattern area. The present invention provides a preparation method of a heterojunction battery to improve the electrical performance and yield rate of the heterojunction battery.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell preparation, and in particular to a preparation method of a heterojunction cell and a heterojunction cell. Background Art

[0002] Crystalline silicon heterojunction solar cells (SHJ or HJT) deposit amorphous silicon thin films on crystalline silicon. They combine the advantages of crystalline silicon cells and thin-film cells, and have the advantages of simple structure, low process temperature, good passivation effect, high open circuit voltage / good temperature characteristics, and double-sided power generation. Copper electroplating is a new technology that reduces costs and increases efficiency in the metallization of gate electrodes, replacing the existing mainstream screen printing technology with high silver consumption, and is more suitable for application in heterojunction solar cells.

[0003] The process flow of copper electroplating in the prior art includes:

[0004] 1) Seed layer preparation: It is carried out on a textured silicon wafer (semiconductor substrate layer);

[0005] 2) Graphicalization: Screen printing or spraying a photosensitive resin layer on the seed layer, and through exposure and development, the photosensitive resin layer is formed into a layer structure corresponding to the pattern of the conductive graphic layer;

[0006] 3) Electroplating to form gate line electrodes in part of the conductive pattern.

[0007] In the above process flow, in 2), since the surface of the silicon wafer is all velvet, the surface of the seed layer obtained after velveting on one side of the silicon wafer is pyramid-shaped. After screen printing or spraying the photosensitive adhesive layer on the seed layer, the photosensitive adhesive layer and the seed layer are not fully in contact and a gap is left. Since there is residual developer after development in the graphic process of 2), the gate electrode and the seed layer in 3) are not fully in contact and a gap is left. On the one hand, it leads to poor electrical performance of the heterojunction battery; on the other hand, the contact effect between the gate electrode and the seed layer is poor, which leads to low adhesion between the gate electrode and the silicon wafer and low yield rate of the heterojunction battery. Summary of the invention

[0008] Therefore, the technical problem to be solved by the present invention is to overcome the defects of poor electrical performance and low yield of heterojunction batteries in the prior art, thereby providing a method for preparing a heterojunction battery and a heterojunction battery.

[0009] The present invention provides a method for preparing a heterojunction battery, comprising: providing a semiconductor substrate layer, the semiconductor substrate layer comprising a first surface and a second surface relative to each other; forming a patterned mask on the first surface and / or the second surface of the semiconductor substrate layer; performing a texturing treatment on the area of ​​the semiconductor substrate layer not covered by the patterned mask, so that the first surface and / or the second surface of the semiconductor substrate layer are partially texturized; removing the patterned mask, and the first surface and / or the second surface of the semiconductor substrate layer are light surfaces in the area corresponding to the patterned mask; forming a photosensitive film layer on one side of the first surface and / or the second surface of the semiconductor substrate layer; after the photosensitive film layer is formed on the first surface and / or the second surface of the semiconductor substrate layer, processing the photosensitive film layer to form a gate line pre-formed layer; the gate line pre-formed layer comprises a conductive pattern area, and the projection of the conductive pattern area on the first surface and / or the second surface of the semiconductor substrate layer corresponds to the light surface; and forming a gate line electrode by electroplating in the area corresponding to the conductive pattern area.

[0010] Optionally, the graphic mask is an acid-resistant mask; the texturing treatment adopts an acidic texturing solution, the acidic texturing solution includes a mixed solution of HF and / or HNO3, the texturing treatment temperature is 25°C-80°C, and the texturing treatment time is 100s-800s; or, the graphic mask is an alkali-resistant mask; the texturing treatment adopts an alkaline texturing solution, the alkaline texturing solution includes a NaOH solution, the mass percentage concentration of the alkaline texturing solution is 1%-10%, the texturing treatment temperature is 25°C-100°C, and the texturing treatment time is 200s-800s.

[0011] Optionally, before forming a patterned mask on the first surface and / or the second surface of the semiconductor substrate layer, the first surface and / or the second surface of the semiconductor substrate layer is polished; the polishing treatment uses an alkaline solution, the alkaline solution includes NaOH, the mass percentage concentration of NaOH is 1%-20%, the polishing treatment temperature is 25°C-80°C, and the polishing treatment time is 10s-300s; after the polishing treatment, the surface roughness of the semiconductor substrate layer is less than 0.2μm.

[0012] Optionally, the step of processing the photosensitive film layer to form a gate line pre-forming layer includes: providing a patterned shading film; laying the patterned shading film on the surface of the photosensitive film layer; exposing the first surface and / or the second surface of the semiconductor substrate layer; after the exposure treatment, developing the first surface and / or the second surface of the semiconductor substrate layer; wherein: the exposure treatment adopts laser direct imaging exposure; the development treatment adopts NaCO3 solution, the mass percentage concentration of NaCO3 is 1%-5%, and the temperature is 20℃-40℃; the gate line pre-forming layer also includes a non-conductive graphic area, and the non-conductive graphic area completely corresponds to the velvet of the first surface and / or the second surface; or, the velvet of the first surface of the non-conductive graphic area and / or the second surface also corresponds to the part of the smooth surface adjacent to the velvet; the conductive graphic area includes a main grid graphic area and a secondary grid graphic area, the width of the main grid graphic area is 30μm-100μm; the width of the secondary grid graphic area is 5μm-30μm.

[0013] Optionally, the step of removing the graphic mask includes: using a first stripping solution to perform a first cleaning treatment on the graphic mask; when the graphic mask is an acid-resistant mask, the first stripping solution includes NaOH; the mass percentage concentration of NaOH is 1%-10%, the temperature of the first cleaning treatment is 25°C-80°C, and the time of the first cleaning treatment is 30s-300s; when the graphic mask is an alkali-resistant mask, the first stripping solution includes HF; the mass percentage concentration of HF is 1%-10%, the temperature of the first cleaning treatment is 25°C-80°C, and the time of the first cleaning treatment is 60s-300s.

[0014] Optionally, after removing the patterned mask, the process further includes: forming an intrinsic semiconductor layer on the first surface and / or the second surface of the semiconductor substrate layer; after forming the intrinsic semiconductor layer, forming a doped semiconductor layer on a side of the intrinsic semiconductor layer away from the semiconductor substrate layer; after forming the doped semiconductor layer on a side of the intrinsic semiconductor layer away from the semiconductor substrate layer, forming a transparent conductive film on a side of the doped semiconductor layer away from the semiconductor substrate layer; after forming the transparent conductive film on a side of the doped semiconductor layer away from the semiconductor substrate layer, forming a seed layer on a side of the transparent conductive film away from the semiconductor substrate layer; after forming the seed layer on a side of the transparent conductive film away from the semiconductor substrate layer, forming a photosensitive film layer on a side of the seed layer away from the semiconductor substrate layer; the seed layer covers the light surface and the velvet surface; the photosensitive film layer covers the entire surface of the light surface and the velvet surface; the material of the seed layer includes copper; the material of the gate line electrode includes copper.

[0015] Optionally, after forming the gate line electrode by electroplating in the corresponding conductive graphic area, it also includes: removing the non-conductive graphic area in the gate line pre-formed layer; the step of removing the non-conductive graphic area includes: using a second film stripping solution to perform a second cleaning treatment on the non-conductive graphic area; the second film stripping solution includes NaOH; the mass percentage concentration of NaOH is 1%-10%, the temperature of the second cleaning treatment is 25°C-50°C, and the time of the second cleaning treatment is 60s-300s.

[0016] Optionally, after removing the non-conductive graphic area, part of the seed layer is removed; the step of removing part of the seed layer includes: using an etching solution to etch the part of the seed layer corresponding to the non-conductive graphic area; the etching solution includes a mixed solution of H2O2 and H2SO4; in the mixed solution of H2O2 and H2SO4, the molar ratio of H2O2 and H2SO4 in the etching solution is 0.1-1; the etching treatment temperature is 25°C-50°C, and the etching treatment time is 10s-100s.

[0017] The present invention also provides a heterojunction battery, which is prepared by the preparation method of the heterojunction battery described in the present invention, and includes: a semiconductor substrate layer, the semiconductor substrate layer includes a first surface and a second surface relative to each other; the first surface and / or the second surface are partially velvety and partially smooth; a gate line electrode, the projection of the gate line electrode on the first surface and / or the second surface of the semiconductor substrate layer corresponds only to the smooth surface.

[0018] Optionally, it also includes: an intrinsic semiconductor layer; located on the first surface and / or the second surface of the semiconductor substrate layer, and located between the semiconductor substrate layer and the gate electrode; a doped semiconductor layer, located on the side of the intrinsic semiconductor layer away from the semiconductor substrate layer, and located between the intrinsic semiconductor layer and the gate electrode; a transparent conductive film, located on the side of the doped semiconductor layer away from the semiconductor substrate layer, and located between the doped semiconductor layer and the gate electrode; a seed layer; located on the side of the transparent conductive film away from the semiconductor substrate layer; and located between the transparent conductive film and the gate electrode.

[0019] The beneficial effects of the present invention are:

[0020] The present invention provides a method for preparing a heterojunction battery, firstly, forming a patterned mask on the first surface and / or the second surface of the semiconductor substrate layer; performing a texturing treatment on the area of ​​the semiconductor substrate layer not covered by the patterned mask, and after removing the patterned mask, the first surface and / or the second surface of the semiconductor substrate layer is partially texturized and partially light; secondly, forming a photosensitive film layer on one side of the first surface and / or the second surface of the semiconductor substrate layer, and part of the photosensitive film layer is arranged corresponding to the light surface, so as to reduce the probability of a gap between the photosensitive film layer and the texturized surface; performing a texturing treatment on the photosensitive film layer The method is to process the gate line pre-formed layer to form a gate line pre-formed layer, wherein the gate line pre-formed layer includes a conductive pattern area, the projection of the conductive pattern area on the first surface and / or the second surface of the semiconductor substrate layer corresponds to the light surface, and the gate line electrode is formed by electroplating in the corresponding conductive pattern area, so that at least part of the gate line electrode is arranged corresponding to the light surface to avoid a gap between the gate line electrode and the velvet structure, on the one hand, reducing the contact resistance between the gate line electrode and the semiconductor substrate layer, thereby improving the electrical performance of the battery; on the other hand, improving the adhesion between the gate line electrode and the semiconductor substrate layer, thereby improving the yield rate of the heterojunction battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 is a flow chart of a method for preparing a heterojunction battery in an embodiment of the present invention;

[0023] Figures 2 to 14 It is a structural schematic diagram of each process in the method for preparing a heterojunction battery in an embodiment of the present invention;

[0024] Description of reference numerals:

[0025] 1-semiconductor substrate layer; 2-patterned mask; 3-seed layer; 4-photosensitive film layer; 5-gate line pre-formation layer; 51-conductive pattern area; 52-non-conductive pattern area; 511-main gate pattern area; 512-sub-gate pattern area; 6-gate line electrode. DETAILED DESCRIPTION

[0026] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0028] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0029] Example

[0030] An embodiment of the present invention provides a method for preparing a heterojunction battery, characterized in that:

[0031] S1: providing a semiconductor substrate layer, wherein the semiconductor substrate layer comprises a first surface and a second surface opposite to each other;

[0032] S2: forming a patterned mask on the first surface and / or the second surface of the semiconductor substrate layer;

[0033] S3: performing a texturing process on the area of ​​the semiconductor substrate layer not covered by the patterned mask, so that the first surface and / or the second surface of the semiconductor substrate layer is partially textured;

[0034] S4: removing the patterned mask, so that the first surface and / or the second surface of the semiconductor substrate layer is a smooth surface in the area corresponding to the patterned mask;

[0035] S5: forming a photosensitive film layer on one side of the first surface and / or the second surface of the semiconductor substrate layer;

[0036] S6: After forming a photosensitive film layer on the first surface and / or the second surface of the semiconductor substrate layer, processing the photosensitive film layer to form a gate line pre-formed layer; the gate line pre-formed layer includes a conductive pattern area, and the projection of the conductive pattern area on the first surface and / or the second surface of the semiconductor substrate layer corresponds to the optical surface.

[0037] S7: forming gate line electrodes by electroplating in the areas corresponding to the conductive patterns.

[0038] In this embodiment, firstly, a patterned mask is formed on the first surface and / or the second surface of the semiconductor substrate layer; a texture treatment is performed on the area of ​​the semiconductor substrate layer not covered by the patterned mask, and after the patterned mask is removed, the first surface and / or the second surface of the semiconductor substrate layer is partially textured and partially light; secondly, a photosensitive film layer is formed on one side of the first surface and / or the second surface of the semiconductor substrate layer, and part of the photosensitive film layer is arranged corresponding to the light surface, so as to reduce the probability of a gap between the photosensitive film layer and the texture surface; the photosensitive film layer is processed to form a gate electrode; A gate line pre-formed layer, wherein the gate line pre-formed layer includes a conductive pattern area, the projection of the conductive pattern area on the first surface and / or the second surface of the semiconductor substrate layer corresponds to the light surface, and a gate line electrode is formed by electroplating in the corresponding conductive pattern area, so that at least part of the gate line electrode is arranged corresponding to the light surface, avoiding a gap between the gate line electrode and the velvet structure, on the one hand reducing the contact resistance between the gate line electrode and the semiconductor substrate layer, thereby improving the electrical performance of the battery; on the other hand improving the adhesion between the gate line electrode and the semiconductor substrate layer, thereby improving the yield rate of the heterojunction battery.

[0039] The method for preparing the heterojunction battery further includes: before forming a patterned mask on the first surface and / or the second surface of the semiconductor substrate layer, polishing the first surface and / or the second surface of the semiconductor substrate layer.

[0040] After removing the patterned mask, the preparation method of the heterojunction battery also includes: forming an intrinsic semiconductor layer on the first surface and / or the second surface of the semiconductor substrate layer; after forming the intrinsic semiconductor layer, forming a doped semiconductor layer on the side of the intrinsic semiconductor layer away from the semiconductor substrate layer; after forming the doped semiconductor layer on the side of the intrinsic semiconductor layer away from the semiconductor substrate layer, forming a transparent conductive film on the side of the doped semiconductor layer away from the semiconductor substrate layer; after forming the transparent conductive film on the side of the doped semiconductor layer away from the semiconductor substrate layer, forming a seed layer on the side of the transparent conductive film away from the semiconductor substrate layer; after forming the seed layer on the side of the transparent conductive film away from the semiconductor substrate layer, forming a photosensitive film layer on the side of the seed layer away from the semiconductor substrate layer.

[0041] The steps of processing the photosensitive film layer to form a gate line pre-formed layer include: providing a patterned light-shielding film; laying the patterned light-shielding film on the surface of the photosensitive film layer; exposing the first surface and / or the second surface of the semiconductor substrate layer; and after the exposure treatment, developing the first surface and / or the second surface of the semiconductor substrate layer.

[0042] The gate line pre-formed layer also includes a non-conductive graphic area, which completely corresponds to the velvet surface of the first surface and / or the second surface; or, the non-conductive graphic area corresponds to the velvet surface of the first surface and / or the second surface, and also corresponds to the part of the smooth surface adjacent to the velvet surface.

[0043] Reference below Figure 2-Figure 14 The preparation method of the heterojunction battery is described in detail, taking the preparation on the first surface of the semiconductor substrate layer as an example.

[0044] refer to Figure 2 , providing a semiconductor substrate layer 1.

[0045] The semiconductor substrate layer 1 includes a first surface and a second surface opposite to each other.

[0046] Specifically, the first surface of the semiconductor substrate layer 1 is the front surface of the semiconductor substrate layer 1, and the second surface of the semiconductor substrate layer 1 is the back surface of the semiconductor substrate layer 1. In other embodiments, the first surface of the semiconductor substrate layer is the back surface of the semiconductor substrate layer, and the second surface of the semiconductor substrate layer is the front surface of the semiconductor substrate layer.

[0047] The material of the semiconductor substrate layer 1 includes silicon. In other embodiments, the material of the semiconductor substrate layer is other semiconductor materials, such as silicon germanium.

[0048] In this embodiment, the conductivity type of the semiconductor substrate layer is N-type, for example, it can be an N-type silicon wafer, which is suitable for the preparation of heterojunction batteries.

[0049] In one embodiment, the semiconductor substrate layer 1 has a thickness of 80 μm-200 μm, for example, 80 μm, 100 μm, 150 μm or 200 μm.

[0050] refer to Figure 3 , the first surface of the semiconductor substrate layer 1 is polished.

[0051] In one embodiment, the polishing treatment adopts alkali solution, and the alkali solution includes NaOH, and the mass percentage concentration of NaOH is 1%-20%, for example, 1%, 5%, 10%, 15% or 20%; the polishing treatment temperature is 25°C-80°C, for example, 25°C, 40°C, 60°C or 80°C; the polishing treatment time is 10s-300s, for example, 10s, 50s, 100s, 150s, 200s, 250s or 300s.

[0052] In this embodiment, after the polishing process, the surface roughness of the semiconductor substrate layer is less than 0.2 μm. Since the subsequently formed photosensitive film layer is in vertical contact with the surface of the semiconductor substrate layer, the surface roughness of the semiconductor substrate layer is less than 0.2 μm, and residual feet are not easily generated when the surface of the semiconductor substrate layer is developed.

[0053] In other embodiments, the second surface of the semiconductor substrate layer may be polished while the first surface of the semiconductor substrate layer is polished.

[0054] refer to Figure 4 , a patterned mask 2 is formed on the first surface of the semiconductor substrate layer 1.

[0055] After the first surface of the semiconductor substrate layer 1 is polished, a patterned mask 2 is formed on the first surface of the semiconductor substrate layer 1 .

[0056] In one embodiment, the process of forming the patterned mask 2 includes a screen printing process or a spray coating process.

[0057] In one embodiment, the patterned mask 2 is an acid-resistant mask; in another embodiment, the patterned mask 2 is an alkali-resistant mask.

[0058] In other embodiments, while forming a patterned mask on the first surface of the semiconductor substrate layer, a patterned mask is formed on the second surface of the semiconductor substrate layer.

[0059] refer to Figure 5 , a texturing process is performed on the area of ​​the first surface of the semiconductor substrate layer 1 that is not covered by the patterned mask 2.

[0060] After forming a patterned mask 2 on the first surface of the semiconductor substrate layer 1, a texturing process is performed on the area of ​​the semiconductor substrate layer 1 not covered by the patterned mask 2, so that the first surface of the semiconductor substrate layer is partially textured.

[0061] In one embodiment, the patterned mask 2 is an acid-resistant mask; the texturing treatment adopts an acidic texturing solution, and the acidic texturing solution includes a mixed solution of HF and / or HNO3, and the temperature of the texturing treatment is 25°C-80°C, for example, 25°C, 40°C, 60°C or 80°C; the time of the texturing treatment is 100s-800s, for example, 100s, 200s, 300s, 400s, 500s, 600s, 700s or 800s.

[0062] In another embodiment, the patterned mask 2 is an alkali-resistant mask; the texturing treatment adopts an alkaline texturing solution, and the alkaline texturing solution includes a NaOH solution, and the mass percentage concentration of the alkaline texturing solution is 1%-10%, for example, 1%, 3%, 5%, 7%, 9% or 10%; the texturing treatment temperature is 25°C-100°C, for example, 25°C, 40°C, 60°C, 80°C or 100°C; the texturing treatment time is 200s-800s, for example, 200s, 300s, 400s, 500s, 600s, 700s or 800s.

[0063] In other embodiments, the area of ​​the first surface of the semiconductor substrate layer 1 not covered by the patterned mask 2 may be textured while the area of ​​the second surface of the semiconductor substrate layer not covered by the patterned mask is textured.

[0064] refer to Figure 6 , remove the patterned mask 2.

[0065] After texturing the area of ​​the semiconductor substrate layer 1 not covered by the patterned mask 2 , the patterned mask 2 is removed.

[0066] In one embodiment, the step of removing the patterned mask includes: performing a first cleaning process on the patterned mask using a first stripping solution.

[0067] In one embodiment, when the patterned mask is an acid-resistant mask, the first stripping solution includes NaOH; the mass percentage concentration of NaOH is 1%-10%, for example, 1%, 3%, 5%, 7%, 9% or 10%; the temperature of the first cleaning treatment is 25°C-80°C, for example, 25°C, 40°C, 60°C or 80°C; the time of the first cleaning treatment is 30s-300s, for example, 30s, 100s, 200s or 300s.

[0068] In another embodiment, when the patterned mask is an alkali-resistant mask, the first stripping solution includes HF; the mass percentage concentration of HF is 1%-10%, for example, 1%, 3%, 5%, 7%, 9% or 10%; the temperature of the first cleaning treatment is 25°C-80°C, for example, 25°C, 40°C, 60°C or 80°C; the time of the first cleaning treatment is 60s-300s, for example, 60s, 100s, 200s or 300s.

[0069] refer to Figure 7 , a seed layer 3 is formed on one side of the first surface of the semiconductor substrate layer 1.

[0070] After removing the patterned mask 2, the preparation method of the heterojunction battery further includes: forming an intrinsic semiconductor layer (not shown in the figure) on the first surface of the semiconductor substrate layer 1; after forming the intrinsic semiconductor layer on the first surface of the semiconductor substrate layer 1, forming a doped semiconductor layer (not shown in the figure) on the side of the intrinsic semiconductor layer away from the semiconductor substrate layer 1; after forming the doped semiconductor layer on the side of the intrinsic semiconductor layer away from the semiconductor substrate layer 1, forming a transparent conductive film (not shown in the figure) on the side of the doped semiconductor layer away from the semiconductor substrate layer 1; after forming the transparent conductive film on the side of the doped semiconductor layer away from the semiconductor substrate layer 1, forming a seed layer 3 on the side of the transparent conductive film away from the semiconductor substrate layer. The seed layer 3 can be better combined with the transparent conductive film, which is conducive to the subsequent electroplating to form a more dense gate electrode and improve the reliability of the gate electrode.

[0071] It should be noted that after the seed layer 3 is formed on the side of the transparent conductive film away from the semiconductor substrate layer, the seed layer 3 covers the smooth surface and the velvet surface. In the subsequent process, part of the seed layer 3 needs to be removed so that the seed layer 3 is arranged corresponding to the projection area of ​​the gate line electrode on the semiconductor substrate layer.

[0072] In this embodiment, the material of the seed layer 3 includes copper. In one embodiment, the process of forming the intrinsic semiconductor layer includes a chemical vapor deposition process; the process of forming the doped semiconductor layer includes a chemical vapor deposition process; and the process of forming the transparent conductive film includes a physical vapor deposition process.

[0073] In other embodiments, a seed layer may be formed on the second surface of the semiconductor substrate layer while a seed layer is formed on the first surface of the semiconductor substrate layer.

[0074] refer to Figure 8 A photosensitive film layer 4 is formed on a side of the seed layer 3 away from the semiconductor substrate layer 1 .

[0075] After forming the seed layer 3 on the first surface of the semiconductor substrate layer 1, a photosensitive film layer 4 is formed on the side of the seed layer 3 away from the semiconductor substrate layer 1. The photosensitive film layer 4 covers the entire surface of the light surface and the velvet surface.

[0076] In other embodiments, a photosensitive film layer may be formed on one side of the second surface of the semiconductor substrate layer while a photosensitive film layer is formed on the side of the seed layer away from the semiconductor substrate layer.

[0077] refer to Fig. 9 and Fig.10 , the photosensitive film layer 4 is processed to form a gate line pre-forming layer 5.

[0078] After forming a photosensitive film layer 4 on a side of the seed layer 3 away from the semiconductor substrate layer 1, the photosensitive film layer 4 is processed to form a gate line pre-formed layer 5, wherein the gate line pre-formed layer 5 includes a conductive pattern area 51, and the projection of the conductive pattern area 51 on the first surface of the semiconductor substrate layer 1 corresponds to the light surface. In this way, a gap can be avoided between the gate line electrode formed subsequently and the semiconductor substrate layer.

[0079] It should be noted that the gate line pre-formed layer 5 also includes a non-conductive pattern area 52, and the non-conductive pattern area 52 completely corresponds to the suede surface of the first surface (refer to Fig. 9 ); or, the non-conductive pattern area 52 corresponds to the velvet surface of the first surface, and also corresponds to the part of the smooth surface adjacent to the velvet surface (reference Fig.10 In this embodiment, after the gate line pre-formed layer 5 is formed, the non-conductive pattern area 52 is completely arranged corresponding to the velvet surface of the first surface (refer to Fig. 9 ) is used to carry out subsequent processes for explanation. In other embodiments, reference may be made to Fig.10 A subsequent electroplating process is performed to form gate line electrodes.

[0080] The steps of processing the photosensitive film layer 4 to form a gate line pre-formed layer 5 include: providing a patterned light-shielding film (not shown in the figure); laying the patterned light-shielding film on the surface of the photosensitive film layer 4; exposing the first surface of the semiconductor substrate layer 1; and after the exposure treatment, developing the first surface of the semiconductor substrate layer.

[0081] In one embodiment, the exposure process uses laser direct imaging exposure technology. Laser direct imaging technology, namely Laser Direct Imaging (abbreviated as LDI), is a type of direct writing exposure technology. After this technology is applied to the exposure process, compared with traditional mask (film) exposure, it can save the time required for multiple processes such as plate making and process verification, and greatly improve production efficiency. In addition, since no mask (film) is required, it is possible to optimize the alignment error caused by thermal expansion, avoid defects caused by mask defects, etc., thereby improving the accuracy and yield of mask pattern production. In other embodiments, the exposure process uses other exposure processing methods.

[0082] In one embodiment, the development treatment uses a NaCO3 solution, the mass percentage concentration of the NaCO3 is 1%-5%, for example, 1%, 3% or 5%; the temperature is 20°C-40°C, for example, 20°C, 30°C or 40°C.

[0083] refer to Fig.11 , Fig.11 It is a top view of the semiconductor substrate layer 1. Fig.11The dotted line frame area in the figure is the conductive pattern area 51, which corresponds to the light surface area of ​​the first surface of the semiconductor substrate layer. The conductive pattern area 51 includes a main grid pattern area 511 and a secondary grid pattern area 512. The main grid pattern area 511 and the secondary grid pattern area 512 are arranged vertically to each other. Fig.11 Where X is the width of the main grid pattern area 511, Fig.11 Where Y is the width of the auxiliary grid pattern area 512, Fig.11 The white area outside the middle dotted frame is the non-conductive pattern area 52, corresponding to the suede area of ​​the first surface of the semiconductor substrate layer.

[0084] In one embodiment, the width of the secondary grid pattern area 512 is 5 μm-30 μm, for example, 5, 10, 15 μm, 20 μm, 25 μm or 30 μm; the width of the main grid pattern area 511 is 30 μm-100 μm, for example, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm or 100 μm. If the width of the conductive pattern area 51 is too large, the width of the gate electrode formed subsequently is too large, the shading area of ​​the heterojunction battery is large, and the power loss is large; if the width of the conductive pattern area 51 is too small, the width of the gate electrode formed subsequently is too small, and the effect of improving the adhesion between the gate electrode and the semiconductor substrate layer is small.

[0085] refer to Fig.12 , a gate line electrode 6 is formed by electroplating in the conductive pattern area 51 .

[0086] After the photosensitive film layer 4 is processed to form the gate line pre-formed layer 5, the gate line electrode 6 is formed by electroplating in the corresponding conductive pattern area 51, and the projection of the conductive pattern area 51 on the first surface of the semiconductor substrate layer 1 corresponds to the light surface. In this way, a gap is avoided between the gate line electrode 6 and the semiconductor substrate layer 1, which reduces the contact resistance between the gate line electrode 6 and the semiconductor substrate layer 1, thereby improving the electrical performance of the battery; on the other hand, the adhesion between the gate line electrode 6 and the semiconductor substrate layer 1 is improved, thereby improving the yield rate of the heterojunction battery.

[0087] In this embodiment, the material of the gate line electrode 6 includes copper.

[0088] refer to Fig.13 , remove the non-conductive pattern area 52 in the gate line pre-formed layer 5.

[0089] After the gate line electrode 6 is formed by electroplating corresponding to the conductive pattern area 51 , the non-conductive pattern area 52 in the gate line pre-formed layer 5 is removed.

[0090] In one embodiment, the step of removing the non-conductive graphic area 52 includes: performing a second cleaning treatment on the non-conductive graphic area 52 using a second film stripping solution; the second film stripping solution includes NaOH; the mass percentage concentration of NaOH is 1%-10%, for example, 1%, 3%, 5%, 7%, 9% or 10%; the temperature of the second cleaning treatment is 25°C-50°C, for example, 25°C, 30°C, 35°C, 40°C, 45°C or 50°C; the time of the second cleaning treatment is 60s-300s, for example, 60s, 100s, 200s or 300s.

[0091] refer to Fig.14 , remove part of the seed layer 3.

[0092] After removing the non-conductive pattern area 52 , a portion of the seed layer 3 is removed.

[0093] Specifically, the seed layer 3 corresponding to the velvet surface is removed, and the seed layer 3 corresponding to the smooth surface is retained. The gate electrode formed above can be in seamless contact with the transparent conductive layer, avoiding back etching during the process of removing part of the seed layer 3, thereby improving the electrical performance of the heterojunction battery.

[0094] In one embodiment, the step of removing part of the seed layer 3 includes: etching the part of the seed layer corresponding to the non-conductive graphic area 52 with an etching solution; the etching solution includes a mixed solution of H2O2 and H2SO4; in the mixed solution of H2O2 and H2SO4, the molar ratio of H2O2 and H2SO4 in the etching solution is 0.1-1, for example, 0.1, 0.3, 0.5, 0.7, 0.9 or 1; the etching treatment temperature is 25°C-50°C, for example, 25, 30°C, 35°C, 40°C, 45°C or 50°C; the etching treatment time is 10s-100s, for example, 10s, 20s, 40s, 60s, 80s or 100s.

[0095] This embodiment also provides a heterojunction battery, which is prepared by the above-mentioned heterojunction battery preparation method, referring to Fig.14, including: a semiconductor substrate layer 1, the semiconductor substrate layer 1 includes a first surface and a second surface opposite to each other; the first surface and / or the second surface are partially velvety and partially smooth; a gate electrode 6, the projection of the gate electrode 6 on the first surface and / or the second surface of the semiconductor substrate layer 1 corresponds to and only corresponds to the smooth surface; also including: an intrinsic semiconductor layer (not shown in the figure); located on the first surface and / or the second surface of the semiconductor substrate layer 1, and located between the semiconductor substrate layer 1 and the gate electrode 6; a doped semiconductor layer (not shown in the figure), located on the side of the intrinsic semiconductor layer away from the semiconductor substrate layer 1, and located between the intrinsic semiconductor layer and the gate electrode 6; a transparent conductive film (not shown in the figure), located on the side of the doped semiconductor layer away from the semiconductor substrate layer, and located between the doped semiconductor layer and the gate electrode 6; a seed layer 3; located on the side of the transparent conductive film away from the semiconductor substrate layer 1; and located between the transparent conductive film and the gate electrode 6.

[0096] Since the first surface and / or the second surface in the heterojunction battery is partially velvety and partially smooth, the surface of the intrinsic semiconductor layer, the surface of the doped semiconductor layer, the surface of the transparent conductive film and the surface of one side of the seed layer 3 are all partially velvety and partially smooth. The projection of the gate line electrode 6 on the first surface and / or the second surface of the semiconductor substrate layer 1 corresponds to the smooth surface. The gate line electrode 6 contacts the smooth area of ​​the seed layer, which can avoid the contact between the gate line electrode and the velvet structure. On the one hand, the contact resistance between the gate line electrode 6 and the seed layer 3 is reduced, and then the contact resistance between the gate line electrode 6 and the semiconductor substrate layer 1 is reduced, thereby improving the electrical performance of the battery; on the other hand, the adhesion between the gate line electrode 6 and the semiconductor substrate layer is improved, thereby improving the yield rate of the heterojunction battery.

[0097] Comparative Example

[0098] The comparative example provides a heterojunction battery formed by using an existing heterojunction battery preparation method, the preparation method comprising:

[0099] providing a semiconductor substrate layer;

[0100] Performing a texturing treatment on at least one side surface of the semiconductor substrate layer;

[0101] After performing a texturing process on at least one side surface of the semiconductor substrate layer, an intrinsic semiconductor layer, a doped semiconductor layer and a transparent conductive film are sequentially formed on at least one side surface of the semiconductor substrate layer;

[0102] forming a seed layer on a side of the transparent conductive film away from the semiconductor substrate layer;

[0103] forming a photosensitive film layer on a side of the seed layer away from the semiconductor substrate layer;

[0104] After forming a photosensitive film layer on a side of the seed layer away from the semiconductor substrate layer, processing the photosensitive film layer to form a gate line pre-formed layer; the gate line pre-formed layer includes a conductive pattern area;

[0105] The gate line electrodes are formed by electroplating in the areas corresponding to the conductive pattern layer.

[0106] Table 1

[0107] Conversion efficiency (%) Open circuit voltage(mV) <![CDATA[Short-circuit current density (mA / cm 2 )]]> Fill factor (%) Comparative Example 25.09 747 39.73 84.55 Example 25.38 748 39.74 85.4

[0108] The electrical properties of heterojunction batteries include conversion efficiency, open circuit voltage, short circuit current density and fill factor. After testing, the conversion efficiency of the heterojunction battery obtained by the preparation method of the heterojunction battery provided by the embodiment of the present invention is increased to 25.38%; the open circuit voltage is increased to 748mV; the short circuit current density is increased to 39.74mA / cm 2 ; The filling factor increases to 85.4%, which is improved compared with the comparative example of the prior art.

[0109] The present invention is different from the prior art in which at least one side surface of the semiconductor substrate layer is completely velvet. Instead, the first surface and / or the second surface of the semiconductor substrate layer is partially velvet and partially glossy. A photosensitive film layer is formed on the first surface and / or the second surface of the semiconductor substrate layer, and the photosensitive film layer is processed to form a gate line pre-formed layer. The gate line pre-formed layer includes a conductive graphic area and a non-conductive graphic area. The projection of the conductive graphic area on the first surface and / or the second surface of the semiconductor substrate layer corresponds to the glossy surface; the projection of the non-conductive graphic area on the first surface and / or the second surface of the semiconductor substrate layer corresponds to the velvet. Specifically, in the preparation method of the heterojunction battery mentioned in the present invention, the first surface and / or the second surface of the semiconductor substrate layer is partially smooth, and a non-conductive graphic area is formed on the velvet side of the semiconductor substrate layer, so that the conductive graphic area is arranged opposite to the smooth surface, thereby avoiding the existence of a gap between the gate line electrode subsequently formed by electroplating in the corresponding conductive graphic area and the semiconductor substrate layer. On the one hand, the contact resistance between the gate line electrode and the semiconductor substrate layer is reduced, thereby improving the electrical performance of the heterojunction battery; on the other hand, the adhesion between the gate line electrode and the semiconductor substrate layer is improved, thereby improving the yield rate of the heterojunction battery.

[0110] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A method for preparing a heterojunction battery, characterized in that: include: Providing a semiconductor substrate layer, the semiconductor substrate layer comprising a first surface and a second surface opposite to each other; forming a patterned mask on the first surface and / or the second surface of the semiconductor substrate layer; Performing a texturing process on the area of ​​the semiconductor substrate layer not covered by the patterned mask, so that the first surface and / or the second surface of the semiconductor substrate layer is partially textured; The patterned mask is removed, and the first surface and / or the second surface of the semiconductor substrate layer is / area corresponding to the patterned mask as a smooth surface; forming a photosensitive film layer on one side of the first surface and / or the second surface of the semiconductor substrate layer; After forming a photosensitive film layer on the first surface and / or the second surface of the semiconductor substrate layer, the photosensitive film layer is processed to form a gate line pre-formed layer; the gate line pre-formed layer includes a conductive pattern area, and the projection of the conductive pattern area on the first surface and / or the second surface of the semiconductor substrate layer corresponds to the light surface; The gate line electrodes are formed by electroplating in the areas corresponding to the conductive patterns.

2. The method for preparing a heterojunction battery according to claim 1, characterized in that: The patterned mask is an acid-resistant mask; the texturing treatment uses an acidic texturing solution, the acidic texturing solution includes a mixed solution of HF and / or HNO3, the texturing treatment temperature is 25°C-80°C, and the texturing treatment time is 100s-800s; Alternatively, the graphic mask is an alkali-resistant mask; the texturing treatment uses an alkaline texturing solution, the alkaline texturing solution includes a NaOH solution, the mass percentage concentration of the alkaline texturing solution is 1%-10%, the texturing treatment temperature is 25°C-100°C, and the texturing treatment time is 200s-800s.

3. The method for preparing a heterojunction battery according to claim 1, characterized in that: Before forming a patterned mask on the first surface and / or the second surface of the semiconductor substrate layer, polishing the first surface and / or the second surface of the semiconductor substrate layer; The polishing process uses an alkali solution, the alkali solution includes NaOH, the mass percentage concentration of NaOH is 1%-20%, the polishing process temperature is 25°C-80°C, and the polishing process time is 10s-300s; After the polishing process, the surface roughness of the semiconductor substrate layer is less than 0.2 μm.

4. The method for preparing a heterojunction battery according to claim 1, characterized in that: The step of processing the photosensitive film layer to form a gate line pre-formed layer comprises: Provide graphic shading film; Laying a patterned light-shielding film on the surface of the photosensitive film layer; Performing exposure processing on the first surface and / or the second surface of the semiconductor substrate layer; After the exposure process, developing the first surface and / or the second surface of the semiconductor substrate layer; Wherein: the exposure process adopts laser direct imaging exposure; the development process adopts NaCO3 solution, the mass percentage concentration of the NaCO3 solution is 1%-5%, and the temperature is 20℃-40℃; The gate line pre-formed layer further includes a non-conductive pattern area, and the non-conductive pattern area completely corresponds to the suede surface of the first surface and / or the second surface; or, the non-conductive pattern area corresponds to the suede surface of the first surface and / or the second surface, and also corresponds to a part of the smooth surface adjacent to the suede surface; The conductive pattern area includes a main grid pattern area and a secondary grid pattern area. The width of the main grid pattern area is 30 μm-100 μm; the width of the secondary grid pattern area is 5 μm-30 μm.

5. The method for preparing a heterojunction battery according to claim 1, characterized in that: The step of removing the patterned mask includes: performing a first cleaning treatment on the patterned mask using a first film stripping solution; When the patterned mask is an acid-resistant mask, the first stripping solution includes NaOH; the mass percentage concentration of NaOH is 1%-10%, the temperature of the first cleaning treatment is 25° C.-80° C., and the time of the first cleaning treatment is 30s-300s; When the patterned mask is an alkali-resistant mask, the first stripping solution includes HF; the mass percentage concentration of HF is 1%-10%, the temperature of the first cleaning treatment is 25° C.-80° C., and the time of the first cleaning treatment is 60s-300s.

6. The method for preparing a heterojunction battery according to claim 4, characterized in that: After removing the patterned mask, the method further comprises: forming an intrinsic semiconductor layer on the first surface and / or the second surface of the semiconductor substrate layer; After forming the intrinsic semiconductor layer, forming a doped semiconductor layer on a side of the intrinsic semiconductor layer away from the semiconductor substrate layer; After forming a doped semiconductor layer on a side of the intrinsic semiconductor layer away from the semiconductor substrate layer, forming a transparent conductive film on a side of the doped semiconductor layer away from the semiconductor substrate layer; After forming the transparent conductive film on a side of the doped semiconductor layer away from the semiconductor substrate layer, forming a seed layer on a side of the transparent conductive film away from the semiconductor substrate layer; After forming the seed layer on the side of the transparent conductive film away from the semiconductor substrate layer, forming a photosensitive film layer on the side of the seed layer away from the semiconductor substrate layer; The seed layer covers the light surface and the velvet surface; the photosensitive film layer covers the entire light surface and the velvet surface; the material of the seed layer includes copper; and the material of the gate line electrode includes copper.

7. The method for preparing a heterojunction battery according to claim 4, characterized in that: After forming the gate line electrode by electroplating corresponding to the conductive pattern area, the method further comprises: removing the non-conductive pattern area in the gate line pre-formed layer; The step of removing the non-conductive pattern area includes: performing a second cleaning treatment on the non-conductive pattern area using a second film stripping solution; The second film-demolding solution includes NaOH; the mass percentage concentration of NaOH is 1%-10%, the temperature of the second cleaning treatment is 25° C.-50° C., and the time of the second cleaning treatment is 60s-300s.

8. A heterojunction battery, prepared by the method for preparing a heterojunction battery according to any one of claims 1 to 7, characterized in that: include: A semiconductor substrate layer, the semiconductor substrate layer comprising a first surface and a second surface opposite to each other; the first surface and / or the second surface is partially velvety and partially smooth; A gate line electrode, wherein a projection of the gate line electrode on the first surface and / or the second surface of the semiconductor substrate layer corresponds to and only corresponds to the light surface.

9. The heterojunction battery according to claim 8, characterized in that: Also includes: An intrinsic semiconductor layer, located on the first surface and / or the second surface of the semiconductor substrate layer, and located between the semiconductor substrate layer and the gate line electrode; a doped semiconductor layer, located on a side of the intrinsic semiconductor layer away from the semiconductor substrate layer and between the intrinsic semiconductor layer and the gate line electrode; A transparent conductive film, located on a side of the doped semiconductor layer away from the semiconductor substrate layer, and located between the doped semiconductor layer and the gate line electrode; The seed layer is located on a side of the transparent conductive film away from the semiconductor substrate layer; and is located between the transparent conductive film and the gate line electrode.

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