Low-area digital correlated double sampling circuit for multiplexed readout of multiple columns of pixels

Abstract

The present invention discloses a low-area digital correlated double sampling circuit for multiplexed readout of multiple columns of pixels, and belongs to the technical field of CMOS image sensors. The present invention utilizes the selection of controlled switches and control signals to store only exposure quantization data in a correlated double sampling state, thereby reducing the use of reset quantization data storage units, and the correlated double sampling work of multiple columns of pixels can be completed with only one subtractor, thereby reducing the use of subtraction units. The present invention introduces three different data modes, and optionally outputs original exposure quantization data, original reset quantization data, and correlated double sampling quantization data, which helps to process and analyze distorted or smeared images using original exposure quantization data and reset quantization data, and evaluates the dark current and reset noise of pixel devices through original reset quantization data to evaluate the performance of pixel devices.

Description

Technical Field

[0001] The invention relates to a low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout, belonging to the technical field of CMOS image sensors. Background Art

[0002] CMOS image sensors have been widely used in various imaging fields due to their high integration and low power consumption. According to the different architecture levels, the analog digital converter (ADC) in CMOS image sensors can be divided into pixel level, column level and chip level. Among them, the column-level ADC architecture is widely used because it can achieve a good balance between speed, area and power consumption. Therefore, the column-level parallel readout architecture based on column-level ADC is also widely used in CMOS image sensor circuits.

[0003] In the column-level parallel readout architecture, the method of performing ADC operation and reading out a single column of pixels requires equipping each column of pixels with a set of readout circuits, which consumes a large chip area. In addition, as the process node continues to shrink, the size of the pixel unit continues to decrease, and the structure of one column of pixel units corresponding to one column of readout circuits becomes increasingly difficult to implement in physical layout. Therefore, in actual image sensor engineering applications, the method of sharing a set of readout circuits for multiple columns of pixel units has gradually been used due to its advantage in low area cost.

[0004] In CMOS image sensors, there is fixed pattern noise (FPN) between pixels caused by factors such as process and temperature. FPN is one of the main factors causing image quality degradation. Usually, the correlated double sampling (CDS) technology can eliminate FPN. Analog domain CDS operation usually uses a larger capacitor to improve accuracy, but there are problems such as capacitor mismatch and clock feedthrough. Although the digital domain CDS operation is slow, it can not only eliminate FPN in the image sensor, but also has higher quantization accuracy because it makes a difference in the quantization result in the digital domain, which helps to obtain high-quality images. However, although the digital CDS technology can eliminate FPN in the image sensor, it cannot handle image distortion or smear caused by the motion of the photographed object. Usually, such images can be analyzed and processed by using image processing algorithms to process the original exposure data and the original reset data. In addition, there are dark current and reset noise in the pixel device that affect the pixel performance. Usually, the original reset data is analyzed to evaluate the dark current and reset noise, thereby analyzing the performance of the pixel device. Therefore, in the process of correlated double sampling of the image sensor, considering how to output the original exposure quantization data and the reset quantization data has a good guiding significance for the analysis of image quality and the optimization of subsequent pixel devices.

[0005] When performing CDS operation on a CMOS image sensor with multiple columns of pixels read out, there are two readout processes. The first is based on the expansion of the traditional single column readout timing, such as Figure 1 As shown in (a). After a row of pixels is exposed, exposure quantization is first performed on a column of pixels that multiplexes a certain readout circuit, and then a reset operation is performed on the row of pixels. Subsequently, the reset signal quantization is continued for the column of pixels, and the CDS operation of the pixel is completed by subtracting the exposure quantization data and the reset quantization data. On this basis, the same operation is performed on other columns of pixels that multiplex the same readout circuit to achieve CDS operation on each column of pixels. This readout process requires multiple exposure and reset operations, resulting in discontinuous readout, thereby reducing the frame rate of the image. In addition, the practice of exposing during the readout process does not conform to the normal workflow of CMOS image sensors and is therefore not suitable for practical applications. The second readout process is as follows Figure 1As shown in (b), after a row of pixels is exposed, the exposure signal of all columns of pixels that reuse a certain readout circuit is quantized in sequence, and then the row of pixels is reset. Subsequently, the reset signal of all columns of pixels that reuse the same readout circuit is quantized in sequence, and finally the CDS operation of each column of pixels is realized by subtracting the exposure quantization data and the reset quantization data. This readout process only requires one row exposure operation and one row reset operation to complete the quantization and CDS operation of each column of pixels. The timing is relatively simple and can be applied in practice. However, it is not difficult to see that in the second readout process, when the same readout circuit reads out multiple columns of pixels and performs CDS operations, it is necessary to store the first quantized data to prevent data overwriting, which will result in the use of a large number of storage units and subtractors, thereby introducing a larger area for the chip. Therefore, it is necessary to consider how to reduce the use of storage units and subtractors in the CDS process under the above readout timing to reduce area overhead. Summary of the invention

[0006] The purpose of the present invention is to provide a low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout in view of the problems existing when performing CDS operation in the above-mentioned CMOS image sensor with multiple-column pixel unit multiplexing readout. The present invention reduces the use of storage units and subtraction units in the digital domain CDS operation by introducing control signals and controlled switches, thereby reducing area overhead. In addition, the present invention introduces three different data modes to selectively output original exposure quantization data, original reset quantization data and digital correlated double sampling quantization data, which helps to process and analyze distorted or smeared images using original exposure quantization data and reset quantization data, and evaluates the dark current and reset noise of the pixel device through the original reset quantization data to evaluate the performance of the pixel device.

[0007] The first object of the present invention is to provide a low-area digital correlated double sampling circuit for multiple column pixel multiplexing readout, comprising: a control circuit; controlled switches S1-S3; latch groups LAT1-LATN; a multiplexer circuit MUX; and a subtractor circuit.

[0008] The control circuit is used to generate a control signal to control the entire circuit. The input of the control circuit includes a data mode signal DATA_MODE, an exposure quantization completion signal EXPBL1 to EXPBLN of an N-column pixel unit of a multiplexing readout circuit, and a reset quantization completion signal RSTBL1 to RSTBLN of an N-column pixel unit of a multiplexing readout circuit; the exposure quantization completion signal and the reset quantization completion signal are generated by the ADC module, and the data mode selection signal is generated by the control unit of the image sensor chip as a whole; the output of the control circuit includes control signals C1 to C3 connected to the control end of the controlled switches S1 to S3, enable signals EN1 to ENN connected to the enable end of the latch group LAT1 to LATN, and selection signals SEL1 to SELN connected to the selection end of the multiplexer circuit MUX.

[0009] Preferably, the data mode signal DATA_MODE is a 2-bit signal, which controls the exposure state (EXP_STATE), reset state (RST_STATE), and correlated double sampling state (CDS_STATE) respectively. The exposure quantization completion signals EXPBL1 to EXPBLN correspond to the flag signals generated after the N columns of pixels in the multiplexing readout circuit complete the quantization of their exposure signals. The reset quantization completion signals RSTBL1 to RSTBLN correspond to the flag signals generated after the N columns of pixels in the multiplexing readout circuit complete the quantization of their reset signals.

[0010] Specifically, in the EXP_STATE state, the digital correlated double sampling circuit only outputs the exposure quantization data of each column of pixels; in the RST_STATE state, the digital correlated double sampling circuit only outputs the reset quantization data of each column of pixels; in the CDS_STATE state, the digital correlated double sampling circuit only outputs the quantization data of each column of pixels after executing CDS.

[0011] Further, for the control signal C1, it is valid in CDS_STATE and invalid in other states. For the control signal C2, it is invalid in CDS_STATE; in EXP_STATE, the control signal C2 is only related to the exposure quantization completion signal, and when any one of EXPBL1~EXPBLN is valid, C2 is valid; in RST_STATE, the control signal C2 is only related to the reset quantization completion signal, and when any one of RSTBL1~RSTBLN is valid, C2 is valid. For the control signal C3, it is only related to the reset quantization completion signal, and when any one of RSTBL1~RSTBLN is valid, C3 is valid. For the enable signals EN1~ENN, they are only related to the exposure quantization completion signals EXPBL1~EXPBLN and correspond one to one. When EXPBL1~EXPBLN is valid, the corresponding EN1~ENN is valid. The selection signals SEL1-SELN are only related to the reset quantization completion signals RSTBL1-RSTBLN and have a one-to-one correspondence. When RSTBL1-RSTBLN are valid, the corresponding SEL1-SELN are valid.

[0012] The controlled switches S1 to S3 are used to select the quantized data output by the column-level ADC in different data modes. One end of the controlled switch S1 is connected to the quantized output end of the column-level ADC, the other end is connected to the input end of the latch group, and the control signal end is connected to the output end C1 of the control circuit. One end of the controlled switch S2 is connected to the quantized output end of the column-level ADC, the other end is connected to the data output end, and the control signal end is connected to the output end C2 of the control circuit. One end of the controlled switch S3 is connected to the data input end of the latch group, the other end is connected to the subtrahend input end of the subtractor circuit, and the control signal end is connected to the output end C3 of the control circuit.

[0013] Furthermore, for the controlled switch S1, when the data mode is in CDS_STATE, the control signal C1 is valid, the controlled switch S1 is closed, the quantized data output by the column-level ADC is transmitted to the input end of the latch group, and is stored in the latch under the control of the latch enable signal; when the data mode is in other states, the control signal C1 is invalid, and the controlled switch S1 is opened.

[0014] Further, for the controlled switch S2, when the data mode is in EXP_STATE, the exposure quantization completion signals EXPBL1 to EXPBLN are sequentially output through the control signal C2 under the action of the control circuit, and the reset quantization completion signal is not output. When the exposure quantization completion signal is valid, the control signal C2 is valid, the controlled switch S2 is closed, and the exposure quantization data of the corresponding pixel column is sequentially output to the data output terminal through S2, completing the output of the EXP_STATE exposure quantization data. Similarly, when the data mode is in RST_STATE, the reset quantization completion signals RSTBL1 to RSTBLN are sequentially output through the control signal C2 under the action of the control circuit, and the exposure quantization completion signal is not output. When the reset quantization completion signal is valid, the control signal C2 is valid, the controlled switch S2 is closed, and the reset quantization data of the corresponding pixel column is sequentially output to the data output terminal through S2, completing the output of the RST_STATE reset quantization data. When the data mode is in other states, the controlled switch S2 is disconnected.

[0015] Furthermore, for the controlled switch S3, the reset quantization completion signals RSTBL1 to RSTBLN are output in sequence through the control signal C3 under the action of the control circuit. When the reset quantization completion signal is valid, the control signal C3 is valid, the controlled switch S3 is closed, and the reset quantization data of the corresponding pixel column transmitted through the controlled switch S1 is then transmitted to the subtrahend input terminal of the subtractor circuit through the controlled switch S3 in sequence.

[0016] The latch group LAT1~LATN is used to latch the exposure quantization data when the data mode is CDS_STATE. The latch group is composed of N latches equal to the number of pixel columns read out by multiplexing. The N data input terminals of the latch group LAT1~LATN are connected together and connected to the quantization output terminal of the column-level ADC through a controlled switch S1. The N data output terminals of the latch group LAT1~LATN are respectively connected to the N input terminals of the multiplexer. The N enable terminals of the latch group LAT1~LATN are respectively connected to the enable signals EN1~ENN output by the control circuit.

[0017] Preferably, when the enable signals EN1-ENN are valid, the latch group is in a transparent state, and data directly reaches the output end from the input end; when the enable signals EN1-ENN are invalid, the latch is in a latched state, and the input data is latched at the output end.

[0018] Furthermore, for the latch group, the exposure quantization completion signals EXPBL1 to EXPBLN are sequentially output through the enable signals EN1 to ENN under the action of the control circuit, thereby enabling the latch group. When the data mode is in CDS_STATE, when the exposure quantization completion signals EXPBL1 to EXPBLN are sequentially valid, the enable signals EN1 to ENN are sequentially valid, and the exposure quantization data of each column of pixels input through the controlled switch S1 are sequentially input to the output end of each latch; when the exposure quantization completion signals are sequentially invalidated, the enable signals EN1 to ENN are sequentially invalidated, and the exposure quantization data of each column of pixels are latched in the latch group.

[0019] The multiplexer circuit MUX is used to perform a multiple-select operation on the latched N columns of pixel exposure quantization data. The N input terminals of the multiplexer circuit MUX are respectively connected to the N data output terminals of the latch groups LAT1 to LATN; the output terminal of the multiplexer circuit MUX is connected to the minuend input terminal of the subtractor circuit; and the N control selection signal terminals of the multiplexer circuit MUX are respectively connected to the selection signals SEL1 to SELN output by the control circuit.

[0020] Preferably, the multiplexer circuit MUX selects the data outputs corresponding to the latch groups LAT1-LATN respectively through the selection signals SEL1-SELN, and transmits them to the minuend input terminal of the subtractor circuit. Specifically, when SELN is valid, the multiplexer selects the quantized data latched corresponding to LATN and outputs it.

[0021] Furthermore, for the multiplexer circuit MUX, the reset quantization completion signals RSTBL1 to RSTBLN are sequentially output through the selection signals SEL1 to SELN under the action of the control circuit, and then the multiplexer data input is sequentially operated to select one. When the reset quantization of the multiplexed Nth column of pixels is completed, RSTBLN is valid, and then SELN is valid, and the exposure quantization data of the Nth column of pixels stored in the latch LATN is selected and output, and input into the subtractor circuit.

[0022] The subtractor circuit is used to perform a subtraction operation on the input exposure quantization data and reset quantization data in the digital domain, thereby realizing a digital CDS operation. The minuend input terminal of the subtractor circuit is connected to the output terminal of the multiplexer circuit MUX; the subtrahend input terminal of the subtractor circuit is connected to the quantization output terminal of the column-level ADC through the controlled switch S3 and the controlled switch S1. The output terminal of the subtractor circuit is connected to the data output terminal.

[0023] Specifically, when the data mode is CDS_STATE, when the reset quantization of the multiplexed Nth column of pixels is completed, RSTBLN is valid, and then the selection signal SELN of the multiplexer circuit MUX is valid, and the exposure quantization data of the Nth column of pixels stored in the latch LATN is selected and output, and input to the minuend input terminal of the subtractor circuit; at the same time, the controlled switch S3 is closed, and the reset quantization data of the Nth column of pixels is transmitted to the subtrahend input terminal of the subtractor circuit, thereby completing the digital correlated double sampling work in the subtractor circuit and outputting the CDS result.

[0024] A second object of the present invention is to provide an image sensor, comprising the low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout.

[0025] In the existing digital correlated double sampling circuit for multiplexed readout of multiple columns of pixel units, the exposure quantization data and reset quantization data of each column of pixels are usually stored separately, and then a subtractor circuit is used for each column to complete the CDS operation, such as Figure 2 shown.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention is applied to a CMOS image sensor with a multiplexed readout circuit of a multi-column pixel unit. By using a controlled switch and a control signal selection, only the exposure quantization data is stored in a correlated double sampling state (CDS_STATE), thereby reducing the use of a reset quantization data storage unit, and the correlated double sampling of multiple columns of pixels can be completed by only one subtractor circuit, thereby reducing the use of subtraction units. Compared with the prior art, the control circuit and the controlled switch introduced by the present invention are much smaller in area than the reduced storage unit and subtraction unit, which can reduce the area overhead.

[0028] In addition, the present invention introduces three different data modes, which can optionally output original exposure quantization data, original reset quantization data and correlated double sampling quantization data, which helps to process and analyze distorted or smeared images using the original exposure quantization data and reset quantization data, and evaluate the dark current and reset noise of the pixel device through the original reset quantization data to evaluate the performance of the pixel device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1Schematic diagram of the readout process of a CMOS image sensor with multiple columns of pixels readout performing a CDS operation; wherein (a) is to perform exposure quantization and reset quantization on each column of pixels multiplexing a certain readout circuit one by one to complete the readout process of the CDS operation; (b) is to perform exposure quantization and reset quantization on each column of pixels multiplexing a certain readout circuit uniformly to complete the readout process of the CDS operation.

[0031] Figure 2 The present invention is a schematic diagram of a structure for performing CDS operation on a multi-column pixel multiplexing readout CMOS image sensor under the prior art.

[0032] Figure 3 The present invention provides a schematic diagram of the structure of a digital correlated double sampling circuit for a CMOS image sensor with multiple columns of pixels read out.

[0033] Figure 4 It is a schematic diagram of the structure of a digital correlated double sampling circuit for a CMOS image sensor with two columns of pixels multiplexed and readout provided in the second embodiment of the present invention.

[0034] Figure 5 This is a working timing diagram corresponding to the circuit provided in the second embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0036] Embodiment 1:

[0037] This embodiment provides an image sensor digital correlated double sampling circuit for multiple column pixel multiplexing readout, such as Figure 3 As shown, including:

[0038] A control circuit for generating a control signal to control the overall circuit; a controlled switch S1-S3 for selecting the quantized data output by the column-level ADC in different data modes; a latch group LAT1-LATN for latching the exposure quantized data when the data mode is the correlated double sampling state (CDS_STATE); a multiplexer circuit MUX for performing a multiple-select operation on the latched N columns of pixel exposure quantized data; and a subtractor circuit for performing a subtraction operation on the input exposure quantized data and reset quantized data in the digital domain, thereby realizing a digital CDS operation.

[0039] The input of the control circuit includes a data mode signal DATA_MODE, an exposure quantization completion signal EXPBL1~EXPBLN of an N-column pixel unit of a multiplexed readout circuit, and a reset quantization completion signal RSTBL1~RSTBLN of an N-column pixel unit of a multiplexed readout circuit; the output of the control circuit includes control signals C1~C3 connected to the control ends of controlled switches S1~S3, enable signals EN1~ENN connected to the enable ends of latch groups LAT1~LATN, and selection signals SEL1~SELN connected to the selection ends of multiplexer circuits MUX.

[0040] Preferably, the data mode signal DATA_MODE is a 2-bit signal, which controls the exposure state (EXP_STATE), reset state (RST_STATE), and correlated double sampling state (CDS_STATE) respectively. The exposure quantization completion signals EXPBL1 to EXPBLN correspond to the flag signals generated after the N columns of pixels in the multiplexing readout circuit complete the quantization of their exposure signals. The reset quantization completion signals RSTBL1 to RSTBLN correspond to the flag signals generated after the N columns of pixels in the multiplexing readout circuit complete the quantization of their reset signals.

[0041] Specifically, in the EXP_STATE state, the digital correlated double sampling circuit only outputs the exposure quantization data of each column of pixels; in the RST_STATE state, the digital correlated double sampling circuit only outputs the reset quantization data of each column of pixels; in the CDS_STATE state, the digital correlated double sampling circuit only outputs the quantization data of each column of pixels after executing CDS.

[0042] Further, for the control signal C1, it is valid in CDS_STATE and invalid in other states. For the control signal C2, it is invalid in CDS_STATE; in EXP_STATE, the control signal C2 is only related to the exposure quantization completion signal, and when any one of EXPBL1~EXPBLN is valid, C2 is valid; in RST_STATE, the control signal C2 is only related to the reset quantization completion signal, and when any one of RSTBL1~RSTBLN is valid, C2 is valid. For the control signal C3, it is only related to the reset quantization completion signal, and when any one of RSTBL1~RSTBLN is valid, C3 is valid. For the enable signals EN1~ENN, they are only related to the exposure quantization completion signals EXPBL1~EXPBLN and correspond one to one. When EXPBL1~EXPBLN is valid, the corresponding EN1~ENN is valid. The selection signals SEL1-SELN are only related to the reset quantization completion signals RSTBL1-RSTBLN and have a one-to-one correspondence. When RSTBL1-RSTBLN are valid, the corresponding SEL1-SELN are valid.

[0043] The controlled switches S1 to S3 are used to select the quantized data output by the column-level ADC in different data modes. One end of the controlled switch S1 is connected to the quantized output end of the column-level ADC, the other end is connected to the input end of the latch group, and the control signal end is connected to the output end C1 of the control circuit. One end of the controlled switch S2 is connected to the quantized output end of the column-level ADC, the other end is connected to the data output end, and the control signal end is connected to the output end C2 of the control circuit. One end of the controlled switch S3 is connected to the data input end of the latch group, the other end is connected to the subtrahend input end of the subtractor circuit, and the control signal end is connected to the output end C3 of the control circuit.

[0044] Furthermore, for the controlled switch S1, when the data mode is in CDS_STATE, the control signal C1 is valid, the controlled switch S1 is closed, the quantized data output by the column-level ADC is transmitted to the input end of the latch group, and is stored in the latch under the control of the latch enable signal; when the data mode is in other states, the control signal C1 is invalid, and the controlled switch S1 is opened.

[0045] Further, for the controlled switch S2, when the data mode is in EXP_STATE, the exposure quantization completion signals EXPBL1 to EXPBLN are sequentially output through the control signal C2 under the action of the control circuit, and the reset quantization completion signal is not output. When the exposure quantization completion signal is valid, the control signal C2 is valid, the controlled switch S2 is closed, and the exposure quantization data of the corresponding pixel column is sequentially output to the data output terminal through S2, completing the output of the EXP_STATE exposure quantization data. Similarly, when the data mode is in RST_STATE, the reset quantization completion signals RSTBL1 to RSTBLN are sequentially output through the control signal C2 under the action of the control circuit, and the exposure quantization completion signal is not output. When the reset quantization completion signal is valid, the control signal C2 is valid, the controlled switch S2 is closed, and the reset quantization data of the corresponding pixel column is sequentially output to the data output terminal through S2, completing the output of the RST_STATE reset quantization data. When the data mode is in other states, the controlled switch S2 is disconnected.

[0046] Furthermore, for the controlled switch S3, the reset quantization completion signals RSTBL1 to RSTBLN are output in sequence through the control signal C3 under the action of the control circuit. When the reset quantization completion signal is valid, the control signal C3 is valid, the controlled switch S3 is closed, and the reset quantization data of the corresponding pixel column transmitted through the controlled switch S1 is then transmitted to the subtrahend input terminal of the subtractor circuit through the controlled switch S3 in sequence.

[0047] The latch group LAT1~LATN is used to latch the exposure quantization data when the data mode is CDS_STATE. The latch group is composed of N latches equal to the number of pixel columns read out by multiplexing. The N data input terminals of the latch group LAT1~LATN are connected together and connected to the quantization output terminal of the column-level ADC through a controlled switch S1. The N data output terminals of the latch group LAT1~LATN are respectively connected to the N input terminals of the multiplexer. The N enable terminals of the latch group LAT1~LATN are respectively connected to the enable signals EN1~ENN output by the control circuit.

[0048] Preferably, when the enable signals EN1-ENN are valid, the latch group is in a transparent state, and data directly reaches the output end from the input end; when the enable signals EN1-ENN are invalid, the latch is in a latched state, and the input data is latched at the output end.

[0049] Furthermore, for the latch group, the exposure quantization completion signals EXPBL1 to EXPBLN are sequentially output through the enable signals EN1 to ENN under the action of the control circuit, thereby enabling the latch group. When the data mode is in CDS_STATE, when the exposure quantization completion signals EXPBL1 to EXPBLN are sequentially valid, the enable signals EN1 to ENN are sequentially valid, and the exposure quantization data of each column of pixels input through the controlled switch S1 are sequentially input to the output end of each latch; when the exposure quantization completion signals are sequentially invalidated, the enable signals EN1 to ENN are sequentially invalidated, and the exposure quantization data of each column of pixels are latched in the latch group.

[0050] The multiplexer circuit MUX is used to perform a multiple-select operation on the latched N columns of pixel exposure quantization data. The N input terminals of the multiplexer circuit MUX are respectively connected to the N data output terminals of the latch groups LAT1 to LATN; the output terminal of the multiplexer circuit MUX is connected to the minuend input terminal of the subtractor circuit; and the N control selection signal terminals of the multiplexer circuit MUX are respectively connected to the selection signals SEL1 to SELN output by the control circuit.

[0051] Preferably, the multiplexer circuit MUX selects the data outputs corresponding to the latch groups LAT1-LATN respectively through the selection signals SEL1-SELN, and transmits them to the minuend input terminal of the subtractor circuit. Specifically, when SELN is valid, the multiplexer selects the quantized data latched corresponding to LATN and outputs it.

[0052] Furthermore, for the multiplexer circuit MUX, the reset quantization completion signals RSTBL1 to RSTBLN are sequentially output through the selection signals SEL1 to SELN under the action of the control circuit, and then the multiplexer data input is sequentially operated to select one. When the reset quantization of the multiplexed Nth column of pixels is completed, RSTBLN is valid, and then SELN is valid, and the exposure quantization data of the Nth column of pixels stored in the latch LATN is selected and output, and input into the subtractor circuit.

[0053] The subtractor circuit is used to perform a subtraction operation on the input exposure quantization data and reset quantization data in the digital domain, thereby realizing a digital CDS operation. The minuend input terminal of the subtractor circuit is connected to the output terminal of the multiplexer circuit MUX; the subtrahend input terminal of the subtractor circuit is connected to the quantization output terminal of the column-level ADC through the controlled switch S3 and the controlled switch S1. The output terminal of the subtractor circuit is connected to the data output terminal.

[0054] Specifically, when the data mode is CDS_STATE, when the reset quantization of the multiplexed Nth column of pixels is completed, RSTBLN is valid, and then the selection signal SELN of the multiplexer circuit MUX is valid, and the exposure quantization data of the Nth column of pixels stored in the latch LATN is selected and output, and input to the minuend input terminal of the subtractor circuit; at the same time, the controlled switch S3 is closed, and the reset quantization data of the Nth column of pixels is transmitted to the subtrahend input terminal of the subtractor circuit, thereby completing the digital correlated double sampling work in the subtractor circuit and outputting the CDS result.

[0055] Embodiment 2:

[0056] This embodiment provides an image sensor digital correlated double sampling circuit for a two-column pixel unit multiplexing readout circuit applied to a single-slope ADC architecture, such as Figure 4 As shown, including:

[0057] A ramp generator for generating a ramp signal Vramp; a gating circuit for selecting a voltage signal Vpixel generated by two columns of pixel units that multiplex the same readout circuit; a comparator and a counter for performing a single-slope ADC conversion operation; and a digital correlated double sampling circuit for performing a digital correlated double sampling operation.

[0058] In this embodiment, the input end of the selection circuit is connected to the voltage signals Vpixel1~Vpixel2 (including exposure signals Vexp1~Vexp2 and reset signals Vrst1~Vrst2) generated by two columns of pixel units that reuse the same readout circuit, and one of the pixel signals Vpixel is selected for output in turn, and the output end is connected to the positive input end of the comparator.

[0059] In this embodiment, the signal output terminal of the ramp generator is connected to the negative input terminal of the comparator, and a plurality of ramp signals Vramp are sequentially generated to the comparator for comparison with the pixel signals Vpixel sequentially outputted by the gating circuit.

[0060] In this embodiment, the output end of the comparator is connected to the count enable end of the counter. When the Vramp signal is equal to the Vpixel signal, the output signal of the comparator is flipped, controlling the counter to stop counting, thereby completing ADC quantization of the pixel signal.

[0061] In this embodiment, the counting output terminal of the counter is connected to a digital correlated double sampling circuit.

[0062] The digital correlated double sampling circuit includes: a control circuit for generating a control signal to control the overall circuit; a controlled switch S1-S3 for selecting the quantized data output by the counter in different data modes; a latch group LAT1-LAT2 for latching the exposure quantized data when the data mode is CDS_STATE; a multiplexer circuit MUX for performing a two-select operation on the latched exposure quantized data of two columns of pixels; and a subtractor circuit for performing a subtraction operation on the input exposure quantized data and reset quantized data in the digital domain, thereby realizing a digital CDS operation.

[0063] Specifically, the working timing of the circuit of the second embodiment is shown in Figure 5 .

[0064] After the pixel array is exposed, the selection circuit selects the exposure voltage of the two columns of pixel units that reuse the same readout circuit and outputs them to the comparator to compare with the ramp signal generated by the ramp generator. The counter starts counting when the ramp starts to rise. When the ramp voltage is equal to the exposure voltage, the comparator output flips, the counter stops counting, and the quantization of the pixel exposure voltage is completed. The exposure quantization value of the counter is output to the digital correlated double sampling circuit, and the exposure quantization completion signals EXPBL1 and EXPBL2 are output at the same time. After the exposure quantization is completed, the pixel unit is reset, and then the pixel reset voltage is quantized. The reset quantization process is the same as the exposure quantization process, and the reset quantization value of the counter is output to the digital correlated double sampling circuit, and the reset quantization completion signals RSTBL1 and RSTBL2 are output at the same time.

[0065] The data mode signal DATA_MODE is a 2-bit signal, the high bit DATA_MODE <1> , low DATA_MODE <0> When the DATA_MODE signal is 01, the circuit is in the EXP_STATE state; when the DATA_MODE signal is 10, the circuit is in the RST_STATE state; when the DATA_MODE signal is 11, the circuit is in the CDS_STATE state.

[0066] Specifically, when the data mode is in EXP_STATE, DATA_MODE is 01. In this state, C1 outputs a low level, the controlled switch S1 is disconnected, and the quantization value output by the counter can only be transmitted to the data output terminal through the controlled switch S2. When any one of the exposure quantization completion signals EXPBL1 and EXPBL2 of the two columns of pixel units is a high level, C2 outputs a high level, the controlled switch S2 is closed, and the corresponding first column pixel exposure quantization data EXP1 and second column pixel exposure quantization data EXP2 are output in sequence. When any one of the reset quantization completion signals RSTBL1 and RSTBL2 of the two columns of pixel units is a high level, the C2 output remains at a low level, the controlled switch S2 is disconnected, and the reset data is not output. In this way, the output of the exposure quantization data under EXP_STATE is completed.

[0067] Specifically, when the data mode is in RST_STATE, DATA_MODE is 10. In this state, C1 outputs a low level, the controlled switch S1 is disconnected, and the quantization value output by the counter can only be transmitted to the data output terminal through the controlled switch S2. When any one of the reset quantization completion signals RSTBL1 and RSTBL2 of the two columns of pixel units is a high level, C2 outputs a high level, the controlled switch S2 is closed, and the corresponding first column pixel reset quantization data RST1 and second column pixel reset quantization data RST2 are output in turn. When any one of the exposure quantization completion signals EXPBL1 and EXPBL2 of the two columns of pixel units is a high level, the C2 output remains at a low level, the controlled switch S2 is disconnected, and the exposure data is not output. In this way, the output of the reset quantization data under RST_STATE is completed.

[0068] Specifically, when the data mode is in CDS_STATE, DATA_MODE is 11. In this state, C1 outputs a high level, and the controlled switch S1 is closed; C2 outputs a low level, and the controlled switch S2 is open. The quantization value output by the counter is transmitted to the data input end of the latch group LAT1 and LAT2 through the controlled switch S1. When the exposure quantization completion signals EXPBL1 and EXPBL2 are high levels in turn, EN1 and EN2 are high levels in turn, and the latches LAT1 and LAT2 are in a transparent state in turn, and the quantization data is transmitted from the input end to the output end. When EXPBL1 and EXPBL2 are turned to low levels in turn, EN1 and EN2 are turned to low levels in turn, and the latches LAT1 and LAT2 store the first column pixel exposure quantization data EXP1 and the second column pixel exposure quantization data EXP2 in turn.

[0069] Further, when the reset quantization completion signal RSTBL1 of the first column of pixels is at a high level, C3 outputs a high level, and the controlled switch S3 is closed; at the same time, SEL1 outputs a high level, and the controlled switch S5 in the multiplexer circuit MUX is closed, and the reset quantization data RST1 of the first column of pixels is transmitted to the subtrahend input terminal of the subtractor circuit through the controlled switch S1 and the controlled switch S3; at the same time, the exposure quantization data EXP1 of the first column of pixels stored in the latch LAT1 is transmitted to the minuend input terminal of the subtractor circuit through the controlled switch S5, and the subtractor circuit performs a subtraction operation and outputs the correlated double sampling quantization data CDS1 of the first column of pixels. The digital correlated double sampling operation of the first column of pixels is completed.

[0070] Further, when the reset quantization completion signal RSTBL2 of the second column of pixels is at a high level, C3 outputs a high level, and the controlled switch S3 is closed; at the same time, SEL2 outputs a high level, and the controlled switch S4 in the multiplexer circuit MUX is closed, and the reset quantization data RST2 of the second column of pixels is transmitted to the subtrahend input terminal of the subtractor circuit through the controlled switch S1 and the controlled switch S3; at the same time, the exposure quantization data EXP2 of the second column of pixels stored in the latch LAT2 is transmitted to the minuend input terminal of the subtractor circuit through the controlled switch S4, and the subtractor circuit performs a subtraction operation and outputs the correlated double sampling quantization data CDS2 of the second column of pixels. The digital correlated double sampling operation of the second column of pixels is completed.

[0071] Through the above analysis, it can be seen that the present invention utilizes the selection of controlled switches and control signals to store only the exposure quantization data in the correlated double sampling state (CDS_STATE), thereby reducing the use of reset quantization data storage units, and only using one subtractor circuit to complete the CDS operation of multiplexing each column of pixels, thereby reducing the use of storage units and subtraction units, and reducing area overhead. Based on the CMOS 55nm process and the single slope ADC quantization accuracy of 10bit, the present invention is applied. When two columns of pixel units reuse the readout circuit, the circuit area of ​​the introduced part in the digital correlated double sampling circuit accounts for about 13.2% of the circuit area of ​​the reduced part, which is 13.2% of the circuit area of ​​the reduced part. Figure 2 Compared with the structure shown in FIG. 1 , the area overhead of the present invention is reduced by about 43.4%.

[0072] In addition, the present invention introduces three different data modes, which can optionally output original exposure quantization data, original reset quantization data and correlated double sampling quantization data, which helps to process and analyze distorted or smeared images using the original exposure quantization data and reset quantization data, and evaluate the dark current and reset noise of the pixel device through the original reset quantization data to evaluate the performance of the pixel device.

[0073] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout, characterized in that: The circuit comprises: a control circuit; controlled switches S1-S3; latch groups LAT1-LATN; a multiplexer circuit MUX; a subtractor circuit; The control circuit is connected to the controlled switches S1-S3, the latch groups LAT1-LATN, and the multiplexer circuit MUX, the controlled switches S1-S3 are also connected to the latch groups LAT1-LATN and the subtractor circuit, the latch groups LAT1-LATN are also connected to the multiplexer circuit MUX, and the multiplexer circuit MUX is also connected to the subtractor circuit; The control circuit is used to generate a control signal to control the overall circuit; the input of the control circuit includes a data mode signal DATA_MODE, an exposure quantization completion signal EXPBL1 to EXPBLN of an N-column pixel unit of a multiplexing readout circuit, and a reset quantization completion signal RSTBL1 to RSTBLN of an N-column pixel unit of a multiplexing readout circuit; the output of the control circuit includes control signals C1 to C3 connected to control ends of controlled switches S1 to S3, enable signals EN1 to ENN connected to enable ends of latch groups LAT1 to LATN, and selection signals SEL1 to SELN connected to selection ends of multiplexer circuits MUX; The controlled switches S1~S3 are used to select the quantized data output by the column-level ADC in different data modes; the latch group LAT1~LATN is used to latch the exposure quantized data; the multiplexer circuit MUX is used to perform a multiple-select operation on the latched N columns of pixel exposure quantized data; the subtractor circuit is used to perform a subtraction operation on the input exposure quantized data and reset quantized data in the digital domain, thereby realizing a digital CDS operation.

2. A low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout according to claim 1, characterized in that: The data modes in the controlled switches S1-S3 include an exposure state EXP_STATE, a reset state RST_STATE and a correlated double sampling state CDS_STATE.

3. A low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout according to claim 2, characterized in that: When the data mode is in the exposure state EXP_STATE and the reset state RST_STATE, respectively, the digital correlated double sampling circuit directly outputs the corresponding exposure quantization data and reset quantization data to the data output terminal respectively; when the data mode is in the correlated double sampling state CDS_STATE, under the action of the controlled switches S1~S3 and the control signals C1~C3, the digital correlated double sampling circuit first stores the exposure quantization data in the latch group, and when the reset quantization data is input to the subtrahend input terminal of the subtractor circuit, the corresponding exposure quantization data is input to the minuend input terminal of the subtractor circuit through the multiplexer circuit MUX to perform the subtraction operation, complete the digital correlated double sampling, and output the result to the data output terminal.

4. A low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout according to claim 1, characterized in that: One end of the controlled switch S1 is connected to the quantization output end of the column-level ADC, the other end is connected to the input end of the latch group, and the control signal end is connected to the output end of the control signal C1 of the control circuit; One end of the controlled switch S2 is connected to the quantization output end of the column-level ADC, the other end is connected to the data output end, and the control signal end is connected to the output end of the control signal C2 of the control circuit; one end of the controlled switch S3 is connected to the data input end of the latch group, the other end is connected to the subtrahend input end of the subtractor circuit, and the control signal end is connected to the output end of the control signal C3 of the control circuit.

5. The low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout according to claim 1, characterized in that: The latch group is composed of N latches equal to the number of pixel columns read out by multiplexing; the N data input terminals of the latch group LAT1~LATN are connected together and connected to the quantization output terminal of the column-level ADC through a controlled switch S1; the N data output terminals of the latch group LAT1~LATN are respectively connected to the N input terminals of the multiplexer; the N enable terminals of the latch group LAT1~LATN are respectively connected to the enable signals EN1~ENN output by the control circuit.

6. A low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout according to claim 5, characterized in that: When the enable signals EN1 to ENN are valid, the latch group is in a transparent state, and the data goes directly from the input end to the output end; when the enable signals EN1 to ENN are invalid, the latch is in a latched state, and the input data is latched at the output end; for the latch group, the exposure quantization completion signals EXPBL1 to EXPBLN are sequentially output through the enable signals EN1 to ENN under the action of the control circuit, thereby enabling the latch group; when the data mode is in CDS_STATE, when the exposure quantization completion signals EXPBL1 to EXPBLN are sequentially valid, the enable signals EN1 to ENN are sequentially valid, and the exposure quantization data of each column of pixels input through the controlled switch S1 are sequentially input to the output end of each latch; when the exposure quantization completion signals are sequentially invalid, the enable signals EN1 to ENN are sequentially invalid, and the exposure quantization data of each column of pixels are latched in the latch group.

7. The low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout according to claim 1, characterized in that: The N input terminals of the multiplexer circuit MUX are respectively connected to the N data output terminals of the latch groups LAT1~LATN; the output terminal of the multiplexer circuit MUX is connected to the minuend input terminal of the subtractor circuit; and the N control selection signal terminals of the multiplexer circuit MUX are respectively connected to the selection signals SEL1~SELN output by the control circuit.

8. The low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout according to claim 7, characterized in that: The multiplexer circuit MUX respectively selects the data output corresponding to the latch groups LAT1-LATN through the selection signals SEL1-SELN, and transmits them to the minuend input terminal of the subtractor circuit; when SELN is valid, the multiplexer selects the quantized data latched corresponding to LATN and outputs it.

9. The low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout according to claim 1, characterized in that: The minuend input terminal of the subtractor circuit is connected to the output terminal of the multiplexer circuit MUX; the subtrahend input terminal of the subtractor circuit is connected to the quantization output terminal of the column-level ADC through the controlled switch S3 and the controlled switch S1; the output terminal of the subtractor circuit is connected to the data output terminal.

10. An image sensor, characterized in that: The image sensor comprises the low-area digital correlated double sampling circuit for multiple-column pixel multiplexing readout according to any one of claims 1 to 9.

Images