Array substrate, display panel

Abstract

The application provides an array substrate and a display panel. The array substrate comprises a gate electrode of a thin film transistor extending along a first direction; a first electrode of the thin film transistor comprising a first body and a first end portion connected to each other; and a second electrode of the thin film transistor comprising a second body and a second end portion connected to each other. The orthographic projections of the first body and the second body on a substrate of the array substrate are located within the orthographic projection of the gate electrode on the substrate, and the orthographic projections of at least partial areas of the first end portion and the second end portion on the substrate do not overlap with the orthographic projection of the gate electrode on the substrate, and the orthographic projections of the first end portion and the second end portion on the substrate are located on the same side of the orthographic projection of the gate electrode on the substrate. In the first direction, the average distance between the first end portion and the second end portion is greater than the average distance between the first body and the second body.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] With the rapid development of display technology, the industry has increasingly higher requirements for the performance and quality of array substrates in display products. However, in related technologies, when the manufacturing process is unstable or the manufacturing precision is limited, parasitic capacitance with different capacitance values ​​or other defects are easily generated between film layers, resulting in a reduction in the manufacturing yield and quality of the array substrate. Summary of the Invention

[0003] The embodiments of this application adopt the following technical solutions:

[0004] In a first aspect, embodiments of this application provide an array substrate, comprising:

[0005] The gate of the thin-film transistor extends along a first direction;

[0006] The first electrode of the thin-film transistor includes a first body and a first end connected together;

[0007] The second electrode of the thin-film transistor includes a connected second body and a second end;

[0008] The orthographic projections of the first body and the second body on the substrate of the array substrate are respectively located within the orthographic projection of the gate on the substrate. The orthographic projections of at least a portion of the first end and at least a portion of the second end on the substrate do not overlap with the orthographic projection of the gate on the substrate. The orthographic projections of the first end and the second end on the substrate are both located on the same side of the orthographic projection of the gate on the substrate.

[0009] In the first direction, the average distance between the first end and the second end is greater than the average distance between the first body and the second body.

[0010] In some embodiments of this application, the first pole further includes a third end, and the first body connects the first end and the third end; the second pole further includes a fourth end, and the second body connects the second end and the fourth end;

[0011] The orthographic projections of at least a portion of the third end and at least a portion of the fourth end onto the substrate do not overlap with the orthographic projection of the gate onto the substrate.

[0012] In the first direction, the average distance between the third end and the fourth end is greater than the average distance between the first body and the second body.

[0013] In some embodiments of this application, the array substrate further includes gate lines, data lines, pixel electrodes, a first trace and a second trace, wherein the data lines and the gate lines intersect and are insulated from each other, the gate electrode and the gate lines are electrically connected, the pixel electrode is located at a position defined by two adjacent data lines and two adjacent gate lines, the third end of the first electrode is electrically connected to the data lines through the first trace, and the second end of the second electrode is electrically connected to the pixel electrode through the second trace;

[0014] In the direction from the portion of the third end connected to the first body to the portion of the third end connected to the first trace, the minimum distance between the third end and the data line gradually decreases.

[0015] Along the direction from the portion where the second end connects to the second body to the portion where the second end connects to the second trace, the minimum distance between the second end and the data line gradually increases.

[0016] In some embodiments of this application, along the direction from the portion of the first end connected to the first body to the portion of the first end away from the first body, the minimum distance between the first end and the second end gradually increases, and the minimum distance between the first end and the data line gradually decreases.

[0017] Along the direction from the portion of the fourth end connected to the second body to the portion of the fourth end away from the second body, the minimum distance between the fourth end and the third end gradually increases, and the minimum distance between the fourth end and the data line gradually increases.

[0018] In some embodiments of this application, the orthogonal projections of the first end, the second end, the third end, and the fourth end onto the substrate do not overlap with the orthogonal projection of the gate onto the substrate.

[0019] In some embodiments of this application, the orthogonal projections of the first end, the second end, the third end, and the fourth end onto the substrate overlap with the orthogonal projection portion of the gate onto the substrate.

[0020] In some embodiments of this application, the first end portion includes a first adjustment sub-part and a first protection sub-part, wherein the first adjustment sub-part is located between the first body and the first protection sub-part;

[0021] Along the direction from the first body to the first end, the minimum distance between the first adjustment sub-part and the data line gradually decreases, while the minimum distance between the first protection sub-part and the data line remains unchanged.

[0022] In some embodiments of this application, the fourth end portion includes a fourth adjustment sub-part and a second protection sub-part, wherein the fourth adjustment sub-part is located between the second body and the second protection sub-part;

[0023] Along the direction from the second body to the fourth end, the minimum distance between the fourth adjustment sub-part and the data line gradually increases, while the minimum distance between the second protection sub-part and the data line remains unchanged.

[0024] In some embodiments of this application, the first end portion includes a first adjustment sub-part and a first protection sub-part, the first adjustment sub-part being located between the first body and the first protection sub-part; the second end portion includes a second adjustment sub-part; the third end portion includes a third adjustment sub-part; and the fourth end portion includes a fourth adjustment sub-part and a second protection sub-part, the fourth adjustment sub-part being located between the second body and the second protection sub-part.

[0025] The orthographic projections of the geometric centers of the first adjustment sub-section, the second adjustment sub-section, the third adjustment sub-section, and the fourth adjustment sub-section onto the substrate respectively fall on the outline of the orthographic projection of the gate onto the substrate.

[0026] In some embodiments of this application, the minimum distance between the orthographic projection of the first protective sub-part on the substrate and the orthographic projection of the gate on the substrate, the minimum distance between the orthographic projection of the second protective sub-part on the substrate and the orthographic projection of the gate on the substrate, the minimum distance between the orthographic projection of the first trace on the substrate and the orthographic projection of the gate on the substrate, and the minimum distance between the orthographic projection of the second trace on the substrate and the orthographic projection of the gate on the substrate are all greater than or equal to 2 μm.

[0027] In some embodiments of this application, the orthographic projections of the first end, the second end, the third end, and the fourth end onto the substrate include at least one of an arc shape, a polygon shape, and a combination of an arc shape and a polygon shape.

[0028] In some embodiments of this application, the orthographic projection shapes of the first adjustment sub-part, the second adjustment sub-part, the third adjustment sub-part, and the fourth adjustment sub-part on the substrate are all parallelograms, and the orthographic projection shapes of the first protection sub-part and the second protection sub-part on the substrate are both rectangles.

[0029] In some embodiments of this application, the size of the orthographic projection of the first adjustment sub-part on the substrate along the first direction is equal to the size of the orthographic projection of the first protection sub-part on the substrate along the first direction, and the size of the orthographic projection of the fourth adjustment sub-part on the substrate along the first direction is equal to the size of the orthographic projection of the second protection sub-part on the substrate along the first direction.

[0030] In some embodiments of this application, the gate line includes a first segment and a second segment, the first segment intersecting with and being insulated from the data line, and a portion of the second segment serving as the gate.

[0031] Wherein, the dimension of the orthographic projection of the second line segment on the substrate along the direction perpendicular to the first direction is greater than the dimension of the orthographic projection of the first line segment on the substrate along the direction perpendicular to the first direction.

[0032] In some embodiments of this application, the gate line includes a first segment, a second segment, and a third segment. The first segment intersects with and is insulated from the data line, the second segment serves as the gate, and the third segment is located at the end of the second segment away from the first segment.

[0033] Wherein, the orthographic projection of the second line segment on the substrate along the direction perpendicular to the first direction is greater than the orthographic projection of the third line segment on the substrate along the direction perpendicular to the first direction, and the orthographic projection of the third line segment on the substrate along the direction perpendicular to the first direction is greater than the orthographic projection of the first line segment on the substrate along the direction perpendicular to the first direction.

[0034] In some embodiments of this application, the array substrate further includes an active layer, the active layer being located on the side of the gate away from the substrate, the outer contour of the orthogonal projection of the active layer on the substrate being located within the outer contour of the orthogonal projection of the gate on the substrate, and a portion of the first electrode and a portion of the second electrode being in direct contact with the active layer, respectively.

[0035] Wherein, the size of the orthographic projection of the active layer on the substrate along the direction perpendicular to the first direction is smaller than the size of the orthographic projection of the first body on the substrate along the direction perpendicular to the first direction, and the size of the orthographic projection of the active layer on the substrate along the direction perpendicular to the first direction is smaller than the size of the orthographic projection of the second body on the substrate along the direction perpendicular to the first direction.

[0036] In some embodiments of this application, the array substrate includes a first storage capacitor line, a second storage capacitor line, a third storage capacitor line, and a fourth storage capacitor line disposed on the same layer as the gate.

[0037] The first storage capacitor line, the second storage capacitor line, and the third storage capacitor line are all located between two adjacent data lines, and all have the same extension direction as the data lines.

[0038] The fourth storage capacitor line intersects and connects with the first storage capacitor line, the second storage capacitor line, and the third storage capacitor line, respectively, and the orthographic projections of the first storage capacitor line, the second storage capacitor line, the third storage capacitor line, and the fourth storage capacitor line on the substrate overlap with the orthographic projections of the pixel electrode on the substrate.

[0039] In some embodiments of this application, the second storage capacitor line is located between the first storage capacitor line and the third storage capacitor line. The array substrate further includes a conductive island disposed on the same layer as the data line. The orthographic projection of the intersection of the second storage capacitor line and the fourth storage capacitor line on the substrate overlaps with the orthographic projection of the conductive island on the substrate, and the conductive island is electrically connected to the pixel electrode.

[0040] Secondly, embodiments of this application provide a display panel including the array substrate as described above.

[0041] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 and Figure 2 The diagram shows the structure of the array substrate in two related technologies provided in the embodiments of this application.

[0044] Figures 3-13 These are schematic diagrams of the structures of eleven array substrates provided in the embodiments of this application;

[0045] Figure 14 for Figure 13 Cross-sectional view along the B1B1 direction;

[0046] Figure 15 for Figure 13 Cross-sectional view along the C1C2 direction. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] For clarity, the thickness of regions and layers may be exaggerated in the figures. The same reference numerals in the figures denote the same or similar structures, and therefore their detailed descriptions are omitted. Furthermore, the figures are merely illustrative of this application and are not necessarily drawn to scale.

[0049] In the embodiments of this application, unless otherwise stated, "a plurality of" means two or more; the orientation or positional relationship indicated by the term "above" is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing this application and simplifying the description, and is not intended to indicate or imply that the structure or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0050] In the embodiments of this application, since the source and drain of the transistor are symmetrical, their source and drain can be interchanged. In the embodiments of this application, one of the source and drain of the transistor is called the first terminal, and the other of the source and drain is called the second terminal.

[0051] In embodiments of the present invention, the term "electrical connection" may refer to a direct electrical connection between two components, or to an electrical connection between two components via one or more other components.

[0052] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0053] In the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0054] Embodiments of this application provide an array substrate, with reference to... Figures 3-8 As shown, it includes:

[0055] The gate of the thin-film transistor extends along the first direction OA;

[0056] The first electrode 4 of the thin-film transistor includes a first body 41 and a first end 42 connected together;

[0057] The second electrode 5 of the thin-film transistor includes a connected second body 51 and a second end 52;

[0058] The orthographic projections of the first body 41 and the second body 51 on the substrate of the array substrate are respectively located within the orthographic projection of the gate on the substrate. The orthographic projections of at least a portion of the first end 42 and at least a portion of the second end 52 on the substrate do not overlap with the orthographic projection of the gate on the substrate. Furthermore, the orthographic projections of the first end 42 and the second end 52 on the substrate are both located on the same side of the orthographic projection of the gate on the substrate.

[0059] In the first direction OA, the average distance between the first end 42 and the second end 52 is greater than the average distance between the first body 41 and the second body 51.

[0060] In an exemplary embodiment, the average distance between the first end 42 and the second end 52 refers to the average of the maximum distance between the first end 42 and the second end 52 and the minimum distance between the first end 42 and the second end 52 in the first direction OA.

[0061] In an exemplary embodiment, the average distance between the first body 41 and the second body 51 refers to the average of the maximum distance between the first body 41 and the minimum distance between the second body 51. Exemplarily, the maximum distance, minimum distance, and average distance between the first body 41 and the second body 51 are all equal to d1.

[0062] For example, refer to Figure 3As shown, in the first direction OA, the minimum distance between the first end 42 and the second end 52 is equal to the average distance d1 between the first body 41 and the second body 51. In the first direction OA, the distance between the region where the first end 42 does not overlap with the gate and the region where the second end 43 does not overlap with the gate is greater than the average distance d1 between the first body 41 and the second body 51.

[0063] Except for the minimum distance between the first end 42 and the second end 52, the distance between the first end 42 and the second end 52 in the first direction OA is denoted by d2, where d2 > d1.

[0064] The type of thin-film transistor described above is not limited here. For example, the thin-film transistor can be an N-type transistor, or it can be a P-type transistor.

[0065] In an exemplary embodiment, reference is made to Figure 3 As shown, a portion of the gate line 2 in the array substrate can serve as the gate of a thin-film transistor; alternatively, the gate line and the gate of the thin-film transistor can be independently configured and connected together. In the accompanying drawings provided in the embodiments of this application, a portion of the gate line 2 is used as an example of the gate of a thin-film transistor.

[0066] For example, the gate line and the gate of the thin-film transistor are made of the same material, such as any one of copper, aluminum, nickel, molybdenum and titanium or a combination of at least two metals stacked together.

[0067] For example, in Figure 3 In this context, the first direction OA is the horizontal direction. In fact, the first direction OA can also be other directions, which can be determined according to the design of the array substrate. In the embodiments of this application, the first direction OA is the horizontal direction as an example for illustration.

[0068] In an exemplary embodiment, the first electrode 4 of the thin-film transistor can be the source, and the second electrode 5 of the thin-film transistor can be the drain; or, the first electrode 4 of the thin-film transistor can be the drain, and the second electrode 5 of the thin-film transistor can be the source. In the embodiments of this application, the example of the first electrode 4 of the thin-film transistor being the source and the second electrode 5 of the thin-film transistor being the drain will be used for illustration.

[0069] In an exemplary embodiment, the first electrode 4 and the second electrode 5 of the thin-film transistor are both located in the same conductive layer, such as the source / drain metal layer SD. Exemplarily, the material of the source / drain metal layer may include any one of copper, aluminum, nickel, molybdenum, and titanium, or a combination of at least two metals stacked together.

[0070] Wherein, the orthogonal projections of the first body 41 and the second body 51 onto the substrate of the array substrate are respectively located within the orthogonal projection of the gate onto the substrate, including the following cases:

[0071] The first type, reference Figure 3 , Figure 4 or Figure 5 As shown, the outer contour of the orthographic projection of the first body 41 on the substrate of the array substrate and the outer contour of the orthographic projection of the second body 51 on the substrate of the array substrate respectively overlap with the outer contour of the orthographic projection of the gate on the substrate.

[0072] The second option is to refer to... Figure 6 As shown, the outer contour of the orthographic projection of the first body 41 on the substrate of the array substrate and the outer contour of the orthographic projection of the second body 51 on the substrate of the array substrate are respectively located within the outer contour of the orthographic projection of the gate on the substrate.

[0073] Wherein, the orthographic projections of at least a portion of the first end 42 and at least a portion of the second end 52 onto the substrate do not overlap with the orthographic projection of the gate onto the substrate, including the following cases:

[0074] The first type, reference Figure 6 As shown, the orthographic projection of a portion of the first end 42 onto the substrate and the orthographic projection of a portion of the second end 52 onto the substrate do not overlap with the orthographic projection of the gate onto the substrate.

[0075] The second option is to refer to... Figure 3 , Figure 4 or Figure 5 As shown, the orthographic projection of the first end 42 on the substrate and the orthographic projection of the second end 52 on the substrate do not overlap with the orthographic projection of the gate on the substrate.

[0076] The shape of the orthographic projection of the first end 42 onto the substrate and the shape of the orthographic projection of the second end 52 onto the substrate are not limited here, and can be determined according to the actual design.

[0077] In addition, the shape of the orthographic projection of the first end 42 on the substrate and the shape of the orthographic projection of the second end 52 on the substrate can be the same, or the shape of the orthographic projection of the first end 42 on the substrate and the shape of the orthographic projection of the second end 52 on the substrate can be different.

[0078] For example, refer to Figure 3 As shown, the orthographic projection of the first end 42 onto the substrate is a rectangle, and the orthographic projection of the second end 52 onto the substrate is a parallelogram.

[0079] For example, refer to Figure 4As shown, the orthographic projection of the first end 42 onto the substrate is a shape composed of a rectangle and a parallelogram, and the orthographic projection of the second end 52 onto the substrate is a rectangle.

[0080] In related technologies, during the fabrication of the array substrate, under conditions of process fluctuations or limited alignment accuracy, the overlapping region between the first and second electrodes of the thin-film transistors in the source / drain metal layers and the gate in the gate layer may shift or its area may change. This causes a change in the capacitance value of the parasitic capacitance generated in the two conductive layers, resulting in different parasitic capacitance values ​​in different sub-pixels of the array substrate. Consequently, the influence of different parasitic capacitances on the charging rate of each sub-pixel is inconsistent, leading to different charging rates among different sub-pixels. To improve this problem, reference... Figure 1 As shown, in related technologies, the lengths of the first electrode 4 and the second electrode 5 of the thin-film transistor along the direction parallel to the data line 6 are greater than the width of the gate along the direction parallel to the data line 6. This is so that even with variations in the fabrication process, the overlapping area between the first electrode 4 and the second electrode 5 of the thin-film transistor and the gate located in the gate layer tends to be consistent in different sub-pixels. However, due to the influence of the thickness of the gate located in the bottom layer, some areas of the first electrode 4 and the second electrode 5 are in a state of... Figure 2 At the ramp position indicated by the dashed coil, conductive material residue (such as metal residue) is easily generated during the array substrate fabrication process, leading to... Figure 1 The location of the dotted coil shown is prone to short circuits between the first pole 4 and the second pole 5, causing abnormal use of the array substrate.

[0081] In the embodiments of this application, the first electrode 4 includes a first body 41 and a first end 42, and the second electrode 5 includes a second body 51 and a second end 52. The first end 42 and the second end 52 are located on the same side of the gate, and the projections of the first end 42 and the second end 52 do not overlap with the projection of the gate. By setting them on the first direction OA, the average distance between the first end 42 and the second end 52 is greater than the average distance between the first body 41 and the second body 51. In this way, without changing the spacing between the first body 41 and the second body 51, and ensuring that the aspect ratio of the thin film transistor remains unchanged, the average distance between the first end 42 and the second end 52 can be increased as much as possible. This greatly reduces the probability of short circuits occurring between the first electrode 4 and the second electrode 5 at the ramp position, and improves the fabrication yield and quality of the array substrate.

[0082] In some embodiments of this application, reference is made to Figures 3-8As shown, the first pole 4 also includes a third end 43, and the first body 41 connects the first end 42 and the third end 43; the second pole 5 also includes a fourth end 53, and the second body 51 connects the second end 52 and the fourth end 53.

[0083] The orthographic projections of at least a portion of the third end 43 and at least a portion of the fourth end 53 onto the substrate do not overlap with the orthographic projection of the gate onto the substrate.

[0084] In the first direction OA, the average distance between the third end 43 and the fourth end 53 is greater than the average distance between the first body 41 and the second body 51.

[0085] In an exemplary embodiment, the average distance between the third end 43 and the fourth end 53 refers to the average of the maximum distance between the third end 43 and the fourth end 53 and the minimum distance between the third end 43 and the fourth end 53 in the first direction OA.

[0086] In an exemplary embodiment, the average distance between the first body 41 and the second body 51 refers to the average of the maximum distance between the first body 41 and the minimum distance between the second body 51. Exemplarily, the maximum distance, minimum distance, and average distance between the first body 41 and the second body 51 are all equal to d1.

[0087] For example, refer to Figure 3 As shown, in the first direction OA, the minimum distance between the third end 43 and the fourth end 53 is equal to the average distance d1 between the first body 41 and the second body 51. In the first direction OA, the distance between the region where the third end 43 does not overlap with the gate and the region where the fourth end 53 does not overlap with the gate is greater than the average distance d1 between the first body 41 and the second body 51.

[0088] Except for the minimum distance between the third end 43 and the fourth end 53, the distance between the third end 43 and the fourth end 53 in the first direction OA is denoted by d3, where d3 > d1.

[0089] The relationship between the average distance between the third end 43 and the fourth end 53 and the average distance between the first end 42 and the second end 52 is not limited here; it can be determined based on the design of the actual product.

[0090] The shape of the orthographic projection of the third end 43 onto the substrate and the shape of the orthographic projection of the fourth end 53 onto the substrate are not limited here, and can be determined according to the actual design.

[0091] In addition, the shape of the orthographic projection of the third end 43 on the substrate and the shape of the orthographic projection of the fourth end 53 on the substrate can be the same, or the shape of the orthographic projection of the third end 43 on the substrate and the shape of the orthographic projection of the fourth end 53 on the substrate can be different.

[0092] Wherein, the orthographic projections of at least a portion of the third end 43 and at least a portion of the fourth end 53 onto the substrate do not overlap with the orthographic projection of the gate onto the substrate, including the following cases:

[0093] The first type, reference Figure 6 As shown, the orthographic projections of a portion of the third end 43 and a portion of the fourth end 53 onto the substrate do not overlap with the orthographic projections of the gate onto the substrate.

[0094] The second option is to refer to... Figures 3-5 As shown, the orthographic projections of the third end 43 and the fourth end 53 on the substrate do not overlap with the orthographic projections of the gate on the substrate.

[0095] In the embodiments of this application, a third end 43 is further included, and the first body 41 is connected to the first end 42 and the third end 43; the second electrode 5 also includes a fourth end 53, and the second body 51 is connected to the second end 52 and the fourth end 53; the orthogonal projections of at least a portion of the third end 43 and at least a portion of the fourth end 53 on the substrate do not overlap with the orthogonal projections of the gate on the substrate; in the first direction OA, the average distance between the third end 43 and the fourth end 53 is greater than the average distance between the first body 41 and the second body 51. In this way, without changing the spacing between the first body 41 and the second body 51, the average distance between the third end 43 and the fourth end 53 can be increased as much as possible, further reducing the probability of short circuit between the first electrode 4 and the second electrode 5 at the ramp position, and improving the fabrication yield and quality of the array substrate.

[0096] In some embodiments of this application, combined with Figure 3 and Figure 13 As shown, the array substrate also includes gate line 2, data line 6, pixel electrode 15, first trace 9 and second trace 10. Data line 6 and gate line 2 intersect and are insulated from each other. Gate and gate line 2 are electrically connected. Pixel electrode 15 is located at the position defined by two adjacent data lines 6 and two adjacent gate lines 2. The third end 43 of the first electrode 4 is electrically connected to the data line 6 through the first trace 9. The second end 52 of the second electrode 5 is electrically connected to the pixel electrode 15 through the second trace 10. The second trace 10 is electrically connected to the pixel electrode 15 through via VIA1.

[0097] Among them, Figure 3In the direction from the part where the third end 43 is connected to the first body 41 to the part where the third end 43 is connected to the first trace 9, the minimum distance between the third end 43 and the data line 6 gradually decreases.

[0098] Along the direction from the portion where the second end 52 is connected to the second body 51 to the portion where the second end 52 is connected to the second trace 10, the minimum distance between the second end 52 and the data line 6 gradually increases.

[0099] In the embodiments of this application, reference is made to Figure 3 As shown, the third end 43 of the first electrode 4 can be tilted away from the fourth end 53 of the second electrode 5, and the second end 52 of the second electrode 5 can be tilted away from the first end 42 of the first electrode 4. The third end 43 is electrically connected to the data line through the first trace 9, and the second end 52 is electrically connected to the second trace 10. In this way, in the first direction OA, the average distance between the third end 43 and the fourth end 53 is greater than the average distance between the first body 41 and the second body 51, and the average distance between the first end 42 and the second end 52 is greater than the average distance between the first body 41 and the second body 51. Thus, without changing the spacing between the first body 41 and the second body 51, the average distance between the first end 42 and the second end 52 and the average distance between the third end 43 and the fourth end 53 can be increased as much as possible. This greatly reduces the probability of short circuits occurring between the first electrode 4 and the second electrode 5 at the ramp position, and improves the fabrication yield and quality of the array substrate.

[0100] In some embodiments of this application, reference is made to Figure 5 As shown, along the direction from the portion of the first end 42 connected to the first body 41 to the portion of the first end 42 away from the first body 41, the minimum distance between the first end 42 and the second end 52 gradually increases, and the minimum distance between the first end 42 and the data line 6 gradually decreases.

[0101] Along the portion of the fourth end 53 connected to the second body 51, pointing towards the portion of the fourth end 53 away from the second body 51, the minimum distance between the fourth end 53 and the third end 43 gradually increases, and the minimum distance between the fourth end 43 and the data line 6 gradually increases.

[0102] In the embodiments of this application, the first end 42 of the first electrode 4 can be tilted away from the second end 52 of the second electrode 5, and the fourth end 53 of the second electrode 5 can be tilted away from the third end 43 of the first electrode 4, thereby increasing the average distance between the third end 43 and the fourth end 53 and the average distance between the first end 42 and the second end 52, thereby further reducing the probability of short circuit between the first electrode 4 and the second electrode 5 at the ramp position and improving the fabrication yield and quality of the array substrate.

[0103] In some embodiments of this application, reference is made to Figure 5 As shown, the orthogonal projections of the first end 42, the second end 52, the third end 43 and the fourth end 53 on the substrate do not overlap with the orthogonal projection of the gate on the substrate.

[0104] In some embodiments of this application, reference is made to Figure 6 As shown, the orthogonal projections of the first end, the second end, the third end, and the fourth end onto the substrate overlap with the orthogonal projection of the gate onto the substrate.

[0105] In some embodiments of this application, reference is made to Figures 5-8 As shown, the first end portion 42 includes a first adjustment sub-part 421 and a first protection sub-part 422. The first adjustment sub-part 421 is located between the first body 41 and the first protection sub-part 422. Along the direction from the first body 41 to the first end portion 42, the minimum distance between the first adjustment sub-part 421 and the data line 6 gradually decreases, while the minimum distance between the first protection sub-part 422 and the data line 6 remains unchanged.

[0106] In the embodiments of this application, the first adjustment sub-part 421 can adjust the distance between the first end 42 of the first electrode 4 and the second end 52 of the second electrode 5, thereby reducing the probability of a short circuit between the first electrode 4 and the second electrode 5 and improving the fabrication yield of the array substrate. Furthermore, by providing the first protection sub-part 422, on the one hand, it is possible to avoid phenomena such as... Figure 5 The sharp conductive pattern of the first adjustment sub-section 421, which is a parallelogram-shaped projection, increases the distance between the tip of the first end 42 and the gate, preventing electrostatic breakdown between the first end 42 and the gate, thereby further improving the fabrication yield and quality of the array substrate. Furthermore, by gradually decreasing the minimum distance between the first adjustment sub-section 421 and the data line 6, while keeping the minimum distance between the first protection sub-section 422 and the data line 6 constant, the probability of a short circuit between the first electrode 4 and the second electrode 5 is reduced, while preventing other abnormal problems caused by an excessively small distance between the first end 42 of the first electrode and the data line 6, and design space is also saved.

[0107] In some embodiments of this application, reference is made to Figures 5-8 As shown, the fourth end 53 includes a fourth adjustment sub-part 531 and a second protection sub-part 532. The fourth adjustment sub-part 531 is located between the second body 51 and the second protection sub-part 532. Along the direction from the second body 51 to the fourth end 53, the minimum distance between the fourth adjustment sub-part 531 and the data line 6 gradually increases, while the minimum distance between the second protection sub-part 532 and the data line 6 remains unchanged.

[0108] In the embodiments of this application, the fourth adjustment sub-section 531 can adjust the distance between the fourth end 53 and the third end 43, reducing the probability of a short circuit between them. After the second protection sub-section 532 is connected to the fourth adjustment sub-section 531, sharp conductive patterns can be avoided in the array substrate, thereby reducing the probability of electrostatic breakdown between the fourth end 53 and the gate. In addition, the minimum distance between the fourth adjustment sub-section 531 and the data line 6 is gradually increased, while the minimum distance between the second protection sub-section 532 and the data line 6 remains unchanged, reducing the probability of a short circuit between the first electrode 4 and the second electrode 5 while saving design space.

[0109] In an exemplary embodiment, as in Figure 5 In the structure shown, the dimensions of the first adjustment sub-section, the second adjustment sub-section, the third adjustment sub-section, and the fourth adjustment sub-section along the direction parallel to the data line 6 can all be greater than or equal to 2μm.

[0110] In some embodiments of this application, reference is made to Figure 6 As shown, the first end portion 42 includes a first adjustment sub-part 421 and a first protection sub-part 422, with the first adjustment sub-part 421 located between the first body 41 and the first protection sub-part 422; the second end portion 52 includes a second adjustment sub-part; the third end portion 43 includes a third adjustment sub-part; and the fourth end portion 53 includes a fourth adjustment sub-part 531 and a second protection sub-part 532, with the fourth adjustment sub-part 531 located between the second body 51 and the second protection sub-part 532.

[0111] The orthographic projections of the geometric center of the first adjustment sub-section 421, the geometric center of the second adjustment sub-section of the second end 52, the geometric center of the third adjustment sub-section of the third end 43, and the geometric center of the fourth adjustment sub-section 531 onto the substrate respectively fall on the outline of the orthographic projection of the gate onto the substrate.

[0112] In practical applications, since the gate has a certain thickness, the first, second, third, and fourth adjustment sub-parts are all located at the ramp position on the side of the gate. The conductive pattern at the ramp position is prone to cracking due to local stress concentration. In the embodiments of this application, by setting the orthogonal projections of the geometric center of the first adjustment sub-part 421, the geometric center of the second adjustment sub-part at the second end 52, the geometric center of the third adjustment sub-part at the third end 43, and the geometric center of the fourth adjustment sub-part 531 on the substrate to fall on the outline of the orthogonal projection of the gate on the substrate, the stress is more evenly distributed on the first, second, third, and fourth adjustment sub-parts, thereby reducing the probability of cracking or breaking and improving the fabrication yield and quality of the array substrate.

[0113] In addition, Figure 6 In the case of fluctuations in the fabrication process, when the position between the first electrode (second electrode) and the gate is offset, the first adjustment sub-section of the first electrode (fourth adjustment sub-section of the second electrode) can still be located at the ramp position of the gate. This results in a larger distance between the first end and the second end at the ramp position, and a larger distance between the third end and the fourth end, thus avoiding short circuits between the first electrode and the second electrode and reducing the difficulty of the fabrication process.

[0114] In an exemplary embodiment, in Figure 6 In order to distribute the stress more evenly on the first adjustment sub-section, the second adjustment sub-section, the third adjustment sub-section and the fourth adjustment sub-section, the dimensions of the first adjustment sub-section, the second adjustment sub-section, the third adjustment sub-section and the fourth adjustment sub-section along the direction OB parallel to the data line 6 are all greater than or equal to 4μm.

[0115] In an exemplary embodiment, the dimensions of the first protection sub-part 422 and the second protection sub-part 532 along the direction OB parallel to the data line 6 are both greater than or equal to 2 μm.

[0116] In some embodiments of this application, reference is made to Figure 9 or Figure 10 As shown, the minimum distance h1 between the orthographic projection of the first protection sub-part 422 on the substrate and the orthographic projection of the gate (e.g., a portion of the gate line 2) on the substrate, the minimum distance h4 between the orthographic projection of the second protection sub-part 532 on the substrate and the orthographic projection of the gate on the substrate, the minimum distance h3 between the orthographic projection of the first trace 9 on the substrate and the orthographic projection of the gate on the substrate, and the minimum distance h2 between the orthographic projection of the second trace 10 on the substrate and the orthographic projection of the gate on the substrate are all greater than or equal to 2 μm.

[0117] At this time, the dimensions of the portions of the first, second, third, and fourth adjustment sub-sections that do not overlap with the gate along the direction OB parallel to the data line 6 are all greater than or equal to 2 μm.

[0118] In some embodiments of this application, the orthographic projections of the first end 42, the second end 52, the third end 43, and the fourth end 53 onto the substrate include at least one of an arc shape, a polygon shape, and a shape formed by a combination of an arc shape and a polygon shape.

[0119] For example, refer to Figure 3 As shown, the orthographic projection shape of the first end 42 on the substrate and the orthographic projection shape of the fourth end 53 on the substrate are both rectangles, while the orthographic projection shape of the second end 52 on the substrate and the orthographic projection shape of the third end 43 on the substrate are both parallelograms.

[0120] For example, refer to Figure 4 As shown, the orthographic projection shape of the second end 52 on the substrate and the orthographic projection shape of the third end 43 on the substrate are both rectangles, and the orthographic projection shape of the first end 42 on the substrate and the orthographic projection shape of the fourth end 53 on the substrate are both shapes formed by a combination of rectangles and parallelograms.

[0121] For example, refer to Figure 5 and Figure 6 As shown, the orthographic projection shape of the second end 52 on the substrate and the orthographic projection shape of the third end 43 on the substrate are both parallelograms, while the orthographic projection shape of the first end 42 on the substrate and the orthographic projection shape of the fourth end 53 on the substrate are both shapes formed by a combination of rectangles and parallelograms.

[0122] For example, refer to Figure 7 and Figure 8 As shown, the orthographic projection shape of the second end 52 on the substrate and the orthographic projection shape of the third end 43 on the substrate are both arc-shaped, while the orthographic projection shape of the first end 42 on the substrate and the orthographic projection shape of the fourth end 53 on the substrate are both shapes formed by a combination of rectangles and arcs.

[0123] In some embodiments of this application, reference is made to Figure 9 and Figure 10 As shown, the orthographic projection shapes of the first adjustment sub-part 421, the second adjustment sub-part, the third adjustment sub-part, and the fourth adjustment sub-part 531 on the substrate are all parallelograms, and the orthographic projection shapes of the first protection sub-part 422 and the second protection sub-part 532 on the substrate are both rectangles.

[0124] In some embodiments of this application, the size of the first adjustment sub-part 421 projected onto the substrate along the first direction OA is equal to the size of the first protection sub-part 422 projected onto the substrate along the first direction OA, and the size of the fourth adjustment sub-part 531 projected onto the substrate along the first direction OA is equal to the size of the second protection sub-part 532 projected onto the substrate along the first direction OA.

[0125] In the embodiments of this application, by setting the width of the first adjustment sub-part 421 to be equal to the width of the first protection sub-part 422, and the width of the fourth adjustment sub-part 531 to be equal to the width of the second protection sub-part 532, sharp conductive patterns are avoided from being exposed in the first adjustment sub-part 421 and the fourth adjustment sub-part 531, thereby further reducing the probability of electrostatic discharge (ESD) between the first end 42 and the gate, and between the fourth end 53 and the gate, and further improving the fabrication yield and quality of the array substrate.

[0126] In some embodiments of this application, reference is made to Figure 11 As shown, the gate line 2 includes a first segment 21 and a second segment 22. The first segment 21 intersects with and is insulated from the data line 6, and a portion of the second segment 22 serves as the gate. A gate insulating layer is provided between the gate line 2 and the data line 6.

[0127] The size of the orthographic projection of the second line segment 22 onto the substrate along the first direction OA is greater than the size of the orthographic projection of the first line segment 21 onto the substrate along the first direction OA.

[0128] In the embodiments of this application, on the one hand, by reducing the width of the first line segment 21 intersecting with the data line 6, the size of the parasitic capacitance generated between the data line 6 and the first line segment 21 can be reduced, thereby minimizing the negative impact of the parasitic capacitance on the electrical signals in the array substrate. On the other hand, by widening the width of the second line segment 22, even if process fluctuations or misalignment occur during the fabrication of the first electrode 4 and the second electrode 5 of the thin-film transistor, it can be ensured that the area of ​​the region where the gate overlaps with the first electrode 4 and the area of ​​the region where the gate overlaps with the second electrode 5 are consistent in different transistors, thereby reducing the performance differences between thin-film transistors fabricated under process fluctuations or misalignment and improving the quality of the array substrate.

[0129] In some embodiments of this application, reference is made to Figure 2 As shown, the gate line 2 includes a first segment 21, a second segment 22 and a third segment 23. The first segment 21 intersects with and is insulated from the data line 6. The second segment 22 serves as the gate, and the third segment 23 is located at the end of the second segment 22 away from the first segment 21.

[0130] Wherein, the size of the orthographic projection of the second line segment 22 on the substrate along the first direction OA is greater than the size of the orthographic projection of the third line segment 23 on the substrate along the first direction OA, and the size of the orthographic projection of the third line segment 23 on the substrate along the first direction OA is greater than the size of the orthographic projection of the first line segment 21 on the substrate along the first direction OA.

[0131] In the embodiments of this application, by setting the gate line to include three segments with different widths, on the one hand, the size of the parasitic capacitance generated at the intersection of the data line 6 and the gate line 2 can be reduced, avoiding the negative impact of parasitic capacitance on the charging rate of the array substrate; on the other hand, setting the width of the second segment 22, which serves as the gate, to be the largest allows the area of ​​the overlapping region between the first electrode (second electrode) and the gate to remain stable when the positions of the first electrode (second electrode) and the gate shift due to fluctuations in the fabrication process, thereby ensuring that the electrical properties of the thin-film transistor remain stable; furthermore, setting the width of the third segment to be smaller than the width of the second segment but larger than the width of the first segment saves design space and increases the aperture ratio of the array substrate while ensuring stable transmission of electrical signals, thereby improving the light transmittance of the display panel fabricated from the array substrate.

[0132] In some embodiments of this application, combined with Figure 12 and Figure 14 As shown, the array substrate also includes an active layer 7, which is located on the side of the gate away from the substrate 1. The outer contour of the orthogonal projection of the active layer 7 on the substrate 1 is located within the outer contour of the orthogonal projection of the gate on the substrate 1. Parts of the first electrode 4 and the second electrode 5 are in direct contact with the active layer 7.

[0133] The size of the active layer 7 projected onto the substrate 1 along the first direction OA is smaller than the size of the first body 41 projected onto the substrate 1 along the first direction OA, and the size of the active layer 7 projected onto the substrate 1 along the first direction OA is smaller than the size of the second body 51 projected onto the substrate 1 along the first direction OA.

[0134] In an exemplary embodiment, the material of the active layer 7 may include crystalline silicon or a metal oxide. For example, crystalline silicon may include monocrystalline silicon, polycrystalline silicon, and amorphous silicon, and the metal oxide may include indium gallium zinc oxide (IGZO).

[0135] in, Figure 14 yes Figure 13 A cross-sectional view of the thin-film transistor T along the B1B2 direction.

[0136] In the embodiments of this application, by setting the width of the active layer 7 to be less than the length of the first body 41 and less than the length of the second body 51, since the spacing between the first body 41 and the second body 51 is fixed, the influence of process fluctuations on the width-to-length ratio of the thin-film transistor channel can be avoided as much as possible in the event of fluctuations in the fabrication process, and the negative impact of the width-to-length ratio change on the electrical properties of the thin-film transistor can be avoided, thereby avoiding the inconsistency of the electrical properties of the thin-film transistors in different sub-pixels.

[0137] Among them, with Figure 6 For example, the dimension of the active layer 7 projected onto the substrate 1 along the direction OA perpendicular to the first direction is the channel width of the thin film transistor, and the dimension of the first body 41 along the first direction OA to the second body 51 is the channel width of the thin film transistor.

[0138] It should be noted that, in the embodiments of this application, the minimum distance between the first body 41 and the second body 51 in the first direction OA is equal to the maximum distance between the first body 41 and the second body 51.

[0139] In an exemplary embodiment, the size of the active layer 7 projected onto the substrate 1 along the first direction OA is greater than or equal to 5 μm.

[0140] In an exemplary embodiment, the size of the orthographic projection of the first body 41 onto the substrate 1 along the first direction OA is equal to the size of the orthographic projection of the second body 51 onto the substrate 1 along the first direction OA.

[0141] For example, the orthographic projection of the first body 41 onto the substrate 1 along the first direction OA has a size greater than or equal to 8 μm.

[0142] In some embodiments, the size of the gate's orthogonal projection on the substrate 1 along the first direction OA is equal to the size of the first body 41's orthogonal projection on the substrate 1 along the first direction OA.

[0143] In some embodiments, the size of the gate's orthogonal projection on the substrate 1 along the first direction OA is greater than the size of the first body 41's orthogonal projection on the substrate 1 along the first direction OA.

[0144] For example, the difference between the size of the gate on the substrate 1 along the first direction OA and the size of the first body 41 on the substrate 1 along the first direction OA is greater than or equal to 4 μm.

[0145] For example, the difference between the size of the gate on the substrate 1 projected along the first direction OA and the size of the active layer 7 on the substrate 1 projected along the first direction OA is greater than or equal to 5 μm.

[0146] In some embodiments of this application, reference is made to Figure 13 As shown, the array substrate includes a first storage capacitor line 11, a second storage capacitor line 12, a third storage capacitor line 13 and a fourth storage capacitor line 14 disposed on the same layer as the gate.

[0147] The first storage capacitor line 11, the second storage capacitor line 12, and the third storage capacitor line 13 are all located between two adjacent data lines 6, and all have the same extension direction as the data lines 6.

[0148] The fourth storage capacitor line 14 intersects and connects with the first storage capacitor line 11, the second storage capacitor line 12 and the third storage capacitor line 13 respectively, and the orthogonal projections of the first storage capacitor line 11, the second storage capacitor line 12, the third storage capacitor line 13 and the fourth storage capacitor line 14 on the substrate overlap with the orthogonal projections of the pixel electrode 15 on the substrate respectively.

[0149] In the embodiments of this application, a storage capacitor is formed between each storage capacitor line and the pixel electrode to store the amount of electricity acquired by the sub-pixel during the charging process.

[0150] In some embodiments of this application, combined with Figure 13 and Figure 15 As shown, the second storage capacitor line 12 is located between the first storage capacitor line 11 and the third storage capacitor line 13. The array substrate also includes a conductive island 17 disposed on the same layer as the data line 6. The orthographic projection of the intersection of the second storage capacitor line 12 and the fourth storage capacitor line 14 on the substrate 1 overlaps with the orthographic projection of the conductive island 17 on the substrate 1. The conductive island 17 is electrically connected to the pixel electrode 15 through a via VIA2. Figure 15 yes Figure 13 Cross-sectional view along the C1C2 direction.

[0151] It should be noted that the gate and gate line are located in the same conductive layer, such as in the gate layer; the first electrode of the thin-film transistor, the second electrode of the thin-film transistor, the data line, and the conductive island are located in the same conductive layer, such as in the source / drain metal layer (SD). Additionally, in... Figure 13 In the diagram, the film labeled Active represents the active layer, and the film labeled PixelITO represents the pixel electrode.

[0152] A gate insulating layer 3 is disposed between the gate layer and the source / drain metal layer SD, and an interlayer dielectric layer 16 is disposed between the source / drain metal layer SD and the pixel electrode PixelITO.

[0153] In the embodiments of this application, by setting conductive islands 17, when a certain sub-pixel in the array substrate displays abnormally, such as flickering, the location of the conductive island 17 can be broken down by laser lithography, so that the pixel electrode 15 and the storage electrode line 12 / 14 are connected, thereby short-circuiting the circuit in the sub-pixel with abnormal display, so that it does not display, thereby avoiding the negative impact of the abnormal sub-pixel on the overall display effect of the display panel prepared by the array substrate and improving the display effect.

[0154] Embodiments of this application provide a display panel including an array substrate as described above.

[0155] The specific structure of the array substrate included in the embodiment of this application can be referred to the above description, and will not be described again here.

[0156] In an exemplary embodiment, the display panel may further include a color filter substrate, which is disposed opposite to the array substrate.

[0157] The display panel provided in the embodiments of this application is a liquid crystal display (LCD). Alternatively, the display panel can be an LCD monitor or other display device, as well as any product or component with display function, such as a television, digital camera, mobile phone, or tablet computer that includes such display devices.

[0158] For example, the above-mentioned display panel is a liquid crystal display panel with ADS (Advanced Super Dimension Switch) display mode, where ADS is a general term for core technologies represented by wide viewing angle technology.

[0159] In the display panel provided in the embodiments of this application, the first electrode 4 includes a first body 41 and a first end 42, and the second electrode 5 includes a second body 51 and a second end 52. The first end 42 and the second end 52 are located on the same side of the gate, and the projections of the first end 42 and the second end 52 do not overlap with the projection of the gate. By setting them on the first direction OA, the average distance between the first end 42 and the second end 52 is greater than the average distance between the first body 41 and the second body 51. In this way, without changing the spacing between the first body 41 and the second body 51, and ensuring that the aspect ratio of the thin film transistor remains unchanged, the distance between the first end 42 and the second end 52 can be increased as much as possible. This greatly reduces the probability of short circuit between the first electrode 4 and the second electrode 5 at the ramp position, improves the manufacturing yield and quality of the display panel, and improves the display effect of the display panel.

[0160] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An array substrate, wherein, include: The gate of the thin-film transistor extends along a first direction; The first electrode of the thin-film transistor includes a first body and a first end connected together; The second electrode of the thin-film transistor includes a connected second body and a second end; The orthographic projections of the first body and the second body on the substrate of the array substrate are respectively located within the orthographic projection of the gate on the substrate. The orthographic projections of at least a portion of the first end and at least a portion of the second end on the substrate do not overlap with the orthographic projection of the gate on the substrate. The orthographic projections of the first end and the second end on the substrate are both located on the same side of the orthographic projection of the gate on the substrate. In the first direction, the average distance between the first end and the second end is greater than the average distance between the first body and the second body; The first electrode further includes a third end, and the first body connects the first end and the third end; the second electrode further includes a fourth end, and the second body connects the second end and the fourth end; The orthographic projections of at least a portion of the third end and at least a portion of the fourth end onto the substrate do not overlap with the orthographic projection of the gate onto the substrate. In the first direction, the average distance between the third end and the fourth end is greater than the average distance between the first body and the second body; The array substrate further includes gate lines, data lines, pixel electrodes, a first trace and a second trace. The data lines and the gate lines intersect and are insulated from each other. The gate electrode and the gate line are electrically connected. The pixel electrode is located at a position defined by two adjacent data lines and two adjacent gate lines. The third end of the first electrode is electrically connected to the data line through the first trace. The second end of the second electrode is electrically connected to the pixel electrode through the second trace. In the direction from the portion of the third end connected to the first body to the portion of the third end connected to the first trace, the minimum distance between the third end and the data line gradually decreases. Along the direction from the portion where the second end connects to the second body to the portion where the second end connects to the second trace, the minimum distance between the second end and the data line gradually increases.

2. The array substrate according to claim 1, wherein, Along the direction from the portion where the first end connects to the first body to the portion of the first end away from the first body, the minimum distance between the first end and the second end gradually increases, and the minimum distance between the first end and the data line gradually decreases. Along the direction from the portion of the fourth end connected to the second body to the portion of the fourth end away from the second body, the minimum distance between the fourth end and the third end gradually increases, and the minimum distance between the fourth end and the data line gradually increases.

3. The array substrate according to claim 2, wherein, The orthographic projections of the first end, the second end, the third end, and the fourth end onto the substrate do not overlap with the orthographic projection of the gate onto the substrate.

4. The array substrate according to claim 2, wherein, The orthographic projections of the first end, the second end, the third end, and the fourth end onto the substrate overlap with the orthographic projection portion of the gate onto the substrate.

5. The array substrate according to claim 3 or 4, wherein, The first end portion includes a first adjustment sub-part and a first protection sub-part, wherein the first adjustment sub-part is located between the first body and the first protection sub-part; Along the direction from the first body to the first end, the minimum distance between the first adjustment sub-part and the data line gradually decreases, while the minimum distance between the first protection sub-part and the data line remains unchanged.

6. The array substrate according to claim 3 or 4, wherein, The fourth end portion includes a fourth adjustment sub-part and a second protection sub-part, wherein the fourth adjustment sub-part is located between the second body and the second protection sub-part; Along the direction from the second body to the fourth end, the minimum distance between the fourth adjustment sub-part and the data line gradually increases, while the minimum distance between the second protection sub-part and the data line remains unchanged.

7. The array substrate according to claim 4, wherein, The first end portion includes a first adjustment sub-part and a first protection sub-part, the first adjustment sub-part being located between the first body and the first protection sub-part; the second end portion includes a second adjustment sub-part; the third end portion includes a third adjustment sub-part; the fourth end portion includes a fourth adjustment sub-part and a second protection sub-part, the fourth adjustment sub-part being located between the second body and the second protection sub-part. The orthographic projections of the geometric centers of the first adjustment sub-section, the second adjustment sub-section, the third adjustment sub-section, and the fourth adjustment sub-section onto the substrate respectively fall on the outline of the orthographic projection of the gate onto the substrate.

8. The array substrate according to claim 7, wherein, The minimum distance between the orthographic projection of the first protective sub-part on the substrate and the orthographic projection of the gate on the substrate, the minimum distance between the orthographic projection of the second protective sub-part on the substrate and the orthographic projection of the gate on the substrate, the minimum distance between the orthographic projection of the first trace on the substrate and the orthographic projection of the gate on the substrate, and the minimum distance between the orthographic projection of the second trace on the substrate and the orthographic projection of the gate on the substrate are all greater than or equal to 2 μm.

9. The array substrate according to claim 7, wherein, The shapes of the orthographic projections of the first end, the second end, the third end, and the fourth end onto the substrate all include at least one of the following: arc shape, polygon shape, and a combination of arc shape and polygon shape.

10. The array substrate according to claim 9, wherein, The first adjustment sub-part, the second adjustment sub-part, the third adjustment sub-part, and the fourth adjustment sub-part all have parallelogram shapes when projected onto the substrate, and the first protection sub-part and the second protection sub-part both have rectangular shapes when projected onto the substrate.

11. The array substrate according to claim 9, wherein, The size of the orthographic projection of the first adjustment sub-part onto the substrate along the first direction is equal to the size of the orthographic projection of the first protection sub-part onto the substrate along the first direction, and the size of the orthographic projection of the fourth adjustment sub-part onto the substrate along the first direction is equal to the size of the orthographic projection of the second protection sub-part onto the substrate along the first direction.

12. The array substrate according to claim 1, wherein, The gate line includes a first segment and a second segment. The first segment intersects with and is insulated from the data line, and a portion of the second segment serves as the gate. Wherein, the dimension of the orthographic projection of the second line segment on the substrate along the direction perpendicular to the first direction is greater than the dimension of the orthographic projection of the first line segment on the substrate along the direction perpendicular to the first direction.

13. The array substrate according to claim 1, wherein, The gate line includes a first segment, a second segment, and a third segment. The first segment intersects with and is insulated from the data line. The second segment serves as the gate. The third segment is located at the end of the second segment away from the first segment. Wherein, the orthographic projection of the second line segment on the substrate along the direction perpendicular to the first direction is greater than the orthographic projection of the third line segment on the substrate along the direction perpendicular to the first direction, and the orthographic projection of the third line segment on the substrate along the direction perpendicular to the first direction is greater than the orthographic projection of the first line segment on the substrate along the direction perpendicular to the first direction.

14. The array substrate according to claim 1, wherein, The array substrate further includes an active layer, which is located on the side of the gate away from the substrate. The outer contour of the orthographic projection of the active layer on the substrate is located within the outer contour of the orthographic projection of the gate on the substrate. A portion of the first electrode and a portion of the second electrode are in direct contact with the active layer. Wherein, the size of the orthographic projection of the active layer on the substrate along the direction perpendicular to the first direction is smaller than the size of the orthographic projection of the first body on the substrate along the direction perpendicular to the first direction, and the size of the orthographic projection of the active layer on the substrate along the direction perpendicular to the first direction is smaller than the size of the orthographic projection of the second body on the substrate along the direction perpendicular to the first direction.

15. The array substrate according to claim 1, wherein, The array substrate includes a first storage capacitor line, a second storage capacitor line, a third storage capacitor line, and a fourth storage capacitor line disposed on the same layer as the gate. The first storage capacitor line, the second storage capacitor line, and the third storage capacitor line are all located between two adjacent data lines, and all have the same extension direction as the data lines. The fourth storage capacitor line intersects and connects with the first storage capacitor line, the second storage capacitor line, and the third storage capacitor line, respectively, and the orthographic projections of the first storage capacitor line, the second storage capacitor line, the third storage capacitor line, and the fourth storage capacitor line on the substrate overlap with the orthographic projections of the pixel electrode on the substrate.

16. The array substrate according to claim 15, wherein, The second storage capacitor line is located between the first storage capacitor line and the third storage capacitor line. The array substrate also includes a conductive island disposed on the same layer as the data line. The orthographic projection of the intersection of the second storage capacitor line and the fourth storage capacitor line on the substrate overlaps with the orthographic projection of the conductive island on the substrate, and the conductive island is electrically connected to the pixel electrode.

17. A display panel, wherein, Includes the array substrate as described in any one of claims 1-16.

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