Back contact battery and manufacturing method thereof, photovoltaic module

Abstract

The present invention discloses a back contact cell and a manufacturing method thereof, and a photovoltaic module, which relate to the field of photovoltaic technology and are used to make the N-type doped polysilicon layer containing phosphorus as the doping element in the tunneling passivation back contact solar cell have a good morphology and a formation range that meets the target requirements, which is beneficial to improving the photoelectric conversion efficiency of the tunneling passivation back contact solar cell. The back contact cell includes: a semiconductor substrate, and a tunneling passivation layer and an N-type doped polysilicon layer, which are sequentially stacked on a local area of ​​the backlight surface of the semiconductor substrate along the thickness direction of the semiconductor substrate. The light-facing surface of the semiconductor substrate is a velvet surface. The doping element in the N-type doped polysilicon layer includes phosphorus, and the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge area of ​​the backlight surface to the portion of the N-type doped polysilicon layer located on the central area of ​​the backlight surface is greater than or equal to 1 and less than or equal to 1.2.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a back contact cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] Tunneling passivated back contact solar cells refer to solar cells with positive and negative electrodes on the back of the cell, no metal electrode blocking the front, and with tunneling passivated contact structures. Passivated back contact solar cells have advantages such as large light absorption area and low carrier back recombination rate, which have attracted extensive attention from the photovoltaic academic and industrial circles and become a hot development direction of high-efficiency solar cell technology.

[0003] However, in the tunneling passivated back-contact solar cell formed by the existing manufacturing method, the morphology of the N-type doped polysilicon layer containing phosphorus as the doping element is poor, resulting in poor working performance of the tunneling passivated back-contact solar cell. Summary of the invention

[0004] The object of the present invention is to provide a back contact cell and a method for manufacturing the same, as well as a photovoltaic module, which are used to make the N-type doped polysilicon layer containing phosphorus as the doping element in the tunneling passivated back contact solar cell have a good morphology and a formation range that meets the target requirements, thereby helping to improve the photoelectric conversion efficiency of the tunneling passivated back contact solar cell.

[0005] In order to achieve the above-mentioned objectives, in a first aspect, the present invention provides a back-contact battery, which includes: a semiconductor substrate, and a tunneling passivation layer and an N-type doped polysilicon layer sequentially stacked on a local area of ​​the backlight surface of the semiconductor substrate along the thickness direction of the semiconductor substrate.

[0006] The light-facing surface of the semiconductor substrate is a velvet surface. The doping elements in the N-type doped polysilicon layer include phosphorus, and the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge area of ​​the backlight surface to the portion of the N-type doped polysilicon layer located on the central area of ​​the backlight surface is greater than or equal to 1 and less than or equal to 1.2.

[0007] In the case of adopting the above technical solution, the tunneling passivation contact structure formed by the above tunneling passivation layer and the N-type doped polysilicon layer can achieve excellent interface passivation and carrier selective collection, which is beneficial to improve the photoelectric conversion efficiency of the back contact battery. In addition, compared with the existing N-type doped polysilicon layer, the thickness ratio of the edge portion to the middle portion is greater than 1.3, the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge area of ​​the backlight surface to the portion of the N-type doped polysilicon layer located on the central area of ​​the backlight surface in the present invention is greater than or equal to 1 and less than or equal to 1.2, and at this time, the difference between the thickness of the edge portion and the thickness of the central portion of the N-type doped polysilicon layer is small. In this case, in the actual manufacturing process, chemical vapor deposition and other processes are usually used to form the tunneling passivation material layer and the intrinsic amorphous silicon material layer used to manufacture the tunneling passivation layer and the N-type doped polysilicon layer. Based on this, when the difference between the thickness of the edge portion and the thickness of the center portion of the N-type doped polysilicon layer is small, the difference between the thickness of the edge portion and the thickness of the center portion of the intrinsic amorphous silicon material layer forming the N-type doped polysilicon layer is also small. Because the intrinsic amorphous silicon material layer is formed simultaneously along the portions parallel to the backlight surface, the chemical dosage ratio of the intrinsic amorphous silicon material located on the edge region of the backlight surface and the intrinsic amorphous silicon material located on the center region of the backlight surface is roughly the same, so when the difference between the thickness of the edge portion and the center portion of the intrinsic amorphous silicon material layer is small, the structural density of the edge portion and the center portion of the intrinsic amorphous silicon material layer is less different. Correspondingly, when the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment, the density of the edge portion of the phosphosilicate glass layer obtained by the reaction of silicon in the intrinsic amorphous silicon material layer with oxygen in the diffusion environment is also slightly different from the density of its central portion, so that the edge portion of the phosphosilicate glass layer has a higher corrosion resistance that is roughly the same as that of its central portion. Therefore, during the texturing process of at least the light-facing surface of the semiconductor substrate, the phosphosilicate glass layer can well protect the portion of the N-type doped polycrystalline silicon material layer located therebelow for forming the N-type doped polycrystalline silicon layer, so that the morphology and formation range of the obtained N-type doped polycrystalline silicon layer meet the target requirements, which is beneficial to the collection of carriers, reduces reverse leakage, and further helps to improve the photoelectric conversion efficiency of the back contact battery.

[0008] As a possible implementation manner, the size uniformity of the suede structure on each area of ​​the light-facing surface is greater than or equal to 85% and less than 100%.

[0009] When the above technical solution is adopted, the velvet surface on each area of ​​the light-facing surface has a high size uniformity, which is conducive to making each area of ​​the light-facing surface have a high light transmittance, so that more light can be transmitted through the light-facing surface into the semiconductor substrate, further improving the photoelectric conversion efficiency of the back contact battery.

[0010] As a possible implementation, the semiconductor substrate is a P-type semiconductor substrate. Along a direction parallel to the backlight surface, the backlight surface of the semiconductor substrate has P-type regions alternately distributed with stacked tunnel passivation layers and N-type doped polysilicon layers.

[0011] When the above technical solution is adopted, the backlight surface of the semiconductor substrate has a P-type region that is alternately distributed with the stacked tunnel passivation layer and the N-type doped polysilicon layer, and the P-type region is the back surface field of the back contact battery. In other words, the back surface field in the back contact battery provided by the present invention is a region possessed by the P-type semiconductor substrate, and there is no need to form an additional back surface field, which simplifies the process of the back contact battery and improves the process efficiency. At the same time, it can also prevent the occurrence of problems such as low minority carrier lifetime of the semiconductor substrate and difficulty in removing edge PN junctions due to the need to perform two high-temperature doping of N-type and P-type on the backlight side, which is beneficial to improving the yield of the back contact battery.

[0012] As a possible implementation manner, the thickness of a portion of the N-type doped polysilicon layer located on the edge region of the backlight surface is greater than or equal to 175 nm and less than or equal to 225 nm.

[0013] When the above technical solution is adopted, the thickness of the portion of the N-type doped polysilicon layer located on the edge area of ​​the backlight surface is within the above range, which can prevent the overall thickness of the N-type doped polysilicon layer from being too small and not meeting the target requirements due to the above thickness value being too small, and prevent the difficulty in manufacturing the N-type doped polysilicon layer with high thickness uniformity, which is conducive to obtaining a back contact battery. At the same time, it can also prevent the poor corrosion resistance of the phosphorus silicon glass layer located on the edge portion of the N-type doped polysilicon material layer after the phosphorus diffusion treatment due to the above thickness value being too large, ensuring that the phosphorus silicon glass layer can well include the various portions of the N-type doped polysilicon material layer used to form the N-type doped polysilicon layer during the texturing process, ensuring that the N-type doped polysilicon layer has a good morphology and a formation range that meets the target requirements.

[0014] As a possible implementation manner, the thickness of the portion of the N-type doped polysilicon layer located in the central area of ​​the backlight surface is greater than or equal to 150 nm and less than or equal to 200 nm.

[0015] As a possible implementation method, the average doping concentration of impurities in the N-type doped polysilicon layer is greater than or equal to 3.5×10 20 / cm 3 , and less than or equal to 4.0×10 20 / cm 3 .

[0016] When the above technical solution is adopted, the average doping concentration of impurities in the N-type doped polysilicon layer is within the above range, which can ensure that the N-type doped polysilicon layer has excellent carrier selective collection effect and does not affect the contact resistance between the N-type doped polysilicon layer and the negative electrode. Compared with the existing N-type doped polysilicon layer (the average doping concentration of impurities in the N-type doped polysilicon layer is greater than 5.0×10 20 / cm 3 ), appropriately reducing the impurity doping concentration in the N-type doped polysilicon layer of the present invention. Correspondingly, the average doping concentration of impurities in the N-type doped polysilicon material layer used to manufacture the N-type doped polysilicon layer is also relatively low. Based on this, in the actual manufacturing process, the average doping concentration of impurities in the N-type doped polysilicon material layer after the phosphorus diffusion treatment is proportional to the average doping concentration of impurities in the phosphosilicate glass layer formed on itself, so appropriately reducing the impurity doping concentration in the N-type doped polysilicon layer also means that the average doping concentration of impurities (the impurities include phosphorus) in the phosphosilicate glass layer is reduced. In this case, because the phosphorus doping concentration in the phosphosilicate glass layer is inversely proportional to its own corrosion resistance, appropriately reducing the phosphorus doping concentration in the phosphosilicate glass layer can also improve its own corrosion resistance, further ensuring that the N-type doped polysilicon layer has a good morphology and a formation range that meets the target requirements.

[0017] In a second aspect, the present invention further provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.

[0018] The beneficial effects of the second aspect of the present invention can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, which will not be elaborated here.

[0019] In a third aspect, the present invention also provides a method for manufacturing a back-contact battery, which comprises: first, providing a semiconductor substrate. Next, along the thickness direction of the semiconductor substrate, a tunnel passivation material layer and an intrinsic amorphous silicon material layer are sequentially formed in a stacked manner on the backlight side of the semiconductor substrate. Next, the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment so that the intrinsic amorphous silicon material layer forms an N-type doped polycrystalline silicon material layer, and a phosphosilicate glass layer is formed on the N-type doped polycrystalline silicon material layer. The thickness ratio of the portion of the N-type doped polycrystalline silicon material layer located on the edge area of ​​the backlight surface to the portion of the N-type doped polycrystalline silicon material layer located on the central area of ​​the backlight surface is greater than or equal to 1 and less than or equal to 1.2. Next, under the masking action of the phosphosilicate glass layer, the light-facing surface of the semiconductor substrate is subjected to a texturing treatment so that a velvet surface is formed on the light-facing surface. Then, the phosphosilicate glass layer, the stacked tunnel passivation material layer and the N-type doped polysilicon material layer are patterned to form a tunnel passivation layer and an N-type doped polysilicon layer stacked on a local area of ​​the backlight surface. Next, the remaining phosphosilicate glass layer is removed.

[0020] The beneficial effects of the third aspect of the present invention can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be elaborated here.

[0021] As a possible implementation manner, the ambient pressure for forming the intrinsic amorphous silicon material layer is greater than or equal to 100 mTorr and less than or equal to 150 mTorr.

[0022] In the case of adopting the above technical solution, in the actual process of manufacturing the intrinsic amorphous silicon material layer, within a certain range, reducing the environmental pressure can increase the molecular free path, allowing the reactive molecular groups to reach the various areas on the surface of the tunnel passivation material layer faster, rather than gathering at the same position. Based on this, the environmental pressure for forming the intrinsic amorphous silicon material layer is within the above range, which can prevent the edge portion of the intrinsic amorphous silicon material layer from having a large thickness due to the high environmental pressure, ensure that the thickness difference between the edge portion and the central portion of the intrinsic amorphous silicon material layer is small, ensure that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as the structure of its central portion, and thus make the phosphorus silicon glass layer formed after the phosphorus diffusion treatment have high corrosion resistance in all parts parallel to the backlight surface, and ensure that the morphology and formation range of the formed N-type doped polysilicon meet the target requirements. At the same time, it can also prevent the process efficiency from being low due to low environmental pressure.

[0023] As a possible implementation manner, the gas flow rate for forming the intrinsic amorphous silicon material layer is greater than or equal to 0.9 slm and less than or equal to 1.2 slm.

[0024] In the case of adopting the above technical solution, in the actual process of manufacturing the intrinsic amorphous silicon material layer, within a certain range, reducing the gas flow rate can reduce the total gas flow rate in the diffusion device, thereby reducing the disturbance caused by the gas flow in the diffusion device, which is conducive to optimizing the deposition quality of the portion of the intrinsic amorphous silicon material layer located on the edge area of ​​the backlight surface, ensuring that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as the structure of its central portion, thereby making the phosphorus silicon glass layer formed after the phosphorus diffusion treatment along the direction parallel to the backlight surface have high corrosion resistance, ensuring that the morphology and formation range of the formed N-type doped polysilicon meet the target requirements. At the same time, it can also prevent the process efficiency from being low due to a small gas flow rate.

[0025] As a possible implementation method, after the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment, under the mask of the phosphosilicate glass layer, before the light-facing surface of the semiconductor substrate is subjected to texturing treatment, only the phosphosilicate glass layer is subjected to patterning treatment, so that the remaining part of the phosphosilicate glass layer is formed on a local area of ​​the N-type doped polysilicon material layer. In this case, while the light-facing surface of the semiconductor substrate is subjected to texturing treatment under the mask of the phosphosilicate glass layer, the stacked tunnel passivation material layer and the N-type doped polysilicon material layer are subjected to patterning treatment.

[0026] When adopting the above technical scheme, the phosphosilicate glass layer located on the backlight side is patterned before the texturing treatment, so that in the subsequent texturing process, the texturing etching liquid can not only form a velvet surface at least on the light side, but also can pattern the N-type doped polysilicon material layer under the masking effect of the remaining part of the phosphosilicate glass layer to obtain the N-type doped polysilicon layer, thereby improving the process efficiency of the back contact battery while ensuring that the morphology and formation range of the N-type doped polysilicon layer meet the target requirements.

[0027] As a possible implementation method, while an intrinsic amorphous silicon material layer is formed on the backlight side of the semiconductor substrate along the thickness direction of the semiconductor substrate, a plated amorphous silicon layer is formed on the side and part of the light-facing surface of the semiconductor substrate. The width of the formation area of ​​the plated amorphous silicon layer on the light-facing surface is greater than or equal to 0 and less than 10 mm. The width direction of the formation area is parallel to the radial direction of the semiconductor substrate. In addition, after phosphorus diffusion treatment, the plated amorphous silicon layer forms a plated doped layer, and a plated phosphosilicate glass layer is formed on the plated doped layer. In the above case, after the phosphorus diffusion treatment of the intrinsic amorphous silicon material layer, and before the light-facing surface of the semiconductor substrate is subjected to a texturing treatment under the masking action of the phosphosilicate glass layer, the manufacturing method of the back contact battery also includes: removing the plated phosphosilicate glass layer and the plated doped layer.

[0028] When the above technical solution is adopted, before the texturing treatment is performed, the coiled phosphorus silicon glass layer and the coiled doping layer formed by coiling need to be removed in sequence, and the etching solution for removing the coiled doping layer will also affect the surface of the part of the semiconductor substrate facing the light that is covered by the coiled doping layer, so that a porous structure is formed on the surface of this part, and the surface of the central area of ​​the semiconductor substrate facing the light that is not covered by the coiled doping layer is relatively flat, resulting in the inconsistent size of the velvet structure located on the edge area and the central area of ​​the light-facing surface after the subsequent texturing treatment, thereby affecting the light-trapping effect of the light-facing surface. In this case, compared with the width of the formation area of ​​the coiled doping layer formed on the light-facing surface when manufacturing the back-contact battery in the prior art, which is greater than 10 mm, when the width of the formation area of ​​the coiled amorphous silicon layer on the light-facing surface in the present invention is greater than or equal to 0 and less than 10 mm, its coiling width is smaller, which is beneficial to improve the size uniformity of the velvet structure located in each area of ​​the light-facing surface, thereby improving the light-trapping effect of the light-facing surface, and further improving the photoelectric conversion efficiency of the back-contact battery.

[0029] As a possible implementation manner, the thickness of the phosphosilicate glass layer is greater than or equal to 60 nm and less than or equal to 65 nm.

[0030] When the above technical solution is adopted, the thickness of the phosphosilicate glass layer is within the above range, which can prevent the poor corrosion resistance of the phosphosilicate glass layer due to the small thickness of the phosphosilicate glass layer, and ensure that the morphology and formation range of the formed N-type doped polysilicon layer meet the target requirements. At the same time, it can also prevent the large amount of consumables used in manufacturing the intrinsic amorphous silicon material layer and the phosphosilicate glass layer due to the large thickness of the phosphosilicate glass layer, which is conducive to controlling the manufacturing cost of the back contact battery.

[0031] As a possible implementation, the average thickness of the intrinsic amorphous silicon material layer is H1, the average thickness of the phosphosilicate glass layer is H2, the average thickness of the N-type doped polysilicon material layer is H3, and 40% H2

[0032] ​When the above technical solution is adopted, as mentioned above, the formation of the phosphosilicate glass layer needs to consume silicon elements in the N-type doped polysilicon material layer. Based on this, the average thickness of the intrinsic amorphous silicon material layer, the phosphosilicate glass layer and the N-type doped polysilicon material layer meets the above conditions, indicating that the thickness of the intrinsic amorphous silicon material layer is appropriate, and the density of each region of the intrinsic amorphous silicon material layer along the direction parallel to the backlight surface and the uniformity of the structural density are both high, which is conducive to the formation of the phosphosilicate glass layer. The consumed thickness of the N-type doped polysilicon material layer can meet the theoretical consumption of the N-type doped polysilicon material layer with higher density (that is, the thickness of the phosphosilicate glass layer is approximately equal to half of the reduction in the thickness of the N-type doped polysilicon material layer) or is slightly different from the above theoretical consumption, which further indicates that the formation quality of the optimized phosphosilicate glass layer is high, ensuring that the formed N-type doped polysilicon layer has a good morphology and meets the formation range required by the target.

[0033] As a possible implementation method, the processing conditions of the phosphorus diffusion treatment are:

[0034] The deposition process temperature is greater than or equal to 850°C and less than or equal to 900°C. And / or, the deposition process environment pressure is greater than or equal to 150mbar and less than or equal to 200mbar. And / or, the deposition process phosphorus source pressure is greater than or equal to 250mbar and less than or equal to 450mbar. And / or, the deposition process nitrogen flow rate is greater than or equal to 1500sccm and less than or equal to 2000sccm. And / or, the deposition process oxygen flow rate is greater than or equal to 750sccm and less than or equal to 1000sccm. And / or, the post-oxidation process temperature is greater than or equal to 850°C and less than or equal to 900°C. And / or, the post-oxidation process oxygen flow rate is greater than or equal to 5000sccm and less than or equal to 10000sccm.

[0035] In the case of adopting the above technical solution, in the actual manufacturing process, the deposition process temperature, deposition process environmental pressure, deposition process phosphorus source pressure, deposition process nitrogen flow rate and deposition process oxygen flow rate during the above phosphorus diffusion treatment are changed, and the average doping concentration of impurities in the formed phosphorus silicon glass layer and the N-type doped polysilicon material can be regulated. Based on this, when at least one of the deposition process temperature, deposition process environmental pressure, deposition process phosphorus source pressure, deposition process nitrogen flow rate and deposition process oxygen flow rate is within the above corresponding range, the average doping concentration of phosphorus in the phosphorus silicon glass layer can be appropriately reduced, so that the phosphorus silicon glass layer has a higher corrosion resistance, thereby ensuring that the N-type doped polysilicon layer formed based on the N-type doped polysilicon material layer has a good morphology and meets the target requirements. Formation range. In addition, changing the post-oxidation process temperature and the post-oxidation process oxygen flow rate during the phosphorus diffusion treatment can regulate the thickness of the formed phosphorus silicon glass layer. Based on this, when at least one of the post-oxidation process temperature and the post-oxidation process oxygen flow rate is within the above corresponding range, the formation thickness of the phosphorus silicon glass layer can be appropriately increased, thereby improving the corrosion resistance of the phosphorus silicon glass layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0037] Figure 1 A schematic longitudinal cross-sectional view of the structure of a back-contact battery provided by an embodiment of the present invention;

[0038] Figure 2 is a schematic diagram of the SEM morphology of a portion of an N-type doped polysilicon layer formed in the related art and located on an edge region of a backlight surface;

[0039] Figure 3 Schematic diagram of the SEM morphology of the portion of the N-type doped polysilicon layer located on the edge region of the backlight surface in an embodiment of the present invention;

[0040] Figure 4 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention Figure 1 ;

[0041] Figure 5 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention Figure 2 ;

[0042] Figure 6 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention Figure 3 ;

[0043] Figure 7 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention Figure 4 ;

[0044] Figure 8 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention Figure 5 ;

[0045] Fig. 9 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention Figure 6 ;

[0046] Fig.10 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention Figure 7 .

[0047] Figure numerals: 11 is a semiconductor substrate, 12 is a tunneling passivation material layer, 13 is an intrinsic amorphous silicon material layer, 14 is a plated amorphous silicon layer, 15 is an N-type doped polysilicon material layer, 16 is a phosphosilicate glass layer, 17 is a plated doped layer, 18 is a plated phosphosilicate glass layer, 19 is a velvet surface, 20 is a tunneling passivation layer, 21 is an N-type doped polysilicon layer, 22 is a positive electrode, and 23 is a negative electrode. DETAILED DESCRIPTION

[0048] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0049] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0050] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0052] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] Tunneling passivated back contact solar cells refer to solar cells with positive and negative electrodes on the back of the cell, no metal electrode blocking the front, and with tunneling passivated contact structures. Tunneling passivated back contact solar cells have advantages such as large light absorption area and low carrier back recombination rate, which have attracted extensive attention from the photovoltaic academic and industrial circles and become a hot development direction of high-efficiency solar cell technology.

[0054] Specifically, the existing tunneling passivation back contact solar cell usually includes at least a semiconductor substrate, and a tunneling passivation layer and an N-type doped polysilicon layer stacked in sequence on a local area of ​​the backlight surface of the semiconductor substrate along the thickness direction of the semiconductor substrate. In this case, in the actual manufacturing process of the above-mentioned tunneling passivation back contact solar cell, after the tunneling passivation material layer and the intrinsic amorphous silicon material layer are formed in sequence and cover the backlight surface of the semiconductor substrate, the intrinsic amorphous silicon material layer will be subjected to phosphorus diffusion treatment, so that the intrinsic amorphous silicon material layer forms an N-type doped polysilicon material layer, and a phosphorus silicon glass layer is formed on the N-type doped polysilicon material layer. Then, under the masking action of the phosphorus silicon glass layer, at least the light-facing surface of the semiconductor substrate is subjected to a texturing treatment, so that at least the light-facing surface forms a texturing surface, thereby allowing more light to be transmitted into the semiconductor substrate through the light-facing surface, which is beneficial to improving the photoelectric conversion efficiency of the tunneling passivation back contact solar cell. At the same time, the phosphosilicate glass layer formed in the phosphorus diffusion process is directly used as a mask layer to protect the N-type doped polysilicon layer. There is no need to form other additional mask layers to protect the N-type doped polysilicon layer, so as to simplify the process steps of the tunnel passivation back-contact solar cell and improve the process efficiency.

[0055] However, the thickness of the edge portion of the intrinsic amorphous silicon material layer formed by the existing manufacturing method is relatively large, and the thickness of the central portion thereof is relatively small; and the thickness difference between the edge portion and the middle portion of the intrinsic amorphous silicon material layer is relatively large (the thickness ratio between the two is generally greater than 1.3). In this case, since the intrinsic amorphous silicon material layer is formed simultaneously along the portions parallel to the backlight surface, the chemical dosage ratio of the intrinsic amorphous silicon material located at the edge region of the backlight surface and the intrinsic amorphous silicon material located at the central region of the backlight surface is substantially the same, so when the thickness difference between the edge portion and the central portion of the intrinsic amorphous silicon material layer is relatively large, the structure of the edge portion of the intrinsic amorphous silicon material layer is more loose. When the phosphorus diffusion treatment is carried out, the formation of the phosphosilicate glass layer consumes the silicon element in the intrinsic amorphous silicon material layer and reacts it with the oxygen in the diffusion environment. Therefore, when the structure of the edge portion of the intrinsic amorphous silicon material layer is looser, the formation quality of the phosphosilicate glass layer on the edge portion of the intrinsic amorphous silicon material layer is also poor, resulting in poor corrosion resistance of the phosphosilicate glass layer in this portion, which makes it difficult for the phosphosilicate glass layer to well protect the N-type doped polycrystalline silicon material layer underneath during the texturing process, thereby making the N-type doped polycrystalline silicon layer formed based on the N-type doped polycrystalline silicon material layer have a poor morphology and a small formation range in the edge region, which is not conducive to the collection of carriers and results in poor working performance of the tunneling passivated back-contact solar cell.

[0056] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a back contact battery. Figure 1As shown, the back contact cell includes: a semiconductor substrate 11, and a tunnel passivation layer 20 and an N-type doped polysilicon layer 21, which are sequentially stacked on a local area of ​​the backlight surface of the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11. The light-facing surface of the semiconductor substrate 11 is a velvet surface 19. The doping elements in the N-type doped polysilicon layer 21 include phosphorus, and the thickness ratio of the portion of the N-type doped polysilicon layer 21 located on the edge area of ​​the backlight surface to the portion of the N-type doped polysilicon layer 21 located on the central area of ​​the backlight surface is greater than or equal to 1 and less than or equal to 1.2.

[0057] Specifically, in terms of material, the material of the semiconductor substrate may be semiconductor materials such as silicon, silicon germanium or germanium. In terms of conductivity type, the semiconductor substrate may be an N-type semiconductor substrate or a P-type semiconductor substrate.

[0058] From a structural perspective, the specific structure of the semiconductor substrate can be determined according to the conductivity type of the semiconductor substrate and the actual application scenario.

[0059] Exemplarily, in the case where the semiconductor substrate is a P-type semiconductor substrate, along the direction parallel to the backlight surface, the backlight surface of the semiconductor substrate has a P-type region that is alternately spaced with the stacked tunneling passivation layer and the N-type doped polysilicon layer. At this time, the P-type region is the back surface field of the back contact battery. In other words, the back surface field in the back contact battery provided by the embodiment of the present invention is a region possessed by the P-type semiconductor substrate, and there is no need to perform additional doping treatment to form the back surface field, which simplifies the process steps of the back contact battery and improves the process efficiency. At the same time, it can also prevent the occurrence of problems such as low minority carrier lifetime of the semiconductor substrate and difficulty in removing edge PN junctions due to the need to perform two high-temperature doping of N-type and P-type on one side of the backlight surface, which is beneficial to improving the yield of the back contact battery.

[0060] Of course, when the semiconductor substrate is a P-type semiconductor substrate, a P-type doped region may be formed on a local area of ​​the backlight surface of the semiconductor substrate. Along a direction parallel to the backlight surface, the P-type doped region and the stacked tunnel passivation layer and the N-type doped polysilicon layer are alternately distributed.

[0061] Exemplarily, when the semiconductor substrate is an N-type semiconductor substrate, a P-type doped region is formed in a local area of ​​the backlight surface of the semiconductor substrate or on a local area of ​​the backlight surface. Along a direction parallel to the backlight surface, the P-type doped region and the stacked tunnel passivation layer and the N-type doped polysilicon layer are alternately distributed.

[0062] In terms of morphology, the light-facing surface of the semiconductor substrate is a velvet surface. The side surface of the semiconductor substrate can be a polished surface or a velvet surface. The surface of the area of ​​the semiconductor substrate that is not covered by the stacked tunnel passivation layer and the N-type doped polysilicon layer can be a velvet surface or a polished surface.

[0063] For the above-mentioned tunnel passivation layer, the material and thickness of the tunnel passivation layer can be set according to actual needs, and are not specifically limited here. For example, the material of the tunnel passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbide.

[0064] For the above-mentioned N-type doped polysilicon layer, the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge region of the backlight surface to the portion of the N-type doped polysilicon layer located on the central region of the backlight surface may be any value greater than or equal to 1 and less than or equal to 1.2. For example, the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge region of the backlight surface to the portion of the N-type doped polysilicon layer located on the central region of the backlight surface may be 1, 1.12, 1.14, 1.16, 1.18 or 1.2, etc.

[0065] When the above technical solution is adopted, the tunnel passivation contact structure composed of the above tunnel passivation layer and the N-type doped polysilicon layer can achieve excellent interface passivation and carrier selective collection, which is beneficial to improve the photoelectric conversion efficiency of the back contact battery. In addition, compared with the existing N-type doped polysilicon layer (see Figure 2 ) is greater than 1.3, the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge region of the backlight surface to the portion of the N-type doped polysilicon layer located on the center region of the backlight surface in the embodiment of the present invention is greater than or equal to 1 and less than or equal to 1.2. Figure 1 As shown in FIG. 1 , at this time, the difference between the thickness of the edge portion and the thickness of the center portion of the N-type doped polysilicon layer 21 is small. In this case, in the actual manufacturing process, Figure 4 As shown, a tunneling passivation material layer 12 and an intrinsic amorphous silicon material layer 13 for manufacturing a tunneling passivation layer and an N-type doped polysilicon layer are usually formed by processes such as chemical vapor deposition. Based on this, when the difference between the thickness of the edge portion and the thickness of the central portion of the N-type doped polysilicon layer is small, the difference between the thickness of the edge portion and the thickness of the central portion of the intrinsic amorphous silicon material layer 13 forming the N-type doped polysilicon layer is also small. Since the intrinsic amorphous silicon material layer 13 is formed simultaneously along all portions parallel to the backlight surface, the chemical dosage ratio of the intrinsic amorphous silicon material located on the edge region of the backlight surface and the intrinsic amorphous silicon material located on the central region of the backlight surface is roughly the same, so when the difference between the thickness of the edge portion and the central portion of the intrinsic amorphous silicon material layer 13 is small, the structural density of the edge portion and the central portion of the intrinsic amorphous silicon material layer 13 is less different (see Figure 3 ). Correspondingly, Figure 5As shown in FIG. 1 , when the intrinsic amorphous silicon material layer 13 is subjected to phosphorus diffusion treatment, the density of the edge portion of the phosphosilicate glass layer 16 obtained by the reaction of silicon in the intrinsic amorphous silicon material layer 13 with oxygen in the diffusion environment is also slightly different from the density of the central portion thereof, so that the edge portion of the phosphosilicate glass layer 16 has a high corrosion resistance substantially the same as that of the central portion thereof, so that during the texturing process of at least the light-facing surface of the semiconductor substrate 11, the phosphosilicate glass layer 16 can well protect the portion of the N-type doped polysilicon material layer 15 located therebelow for forming the N-type doped polysilicon layer 21 (see FIG. 1 ). Figure 7 and Figure 8 ), so that the morphology and formation range of the obtained N-type doped polysilicon layer 21 meet the target requirements, which is beneficial to the collection of carriers, reduces reverse leakage, and further helps to improve the photoelectric conversion efficiency of the back contact battery.

[0066] From the above content, it can be known that the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge area of ​​the backlight surface to the portion of the N-type doped polysilicon layer located on the central area of ​​the backlight surface will affect the corrosion resistance of the phosphorus silicon glass layer formed after the phosphorus diffusion treatment, and further affect its own morphology and its own formation range on the backlight side. Based on this, along the direction parallel to the backlight surface, the specific thickness of each portion of the N-type doped polysilicon layer can be determined according to the requirements for the morphology of the N-type doped polysilicon layer and the formation range on the backlight side in the actual application scenario, as long as it can be applied to the back contact battery provided in the embodiment of the present invention.

[0067] For example, Figure 1 As shown, the thickness of the portion of the N-type doped polysilicon layer 21 located on the edge region of the backlight surface may be greater than or equal to 175nm and less than or equal to 225nm. For example, the thickness of the portion of the N-type doped polysilicon layer 21 located on the edge region of the backlight surface may be 175nm, 185nm, 195nm, 205nm, 215nm or 225nm, etc. In this case, the thickness of the portion of the N-type doped polysilicon layer 21 located on the edge region of the backlight surface is within the above range, which can prevent the overall thickness of the N-type doped polysilicon layer 21 from being too small and not meeting the target requirements due to the small thickness value, and prevent the difficulty in manufacturing the N-type doped polysilicon layer 21 with high thickness uniformity, which is conducive to obtaining a back contact battery. At the same time, it can also prevent the poor corrosion resistance of the phosphosilicate glass layer located on the edge of the N-type doped polysilicon material layer after the phosphorus diffusion treatment due to the large thickness value mentioned above, and ensure that the phosphosilicate glass layer can well include the various parts of the N-type doped polysilicon material layer used to form the N-type doped polysilicon layer 21 during the texturing process, and ensure that the N-type doped polysilicon layer 21 has a good morphology and a formation range that meets the target requirements.

[0068] For example, Figure 1 As shown, the thickness of the portion of the N-type doped polysilicon layer 21 located in the central area of ​​the backlight surface may be greater than or equal to 150 nm and less than or equal to 200 nm. For example, the thickness of the portion of the N-type doped polysilicon layer 21 located in the central area of ​​the backlight surface may be 150 nm, 160 nm, 170 nm, 180 nm, 190 nm or 200 nm.

[0069] In terms of doping, the N-type doped polysilicon layer may be doped with only one N-type impurity, phosphorus, or may be doped with N-type impurities, such as nitrogen or arsenic. As for the doping concentration of the impurities in the N-type doped polysilicon layer, it can be set according to actual needs and is not specifically limited here.

[0070] For example, the average doping concentration of impurities in the N-type doped polysilicon layer may be greater than or equal to 3.5×10 20 / cm 3 , and less than or equal to 4.0×10 20 / cm 3 For example, the average doping concentration of impurities in an N-type doped polysilicon layer can be 3.5×10 20 / cm 3 , 3.6×10 20 / cm 3 , 3.7×10 20 / cm 3 , 3.8×10 20 / cm 3 , 3.9×10 20 / cm 3 or 4.0×10 20 / cm 3 In this case, the average doping concentration of impurities in the N-type doped polysilicon layer is within the above range, which can ensure that the N-type doped polysilicon layer has excellent carrier selective collection effect and does not affect the contact resistance between the N-type doped polysilicon layer and the negative electrode. Compared with the existing N-type doped polysilicon layer (the average doping concentration of impurities in the N-type doped polysilicon layer is greater than 5.0×10 20 / cm 3), appropriately reducing the impurity doping concentration in the N-type doped polysilicon layer in the embodiment of the present invention. Correspondingly, the average doping concentration of impurities in the N-type doped polysilicon material layer used to manufacture the N-type doped polysilicon layer is also relatively low. Based on this, in the actual manufacturing process, the average doping concentration of impurities in the N-type doped polysilicon material layer after the phosphorus diffusion treatment is proportional to the average doping concentration of impurities in the phosphosilicate glass layer formed on itself, so appropriately reducing the impurity doping concentration in the N-type doped polysilicon layer also means that the average doping concentration of impurities (the impurities include phosphorus) in the phosphosilicate glass layer is reduced. In this case, because the phosphorus doping concentration in the phosphosilicate glass layer is inversely proportional to its own corrosion resistance, appropriately reducing the phosphorus doping concentration in the phosphosilicate glass layer can also improve its own corrosion resistance, further ensuring that the N-type doped polysilicon layer has a good morphology and a formation range that meets the target requirements.

[0071] In the actual application process, in the process of forming an N-type doped polysilicon layer on the backlight side, a coating doped layer and a coating phosphosilicate glass layer will be formed on the side and part of the light-facing surface of the semiconductor substrate due to coating. In addition, before the at least light-facing surface of the semiconductor substrate is subjected to the texturing treatment, the coating phosphosilicate glass layer and the coating doped layer need to be removed in sequence, and the etching solution for removing the coating doped layer will also affect the surface of the part of the light-facing surface of the semiconductor substrate covered by the coating doped layer, so that a porous structure is formed on the surface of this part, and the surface of the central area of ​​the light-facing surface of the semiconductor substrate that is not covered by the coating doped layer is relatively flat, resulting in inconsistent sizes of the velvet structures located on the edge area and the central area of ​​the light-facing surface after the subsequent texturing treatment, thereby affecting the light trapping effect of the light-facing surface. Specifically, the size uniformity of the velvet structure on each area of ​​the light-facing surface can be determined according to the formation of the N-type doped polysilicon layer, and is not specifically limited here.

[0072] For example, Figure 1 As shown, the size uniformity of the velvet structure on each area of ​​the light-facing surface is greater than or equal to 85% and less than 100%. The specific value of the size uniformity of the velvet structure on each area of ​​the light-facing surface can be determined according to the actual manufacturing process and is not specifically limited here. In this case, the size uniformity of the velvet on each area of ​​the light-facing surface is relatively high, which is conducive to making each area of ​​the light-facing surface have a high light transmittance, so that more light can be transmitted through the light-facing surface into the semiconductor substrate 11, further improving the photoelectric conversion efficiency of the back contact battery.

[0073] In some cases, such as Fig.10 As shown, the back contact cell provided by the embodiment of the present invention may also include a positive electrode 22 and a negative electrode 23. The positive electrode 22 is in ohmic contact with the P-type region of the semiconductor substrate 11. The negative electrode 23 is in ohmic contact with the N-type doped polysilicon layer 21. The materials of the positive electrode 22 and the negative electrode 23 may be conductive materials such as copper, aluminum or silver.

[0074] In a second aspect, an embodiment of the present invention further provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.

[0075] The beneficial effects of the second aspect in the embodiments of the present invention can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be elaborated here.

[0076] In a third aspect, an embodiment of the present invention further provides a method for manufacturing a back contact battery. Figures 4 to 10 The manufacturing process is described with reference to the cross-sectional views of the operations shown.

[0077] Specifically, the manufacturing method of the back contact battery includes: first, providing a semiconductor substrate. Next, Figure 4 As shown, along the thickness direction of the semiconductor substrate 11, a tunnel passivation material layer 12 and an intrinsic amorphous silicon material layer 13 are sequentially formed on the backlight side of the semiconductor substrate 11. Figure 5 As shown, the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment to form an N-type doped polysilicon material layer 15 from the intrinsic amorphous silicon material layer, and a phosphorus silicon glass layer 16 is formed on the N-type doped polysilicon material layer 15. The thickness ratio of the portion of the N-type doped polysilicon material layer 15 located in the central area of ​​the backlight surface is greater than or equal to 1 and less than or equal to 1.2. Next, as Figure 8 As shown, under the masking effect of the phosphorus silicon glass layer 16, the light-facing surface of the semiconductor substrate 11 is textured to form a textured surface 19 on the light-facing surface. Figure 8 As shown, the phosphosilicate glass layer 16, and the stacked tunnel passivation material layer and the N-type doped polysilicon material layer are patterned to form a tunnel passivation layer 20 and an N-type doped polysilicon layer 21 stacked on a local area of ​​the backlight surface. Fig. 9 As shown, the remaining phosphosilicate glass layer is removed.

[0078] The beneficial effects of the third aspect in the embodiments of the present invention can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be elaborated here.

[0079] Specifically, the specific structure, conductivity type and material of the above-mentioned semiconductor substrate can refer to the above text, and will not be repeated here. After providing the semiconductor substrate, the tunnel passivation material layer and the intrinsic amorphous silicon material layer can be formed by chemical vapor deposition and other processes. Among them, the material and thickness of the tunnel passivation material layer can refer to the above text. As for the intrinsic amorphous silicon material layer, the intrinsic amorphous silicon material layer is used to manufacture the N-type doped polycrystalline silicon layer included in the back contact battery. In addition, the phosphorus silicon glass layer formed after the phosphorus diffusion treatment needs to consume part of the silicon in the intrinsic amorphous silicon material layer, resulting in a reduction in the thickness of the N-type polycrystalline silicon material layer formed based on the intrinsic amorphous silicon material layer after the phosphorus diffusion treatment. Based on this, the thickness of each part of the intrinsic amorphous silicon material layer can be determined according to the thickness of each part of the N-type doped polycrystalline silicon material layer and the phosphorus silicon glass layer, and the thickness ratio of the intrinsic amorphous silicon material required to form the phosphorus silicon glass layer of the corresponding thickness.

[0080] Exemplarily, when the average thickness of the intrinsic amorphous silicon material layer is H1, the average thickness of the phosphosilicate glass layer is H2, and the average thickness of the N-type doped polysilicon material layer is H3, 40% H2

[0081] ​In addition, the N-type doped polysilicon material layer formed based on the intrinsic amorphous silicon material layer has a thickness ratio of a portion located on the edge area of ​​the backlight surface to a portion located on the central area of ​​the backlight surface that is greater than or equal to 1 and less than or equal to 1.2, and the corresponding thickness ratio of a portion of the intrinsic amorphous silicon material layer located on the edge area of ​​the backlight surface to a portion located on the central area of ​​the backlight surface also satisfies a thickness ratio of greater than or equal to 1 and less than or equal to 1.2. In this case, in the actual manufacturing process, the thickness of the corresponding area of ​​the intrinsic amorphous silicon material layer can be controlled by adjusting any parameters that can affect the formation thickness of different areas of the intrinsic amorphous silicon material layer, such as the ambient pressure and gas flow rate when the intrinsic amorphous silicon material layer is formed. Specifically, the specific parameter values ​​that affect the formation thickness of different areas of the intrinsic amorphous silicon material layer can be determined according to the specific formation thickness of different areas of the intrinsic amorphous silicon material layer, as long as it can be applied to the manufacturing method of the back contact battery provided in the embodiment of the present invention.

[0082] Exemplarily, the ambient pressure for forming the intrinsic amorphous silicon material layer may be greater than or equal to 100 mTorr and less than or equal to 150 mTorr. For example, the ambient pressure for forming the intrinsic amorphous silicon material layer may be 100 mTorr, 110 mTorr, 120 mTorr, 130 mTorr, 140 mTorr or 150 mTorr, etc. In this case, in the actual process of manufacturing the intrinsic amorphous silicon material layer, within a certain range, reducing the ambient pressure can increase the molecular free path, allowing the reactive molecular groups to reach various areas of the surface of the tunnel passivation material layer faster, rather than gathering at the same position. Based on this, the environmental pressure for forming the intrinsic amorphous silicon material layer is within the above range, which can prevent the edge portion of the intrinsic amorphous silicon material layer from having a large thickness due to the high environmental pressure, ensure that the thickness difference between the edge portion and the central portion of the intrinsic amorphous silicon material layer is small, ensure that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as the structure of its central portion, and thus make the phosphorus silicon glass layer formed after the phosphorus diffusion treatment have high corrosion resistance in all parts parallel to the backlight surface, and ensure that the morphology and formation range of the formed N-type doped polysilicon meet the target requirements. At the same time, it can also prevent the process efficiency from being low due to low environmental pressure.

[0083] Exemplarily, the gas flow rate for forming the intrinsic amorphous silicon material layer may be greater than or equal to 0.9 slm and less than or equal to 1.2 slm. For example, the gas flow rate for forming the intrinsic amorphous silicon material layer may be 0.9 slm, 1.0 slm, 1.1 slm or 1.2 slm. In this case, in the actual process of manufacturing the intrinsic amorphous silicon material layer, within a certain range, reducing the gas flow rate can reduce the total gas flow rate in the diffusion device, thereby reducing the degree of disturbance caused by the gas flow in the diffusion device, which is conducive to optimizing the deposition quality of the portion of the intrinsic amorphous silicon material layer located on the edge area of ​​the backlight surface, ensuring that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as the structure of its central portion, thereby making the phosphorus silicon glass layer formed after the phosphorus diffusion treatment along the direction parallel to the backlight surface have high corrosion resistance, ensuring that the morphology and formation range of the formed N-type doped polysilicon meet the target requirements. At the same time, it can also prevent the process efficiency from being low due to a small gas flow rate.

[0084] It should be noted that if Figure 4 As shown, along the thickness direction of the semiconductor substrate 11, while the intrinsic amorphous silicon material layer 13 is formed on the backlight side of the semiconductor substrate 11, a wrap-around amorphous silicon layer 14 is formed on the side and part of the light-facing surface of the semiconductor substrate 11. The width of the formation area of ​​the wrap-around amorphous silicon layer 14 on the light-facing surface (the width direction of the formation area is parallel to the radial direction of the semiconductor substrate 11) is affected by parameters such as the ambient pressure and gas flow rate when manufacturing the intrinsic amorphous silicon material layer 13. For example: within a certain range, the smaller the ambient pressure when manufacturing the intrinsic amorphous silicon material layer 13, the smaller the width of the formation area of ​​the wrap-around amorphous silicon layer 14 on the light-facing surface. In the above case, the width of the formation area of ​​the wrap-around amorphous silicon layer 14 on the light-facing surface can be determined according to the manufacturing conditions of the intrinsic amorphous silicon material layer 13.

[0085] Exemplarily, the width of the formation area of ​​the above-mentioned plated amorphous silicon layer on the light-facing surface can be greater than or equal to 0 and less than 10 mm. For example: the width of the formation area of ​​the plated amorphous silicon layer on the light-facing surface can be 1 mm, 3 mm, 6 mm, 9 mm or 9.5 mm, etc. In this case, before the texturing process is performed, the plated phosphorus silicon glass layer and the plated doping layer formed by the plating need to be removed in sequence, and the etching solution for removing the plated doping layer will also affect the surface of the portion of the semiconductor substrate facing the light that is covered by the plated doping layer, so that a porous structure is formed on the surface of this portion, and the surface of the central area of ​​the semiconductor substrate facing the light that is not covered by the plated doping layer is relatively flat, resulting in inconsistent sizes of the velvet structures located on the edge area and the central area of ​​the light-facing surface after the subsequent texturing process, thereby affecting the light trapping effect of the light-facing surface. In this case, compared with the width of the formation area of ​​the doped layer on the light-facing surface formed in the prior art manufacturing of back-contact cells being greater than 10 mm, when the width of the formation area of ​​the amorphous silicon layer on the light-facing surface in the embodiment of the present invention is greater than or equal to 0 and less than 10 mm, the plating width is smaller, which is beneficial to improving the size uniformity of the velvet structure located in various areas of the light-facing surface, thereby improving the light trapping effect of the light-facing surface, and further improving the photoelectric conversion efficiency of the back-contact cell. It can be seen that the specific value of the size uniformity of the velvet structure on various areas of the light-facing surface of the semiconductor substrate can be determined according to the width of the formation area of ​​the amorphous silicon layer on the light-facing surface during the actual manufacturing process and the size of the semiconductor substrate, and is not specifically limited here.

[0086] In the actual manufacturing process, after forming the above-mentioned intrinsic amorphous silicon material layer, it is necessary to perform phosphorus diffusion treatment on the intrinsic amorphous silicon material layer to form the above-mentioned N-type doped polysilicon material layer and phosphosilicate glass layer. Among them, the phosphorus diffusion treatment includes a phosphorus source deposition step, a crystallization step, and a post-oxidation step performed in sequence. The above-mentioned phosphorus source deposition step can regulate the doping concentration of phosphorus in the N-type doped polysilicon material layer and the phosphosilicate glass layer, and the above-mentioned post-oxidation step can regulate the thickness of the N-type doped polysilicon material layer and the phosphosilicate glass layer. In addition, the doping concentration of phosphorus in the N-type doped polysilicon material layer and the phosphosilicate glass layer, as well as the thickness of the phosphosilicate glass layer, have an impact on the corrosion resistance of the phosphosilicate glass layer during the texturing process. Based on this, the specific process parameters of the phosphorus diffusion treatment can be determined according to the thickness and doping concentration of the N-type doped polysilicon material layer and the phosphosilicate glass layer, and the requirements of the actual application scenario for the morphology and formation range of the N-type doped polysilicon layer, and no specific limitation is made here.

[0087] Exemplarily, the treatment conditions of the phosphorus diffusion treatment are:

[0088] The deposition process temperature is greater than or equal to 850° C. and less than or equal to 900° C. For example, the deposition process temperature may be 850° C., 860° C., 870° C., 880° C., 890° C., or 900° C., etc.

[0089] The deposition process environment pressure is greater than or equal to 150 mbar and less than or equal to 200 mbar. For example, the deposition process environment pressure may be 150 mbar, 160 mbar, 170 mbar, 180 mbar, 190 mbar or 200 mbar.

[0090] The pressure of the phosphorus source in the deposition process is greater than or equal to 250 mbar and less than or equal to 450 mbar. For example, the pressure of the phosphorus source in the deposition process can be 250 mbar, 300 mbar, 350 mbar, 400 mbar or 450 mbar.

[0091] The nitrogen flow rate of the deposition process is greater than or equal to 1500 sccm and less than or equal to 2000 sccm. For example, the nitrogen flow rate of the deposition process can be 1500 sccm, 1600 sccm, 1700 sccm, 1800 sccm, 1900 sccm or 2000 sccm.

[0092] The oxygen flow rate of the deposition process is greater than or equal to 750 sccm and less than or equal to 1000 sccm. For example, the oxygen flow rate of the deposition process can be 750 sccm, 800 sccm, 850 sccm, 900 sccm, 950 sccm or 1000 sccm.

[0093] The post-oxidation process temperature is greater than or equal to 850° C. and less than or equal to 900° C. For example, the post-oxidation process temperature may be 850° C., 860° C., 870° C., 880° C., 890° C. or 900° C., etc.

[0094] The oxygen flow rate of the post-oxidation process is greater than or equal to 5000 sccm and less than or equal to 10000 sccm. For example, the oxygen flow rate of the post-oxidation process can be 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm or 10000 sccm.

[0095] Among them, any one of the above process parameters may meet the corresponding range requirements, or at least two of the above process parameters may meet the corresponding range requirements.

[0096] In the case of adopting the above technical solution, in the actual manufacturing process, the deposition process temperature, deposition process environmental pressure, deposition process phosphorus source pressure, deposition process nitrogen flow rate and deposition process oxygen flow rate during the above phosphorus diffusion treatment are changed, and the average doping concentration of impurities in the formed phosphorus silicon glass layer and the N-type doped polysilicon material can be regulated. Based on this, when at least one of the deposition process temperature, deposition process environmental pressure, deposition process phosphorus source pressure, deposition process nitrogen flow rate and deposition process oxygen flow rate is within the above corresponding range, the average doping concentration of phosphorus in the phosphorus silicon glass layer can be appropriately reduced, so that the phosphorus silicon glass layer has a higher corrosion resistance, thereby ensuring that the N-type doped polysilicon layer formed based on the N-type doped polysilicon material layer has a good morphology and meets the target requirements. Formation range. In addition, changing the post-oxidation process temperature and the post-oxidation process oxygen flow rate during the phosphorus diffusion treatment can regulate the thickness of the formed phosphorus silicon glass layer. Based on this, when at least one of the post-oxidation process temperature and the post-oxidation process oxygen flow rate is within the above corresponding range, the formation thickness of the phosphorus silicon glass layer can be appropriately increased, thereby improving the corrosion resistance of the phosphorus silicon glass layer.

[0097] Exemplarily, the thickness of the above-mentioned phosphosilicate glass layer may be greater than or equal to 60 nm and less than or equal to 65 nm. For example, the thickness of the phosphosilicate glass layer may be 60 nm, 61 nm, 62 nm, 63 nm, 64 nm or 65 nm, etc. In this case, the thickness of the phosphosilicate glass layer is within the above-mentioned range, which can prevent the poor corrosion resistance of the phosphosilicate glass layer due to the small thickness of the phosphosilicate glass layer, and ensure that the morphology and formation range of the formed N-type doped polysilicon layer meet the target requirements. At the same time, it can also prevent the large amount of consumables used in the manufacture of the intrinsic amorphous silicon material layer and the phosphosilicate glass layer due to the large thickness of the phosphosilicate glass layer, which is beneficial to control the manufacturing cost of the back contact battery.

[0098] It should be noted that if Figure 5 As shown, after phosphorus diffusion treatment, the amorphous silicon layer is plated to form a plated doped layer 17, and a plated phosphorus silicon glass layer 18 is formed on the plated doped layer 17. In this case, after forming the above-mentioned N-type doped polysilicon material layer 15 and before performing a texturing treatment on at least the light-facing surface of the semiconductor substrate 11, as shown in FIG. Figure 6 As shown, a process such as wet etching can be used to sequentially remove the wrap-around phosphosilicate glass layer and the wrap-around doping layer.

[0099] In addition, after the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment, before at least the light-facing surface of the semiconductor substrate is subjected to texturing treatment, such as Figure 7 As shown, laser etching or the like can be used to pattern only the phosphosilicate glass layer 16 so that the remaining portion of the phosphosilicate glass layer 16 is formed on a local area of ​​the N-type doped polysilicon material layer 15. In this case, Figure 8As shown, under the masking action of the phosphosilicate glass layer 16, the light-facing surface of the semiconductor substrate 11 is subjected to texturing, and at the same time, the stacked tunnel passivation material layer and the N-type doped polysilicon material layer can be patterned. In other words, the phosphosilicate glass layer 16 located on the backlight side is patterned before the texturing process, so that in the subsequent texturing process, the texturing etching liquid can not only form a velvet surface 19 on at least the light-facing surface, but also can pattern the N-type doped polysilicon material layer and the tunnel passivation material layer under the masking action of the remaining part of the phosphosilicate glass layer 16, so as to obtain the N-type doped polysilicon layer 21 and the tunnel passivation layer 20, thereby improving the process efficiency of the back contact battery while ensuring that the morphology and formation range of the N-type doped polysilicon layer 21 meet the target requirements.

[0100] Of course, after removing the coated phosphosilicate glass layer and the coated doped layer, at least the light-facing surface of the semiconductor substrate can be textured directly under the mask of the entire phosphosilicate glass layer. At this time, the texture etching solution will not affect each area of ​​the N-type doped polysilicon material layer parallel to the backlight surface. In this case, after the texture treatment, the phosphosilicate glass layer can be patterned by laser etching, and then wet etching or dry etching can be used to pattern the tunnel passivation material layer and the N-type doped polysilicon material layer under the mask of the remaining part of the phosphosilicate glass layer to obtain the tunnel passivation layer and the N-type doped polysilicon layer.

[0101] Then, if Fig. 9 As shown, a process such as wet etching or dry etching can be used to remove the remaining portion of the phosphosilicate glass layer. Fig.10 As shown, the positive electrode 22 and the negative electrode 23 can be formed on the backlight side by screen printing or electroplating. The positive electrode 22 is in ohmic contact with the P-type region of the semiconductor substrate 11, and the negative electrode 23 is in ohmic contact with the N-type doped polysilicon layer 21.

[0102] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0103] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate, wherein the light-facing surface of the semiconductor substrate is a velvet surface; and a tunnel passivation layer and an N-type doped polysilicon layer are sequentially stacked on a local area of ​​a backlight surface of the semiconductor substrate along a thickness direction of the semiconductor substrate; the doping element in the N-type doped polysilicon layer includes phosphorus, and a thickness ratio of a portion of the N-type doped polysilicon layer located on an edge area of ​​the backlight surface to a portion of the N-type doped polysilicon layer located on a central area of ​​the backlight surface is greater than or equal to 1 and less than or equal to 1.2; Among them, the N-type doped polysilicon layer is formed by performing phosphorus diffusion treatment on the intrinsic amorphous silicon material layer. After the phosphorus diffusion treatment, a phosphosilicate glass layer is formed on the N-type doped polysilicon layer, and under the masking effect of the phosphosilicate glass layer, the light-facing surface is subjected to texturing treatment to form the velvet surface.

2. The back contact cell according to claim 1, characterized in that: The size uniformity of the suede structure on each area of ​​the light-facing surface is greater than or equal to 85% and less than 100%.

3. The back contact cell according to claim 1, characterized in that: The semiconductor substrate is a P-type semiconductor substrate; along a direction parallel to the backlight surface, the backlight surface of the semiconductor substrate has a P-type region that is alternately distributed with the stacked tunnel passivation layer and the N-type doped polysilicon layer.

4. The back contact cell according to claim 1, characterized in that: The thickness of the portion of the N-type doped polysilicon layer located on the edge region of the backlight surface is greater than or equal to 175 nm and less than or equal to 225 nm; and / or, The thickness of the portion of the N-type doped polysilicon layer located in the central area of ​​the backlight surface is greater than or equal to 150 nm and less than or equal to 200 nm.

5. The back contact battery according to any one of claims 1 to 4, characterized in that: The average doping concentration of impurities in the N-type doped polysilicon layer is greater than or equal to 3.5×10 20 / cm 3 , and less than or equal to 4.0×10 20 / cm 3 .

6. A photovoltaic module, characterized in that: include: A back contact battery as claimed in any one of claims 1 to 5.

7. A method for manufacturing a back contact battery, characterized in that: include: Providing a semiconductor substrate; A tunnel passivation material layer and an intrinsic amorphous silicon material layer are sequentially formed in a stacked manner on a backlight side of the semiconductor substrate along a thickness direction of the semiconductor substrate; Performing phosphorus diffusion treatment on the intrinsic amorphous silicon material layer to form an N-type doped polysilicon material layer from the intrinsic amorphous silicon material layer, and forming a phosphorus silicon glass layer on the N-type doped polysilicon material layer; The thickness ratio of the portion of the N-type doped polysilicon material layer located on the edge region of the backlight surface to the portion of the N-type doped polysilicon material layer located on the central region of the backlight surface is greater than or equal to 1 and less than or equal to 1.2; Under the masking action of the phosphorus-silicate glass layer, a texture treatment is performed on the light-facing surface of the semiconductor substrate so that a textured surface is formed on the light-facing surface; Patterning the phosphosilicate glass layer, and the stacked tunneling passivation material layer and N-type doped polysilicon material layer to form a tunneling passivation layer and an N-type doped polysilicon layer stacked on a local area of ​​the backlight surface; The remaining phosphosilicate glass layer is removed.

8. The method for manufacturing a back contact battery according to claim 7, characterized in that: The ambient pressure for forming the intrinsic amorphous silicon material layer is greater than or equal to 100 mTorr and less than or equal to 150 mTorr; and / or, The gas flow rate for forming the intrinsic amorphous silicon material layer is greater than or equal to 0.9 slm and less than or equal to 1.2 slm.

9. The method for manufacturing a back contact battery according to claim 7, characterized in that: After the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment, the phosphosilicate glass layer is subjected to patterning treatment only before the light-facing surface of the semiconductor substrate is subjected to texturing treatment under the masking effect of the phosphosilicate glass layer, so that the remaining part of the phosphosilicate glass layer is formed on a local area of ​​the N-type doped polysilicon material layer; Under the masking effect of the phosphosilicate glass layer, the light-facing surface of the semiconductor substrate is textured while the stacked tunnel passivation material layer and the N-type doped polysilicon material layer are patterned.

10. The method for manufacturing a back contact battery according to claim 7, characterized in that: Along the thickness direction of the semiconductor substrate, while forming an intrinsic amorphous silicon material layer on the backlight side of the semiconductor substrate, a plated amorphous silicon layer is formed on the side surface and part of the light-facing surface of the semiconductor substrate; The width of the formation area of ​​the plated amorphous silicon layer on the light-facing surface is greater than or equal to 0 and less than 10 mm; the width direction of the formation area is parallel to the radial direction of the semiconductor substrate; After the phosphorus diffusion treatment, the wrap-around amorphous silicon layer forms a wrap-around doped layer, and a wrap-around phosphorus silicon glass layer is formed on the wrap-around doped layer; After the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment, and before the light-facing surface of the semiconductor substrate is subjected to texturing treatment under the masking action of the phosphosilicate glass layer, the method for manufacturing the back contact battery further includes: removing the wrap-around phosphosilicate glass layer and the wrap-around doping layer.

11. The method for manufacturing a back contact battery according to any one of claims 7 to 10, characterized in that: The thickness of the phosphosilicate glass layer is greater than or equal to 60 nm and less than or equal to 65 nm; and / or, The average thickness of the intrinsic amorphous silicon material layer is H1, the average thickness of the phosphosilicate glass layer is H2, the average thickness of the N-type doped polysilicon material layer is H3, and 40% H2<H1-H3<60% H2.

12. The method for manufacturing a back contact battery according to any one of claims 7 to 10, characterized in that: The treatment conditions of the phosphorus diffusion treatment are: The deposition process temperature is greater than or equal to 850°C and less than or equal to 900°C; and / or, the deposition process environment pressure is greater than or equal to 150mbar and less than or equal to 200mbar; and / or, the deposition process phosphorus source pressure is greater than or equal to 250mbar and less than or equal to 450mbar; and / or, the deposition process nitrogen flow rate is greater than or equal to 1500sccm and less than or equal to 2000sccm; and / or, the deposition process oxygen flow rate is greater than or equal to 750sccm and less than or equal to 1000sccm; and / or, the post-oxidation process temperature is greater than or equal to 850°C and less than or equal to 900°C; and / or, the post-oxidation process oxygen flow rate is greater than or equal to 5000sccm and less than or equal to 10000sccm.

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