Digrf frame processing method and apparatus, computer device, and readable medium

Abstract

The present disclosure provides a DigRF frame processing method, comprising: receiving n first data, mapping the n first data to any one of m data channels, m and n are integers greater than 2, and n > m; performing clock domain conversion on the first data of each data channel to obtain second data; performing bit width conversion on the second data of each data channel to obtain third data, and buffering the third data; when the number of the third data buffered by the data channel reaches the data amount of a frame of data, performing framing according to each third data buffered by the data channel to obtain a DigRF data frame, and the data amount of a frame of data is the data amount of a frame of data corresponding to a preset load; and using a fixed load to perform framing, which maximizes the bandwidth utilization, simplifies the framing logic of the radio frequency chip and the baseband chip, saves the chip area and logic resources, improves the bandwidth utilization, and lowers the chip power consumption. The present disclosure also provides a DigRF frame processing device, a computer device and a readable medium.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of communication, in particular to a DigRF frame processing method and device, computer equipment and readable medium. BACKGROUND

[0002] Some existing baseband chip interface protocols use stream transmission, such as CPRI (Common Public Radio Interface) protocol, Aurora protocol and j204B protocol. Since such interface schemes do not support entering energy-saving shutdown in sleep or idle state, the chip energy consumption is high.

[0003] Some existing terminal chips also use packet transmission, such as DigRF (Digital Radio Frequency) V1.12 protocol. However, this interface protocol is only for GSM (Global System for Mobile communications) and does not have universality, and the fastest interface rate is only 52Mbit / s, which cannot meet the existing transmission requirements. SUMMARY

[0004] The present disclosure provides a DigRF frame processing method and device, computer equipment and readable medium.

[0005] In a first aspect, the present disclosure provides a DigRF frame processing method, comprising:

[0006] receiving n-way first data, and mapping each of the n-way first data to any one of m data channels, wherein m and n are integers greater than 2, and n > m;

[0007] performing clock domain conversion on the first data of each data channel to obtain second data;

[0008] performing bit width conversion on the second data of each data channel to obtain third data, and buffering the third data;

[0009] in a case where the number of the third data buffered in the data channel reaches the data amount of one frame of data, performing framing according to each of the third data buffered in the data channel to obtain a DigRF data frame, and the data amount of one frame of data is determined according to the number of preset loads and the number of physical channels.

[0010] In some embodiments, the n-way first data includes multiple modes.

[0011] In some embodiments, after buffering the third data, the method further comprises:

[0012] In the case of performing the mode switching, the third data currently buffered by each of the data channels is framed.

[0013] In some embodiments, the mode of the first data comprises one or any combination of the following:

[0014] New Radio, New Radio-Vehicle Radio Communication, Long Term Evolution, Long Term Evolution-Vehicle Radio Communication, Wideband Code Division Multiple Access.

[0015] In some embodiments, the load of the first data of various modes is the same.

[0016] In some embodiments, the number of the third data buffered by the data channel reaches the data amount of one frame of data by the following way:

[0017] In the m data channels, the number of the third data buffered by the data channel reaches the data amount of one frame of data by polling.

[0018] In some embodiments, the number of the preset load is 256 bytes.

[0019] In another aspect, the embodiments of the present disclosure also provide a DigRF frame processing device, comprising a channel mapping module, a clock domain conversion module, a bit width conversion module, a buffer module and a data processing module, the channel mapping module is used for receiving n-way first data, and mapping each of the n-way first data to any one of m data channels, wherein m and n are integers greater than 2, and n>m;

[0020] The clock domain conversion module is used for performing clock domain conversion on the first data of each of the data channels to obtain second data;

[0021] The bit width conversion module is used for performing bit width conversion on the second data of each of the data channels to obtain third data;

[0022] The buffer module is used for buffering the third data;

[0023] The data processing module is used for, in the case that the number of the third data buffered by the data channel reaches the data amount of one frame of data, framing the third data buffered by the data channel to obtain a DigRF data frame, and the data amount of one frame of data is determined according to a preset load and the number of physical channels.

[0024] In yet another aspect, the present disclosure also provides a computer device, comprising: one or more processors; a storage device having one or more programs stored thereon; and the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the DigRF frame processing method as described above.

[0025] In yet another aspect, the present disclosure also provides a computer readable medium having a computer program stored thereon, wherein the program, when executed, implements the DigRF frame processing method as described above.

[0026] The DigRF frame processing method provided by the present disclosure comprises: receiving n pieces of first data, mapping the n pieces of first data to any one of m data channels, m and n being integers greater than 2 and n > m; performing clock domain conversion on the first data of each data channel to obtain second data; performing bit width conversion on the second data of each data channel to obtain third data, and buffering the third data; when the number of the third data buffered by the data channel reaches the data amount of a frame of data, performing framing according to the third data buffered by the data channel to obtain a DigRF data frame, the data amount of a frame of data being the data amount of a frame of data corresponding to a preset load; the present disclosure adopts fixed load for framing, maximizes the bandwidth utilization, and compared with the variable load framing mode, the framing logic of the radio frequency chip and the baseband chip is simple, the chip area and logic resources are saved, and the bandwidth utilization is improved, in the case of transmitting the same data amount, the link is in the idle or dormant state for a longer time, and the chip power consumption is lower. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 DigRF frame processing flow provided by the present disclosure Figure 1 ;

[0028] Figure 2 DigRF frame format provided by the present disclosure

[0029] Figure 3 Format of first data provided by the present disclosure

[0030] Figure 4 Format of third data provided by the present disclosure

[0031] Figure 5 DigRF frame processing flow provided by the present disclosure Figure 2 ;

[0032] Figure 6 Module diagram of DigRF frame processing device provided by the present disclosure

[0033] Figure 7 A structural schematic diagram of a DigRF frame processing apparatus provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0034] In the following, example embodiments will be described more fully with reference to the accompanying drawings, in which example embodiments can, however, be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0035] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0037] The embodiments described herein can be described with reference to plan views and / or cross-sectional views by virtue of the ideal schematic nature of the drawings. Accordingly, the example illustrations are not necessarily drawn to scale and certain aspects can be shown exaggerated in the drawings. Accordingly, the embodiments are not limited to the examples illustrated in the drawings, but the configurations of the components formed on the basis of the manufacturing process are included in the embodiments. Therefore, the regions illustrated in the drawings have a schematic property, and the shape of the regions shown in the drawings illustrates a specific shape of the regions of the elements, but is not intended to be limiting.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0039] An embodiment of the present disclosure provides a DigRF frame processing method, applied to a DigRF frame processing apparatus, as shown in Figure 1 The method comprises the following steps:

[0040] In step 11, n pieces of first data are received, and each piece of the first data is mapped to any one of m data channels.

[0041] m and n are integers greater than 2, and n > m. In the embodiment of the present disclosure, n = 12, m = 8, that is, there are 12 first data inputs DigRF frame processing devices, each of the 12 first data is mapped to any one of the 8 data channels by the channel mapping module (CH_MAP) of the DigRF frame processing device, ensuring that each first data enters a data channel.

[0042] Figure 6 Fig. 1 is a structural schematic diagram of a DigRF frame processing device, and Fig. 2 is a structural schematic diagram of a channel mapping module (CH_MAP) of the DigRF frame processing device. Figure 7 As shown in Fig. 2, the channel mapping module (CH_MAP) can select a data selector, and 12 first data (i_dfe_data0-i_dfe_data1) are input to the corresponding 8 data selectors (MUX1-MUX8) of the 8 data channels, respectively. After selection by the 8 data selectors, the above-mentioned 12 first data enter the 8 data channels, respectively.

[0043] Step 12: performing clock domain conversion on the first data of each data channel to obtain second data.

[0044] In the embodiment of the present disclosure, there are two clock domains, clk_tx_sample* and clk_tx_work, respectively. In each of the 8 data channels, the clock domain conversion is performed by a cross-clock fifo to obtain the second data.

[0045] Step 13: performing bit width conversion on the second data of each data channel to obtain third data, and buffering the third data.

[0046] After the antenna signal is subjected to analog-digital conversion, the precision is 12 bits, that is, the bit width (precision) of the second data is 12 bits. In this step, for each data channel, the 12-bit bit width second data is converted to 8-bit bit width third data by bit width conversion operation, and the third data is buffered in the fifo buffer of the corresponding data channel. For example, the bit width of the second data of 2 channels is 48 bits, and the bus configuration is 1 physical channel. When 6 data are buffered in the fifo, the data is converted to 8-bit bit width data.

[0047] Step 14: when the number of the third data buffered in the data channel reaches the data amount of a frame data, the DigRF data frame is obtained according to each third data buffered in the data channel. The data amount of a frame data is determined according to the number of preset loads and the number of physical channels.

[0048] The maximum value of the amount of data cached by the fifo buffer in each data channel is the amount of data of a frame of data corresponding to the preset load. Under normal circumstances, that is, when the channel is not closed, when the amount of data cached in the fifo buffer reaches the upper limit of storage, that is, the amount of data of a frame of data, the fifo buffer sends an indication signal to the digrfv4_tx_dlc_read module in the DigRF frame processing device to indicate that the digrfv4_tx_dlc_read module reads all the third data from the fifo buffer, and the digrfv4_tx_dlc_read module frames all the read third data to obtain a DigRF data frame.

[0049] The amount of data of a frame of data corresponding to the preset load is determined according to the number of preset loads and the number of physical channels. For example, the number of preset loads is 256 bytes, in the case of 1 physical channel, the digrfv4_tx_dlc_read module reads 256 third data at a time; in the case of 2 physical channels, the digrfv4_tx_dlc_read module reads 126 third data at a time, and so on. The embodiment of the present disclosure supports up to 4 physical channels.

[0050] The DigRF basic frame format is as shown in Figure 2 The DigRF basic frame format is as shown in

[0051] In the embodiment of the present disclosure, each data channel has a fixed load, that is, the number of loads of each data channel is the same. Compared with the variable load framing method, the framing scheme using the fixed load has simpler logic related to framing between the radio frequency chip and the baseband chip, saving chip area and logic resources. Moreover, the framing scheme with fixed load has high bandwidth utilization, shorter time for transmitting the same amount of data, longer time for the chip to enter an idle or sleep state, and lower power consumption. The chip can enter an idle or sleep state through the EOT of the DigRF v4 frame tail to achieve the purpose of energy saving and power reduction.

[0052] The method for processing DigRF frames provided by the embodiments of the present disclosure includes: receiving n pieces of first data, mapping the n pieces of first data to any one of m data channels, m and n are integers greater than 2, and n > m; performing clock domain conversion on the first data of each data channel to obtain second data; performing bit width conversion on the second data of each data channel to obtain third data, and buffering the third data; when the number of the third data buffered by the data channel reaches the data amount of a frame of data, performing framing according to each third data buffered by the data channel to obtain a DigRF data frame, and the data amount of a frame of data is the data amount of a frame of data corresponding to a preset load; the embodiments of the present disclosure adopt fixed load for framing, which maximizes the bandwidth utilization, compared with the variable load framing mode, the framing logic of the radio frequency chip and the baseband chip is simple, the chip area and logic resources are saved, and moreover, the bandwidth utilization is improved, in the case of transmitting the same data amount, the link is in an idle or dormant state for a longer time, and the chip power consumption is lower.

[0053] In some embodiments of the present disclosure, the n pieces of first data include multiple formats. The first data of various formats is input into the DigRF frame processing device according to specific application scenarios, and the DigRF frame processing device performs data channel mapping according to software configuration.

[0054] In the related art, the description of the number of loads in the DigRF protocol determines the data amount in a frame by DLC_IQ_NUM, determines the data bit width by DLC_IQ_LEN, and dynamically configures according to the transmission requirements of different formats. The greater the number of loads, the higher the effective line rate. In the case of the same data amount, the higher the effective line rate, the longer the link is in an idle or dormant state, and at this time, the power consumption of the chip is also smaller. Therefore, when many modems are integrated in the system, and the application scenario is complex, it is necessary to consider whether to use the variable load framing scheme described in the protocol or the fixed load framing scheme. At present, the applications of the DigRF protocol are related to frame sending processing, retransmission frame identification or NEST mechanism processing on the receiving side, and these schemes involve fewer data formats, the use scenarios are relatively simple, and the number of loads in a frame of data is not involved in the interface.

[0055] Therefore, it can be seen that the related art has applications for the DigRF protocol, but does not discuss the framing scheme of the load. The variable load framing scheme in the standard protocol is not suitable for complex transmission requirements, and cannot maximize the reduction of chip power consumption. The embodiments of the present disclosure provide an interface scheme based on DigRF fixed load, which adopts fixed load framing for the transmission requirements of data of various formats, maximizes the utilization of bandwidth, saves energy when the link is in an idle or dormant state, and reduces power consumption.

[0056] In some embodiments, the first data is of one or any combination of the following standards: NR (New Radio), NR_V2X (New Radio_Vehicle-to-everything wireless communication), LTE (Long Term Evolution), LTE_V2X (Long Term Evolution_Vehicle-to-everything wireless communication), WCDMA (Wideband Code Division Multiple Access).

[0057] The channel mapping module (CH_MAP) in the DigRF frame processing device can receive first data sent by one or several of the following modems: NR modem, NR_V2X modem, LTE modem, LTE_V2X, WCDMA modem. In the case of multiple standards of first data, 12 channels of first data of various standards are mapped into 8 data channels, and the first data input format is as shown in Table 1:

[0058] Table 1

[0059]

[0060] Among them, 3 carriers (CC) of LTE can carry data services, and the design can cover the demand. The specific mapping of 12 channels of first data to which data channel can be configured by a register.

[0061] Figure 3 The format diagram of the first data provided by the embodiment of the present disclosure is shown in Table 2 and Table 3, wherein the first data format of 2 channels (2T) and 4 channels (4T) is as shown in Table 2: Figure 3 The amount of 1 beat data of 2 channels (2T) is less than that of 4 channels (4T).

[0062] Figure 4 The format diagram of the third data provided by the embodiment of the present disclosure is shown in Table 4, wherein the format of the third data output by 1 physical channel is as shown in Table 4: Figure 4 Among them, data_vld is valid (high level) when header_vld is invalid (low level), and header_vld is valid (high level) when data_vld is invalid (low level).

[0063] In some embodiments, as shown in Table 5, after buffering the third data (i.e., step 13), the DigRF frame processing method further includes the following steps: Figure 5

[0064] Step 14', in the case of standard switching, the third data currently buffered by each data channel is grouped into frames.

[0065] ​If the channel is closed, it means that an exception occurs, and the mode switching is performed. In this case, the third data currently buffered in the fifo buffer can be read without waiting for the amount of data buffered in the fifo buffer in the data channel to reach the upper limit of storage (i.e., the amount of data of one frame of data), that is, the third data in the fifo buffer is read out regardless of the amount of the third data in the fifo buffer, and the third data read out is used for framing.

[0066] In some embodiments, the first data of various modes has the same load.

[0067] In some embodiments, the amount of the third data buffered in the data channel reaches the amount of data of one frame of data by polling the m data channels to determine whether the amount of the third data buffered in the data channel reaches the amount of data of one frame of data. That is, the m data channels are polled, and whether the amount of the third data buffered in the fifo buffer in the current data channel reaches the amount of data of one frame of data is determined. If yes, the current data channel is framed to obtain a DigRF data frame of the data channel. If no, whether the amount of the third data buffered in the fifo buffer in the next data channel reaches the amount of data of one frame of data is determined, and so on.

[0068] In some embodiments, the preset amount of load is 256 bytes. In the embodiment of the present disclosure, the amount of fixed load is the maximum load amount 256 bytes specified by the protocol. In this way, the bandwidth utilization is the highest, the time for transmitting the same amount of data is shorter, the time for the chip to enter the idle and sleep state is longer, and the power consumption is smaller.

[0069] The embodiment of the present disclosure can be applied to a high-speed serial interface with small delay and connected by electrical signals. In a mobile terminal product, the radio frequency chip and the terminal chip usually use such an interface to perform uplink and downlink data interaction. The embodiment of the present disclosure can also be applied to a baseband processing unit or an active antenna processing unit, for example, two board cards in a baseband processing unit perform cell data scheduling processing through a high-speed serial interface.

[0070] Based on the same technical concept, the embodiment of the present disclosure also provides a DigRF frame processing device. Figure 6 A module schematic diagram of the DigRF frame processing device is shown in FIG. 2. Figure 7 A structure schematic diagram of the DigRF frame processing device is shown in FIG. 3.

[0071] As shown in FIG. 2, the DigRF frame processing device includes a data channel, a fifo buffer, a mode switching module, a framing module, and a data output module. Figure 6As shown, the DigRF frame processing apparatus comprises a channel mapping module 101, a clock domain conversion module 102, a bit width conversion module 103, a cache module 104 and a data processing module 105. The channel mapping module 101 is configured to receive n pieces of first data, and map each piece of the first data to any one of m data channels, where m and n are integers greater than 2, and n > m.

[0072] The clock domain conversion module 102 is configured to perform clock domain conversion on the first data of each data channel to obtain second data.

[0073] The bit width conversion module 103 is configured to perform bit width conversion on the second data of each data channel to obtain third data.

[0074] The cache module 104 is configured to cache the third data.

[0075] The data processing module 105 is configured to, when the amount of the third data cached in the data channel reaches the data amount of a frame of data, perform framing on each piece of the third data cached in the data channel to obtain a DigRF data frame, where the data amount of the frame of data is determined according to the number of preset loads and the number of physical channels.

[0076] In combination Figure 6 and Figure 7 As shown, the channel mapping module 101 is a data selector MUX1-MUX8, the clock domain conversion module 102 is a cross-clock fifo, the bit width conversion module 103 is a digrfv4_tx_dlc_splicing module, the cache module 104 is a data cache fifo, and the data processing module 105 is a digrfv4_tx_dlc_read module.

[0077] In some embodiments, the n pieces of first data comprise multiple formats.

[0078] In some embodiments, the data processing module 105 is further configured to, after the cache module 104 caches the third data, perform framing on the third data currently cached in each data channel in the case of format switching.

[0079] In some embodiments, the formats of the first data comprise one or any combination of the following:

[0080] New Radio (NR), New Radio for Vehicle Radio Communication (NR_V2X), Long Term Evolution (LTE), Long Term Evolution for Vehicle Radio Communication (LTE_V2X), Wideband Code Division Multiple Access (WCDMA).

[0081] In some embodiments, the loads of the first data in various formats are the same.

[0082] In some embodiments, the data processing module 105 is configured to determine that the amount of the third data stored in the data channel buffer reaches the data amount of one frame of data by polling the m data channels to determine that the amount of the third data stored in the data channel buffer reaches the data amount of one frame of data.

[0083] In some embodiments, the preset load amount is 256 bytes.

[0084] The embodiments of the present disclosure further provide a computer device, which comprises one or more processors and a storage device; wherein the storage device stores one or more programs; and when the one or more programs are executed by the one or more processors, the one or more processors implement the DigRF frame processing method provided in the foregoing embodiments.

[0085] The embodiments of the present disclosure further provide a computer readable medium, which stores a computer program; and when the computer program is executed, the DigRF frame processing method provided in the foregoing embodiments is implemented.

[0086] Those of ordinary skill in the art will realize and understand, all or certain steps in the methods disclosed above and the functional modules / units in the devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Certain physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, it is well known to those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

[0087] Example embodiments have been disclosed herein and, although the use of specific terms is expressly used herein, they are intended in a generic sense only and, unless expressly stated to the contrary, are not intended to limit the application of the present disclosure. In some instances, features, characteristics or aspects described in connection with a particular embodiment can be used, alone or in combination with other embodiments, and in conjunction with the description of other embodiments, unless expressly stated to the contrary. Accordingly, one of ordinary skill in the art will recognize that the various forms and details of the application can be varied without departing from the scope of the present application as set forth in the appended claims.

Claims

1. A method of DigRF frame processing, the method comprising: The method comprises: receiving n pieces of first data, and mapping each piece of the first data to any one of m data channels, wherein m and n are integers greater than 2, and n > m; performing clock domain conversion on the first data of each data channel to obtain second data; performing bit width conversion on the second data of each data channel to obtain third data, and buffering the third data; in a case where the number of the third data buffered by the data channels reaches the data amount of one frame of data, performing framing on each piece of the third data buffered by the data channels to obtain a DigRF data frame, and the data amount of one frame of data is determined according to a preset load amount and a number of physical channels.

2. The method of claim 1, wherein, The n pieces of first data include multiple formats.

3. The method of claim 2, wherein, After buffering the third data, the method further comprises: in a case where format switching is performed, performing framing on the third data currently buffered by each data channel.

4. The method of claim 2, wherein, The format of the first data includes one or any combination of the following: New Radio (NR), New Radio-Vehicle-to-Everything (NR-V2X), Long Term Evolution (LTE), Long Term Evolution-Vehicle-to-Everything (LTE-V2X), Wideband Code Division Multiple Access (WCDMA).

5. The method of claim 2, wherein, The loads of the first data in various formats are the same.

6. The method of claim 1, wherein, The number of the third data buffered by the data channels reaches the data amount of one frame of data in the following manner: In the m data channels, the number of the third data buffered by the data channels reaches the data amount of one frame of data in a polling manner.

7. The method according to any one of claims 1 to 6, wherein The preset load amount is 256 bytes.

8. A DigRF frame processing apparatus, characterized by: The device comprises a channel mapping module, a clock domain conversion module, a bit width conversion module, a buffering module, and a data processing module. The clock domain conversion module is configured to perform clock domain conversion on the first data of each data channel to obtain second data. The bit width conversion module is configured to perform bit width conversion on the second data of each data channel to obtain third data. The buffering module is configured to buffer the third data. The data processing module is configured to, in a case where the number of the third data buffered by the data channels reaches the data amount of one frame of data, perform framing on each piece of the third data buffered by the data channels to obtain a DigRF data frame, and the data amount of one frame of data is determined according to a preset load amount and a number of physical channels.

9. A computer device, comprising: one or more processors; a storage device having one or more programs stored thereon; when the one or more programs are executed by the one or more processors, the one or more processors implement the DigRF frame processing method according to any one of claims 1-7.

10. A computer readable medium having stored thereon a computer program, wherein, The program is executed to implement the DigRF frame processing method according to any one of claims 1-7.

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