An ultrasonic phased array focusing control device and control system

Abstract

The application discloses an ultrasonic phased array focusing control device and a control system. The ultrasonic phased array focusing control device comprises a host computer, a switch signal control module, a lower computer, a DAC module and a phased array ultrasonic transducer; the host computer is connected with the switch signal control module, and the switch signal control module is connected with the lower computer; the host computer is used for sending pulse train length and repetition frequency data to the switch signal control module; the switch signal control module is used for generating a switch level signal according to the pulse train length and repetition frequency data and transmitting the switch level signal to the lower computer; the lower computer is connected with the DAC module, the DAC module is connected with the phased array ultrasonic transducer, the lower computer is used for controlling the DAC module to convert the switch level signal into a sinusoidal signal and transmitting the sinusoidal signal to the phased array ultrasonic transducer, and the phased array ultrasonic transducer is used for converting the sinusoidal signal into an ultrasonic signal for transcranial magnetic acoustic stimulation. The application has the advantages of low complexity, high synchronization, small error and high focusing resolution.

Description

Technical Field

[0001] This invention relates to the field of medical device technology, and in particular to an ultrasonic phased array focusing control device and control system. Background Technology

[0002] Transcranial magnetic acoustic stimulation (TMS), as a non-invasive neuromodulation technique, offers advantages such as good stimulation focusing, high stimulation resolution, and ease of deep stimulation. To generate a focused ultrasound field within the brain region and control its precision, a precise and adjustable focusing method is required, typically achieved using an ultrasound phased array. An ultrasound phased array integrates multiple ultrasound transducers (e.g., 8×8) to form an array, and controls the phase difference of the ultrasound waves (excitation signal is a sine wave) by adjusting the trigger interval of different transducers, thereby achieving focusing at a specific point in space. Furthermore, since this device is used for stimulation therapy, the required focal point is not fixed depending on the patient and the symptoms targeted. Therefore, the equipment used to control the sinusoidal signal triggering needs to possess capabilities such as parallel control, high precision, flexible adjustable trigger delay range, and easy adjustment of focusing parameters.

[0003] Currently, the Vera Sonics system is commonly used for transcranial stimulation ultrasound generation. This is a highly integrated system for controlling multi-channel (up to 128 to 256 channels) ultrasound generation, which mainly uses FPGA to generate and control multiple ultrasound signals. However, it has the following problems: 1) When stimulation and focusing parameters need to be changed, MATLAB scripts must be used to reprogram each FPGA slave device, which is complex and inefficient; 2) The error accuracy of inter-channel delay is low, about 50 nanoseconds, which ultimately leads to the focusing resolution not meeting the requirements. Summary of the Invention

[0004] This invention provides an ultrasonic phased array focusing control device and control system, which reduces the complexity of device use, improves working efficiency, and has the advantages of strong synchronization, small error and high focusing resolution.

[0005] According to one aspect of the present invention, an ultrasonic phased array focusing control device is provided, the ultrasonic phased array focusing control device comprising: a host computer, a switch signal control module, a slave computer, a DAC module, and a phased array ultrasonic transducer;

[0006] The host computer is connected to the switch signal control module, and the switch signal control module is connected to the slave computer. The host computer is used to send pulse train length and repetition frequency data to the switch signal control module. The switch signal control module is used to generate a switch level signal according to the pulse train length and repetition frequency data and transmit it to the slave computer.

[0007] The lower-level machine is connected to the DAC module, and the DAC module is connected to the phased array ultrasonic transducer. The lower-level machine is used to control the DAC module to convert the switching level signal into a sinusoidal signal and transmit it to the phased array ultrasonic transducer. The phased array ultrasonic transducer is used to convert the sinusoidal signal into a transcranial magnetic acoustic stimulation ultrasonic signal.

[0008] Optionally, the ultrasonic phased array focusing control device further includes a multi-channel power amplifier connected between the DAC module and the phased array ultrasonic transducer. The multi-channel power amplifier is used to amplify the sinusoidal signal and transmit it to the phased array ultrasonic transducer.

[0009] Optionally, the switch signal control module includes a ZYNQ chip, a first DAC unit, and a second DAC unit, wherein the ZYNQ chip is connected to the first DAC unit and the second DAC unit;

[0010] The lower-level machine includes a first FPGA and a second FPGA, the first FPGA being connected to the first DAC unit, and the second FPGA being connected to the second DAC unit.

[0011] Optionally, the ZYNQ chip includes: a processing unit and a programmable logic control unit;

[0012] The processing unit is connected to the programmable logic control unit, which is connected to the host computer, the first DAC unit, and the second DAC unit.

[0013] Optionally, both the first FPGA and the second FPGA include: a phase-locked loop clock divider module, an output delay module, and a trigger sequence module;

[0014] The DAC module includes multiple DACs, and the phase-locked loop clock divider module is connected to the multiple DACs. The phase-locked loop clock divider module is used to increase the output frequency of the multiple DACs.

[0015] The output delay module and the trigger sequence module are connected to the switch signal control module.

[0016] Optionally, the switch signal control module further includes an I / O interface, which is connected to the programmable logic control unit, the first FPGA, and the second FPGA.

[0017] Optionally, the pulse length of the switching level signal is 200μs-500μs, and the repetition frequency of the switching level signal is 1Hz-2kHz.

[0018] Optionally, the host computer communicates with the switch signal control module via a serial port, and the slave computer communicates with the switch signal control module via the I / O interface.

[0019] Optionally, the operating modes of the host computer include: manual input mode or automatic input mode.

[0020] According to another aspect of the present invention, an ultrasonic phased array focusing control system is provided, which includes the ultrasonic phased array focusing control device described in any of the preceding aspects.

[0021] The technical solution of this invention involves a lower-level device using an FPGA to control multiple DACs to generate multiple sinusoidal signals. This achieves high versatility, interactivity, and program flexibility while ensuring extremely low time errors between the excitation of signals from each channel, thus meeting the required focusing resolution. The upper-level device communicates with the switch signal control module via a serial port for inter-chip communication and parameter transfer, reducing the complexity of reprogramming for each parameter change. Due to the heterogeneous characteristics of its Zynq chip integrating ARM and FPGA, the upper-level device offers multiple control solutions and allows users to run a Linux Qt GUI on the chip, enabling independent operation without a PC. In summary, this invention solves the problems of existing devices requiring MATLAB scripts and individual reprogramming of each FPGA lower-level device when stimulation or focusing parameters need to be changed, resulting in complexity and low efficiency; and the low accuracy of inter-channel delay errors (approximately 50 nanoseconds), ultimately leading to insufficient focusing resolution.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of an ultrasonic phased array focusing control device according to an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the structure of another ultrasonic phased array focusing control device provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of the structure of another ultrasonic phased array focusing control device provided in an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of a focusing principle provided according to an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of the program structure of a lower-level machine according to an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of a user interface provided according to an embodiment of the present invention. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] Figure 1 This is a schematic diagram of an ultrasonic phased array focusing control device according to an embodiment of the present invention. (Refer to...) Figure 1This invention provides an ultrasonic phased array focusing control device, which includes: a host computer 10, a switch signal control module 20, a slave computer 30, a DAC module 40, and a phased array ultrasonic transducer 50. The host computer 10 is connected to the switch signal control module 20, and the switch signal control module 20 is connected to the slave computer 30. The host computer 10 is used to send pulse train length and repetition frequency data to the switch signal control module 20. The switch signal control module 20 is used to generate a switch level signal according to the pulse train length and repetition frequency data and transmit it to the slave computer 30. The slave computer 30 is connected to the DAC module 40, and the DAC module 40 is connected to the phased array ultrasonic transducer 50. The slave computer 30 is used to control the DAC module 40 to convert the switch level signal into a sinusoidal signal and transmit it to the phased array ultrasonic transducer 50. The phased array ultrasonic transducer 50 is used to convert the sinusoidal signal into a transcranial magnetic acoustic stimulation (TMS) ultrasonic signal.

[0033] Specifically, the host computer 10 and the slave computer 30 refer to computer devices at different levels in a distributed system. The host computer 10 typically refers to a higher-level computer device, usually a desktop computer, server, or embedded computer. It is responsible for controlling and managing the entire system, collecting and processing data, and executing complex algorithms and logical operations. The host computer 10 usually runs software programs written in high-level languages, providing a user-friendly graphical interface so that users can interact with the system. The slave computer 30 typically refers to a lower-level computer device, usually a microcontroller, single-chip microcomputer, FPGA, sensor, etc. It is responsible for performing simple control tasks, collecting sensor data and transmitting it to the host computer 10, or executing instructions sent by the host computer 10. The slave computer 30 typically uses programs written in low-level languages ​​and can directly interact with the hardware. In many distributed systems, the host computer 10 and the slave computer 30 communicate through a communication protocol so that the host computer 10 can remotely control and monitor the slave computer 30 and obtain real-time data and status information from it.

[0034] For the generation of the switch-level signal, the host computer 10 and the switch signal control module 20 are the main components. The host computer 10 and the switch signal control module 20 are connected via a UART serial port. The UART serial port is used to transmit pulse length and repetition frequency data. The output of the switch signal control module 20 is connected to a 2-channel DAC. Optionally, the pulse length of the switch-level signal is 200μs-500μs, and the repetition frequency of the switch-level signal is 1Hz-2kHz. The switch signal control module 20 generates switch-level signals with pulse lengths of 200μs to 500μs and repetition frequencies of 1Hz to 2kHz.

[0035] The main component for generating the sinusoidal signal is the lower-level machine 30, which can be multiple FPGAs. The input to the lower-level machine 30 is a switching level signal, and its output is connected to the DAC module 40. The DAC module 40 can be a DAC, DDS, oscillation circuit, etc. For example, the DAC module 40 can have eight DACs. The FPGA pins are connected to and control multiple DACs, and the DACs convert the sinusoidal sampling data stored in the FPGA's ROM into sinusoidal signals. Finally, these sinusoidal signals are converted by the phased-array ultrasonic transducer 50 to obtain the ultrasonic signal used for transcranial magnetic acoustic stimulation.

[0036] The focusing of the ultrasound signal is also mainly achieved by the lower-level computer. This requires the ultrasound signals generated by the 50 different phased-array ultrasound transducers to superimpose at the focusing position. Since the frequency of the ultrasound directly depends on the generated sinusoidal signal, the solution is simply to superimpose the sinusoidal signals connected to each transducer. Based on the actual needs of transcranial magnetic acoustic stimulation (TMAS), the main function of this ultrasound phased-array focusing control device is to control the generation of multi-channel sinusoidal signals with pulse train widths of 200μs to 500μs and repetition frequencies of 1Hz to 2kHz; enabling the excited ultrasound signal to be focused at a depth of 4-8cm and achieving a spatial resolution of less than 3mm.

[0037] The switch signal control module 20 can consist of a ZYNQ chip and at least two DACs. Leveraging the ZYNQ chip's integration of Arm and FPGA, it employs and is compatible with two host computer control methods: PC-side control and ZYNQ on-chip interface control, adapting to a wider range of working conditions and environments. The slave device 30 uses the FPGA to control the multiple DACs in the DAC module 40 to generate multiple sinusoidal signals and allows configuration of focus parameters via serial ports and I / O ports. Furthermore, since the DACs can reproduce other signals, it can quickly adapt to generating other excitation signals such as square waves and triangle waves. Simultaneously, because different chips handle switch control and focus control separately, when more signals need to be controlled simultaneously, the number of slave devices can be directly increased in the system, and the control code remains compatible.

[0038] The ultrasonic phased array focusing control device is a control and focusing device for transcranial sinusoidal ultrasonic stimulation. Each module in the device is independent, controllable, and programmable, with strong expandability. It also utilizes the high-efficiency parallel working capability of FPGA, giving the device advantages such as strong synchronization, small error, and high focusing resolution.

[0039] The technical solution of this invention involves a lower-level device using an FPGA to control multiple DACs to generate multiple sinusoidal signals. This achieves high versatility, interactivity, and program flexibility while ensuring extremely low time errors between the excitation of signals from each channel, thus meeting the required focusing resolution. The upper-level device communicates with the switch signal control module via a serial port for inter-chip communication and parameter transfer, reducing the complexity of reprogramming for each parameter change. Due to the heterogeneous characteristics of its Zynq chip integrating ARM and FPGA, the upper-level device offers multiple control solutions and allows users to run a Linux Qt GUI on the chip, enabling independent operation without a PC. In summary, this invention solves the problems of existing devices requiring MATLAB scripts and individual reprogramming of each FPGA lower-level device when stimulation or focusing parameters need to be changed, resulting in complexity and low efficiency; and the low accuracy of inter-channel delay errors (approximately 50 nanoseconds), ultimately leading to insufficient focusing resolution.

[0040] Figure 2 This is a schematic diagram of another ultrasonic phased array focusing control device according to an embodiment of the present invention, with reference to... Figure 2 Optionally, the ultrasonic phased array focusing control device also includes a multiplexer 60, which is connected between the DAC module 40 and the phased array ultrasonic transducer 50. The multiplexer 60 is used to amplify the sinusoidal signal and transmit it to the phased array ultrasonic transducer 50.

[0041] Specifically, the analog sinusoidal signal is amplified by the multi-channel power amplifier 60 and then connected one-to-one with the phased array ultrasound transducer 50 to obtain an ultrasound signal for transcranial magnetoacoustic stimulation.

[0042] Figure 3 This is a schematic diagram of another ultrasonic phased array focusing control device according to an embodiment of the present invention, with reference to... Figure 3 Optionally, the switch signal control module 20 includes a ZYNQ chip 21, a first DAC unit 22, and a second DAC unit 23, with the ZYNQ chip 21 connected to the first DAC unit 22 and the second DAC unit 23; the lower-level machine 30 includes a first FPGA 31 and a second FPGA 32, with the first FPGA 31 connected to the first DAC unit 22 and the second FPGA 32 connected to the second DAC unit 23.

[0043] Specifically, the FPGA model can be INTEL Altera Cyclone IV EP4CE10, which mainly generates sinusoidal signals through a multi-channel DAC. The first FPGA 31 and the second FPGA 32 control the parallel low-latency error output of the multi-channel DAC, respectively. The pins of the first FPGA 31 and the second FPGA 32 are connected to and control the multi-channel DAC. The function of the DAC is to convert the sinusoidal sampling data stored in the ROM of the first FPGA 31 and the second FPGA 32 into sinusoidal signals.

[0044] Continue to refer to Figure 3 Optionally, the ZYNQ chip 21 includes a processing unit 211 and a programmable logic control unit 212; the processing unit 211 is connected to the programmable logic control unit 212, and the programmable logic control unit 212 is connected to the host computer 10, the first DAC unit 22, and the second DAC unit 23.

[0045] Specifically, the ZYNQ chip 21 consists of two main parts: a processing unit 211 (Processing System, PS) based on a dual-core ARM Cortex-A9 core, and a programmable logic control unit 212 (PL) equivalent to an FPGA. The host computer 10 and the development board equipped with the Zynq7000 chip use the processing unit 211 as the main controller, while the programmable logic control unit 212 using the Zynq chip constitutes the module for generating switching level signals.

[0046] Continue to refer to Figure 3 Optionally, the switch signal control module 20 also includes an IO interface 24, which is connected to the programmable logic control unit 212, the first FPGA 31, and the second FPGA 32.

[0047] Continue to refer to Figure 3 Optionally, the host computer 10 communicates with the switch signal control module 20 via a serial port, and the slave computer 30 communicates with the switch signal control module 20 via an I / O interface 24.

[0048] The ultrasonic phased array focusing control device is a multi-channel sinusoidal signal generation and focusing control device based on FPGA and embedded system. This device can be divided into the following parts:

[0049] 1) Trigger Signal Control Section (Switch Signal Control Module): By default, the host computer does not generate a trigger signal, i.e., it is in standby mode, but parameter settings can still be performed. After the pulse train length and repetition frequency data are input to the host computer via the UART serial port, a write enable signal will be generated simultaneously according to the program, converting the data stored in the on-chip registers into actual parameters, and starting to generate the required trigger signal to control the startup or shutdown of the slave device. When there is more than one slave device, it can be triggered separately using another DAC.

[0050] 2) Focusing control section:

[0051] Figure 4 This is a schematic diagram of a focusing principle provided according to an embodiment of the present invention, for reference. Figure 4 Taking two transducers in a phased array as an example, if a focal point P(x, y, z) is defined, then the ultrasonic waves generated by transducers A (x1, y1, z1) and B (x2, y2, z2) need to superimpose waveforms at point P. Since the frequency of the ultrasonic waves directly depends on the generated sinusoidal signal, the sinusoidal signals connected to the two channels of transducers A and B need to be superimposed. This embodiment uses a method of controlling the trigger time to control the phase difference between the channels, thereby controlling the ultrasonic focusing. Therefore:

[0052] Distance between A and P

[0053] Distance between B and P

[0054] Suppose that the speed of ultrasound transmission in a certain medium is v, and d1>d2, then transducer A needs to travel earlier than transducer B. trigger.

[0055] Figure 5 This is a schematic diagram of the program structure of a lower-level machine according to an embodiment of the present invention, with reference to... Figure 5 Optionally, both the first FPGA and the second FPGA include: a phase-locked loop clock divider module, an output delay module, and a trigger sequence module; the DAC module includes multiple DACs, the phase-locked loop clock divider module is connected to the multiple DACs, and the phase-locked loop clock divider module is used to increase the output frequency of the multiple DACs; the output delay module and the trigger sequence module are connected to the switch signal control module.

[0056] Specifically, the inputs in the lower-level machine are divided into two types: when directly controlled by the upper-level machine, the input is the UART serial port; when connected to the ZYNQ chip, the input is the I / O port (which also functions as a serial port). The first and second FPGAs internally contain output delay modules and trigger sequence modules, with parameters input through the same serial port or I / O port. The phase-locked loop (PLL) clock divider module is used to obtain a higher DAC output frequency, improving focusing accuracy; the parameters of the PLL clock divider module are not set via serial port or I / O port input.

[0057] To address the issue of reusing the same input, a mode selection module was added to the lower-level device, with mode switching via on-chip buttons. The channel delay input consists of seven 8-bit delay values, corresponding to the clock interval between each DAC trigger. The trigger sequence input consists of eight 8-bit values, indicating the trigger order of each DAC channel (e.g., inputting 8, 7, 6, ..., 1 in sequence corresponds to DAC1 being the 8th trigger and DAC8 being the first).

[0058] By default, the DAC connected to the lower-level machine starts working when the Trigger signal is high, generating a 500kHz sine wave signal. The default trigger delay between channels is 10 clock cycles, and they are triggered sequentially from DAC1 to DAC8. At the same time, the mode selection signal is 0, ready to receive channel delay data. After writing 7 sets of delayed data to the serial port, a write enable signal is generated, and the registered data is written. When the next Trigger signal arrives, each channel will trigger sequentially with the set delay. Pressing the button on the lower-level machine changes the mode selection signal to 1, at which point the trigger sequence data can be received. After writing 8 sets of sequential data to the serial port, a write enable signal is also generated. When the next Trigger arrives, each channel will trigger in the order of input.

[0059] Figure 6 This is a schematic diagram of a user interface provided according to an embodiment of the present invention, with reference to... Figure 6 Optionally, the host computer's operating modes include: manual input mode or automatic input mode.

[0060] Specifically, the user interface has two modes: manual input mode and automatic input mode. Taking PC control as an example: In manual mode, users can directly input hexadecimal data into the serial port through the interface, sending the corresponding data in sequence to control the trigger signal and the sinusoidal signals of each channel. This mode is more convenient for debugging; in automatic mode, such as Figure 5As shown, the user now inputs actual values ​​such as the pulse train length, repetition frequency, and focal point coordinates. The program then calculates the required serial port output data and output count, and automatically sends this data. Therefore, this mode is more user-friendly and convenient. Furthermore, after leaving the PC, the on-chip Linux system is enabled using ZYNQ's Arm kernel and by changing the ZYNQ host computer's BOOT mode. The system control interface runs within this on-chip system, and its operating principle is the same as described above.

[0061] This invention also provides an ultrasonic phased array focusing control system, which includes the ultrasonic phased array focusing control device in any embodiment of this invention.

[0062] Since the ultrasonic phased array focusing control system includes the ultrasonic phased array focusing control device provided in any embodiment of the present invention, the above-mentioned ultrasonic phased array focusing control system and ultrasonic phased array focusing control device have the same beneficial effects, and will not be described again here.

[0063] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An ultrasonic phased array focusing control device, characterized in that, include: The host computer, switch signal control module, slave computer, DAC module, and phased array ultrasonic transducer; The host computer is connected to the switch signal control module, and the switch signal control module is connected to the slave computer. The host computer is used to send pulse train length and repetition frequency data to the switch signal control module. The switch signal control module is used to generate a switch level signal according to the pulse train length and repetition frequency data and transmit it to the slave computer. The lower-level machine is connected to the DAC module, and the DAC module is connected to the phased array ultrasonic transducer. The lower-level machine is used to control the DAC module to convert the switching level signal into a sinusoidal signal and transmit it to the phased array ultrasonic transducer. The phased array ultrasonic transducer is used to convert the sinusoidal signal into a transcranial magnetic acoustic stimulation ultrasonic signal. The switching signal control module includes a ZYNQ chip, a first DAC unit, and a second DAC unit, wherein the ZYNQ chip is connected to the first DAC unit and the second DAC unit. The lower-level machine includes a first FPGA and a second FPGA, the first FPGA being connected to the first DAC unit, and the second FPGA being connected to the second DAC unit.

2. The control device according to claim 1, characterized in that, It also includes a multi-channel power amplifier connected between the DAC module and the phased array ultrasonic transducer. The multi-channel power amplifier is used to amplify the sinusoidal signal and transmit it to the phased array ultrasonic transducer.

3. The control device according to claim 1, characterized in that, The ZYNQ chip includes: a processing unit and a programmable logic control unit; The processing unit is connected to the programmable logic control unit, which is connected to the host computer, the first DAC unit, and the second DAC unit.

4. The control device according to claim 1, characterized in that, Both the first FPGA and the second FPGA include: a phase-locked loop clock divider module, an output delay module, and a trigger sequence module; The DAC module includes multiple DACs, and the phase-locked loop clock divider module is connected to the multiple DACs. The phase-locked loop clock divider module is used to increase the output frequency of the multiple DACs. The output delay module and the trigger sequence module are connected to the switch signal control module.

5. The control device according to claim 3, characterized in that, The switch signal control module also includes an I / O interface, which is connected to the programmable logic control unit, the first FPGA, and the second FPGA.

6. The control device according to claim 1, characterized in that, The pulse length of the switching level signal is 200μs-500μs, and the repetition frequency of the switching level signal is 1Hz-2kHz.

7. The control device according to claim 5, characterized in that, The host computer communicates with the switch signal control module via a serial port, and the slave computer communicates with the switch signal control module via the I / O interface.

8. The control device according to claim 1, characterized in that, The host computer's operating modes include: manual input mode or automatic input mode.

9. An ultrasonic phased array focusing control system, characterized in that, Includes the ultrasonic phased array focusing control device according to any one of claims 1-8.

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