Memory cell, memristor array, in-memory computing circuit, and operating method

Abstract

Embodiments of the present disclosure provide a storage unit, a memristor array, an integrated storage and calculation circuit, and an operation method. The storage unit includes n weight units and a horizontal selection tube. Each of the n weight units includes a first memristor element and a first switch element, a first electrode of the first memristor element is electrically connected with a first pole of the first switch element, a second electrode of the first memristor element is a second terminal of the corresponding weight unit and is used to receive a first bit line signal, second poles of the first switch elements of the n weight units are respectively used as first terminals of the corresponding weight units and are electrically connected with each other, and are electrically connected with a first terminal of the horizontal selection tube, control poles of the respective first switch elements are respectively used to receive different first word line signals, a second terminal of the horizontal selection tube is used to receive a source line signal, and a control terminal of the horizontal selection tube is used to receive a second word line signal.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a storage unit, a memristor array, a memory computing circuit, and an operating method. Background Technology

[0002] With the rapid development of artificial intelligence and neural network technologies, the importance of hardware acceleration technology is becoming increasingly significant. In-memory computing is a computing architecture used for hardware acceleration of neural networks. The memory cell array integrates computing functions, significantly reducing data movement and memory access overhead. Taking memristor memory cell arrays as an example, the non-volatile conductance state of the devices stores network weights. After applying a voltage pulse encoding the input information, the output analog current value represents the matrix-vector multiplication result. This current-mode in-memory computing circuit based on non-volatile devices can be used to achieve high-parallelism, high-throughput matrix calculations, greatly improving system computing power. The memory cell array is the basic structure of an in-memory computing system; different array structures are required to match different computational accuracies, system computing power, energy efficiency, and cost requirements. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a storage unit, the storage unit comprising:

[0004] There are n weight units, where n is a positive integer. Each of the n weight units includes a first memristor element and a first switching element. The first memristor element includes a first electrode and a second electrode. The first switching element includes a control electrode, a first electrode, and a second electrode.

[0005] The transverse selection tube includes a control terminal, a first terminal, and a second terminal.

[0006] Wherein, the first electrode of the first memristor element is electrically connected to the first terminal of the first switching element, the second electrode of the first memristor element serves as the second terminal of the corresponding weighting unit and is used to receive the first bit line signal, the second terminals of the first switching elements of the n weighting units serve as the first terminals of the corresponding weighting units and are electrically connected to each other, and are electrically connected to the first terminal of the lateral selector, the control terminal of each of the first switching elements is used to receive different first word line signals, the second terminal of the lateral selector is used to receive the source line signal, and the control terminal of the lateral selector is used to receive the second word line signal.

[0007] For example, in the storage unit provided in at least one embodiment of this disclosure, each of the n weighting units further includes a second memristor element and a second switching element. The first electrode of the second memristor element is electrically connected to the first electrode of the second switching element. The second electrode of the second memristor element serves as the third terminal of the corresponding weighting unit and is used to receive a second bit line signal. The control terminal of the second switching element is electrically connected to the control terminal of the first switching element. The second electrode of the second switching element is electrically connected to the second electrode of the first switching element.

[0008] At least one embodiment of this disclosure provides a memristor array, the memristor array comprising:

[0009] A plurality of storage cells as provided in at least one embodiment of the present disclosure, wherein the plurality of storage cells are arranged along a first direction and a second direction as m rows of storage cells and p columns of storage cells, where m and p are positive integers;

[0010] p groups of first word lines extend along the second direction and are connected one-to-one with the p columns of memory cells. Each group of the p groups of first word lines includes n first word lines, and each of the n first word lines is electrically connected to the control electrode of the first switching element of the corresponding column of memory cells.

[0011] m second word lines extend along the first direction and are connected one-to-one with the m rows of memory cells, wherein each of the m second word lines is electrically connected to the control terminal of the lateral selector of the corresponding row of memory cells.

[0012] p source lines extend along the second direction and are connected one-to-one with the p columns of memory cells, wherein each of the p source lines is electrically connected to the second end of the lateral selector of the corresponding column of memory cells.

[0013] m first-bit lines extend along the first direction and are connected one-to-one with the m rows of memory cells, wherein each of the m first-bit lines is electrically connected to the second electrode of the first memristor element of the corresponding row of memory cells.

[0014] For example, in the memristor array provided in at least one embodiment of this disclosure, each of the n weighting units further includes a second memristor element and a second switching element, and the memristor array further includes:

[0015] m second bit lines extend along the first direction and are connected one-to-one with the m rows of memory cells, wherein each of the m second bit lines is electrically connected to the second electrode of the second memristor element of the corresponding row of memory cells.

[0016] For example, in at least one embodiment of the memristor array provided in this disclosure, a driving circuit is further included, wherein the driving circuit includes:

[0017] Bit line driving circuit, electrically connected to the first bit line to provide the first bit line signal;

[0018] A word line driving circuit is electrically connected to the second word line to provide the second word line signal.

[0019] For example, in at least one embodiment of the memristor array provided in this disclosure, the bit line driving circuit includes an amplifier circuit unit, a first output circuit, a second output circuit, a first control circuit, a second control circuit, a third control circuit, a fourth control circuit, and a bit line driving output terminal; the amplifier circuit unit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the first output circuit is electrically connected to a first node, a first voltage terminal, and the bit line driving output terminal, respectively, and is configured to turn on or off the connection between the bit line driving output terminal and the first voltage terminal under the control of the potential of the first node; the second output circuit is electrically connected to a second node, a second voltage terminal, and the bit line driving output terminal, respectively, and is configured to turn on or off the bit line driving output terminal under the control of the potential of the second node. The connection between the first control circuit and the second voltage terminal; the first control circuit is electrically connected to the first voltage terminal and the first node respectively, and is configured to turn on or off the connection between the first node and the first voltage terminal; the second control circuit is electrically connected to the second voltage terminal and the second node respectively, and is configured to turn on or off the connection between the second node and the second voltage terminal; the third control circuit is electrically connected to the first output terminal of the amplifier circuit unit and the first node respectively, and is configured to turn on or off the connection between the first node and the first output terminal of the amplifier circuit unit; the fourth control circuit is electrically connected to the second output terminal of the amplifier circuit unit and the second node respectively, and is configured to turn on or off the connection between the second node and the second output terminal of the amplifier circuit unit.

[0020] For example, in a memristor array provided in at least one embodiment of this disclosure, the word line driving circuit includes a fifth control circuit, a sixth control circuit, and a word line driving output terminal; the fifth control circuit is electrically connected to the first voltage terminal and the word line driving output terminal respectively, and is configured to turn on or off the connection between the first voltage terminal and the word line driving output terminal; the sixth control circuit is electrically connected to the second voltage terminal and the word line driving output terminal respectively, and is configured to turn on or off the connection between the second voltage terminal and the word line driving output terminal.

[0021] At least one embodiment of this disclosure provides a memory computing circuit, including a memristor array as provided in at least one embodiment of this disclosure.

[0022] At least one embodiment of this disclosure provides an operation method for a memristor array as provided in at least one embodiment of this disclosure. The operation method includes: applying a second selection voltage to a second word line corresponding to the row where the target operation unit is located, applying a first selection voltage to a first word line corresponding to the column where the target operation unit is located, thereby selecting the target operation unit; and applying an operation voltage to a first bit line and a source line corresponding to the target operation unit.

[0023] For example, in the operation method provided in at least one embodiment of this disclosure, applying an operation voltage to the first bit line and source line corresponding to the target operation unit includes: applying an operation voltage for setting to the first bit line and source line corresponding to the target operation unit.

[0024] For example, in the operation method provided in at least one embodiment of this disclosure, applying an operation voltage to the first bit line and source line corresponding to the target operation unit includes: applying an operation voltage for resetting to the first bit line and source line corresponding to the target operation unit.

[0025] For example, in an operation method provided in at least one embodiment of this disclosure, the target operation unit includes a non-zero input unit, and applying an operation voltage to the first bit line and source line corresponding to the target operation unit includes: applying an input signal to the first bit line corresponding to the target operation unit; and applying a source line voltage to the column where the target operation unit is located.

[0026] At least one embodiment of this disclosure provides an electronic device, the electronic device comprising: a selection module configured to apply a second selection voltage to a second word line corresponding to the row where the target operation unit is located, and to apply a first selection voltage to a first word line corresponding to the column where the target operation unit is located, thereby selecting the target operation unit; and an operation module configured to apply an operation voltage to a first word line and a source line corresponding to the target operation unit.

[0027] For example, in an electronic device provided in at least one embodiment of this disclosure, the operation module is further configured to apply an operating voltage for setting to the first bit line and the source line corresponding to the target operation unit.

[0028] For example, in an electronic device provided in at least one embodiment of this disclosure, the operation module is further configured to apply an operating voltage for resetting to the first bit line and the source line corresponding to the target operation unit.

[0029] For example, in an electronic device provided in at least one embodiment of this disclosure, the operation module is further configured to apply an input signal to the first bit line corresponding to the target operation unit and apply a source line voltage to the column where the target operation unit is located. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0031] Figure 1A This is a schematic diagram of a common memristor array used in current-mode in-memory computing.

[0032] Figure 1B This is a schematic diagram of another common memristor array used in current-mode in-memory computing.

[0033] Figure 1C This is a schematic diagram illustrating a scenario that can lead to calculation errors.

[0034] Figure 1D This is a schematic diagram illustrating another scenario that can cause calculation errors.

[0035] Figure 2A A schematic diagram of a memory cell based on a 1T1R structure provided for at least one embodiment of this disclosure;

[0036] Figure 2B A schematic diagram of a memory cell based on a 2T2R structure provided in at least one embodiment of this disclosure;

[0037] Figure 3A A schematic diagram of a memristor array provided for at least one embodiment of this disclosure;

[0038] Figure 3B A schematic diagram of a memristor array provided for at least one embodiment of this disclosure;

[0039] Figure 4A A schematic diagram of a driving circuit provided in at least one embodiment of this disclosure;

[0040] Figure 4B A schematic diagram of a driving circuit provided in at least one embodiment of this disclosure;

[0041] Figure 5 A schematic diagram of a memory computing circuit provided for at least one embodiment of this disclosure;

[0042] Figure 6A A schematic diagram illustrating a setting operation method provided in at least one embodiment of this disclosure;

[0043] Figure 6BA schematic diagram illustrating a reset operation method provided in at least one embodiment of this disclosure;

[0044] Figure 6C A schematic diagram of a computational operation method provided in at least one embodiment of this disclosure; and

[0045] Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0048] The memristor array includes multiple rows and columns of memory cells, each memory cell including a weighting unit, implemented in the form of a memristor cell. This memristor cell can be a 1T1R structure or a 2T2R structure. A 1T1R structure memristor cell includes one switching element and one memristor element, with the first terminal of the memristor element electrically connected to the first terminal of the switching element (e.g., the drain of a transistor). A 2T2R structure memristor cell includes two switching elements and two memristor elements. This disclosure does not limit the type or structure of the memristor element. The memristor element used in the embodiments of this disclosure can be, for example, a resistive random access memory (RRAM), a phase-change memory (PCM), a bridged memory, or other memristor elements with the same characteristics. The switching element used in the embodiments of this disclosure can be, for example, a thin-film transistor (TFT), a field-effect transistor (FET), or other switching elements with the same characteristics. The source and drain of the transistor used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable.

[0049] A memristor is a non-volatile device whose conductance can be adjusted by applying an external stimulus. As a two-terminal device, the memristor's adjustable and non-volatile resistance makes it widely used in in-memory computing. Memristors can perform operations directly in the analog domain; for example, they can perform multiplication based on Ohm's law and addition based on Kirchhoff's current law. For instance, according to Kirchhoff's laws, by setting the state of the memristor (e.g., resistance value) and applying corresponding word line and bit line signals, the aforementioned memristor array can perform multiplication and addition calculations in parallel, with both storage and computation occurring within the array's individual elements.

[0050] Write operations to a memristor cell can be achieved by setting and resetting the memristor cell. For example, a set operation involves applying a positive voltage pulse to the bit line and grounding the source line, which lowers the resistance of the memristor cell; a reset operation involves applying a positive voltage pulse to the source line and grounding the bit line, which raises the resistance of the memristor cell. One set or reset operation can be considered as one write operation.

[0051] The read operation of a memristor cell can be performed as follows: apply a read voltage to the memristor cell, obtain the current value output by the memristor cell under the action of the read voltage, and determine the current resistance / conductance value of the memristor cell based on the current value and the read voltage. For example, a read voltage can be applied to the source line, thereby determining the resistance / conductance value of the memristor cell using Ohm's law based on the current value output by the bit line.

[0052] After the memristor cell is manufactured, it needs to be initialized. For example, initialization can be achieved by applying a higher voltage to the memristor cell—that is, applying a positive voltage pulse to the bit line while grounding the source line, with the amplitude and duration of the positive voltage pulse being greater than that of a set operation. This operation causes a change in the resistance value of the memristor cell, giving it an initial resistance value. Because the resistance value of a memristor cell is random, even under the same initialization conditions, the resistance value of each memristor cell will be different.

[0053] The inventors of this disclosure have noted that in high-parallelism mode, conventional arrays cannot shut down unselected weight cells, resulting in complex external circuit loads and additional leakage current, which affects computational accuracy and energy efficiency.

[0054] For example, Figure 1A This is a schematic diagram of a common memristor array used for current-mode in-memory computing. In this array, it is necessary to implement a multiplexed analog-to-digital converter (ADC) for multiple columns of weighted units (memristor units). Therefore, vertical word lines WL (WL[0]~WL[3]) are needed to control the gating of columns and to turn off the word lines of unselected columns to reduce additional leakage power consumption. In this array structure, since the gating of word lines will cause all weighted units on a column corresponding to a source line SL to be turned on, the array load conductance seen on the ADC side is very large, resulting in a large current noise. Furthermore, the voltage deviation corresponding to zero input will cause leakage, affecting the calculation accuracy.

[0055] For example, Figure 1B This is a schematic diagram of another common memristor array used in current-mode in-memory computing. In this array, the word line WL and bit line BL are parallel. Therefore, for a row with zero (0) input (i.e., an input value of 0), the word line BL signal can be pulled low to completely turn it off, thereby reducing the impact of leakage current on calculation accuracy in the zero-input case. However, this structure is not suitable for multi-column multiplexed ADCs, as columns not involved in the calculation will generate additional power consumption, reducing computational efficiency.

[0056] One type of calculation error is the current error caused by the source line SL clamping voltage deviation. Figure 1C A schematic diagram illustrating the situation that causes this type of calculation error is shown. Figure 1C The array current under m-input parallelism is shown, where G i Represents the equivalent conductance of the weighted unit in the i-th row. The reading voltage of the weighted cell in the i-th row is the voltage on the source line SL that is accurately clamped to the clamping voltage V by the analog-to-digital converter (ADC). CLAMP At that time, the current flowing into the analog-to-digital converter (ADC) is an ideal current. :

[0057]

[0058] When there is a deviation in the clamping voltage This will result in additional current deviation. :

[0059]

[0060] Among them, deviation current Equal to clamping deviation voltage The product of the corresponding array conductance and the clamping bias voltage. The clamping bias voltage includes the static bias caused by mismatch and the dynamic bias caused by factors such as noise. The higher the parallelism of the array computation, the larger the conductance and the greater the current error caused by the clamping bias voltage.

[0061] Another calculation error is the current error caused by the zero input voltage deviation of the bit line BL. Figure 1D A schematic diagram illustrating the situation that causes this type of calculation error is shown. Ideally, the bit line voltage BL and clamping voltage V correspond to zero input. CLAMP Same. For example... Figure 1D As shown, there is a deviation in the voltage of bit line BL. This can cause leakage current to occur in zero-input rows, resulting in serious calculation errors.

[0062] At least one embodiment of this disclosure provides a memory cell comprising n weighted units and a lateral selector, where n is a positive integer. Each of the n weighted units includes a first memristor element and a first switching element. The first memristor element includes a first electrode and a second electrode, and the first switching element includes a control electrode, a first terminal, and a second terminal. The lateral selector includes a control terminal, a first terminal, and a second terminal. The first electrode of the first memristor element is electrically connected to the first terminal of the first switching element, and the second electrode of the first memristor element serves as the second terminal of the corresponding weighted unit and is used to receive a first bit line signal. The second terminals of the first switching elements of the n weighted units respectively serve as the first terminals of the corresponding weighted units and are electrically connected to each other, and are electrically connected to the first terminal of the lateral selector. The control electrode of each first switching element is used to receive different first word line signals, the second terminal of the lateral selector is used to receive a source line signal, and the control terminal of the lateral selector is used to receive a second word line signal.

[0063] The memory cell provided in at least one embodiment of this disclosure can effectively utilize input sparsity and completely shut down unselected weight cells by introducing a lateral selection transistor and a second word line signal control, thereby improving calculation accuracy. At least one embodiment of this disclosure can also be used to efficiently reuse peripheral circuits, avoiding the leakage problem of traditional memristor array structures.

[0064] The storage unit provided according to this disclosure is described below in a non-limiting manner through multiple embodiments and examples. As described below, different features in these specific examples or embodiments can be combined with each other without conflict to obtain new examples or embodiments, and these new examples or embodiments are also within the scope of protection of this disclosure.

[0065] Figure 2A A schematic diagram of a storage cell based on a 1T1R structure provided in at least one embodiment of this disclosure.

[0066] For example, such as Figure 2A As shown, the memory cell 30 based on a 1T1R structure provided in this embodiment includes n weighting units 10 and a lateral selector 20, where n is a positive integer. Each weighting unit 10 includes a first memristor element 101 and a first switching element 102, i.e., the weighting unit is a 1T1R structure. The first memristor element 101 includes a first electrode 1011 and a second electrode 1012, and the first switching element 102 includes a first electrode 1021, a second electrode 1022, and a control electrode 1023. The lateral selector 20 includes a first terminal 201, a second terminal 202, and a control terminal 203.

[0067] For example, such as Figure 2A As shown, the first electrode 1011 of the first memristor element 101 is electrically connected to the first terminal 1021 of the first switching element 102. The second electrode 1012 of the first memristor element 101 serves as the second terminal of the corresponding weighting unit 102 and is used to receive the first bit line (BL) signal. The second terminals 1022 of the first switching elements 102 of the n weighting units serve as the first terminals of the corresponding weighting units 102 and are electrically connected to each other, and are electrically connected to the first terminal 201 of the lateral selector 20. Figure 2A In the diagram, WV[0], WV[1], ..., WV[n-1] represent the first, second, ..., nth first word lines, respectively. The control pole 1023 of each first switching element is used to receive different first word line (WV) signals. The second end 202 of the transverse selector 20 is used to receive the source line SL signal, and the control end 203 of the transverse selector 20 is used to receive the second word line (WH) signal.

[0068] The first word line signal controls the multiplexing of n weight cells in the storage cell 30. For a weight cell that needs to be selected for calculation, the first word line signal corresponding to that weight cell can be enabled, and the current of that weight cell can be connected to the first terminal 201 of the transverse selector 20 to enable its participation in the calculation; for an unselected weight cell, the first word line signal corresponding to that weight cell can be pulled low to turn it off.

[0069] Figure 2BThis is a schematic diagram of a storage cell based on a 2T2R structure provided in at least one embodiment of the present disclosure.

[0070] For example, such as Figure 2B As shown, the memory cell 40 based on the 2T2R structure provided in this embodiment includes n weight units 10 and lateral selectors 20, where n is a positive integer. Each weight unit 10 includes a first memristor element 101, a first switching element 102, a second memristor element 103, and a second switching element 104, that is, the weight unit is a 2T2R structure.

[0071] For example, such as Figure 2B As shown, the first electrode 1031 of the second memristor element 103 is electrically connected to the first terminal 1041 of the second switching element 104. The second electrode 1032 of the second memristor element 103 serves as the third terminal of the corresponding weighting unit 10 and is used to receive the second bit line (BLD) signal. The control terminal 1043 of the second switching element 104 is electrically connected to the control terminal 1023 of the first switching element 102. The second terminal 1042 of the second switching element 104 is electrically connected to the second terminal 1022 of the first switching element 102. The connection method of the remaining components is the same as... Figure 2A Similar to those in the text, so I will not elaborate further here.

[0072] Figure 3A This is a schematic diagram of a memristor array provided in at least one embodiment of the present disclosure, the memristor array including multiple Figure 2A The storage unit 30 is based on a 1T1R structure.

[0073] For example, refer to Figure 2A and Figure 3A The memristor array includes p groups of first word lines WV (WV[n-1:0]~WV[pn-1:(p-1)n]), m second word lines WH (WH[0]~WH[m-1]), p source lines SL (SL[0]~SL[p-1]), and m first word lines BL (BL[0]~BL[m-1]), as well as multiple... Figure 2A The storage unit 30 shown is arranged along the first direction D1 and the second direction D2 as m rows and p columns of storage units. Each group of first word lines WV includes n first word lines, for example, WV[n-1:0]. m, n, p, etc. are positive integers, which will not be elaborated further.

[0074] For example, p groups of first word lines WV extend along the second direction D2 and are connected one-to-one with p columns of storage cells 30. Each group of p groups of first word lines WV includes n first word lines, and each of the n first word lines WV is electrically connected to the control electrode of the first switching element of the corresponding column of storage cells 30. Taking the first word line WV[n-1:0] as an example, the first word line WV[n-1:0] realizes the control of multiplexing n weight cells in the storage cell 30. For a weight cell that needs to be selected to participate in the calculation, the first word line signal corresponding to the weight cell can be enabled, and the current of the weight cell can be connected to the first end of the transverse selection transistor to achieve participation in the calculation; for an unselected weight cell, the first word line signal corresponding to the weight cell can be pulled low to achieve shutdown.

[0075] For example, m second word lines WH extend along the first direction D1 and are connected one-to-one with m rows of memory cells 30. Each of the m second word lines WH is electrically connected to the control terminal of the lateral selection transistor of the corresponding row of memory cells 30. The second word line WH controls the conduction of the lateral selection transistor, determining whether to connect the current of the weighted cell selected by the first word line WV to the source line SL.

[0076] For example, p source lines SL extend along the second direction D2 and are connected one-to-one with p columns of storage cells 30. Each of the p source lines SL is electrically connected to the second end of the lateral selection transistor of the corresponding column of storage cells 30. The n weight cells in a storage cell 30 multiplex a set of source lines SL for output.

[0077] For example, m first bit lines BL extend along the first direction D1 and are connected one-to-one with m rows of memory cells 30. Each of the m first bit lines BL is electrically connected to the second electrode of the first memristor element of the corresponding row of memory cells 30. The n weighted cells in a memory cell 30 share a set of first bit lines BL for input.

[0078] With zero (0) input, the second word line signal of the corresponding row is pulled low to turn off the selector. At this time, the corresponding weight unit is disconnected from the source line, which effectively eliminates the leakage caused by the zero input voltage deviation of the first line and reduces the total conductance load on the source line, thus improving the calculation accuracy.

[0079] Figure 3B This is a schematic diagram of a memristor array provided in at least one embodiment of the present disclosure, the memristor array including Figure 2B The storage unit 40 is based on a 2T2R structure.

[0080] For example, refer to Figure 2B and Figure 3BThe memristor array also includes m second bit lines BLD (BLD[0]~BLD[m-1]). For example, the m second bit lines BLD extend along the first direction D1 and are connected one-to-one with the m rows of memory cells 40. Each of the m second bit lines BLD is electrically connected to the second electrode of the second memristor element of the corresponding row of memory cells 40. The remaining components of the memristor array and their connection methods are similar to those of the m-row memory cells 40. Figure 3A Similar to the case in China, it will not be elaborated here.

[0081] The memristor array provided in at least one embodiment of this disclosure also includes various driving circuits, including bit line driving circuits and word line driving circuits. For example, it may also include input circuits, output circuits, etc., as needed. For example, the input circuit may include a digital-to-analog converter (DAC), etc., and the output circuit may include an analog-to-digital converter (ADC), etc.

[0082] For example, the bit line driver circuit is electrically connected to the first bit line BL to provide the first bit line signal.

[0083] For example, the bit line driver circuit includes an amplifier circuit unit OTA, a first output circuit PM0, a second output circuit NM0, a first control circuit SW1, a second control circuit SW2, a third control circuit SW3, a fourth control circuit SW4, and a bit line driver output terminal OB. For example, the bit line driver circuit adopts a Class-AB output stage design.

[0084] For example, the amplifier circuit unit OTA includes a first input terminal VIP, a second input terminal VIN, a first output terminal, and a second output terminal.

[0085] For example, the first output circuit PM0 is electrically connected to the first node N1, the first voltage terminal V1, and the bit line drive output terminal OB, and is configured to turn on or off the connection between the bit line drive output terminal OB and the first voltage terminal V1 under the control of the potential of the first node N1; the second output circuit NM0 is electrically connected to the second node N2, the second voltage terminal V0, and the bit line drive output terminal OB, and is configured to turn on or off the connection between the bit line drive output terminal OB and the second voltage terminal V0 under the control of the potential of the second node N2.

[0086] For example, the first control circuit SW1 is electrically connected to the first voltage terminal V1 and the first node N1, respectively, and is configured to turn on or off the connection between the first node N1 and the first voltage terminal V1; the second control circuit SW2 is electrically connected to the second voltage terminal V0 and the second node N2, respectively, and is configured to turn on or off the connection between the second node N2 and the second voltage terminal V0; the third control circuit SW3 is electrically connected to the first output terminal of the amplifier circuit unit OTA and the first node N1, respectively, and is configured to turn on or off the connection between the first node N1 and the first output terminal of the amplifier circuit unit OTA; the fourth control circuit SW4 is electrically connected to the second output terminal of the amplifier circuit unit OTA and the second node N2, respectively, and is configured to turn on or off the connection between the second node N2 and the second output terminal of the amplifier circuit unit OTA.

[0087] It should be noted that, in the case of the 2T2R structure, the memristor array also includes a second bit line. In this case, the driving voltage required for the first bit line and the second bit line is different. Therefore, each row of the memristor array requires two bit line driving circuits, which are electrically connected to the first bit line and the second bit line respectively to provide the first bit line signal and the second bit line signal.

[0088] For example, the word line driver circuit is electrically connected to the second word line to provide the second word line signal.

[0089] For example, the word line driver circuit includes a fifth control circuit SW5, a sixth control circuit SW6, and a word line driver output terminal OW. The fifth control circuit SW5 is electrically connected to the first voltage terminal V1 and the word line driver output terminal OW, respectively, and is configured to turn on or off the connection between the first voltage terminal V1 and the word line driver output terminal OW; the sixth control circuit SW6 is electrically connected to the second voltage terminal V0 and the word line driver output terminal OW, respectively, and is configured to turn on or off the connection between the second voltage terminal V0 and the word line driver output terminal OW.

[0090] like Figure 4A As shown, in the case of zero input, the voltage applied to the first input terminal VIP of the amplifier circuit unit OTA is equal to the clamping voltage on the source line SL. At this time, the first control circuit SW1 and the second control circuit SW2 are turned on, while the third control circuit SW3 and the fourth control circuit SW4 are turned off. This connects the control terminal of the first output circuit PM0 to the first voltage terminal V1, and the control terminal of the second output circuit NM0 to the second voltage terminal V2. For example, the first voltage terminal V1 is the power supply, and the second voltage terminal V2 is ground (GND).

[0091] like Figure 4BAs shown, under non-zero input conditions, the voltage applied to the first input terminal VIP of the amplifier circuit unit OTA is equal to the sum of the input voltage and the clamping voltage. At this time, the first control circuit SW1 and the second control circuit SW2 are disconnected, while the third control circuit SW3 and the fourth control circuit SW4 are turned on. This connects the control terminals of the first output circuit PM0 and the second output circuit NM0 to the two output terminals of the amplifier circuit unit OTA, respectively. The bit line drive output terminal OB outputs the calculated voltage required for the first bit line BL. Simultaneously, the fifth control circuit SW5 is turned on, the sixth control circuit SW6 is disconnected, and the word line drive output terminal OW outputs the voltage required to drive the second word line WH, pulling the corresponding second word line WH voltage high.

[0092] For example, the first input terminal VIP and the second input terminal VIN of the amplifier circuit unit OTA are connected in a feedback structure, i.e., in the form of a unity-gain buffer. Therefore, it is not necessary to apply a voltage to VIN. The VIN voltage is kept consistent with the VIP voltage through the feedback virtual short, so that the two output terminals of the amplifier circuit unit OTA output the same voltage.

[0093] Based on the above driving circuit, not only can the weight unit corresponding to zero input be completely turned off, but the bit line driving circuit of the row corresponding to zero input can also be completely turned off, which greatly reduces the computational power consumption of the network when the input sparsity is high.

[0094] Figure 5 A schematic diagram of a memory computing circuit provided for at least one embodiment of this disclosure.

[0095] like Figure 5 As shown, the in-memory computing circuit includes a memristor array provided in at least one of the above embodiments. The memristor array includes p groups of first word lines WV (WV[n-1:0]~WV[pn-1:(p-1)n]), m second word lines WH (WH[0]~WH[m-1]), p source lines SL (SL[0]~SL[p-1]), and m first bit lines BL (BL[0]~BL[m-1]), as well as a plurality of memory cells 30, arranged along a first direction D1 and a second direction D2 as m rows and p columns of memory cells. The memristor array also includes a driving circuit 50, which includes a bit line driving circuit 51 and a word line driving circuit 52.

[0096] like Figure 5 As shown, the in-memory computing circuit also includes an input circuit 61, an output circuit 62, a first word line programming driver circuit 71, a second word line programming driver circuit 72, a first bit line programming driver circuit 73, and a source line programming driver circuit 74. The input circuit 61 includes multiple digital-to-analog converters (DACs), and the output circuit 62 includes multiple analog-to-digital converters (ADCs).

[0097] For example, m digital-to-analog converters (DACs) (DAC[0] to DAC[m-1]) are electrically connected one-to-one with the bit line drive circuits 51 of the corresponding rows. The DACs are used to convert the input digital signals into analog signals so that the analog signals can be input to the first input terminal of the amplifier circuit unit of the corresponding bit line drive circuit during parallel computing.

[0098] For example, the first word line programming driver circuit 71 is electrically connected to the first word line WV (WV[n-1:0]~WV[pn-1:(p-1)n]) to provide the first word line programming signal, and the second word line programming driver circuit 72 is electrically connected to the second word line WH (WH[0]~WH[m-1]) to provide the second word line programming signal. The first word line programming signal and the second word line programming signal can be used to select the unit that needs to be operated.

[0099] For example, the first line programming driver circuit 73 is electrically connected to the first line BL (BL[0]~BL[m-1]) to provide the first line programming signal, and the source line programming driver circuit 74 is electrically connected to the source line SL (SL[0]~SL[p-1]) to provide the source line programming signal. The first line programming signal can be used to provide a set voltage to the unit that needs to be set, and the source line programming signal can be used to provide a reset voltage to the unit that needs to be reset.

[0100] For example, p analog-to-digital converters (ADCs) (ADC[0]~ADC[p-1]) are electrically connected one-to-one with source lines SL (SL[0]~SL[p-1]). The ADCs are used to convert analog signals into digital signals and provide clamping voltages to the source lines for computation. In the memristor array, the n weighted units of each memory cell share the same ADC circuit, with one of the n weighted units participating in the computation controlled by the first word line WV. This circuit architecture improves the computational accuracy and energy efficiency of the in-memory computing circuit.

[0101] For example, the in-memory computing circuit may also include a pre-control circuit (not shown in the figure) that provides control voltages to the first to sixth control circuits in the bit line drive circuit 51 based on whether the input digital signal is zero or non-zero data. For example, the pre-control circuit may include analog / digital circuits, etc.

[0102] It should be noted that, in the 2T2R structure, the memristor array also includes a second bit line. In this case, the in-memory computing circuit also includes a second bit line programming driver circuit, which is electrically connected to the second bit line to provide a second bit line programming signal. This second bit line programming signal can be used to provide a set voltage to the cell that needs to be set. Apart from this, in the 2T2R structure, the remaining components of the in-memory computing circuit and their connection methods are the same as... Figure 5Similar to the case in China, it will not be elaborated here.

[0103] At least one embodiment of this disclosure also provides a method for operating a memristor array as described above, including steps S1 and S2.

[0104] Step S1: Apply a second selection voltage to the second word line corresponding to the row where the target operation unit is located, and apply a first selection voltage to the first word line corresponding to the column where the target operation unit is located, thereby selecting the target operation unit.

[0105] For example, the first selected voltage can be obtained through, as follows Figure 5 The first word line programming driver circuit 71 shown applies the second selection voltage, which can be applied via, as shown in the diagram. Figure 5 The second word line programming driver circuit 72 shown is applied.

[0106] Step S2: Apply an operating voltage to the first bit line and source line corresponding to the target operating unit.

[0107] For example, a memristor array includes an operating mode and a computation mode. When the memristor array is in operating mode, the memristor cells are in an initialized state, and the values ​​of elements in a matrix that require multiplication can be written into the memristor array, such as mapping weight values ​​to memristor conductance values. This writing can be achieved, for example, through set and reset operations.

[0108] For example, when performing a set operation, step S2 further involves applying an operating voltage for setting to the first bit line and the source line corresponding to the target operation unit.

[0109] Figure 6A This is a schematic diagram illustrating a setting operation method provided in at least one embodiment of this disclosure. For example... Figure 6A As shown, the specific operation method is as follows:

[0110] A second selection voltage is applied to the second word line WH[1] corresponding to the row where the target operation unit to be set is located, and a first selection voltage is applied to the first word line WV[n-1] corresponding to the column where the target operation unit is located, thereby selecting the target operation unit to be set;

[0111] Apply a set voltage V to the first bit line BL[1] corresponding to the target operation unit. SET This lowers the voltage on the source line SL[0] corresponding to the target operation unit and lowers the voltage on the other signal lines, thereby achieving the set operation of the target operation unit. For example, the set voltage V SET Through such Figure 5 The first line programming driver circuit 73 shown applies the source line voltage, which can be applied via, as shown in the figure. Figure 5 The source line programming driver circuit 74 shown is applied.

[0112] For example, when performing a reset operation, step S2 further involves applying an operating voltage for resetting to the first bit line and source line corresponding to the target operation unit.

[0113] Figure 6B This is a schematic diagram illustrating a reset operation method provided in at least one embodiment of this disclosure. Figure 6B As shown, the specific operation method is as follows:

[0114] A second selection voltage is applied to the second word line WH[1] corresponding to the row where the target operation unit to be reset is located, and a first selection voltage is applied to the first word line WV[n-1] corresponding to the column where the target operation unit is located, thereby selecting the target operation unit to be reset;

[0115] Apply a reset voltage V to the source line SL[0] corresponding to the target operation unit. RESET This lowers the voltage on the first line BL[1] corresponding to the target operation unit and lowers the voltage on the other signal lines, thereby achieving a reset operation on the target operation unit. For example, the voltage on the first line can be lowered by, for example, by... Figure 5 The first line programming drive circuit 73 shown applies a reset voltage V. RESET It can be done as follows Figure 5 The source line programming driver circuit 74 shown is applied.

[0116] For example, when the memristor array is in calculation mode, the memristors in the array are in a conductive state that can be used for calculation. The voltage input on the first line will not change the conductance of the memristor. For example, calculations can be completed by performing multiplication and addition operations through the memristor array.

[0117] For example, when performing parallel computing operations, the target operation unit includes a non-zero input unit, and step S2 further includes: applying an input signal to the first bit line corresponding to the target operation unit, and applying a source line voltage to the column where the target operation unit is located.

[0118] Figure 6C This is a schematic diagram illustrating a parallel computing operation method provided in at least one embodiment of this disclosure. For example... Figure 6C As shown, the specific operation method is as follows:

[0119] A second selection voltage is applied to the second word lines WH[0]~WH[m-1] corresponding to the row where all target operation units participating in the calculation are located, and a first selection voltage is applied to the first word lines WV[0]~WV[n-1] corresponding to the column where they are located, thereby selecting the target operation units participating in the calculation. Specifically, assuming that only the second row of the entire array has zero input and the rest of the rows have non-zero input, then for non-zero input units, the voltage on the corresponding second word lines WH[0], WH[2]~WH[m-1] is pulled high, and for zero input units, the voltage on the corresponding second word line WH[1] is pulled low;

[0120] An input signal is applied to the first bit line BL[0]~BL[m-1] corresponding to the target operation unit, and a clamping voltage is applied to the source line SL[0] of the column where the target operation unit is located, thereby realizing parallel computation operation. For example, the input digital signal can be converted into an analog signal by a digital-to-analog converter (DAC), and then the computation voltage, i.e., the input signal applied to the first bit line, can be output by the bit line driving circuit 51. For example, the clamping voltage applied to the source line can be provided by an analog-to-digital converter (ADC).

[0121] At least one embodiment of this disclosure also provides an electronic device. Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. The electronic device may be, for example, a server device or a terminal device, such as a server, computer, controller, etc.

[0122] For example, such as Figure 7 As shown, the electronic device 700 includes a selection module 701 and an operation module 702.

[0123] For example, the selection module 701 is configured to apply a second selection voltage to the second word line corresponding to the row where the target operation unit is located, and to apply a first selection voltage to the first word line corresponding to the column where the target operation unit is located, thereby selecting the target operation unit. For example, the selection module 701 may include, for example, Figure 5 The first word line programming driver circuit 71 and the second word line programming driver circuit 72 are shown.

[0124] For example, the operation module 702 is configured to apply an operation voltage to the first bit line and the source line corresponding to the target operation unit.

[0125] For example, the operation module 702 is further configured to apply a setting operation voltage to the first bit line and source line corresponding to the target operation unit. For example, the operation module 702 is further configured to apply a resetting operation voltage to the first bit line and source line corresponding to the target operation unit. For example, the operation module 702 may include... Figure 5 The first line programming driver circuit 73 and the source line programming driver circuit 74 are shown.

[0126] For example, the operation module 702 is further configured to apply an input signal to the first line corresponding to the target operation unit and to apply a source line voltage to the column where the target operation unit is located. For example, the operation module 702 may also include... Figure 5 The input circuit 61, output circuit 62, and bit line drive circuit 51 are shown.

[0127] For details regarding the selection module 701 and the operation module 702, please refer to the descriptions of steps S1 and S2 in the above operation method embodiment, which will not be repeated here.

[0128] One or more embodiments of this disclosure provide a storage cell, a memristor array, a memory computing circuit, an operating method, and an electronic device, which have one or more of the following beneficial effects:

[0129] (1) The memory cell provided in at least one embodiment of this disclosure can be effectively applied in a memristor array. By introducing a lateral selector and a lateral second word line signal control, the row corresponding to the zero input can be completely turned off, thereby reducing the source line conductance and load, reducing the zero input leakage current, and improving the calculation accuracy.

[0130] (2) The memristor array provided in at least one embodiment of the present disclosure includes a bit line driving circuit and a lateral second word line driving circuit, which can effectively reduce the power consumption of the peripheral circuit under zero input, thereby improving the computing power efficiency of the system under high sparsity network.

[0131] (3) The in-memory computing circuit provided in at least one embodiment of this disclosure is based on the memristor array of the storage unit in the above embodiment, and can be used to solve the problem of decreased calculation accuracy caused by excessive array conductance load in high parallel in-memory computing.

[0132] (3) The in-memory computing circuit provided in at least one embodiment of the present disclosure is implemented based on the memristor array of the memory cell in the above embodiment. It can be used in conjunction with a turn-off drive circuit to effectively improve the computing efficiency of in-memory computing when computing high input sparsity networks.

[0133] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, such modifications or improvements made without departing from the spirit of the present disclosure are all within the scope of protection claimed by the present disclosure.

[0134] The following points should be noted regarding this disclosure:

[0135] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0136] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0137] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0138] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A memristor array, comprising: Multiple storage cells, wherein the multiple storage cells are arranged along a first direction and a second direction as m rows of storage cells and p columns of storage cells, where m and p are positive integers; p groups of first word lines extend along the second direction and are connected one-to-one with the p columns of memory cells. Each group of the p groups of first word lines includes n first word lines, and each of the n first word lines is electrically connected to the control electrode of the first switching element of the corresponding column of memory cells. m second word lines extend along the first direction and are connected one-to-one with the m rows of memory cells, wherein each of the m second word lines is electrically connected to the control terminal of the lateral selector of the corresponding row of memory cells. p source lines extend along the second direction and are connected one-to-one with the p columns of memory cells, wherein each of the p source lines is electrically connected to the second end of the lateral selector of the corresponding column of memory cells. m first bit lines extend along the first direction and are connected one-to-one with the m rows of memory cells, wherein each of the m first bit lines is electrically connected to the second electrode of the first memristor element in the corresponding row of memory cells. Each of the plurality of storage units includes: There are n weight units, where n is a positive integer. Each of the n weight units includes a first memristor element and a first switching element. The first memristor element includes a first electrode and a second electrode. The first switching element includes a control electrode, a first electrode, and a second electrode. The transverse selection tube includes a control terminal, a first terminal, and a second terminal. In this configuration, the first electrode of the first memristor element is electrically connected to the first terminal of the first switching element, the second electrode of the first memristor element serves as the second terminal of the corresponding weighting unit and is used to receive the first bit line signal, the second terminals of the first switching elements of the n weighting units serve as the first terminals of the corresponding weighting units and are electrically connected to each other, and are electrically connected to the first terminal of the lateral selector, the control terminal of each of the first switching elements is used to receive different first word line signals, the second terminal of the lateral selector is used to receive the source line signal, the control terminal of the lateral selector is used to receive the second word line signal, and the lateral selector is configured to control the on / off state between the corresponding weighting unit and the source line in response to the second word line signal.

2. The memristor array according to claim 1, wherein, Each of the n weighting units further includes a second memristor element and a second switching element. The first electrode of the second memristor element is electrically connected to the first electrode of the second switching element, the second electrode of the second memristor element serves as the third terminal of the corresponding weighting unit and is used to receive the second bit line signal, the control terminal of the second switching element is electrically connected to the control terminal of the first switching element, and the second electrode of the second switching element is electrically connected to the second electrode of the first switching element.

3. The memristor array according to claim 2, wherein, The memristor array also includes: m second bit lines extend along the first direction and are connected one-to-one with the m rows of memory cells, wherein each of the m second bit lines is electrically connected to the second electrode of the second memristor element of the corresponding row of memory cells.

4. The memristor array according to claim 1 further includes a driving circuit, wherein, The driving circuit includes: Bit line driving circuit, electrically connected to the first bit line to provide the first bit line signal; A word line driving circuit is electrically connected to the second word line to provide the second word line signal.

5. The memristor array according to claim 4, wherein, The bit line driving circuit includes an amplifier circuit unit, a first output circuit, a second output circuit, a first control circuit, a second control circuit, a third control circuit, a fourth control circuit, and a bit line driving output terminal; The amplifier circuit unit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; The first output circuit is electrically connected to the first node, the first voltage terminal and the bit line drive output terminal respectively, and is configured to turn on or off the connection between the bit line drive output terminal and the first voltage terminal under the control of the potential of the first node. The second output circuit is electrically connected to the second node, the second voltage terminal, and the bit line drive output terminal, respectively, and is configured to turn on or off the connection between the bit line drive output terminal and the second voltage terminal under the control of the potential of the second node. The first control circuit is electrically connected to the first voltage terminal and the first node respectively, and is configured to turn on or off the connection between the first node and the first voltage terminal; The second control circuit is electrically connected to the second voltage terminal and the second node respectively, and is configured to turn on or off the connection between the second node and the second voltage terminal; The third control circuit is electrically connected to the first output terminal of the amplifier circuit unit and the first node respectively, and is configured to turn on or off the connection between the first node and the first output terminal of the amplifier circuit unit. The fourth control circuit is electrically connected to the second output terminal and the second node of the amplifier circuit unit, respectively, and is configured to turn on or off the connection between the second node and the second output terminal of the amplifier circuit unit.

6. The memristor array according to claim 5, wherein, The word line driving circuit includes a fifth control circuit, a sixth control circuit, and a word line driving output terminal; The fifth control circuit is electrically connected to the first voltage terminal and the word line drive output terminal respectively, and is configured to turn on or off the connection between the first voltage terminal and the word line drive output terminal. The sixth control circuit is electrically connected to the second voltage terminal and the word line drive output terminal respectively, and is configured to turn on or off the connection between the second voltage terminal and the word line drive output terminal.

7. A memory computing circuit comprising a memristor array as described in any one of claims 1-6.

8. A method of operating a memristor array as described in any one of claims 1-6, comprising: A second selection voltage is applied to the second word line corresponding to the row where the target operation unit is located, and a first selection voltage is applied to the first word line corresponding to the column where the target operation unit is located, thereby selecting the target operation unit; An operating voltage is applied to the first bit line and the source line corresponding to the target operating unit.

9. The operating method according to claim 8, wherein, Applying an operating voltage to the first bit line and source line corresponding to the target operating unit includes: An operating voltage for setting is applied to the first bit line and the source line corresponding to the target operation unit.

10. The operating method according to claim 8, wherein, Applying an operating voltage to the first bit line and source line corresponding to the target operating unit includes: An operating voltage for resetting is applied to the first bit line and the source line corresponding to the target operating unit.

11. The operating method according to claim 8, wherein, The target operation unit includes a non-zero input unit, and applying an operation voltage to the first bit line and source line corresponding to the target operation unit includes: An input signal is applied to the first bit line corresponding to the target operation unit; A source line voltage is applied to the column containing the target operating unit.

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