System and method for automatically determining switching states in a power converter

Abstract

Systems and methods are disclosed for automatically detecting switching states in power converters. In one aspect, a power switch includes a first switch coupled between a power input node and a first terminal of a load, a second switch coupled between the power input node and a second terminal of the load, first and second current sensing devices arranged to transmit first and second signals including at least one of a magnitude and a polarity of first and second currents passing through the first and second switches, respectively, a first driver circuit arranged to transmit a first control signal to the first switch based at least in part on a voltage at the power input node and the first signal, and a second driver circuit arranged to transmit a second control signal to the second switch based at least in part on the voltage at the power input node and the second signal.

Description

[0001] This application is a divisional application of Chinese Invention Patent Application No. 202210122595.2, filed on February 9, 2022, entitled “System and Method for Automatically Determining Switch State in Power Converter,” which claims priority to U.S. Provisional Patent Application No. 63 / 147,603, filed on February 9, 2021, entitled “DYNAMIC ZCD THRESHOLD MODULATION,” which is hereby incorporated by reference in its entirety for all purposes.

[0002] Cross Reference to Related Applications

[0003] This application claims priority to U.S. Provisional Patent Application No. 63 / 147,603, filed on February 9, 2021, entitled “DYNAMIC ZCD THRESHOLD MODULATION,” which is hereby incorporated by reference in its entirety for all purposes. TECHNICAL FIELD

[0004] The present disclosure relates generally to power conversion circuits, and in particular to power conversion circuits that automatically detect the state of power switches used in the power conversion circuits. BACKGROUND

[0005] Electronic devices, such as computers, servers, and televisions, use one or more electrical power conversion circuits to convert one form of electrical energy into another. Some electrical power conversion circuits use a circuit topology known as a half-bridge converter to convert a high DC voltage into a lower DC voltage. As many electronic devices are sensitive to the size and efficiency of the power conversion circuits, new power converters can provide relatively higher efficiency and smaller size for new electronic devices. SUMMARY

[0006] In some embodiments, a circuit is disclosed. The circuit includes a first switch coupled between a power input node and a first terminal of a load, a second switch coupled between the power input node and a second terminal of the load, a first current sense device arranged to transmit a first signal including at least one of a magnitude and a polarity of a first current passing through the first switch, a second current sense device configured to transmit a second signal including at least one of a magnitude and a polarity of a second current passing through the second switch, a first driver circuit arranged to transmit a first control signal to the first switch based at least in part on a voltage at the power input node and the first signal, and a second driver circuit arranged to transmit a second control signal to the second switch based at least in part on the voltage at the power input node and the second signal.

[0007] In some embodiments, the first driver circuit includes a first threshold generation circuit and the second driver circuit includes a second threshold generation circuit.

[0008] In some embodiments, the first threshold generating circuit is arranged to generate a first threshold signal based on the voltage at the power input node.

[0009] In some embodiments, a value of the first threshold signal is based on a duty cycle of a pulse width modulation (PWM) signal received from a controller.

[0010] In some embodiments, the value of the first threshold signal is high when the duty cycle of the PWM signal is high.

[0011] In some embodiments, the value of the first threshold signal is low when the duty cycle of the PWM signal is low.

[0012] In some embodiments, the second threshold generating circuit is arranged to generate a second threshold signal based on the voltage at the power input node.

[0013] In some embodiments, the value of the second threshold signal is based on the duty cycle of the PWM signal received from the controller.

[0014] In some embodiments, the first threshold generating circuit includes a first PWM signal receiving circuit and a first resistor coupled to a first current mirror circuit, the first current mirror circuit coupled to the first PWM signal receiving circuit.

[0015] In some embodiments, a method of operating a circuit is disclosed. The method includes switching a first power switch and a second power switch to transfer power from an AC power input node to a load, receiving a control signal for controlling operation of the first power switch and the second power switch, providing a first switching device including a first current sensor arranged to transfer a first signal indicative of a polarity of a first current flowing through the first power switch, providing a second switching device including a second current sensor arranged to transfer a second signal indicative of a polarity of a second current flowing through the second power switch, generating a reference voltage based on a voltage of the AC power input node, and transferring a turn-off signal to the first power switch when a voltage of the first signal is higher than the reference voltage.

[0016] In some embodiments, the transferring of the turn-off signal to the first power switch occurs when the first signal is higher than the reference voltage and a turn-off signal for the first power switch is received from a controller.

[0017] In some embodiments, the reference voltage is a first reference voltage, and the off signal is a first off signal, and the method further includes transmitting a second off signal to the second power switch when a voltage of the second signal is higher than a second reference voltage.

[0018] In some embodiments, the transmitting the second off signal to the second power switch occurs when the second signal is higher than the second reference voltage and the second off signal for the first power switch is received from a controller.

[0019] In some embodiments, the generating the reference voltage based on the voltage of the AC power input node includes receiving a pulse width modulated (PWM) signal, and generating the reference voltage based on a value of a resistance of a first resistor and a duty cycle of the PWM signal.

[0020] In some embodiments, a power factor correction (PFC) circuit is disclosed. The PFC circuit includes a first power switch coupled between a switch node and a first terminal of a load, a second power switch coupled between the switch node and a second terminal of the load; a first current sensing device arranged to transmit a first signal including at least one of a magnitude and a polarity of a first current through the first power switch; a second current sensing device arranged to transmit a second signal including at least one of a magnitude and a polarity of a second current through the second power switch; a first driver circuit arranged to transmit a first control signal to the first power switch based at least in part on a voltage at the power input node and the first signal; a second driver circuit arranged to transmit a second control signal to the second power switch based at least in part on the voltage at the power input node and the second signal; and a controller arranged to transmit control signals to the first power switch and the second power switch.

[0021] In some embodiments, in the PFC circuit, the first driver circuit includes a first threshold generating circuit, and the second driver circuit includes a second threshold generating circuit.

[0022] In some embodiments, in the PFC circuit, the first threshold generating circuit is arranged to generate the first threshold signal based on the voltage at the power input node.

[0023] In some embodiments, in the PFC circuit, the first power switch and the second power switch are arranged to selectively connect the switch node to the first terminal and the second terminal of the load.

[0024] In some embodiments, in the PFC circuit, the connecting of the switch node to the first terminal of the load is performed when the switch node is at substantially the same voltage as the first terminal of the load.

[0025] In some embodiments, in the PFC circuit, the connecting of the switch node to the second terminal of the load is performed when the switch node is at substantially the same voltage as the second terminal of the load. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a simplified schematic illustration of a power conversion circuit according to embodiments of the present disclosure;

[0027] Figure 2 is a simplified schematic illustration of an operating condition of the circuit of Figure 1

[0028] Figure 3 is a simplified schematic illustration of an operating condition of the circuit of Figure 1

[0029] Figure 4 is a simplified schematic illustration of an operating condition of the circuit of Figure 1

[0030] Figure 5 is a simplified schematic illustration of an operating condition of the circuit of Figure 1

[0031] Figure 6 is a simplified schematic illustration of a variable current threshold switching circuit according to embodiments of the present disclosure;

[0032] Figure 7 is a simplified schematic illustration of a control mode operation of the circuit of Figure 6

[0033] Figure 8 is a simplified schematic illustration of a synchronous mode operation of the circuit of Figure 6

[0034] is a flowchart illustrating an exemplary method for determining a state of a power switch and a power switch opening method according to embodiments of the present disclosure; and Figure 9

[0035] is a simplified schematic illustration of a zero current reference voltage generator according to embodiments of the present disclosure. Figure 10 DETAILED DESCRIPTION

[0036] ​​​​​​The circuits and related technology disclosed herein generally relate to power converters. More specifically, the circuits, apparatuses, and related technology disclosed herein relate to power conversion circuits that use power switches that can automatically detect power switching states. In some embodiments, the circuits, apparatuses, and related technology disclosed herein can be used in totem pole bridgeless power factor correction (PFC) circuits to improve their operational efficiency by allowing zero voltage switching (ZVS) of the power switches. In various embodiments, ZVS is achieved by determining whether the power switches are operating in a control mode or a synchronous (sync) mode, and if the power switches are operating in the sync mode, the power switches can not turn off in response to a control signal from a controller. Instead, the power switches can automatically and autonomously determine when to turn off themselves to optimize the amount of current that can flow into a power conversion inductor so that the energy in the power conversion inductor can soft pull a switching node to ground. In this way, hard switching of the switching node can be avoided, thereby improving the operational efficiency of the totem pole bridgeless PFC.

[0037] In some embodiments, the determination of the operating mode of the power switches (control or sync mode) and the optimization of the amount of current that can flow into the power conversion inductor can be performed by generating a current sense signal based on at least one of a threshold signal based on an input line voltage, a direction, and a magnitude of a current flowing through the power switches. In various embodiments, the threshold signal can be based on a difference between an output voltage of the power converter and the input line voltage. The current sense signal can be compared to the threshold signal, and if the current sense signal is less than the threshold signal, the power switches can not turn off in response to a control signal from a controller. Instead, the power switches can delay their turn off until the current sense signal exceeds the threshold signal.

[0038] When the output voltage of the power converter is at a fixed value, the threshold signal can be based on an instantaneous value of the input line voltage. By having the threshold signal based on the instantaneous value of the input line voltage, the amount of reverse current flowing into the power conversion inductor can be optimized to achieve ZVS, thereby improving the efficiency of the power converter. In various embodiments, by having the ability to automatically and autonomously detect whether the power switches are operating in the control mode or the sync mode, the computational load on the controller can be reduced, thereby reducing the system cost.

[0039] In some embodiments, if the power switches determine that they are in the control mode, they can immediately turn off, whereas if the power switches determine that they are in the sync mode, the switches can not immediately turn off. Instead, they can wait until the current through the power switches becomes positive for a relatively small amount before turning off themselves. The relatively small amount of positive current is automatically determined by the power switches so that the inductor can be charged with an optimized amount of energy to be able to soft pull the switching node to ground, i.e., achieve ZVS, thereby increasing the operational efficiency of the power converter.

[0040] Embodiments of the present disclosure can enable a power converter to increase its operating efficiency while increasing the control loop bandwidth of the controller. Determination of the turn-on time of the synchronous switch can be performed autonomously by the power switch itself, thereby freeing the controller from performing this task, and thus increasing the control loop bandwidth, since the controller performs less computation during each control loop update. This can result in improved performance of the power converter. Furthermore, less complex controllers can be used in the power converter, thereby reducing system cost.

[0041] In some embodiments, the totem-pole bridgeless PFC circuit can utilize one or more gallium nitride (GaN) devices, such as GaN power transistors. By utilizing GaN devices, embodiments of the present disclosure can enable a power converter to operate at relatively higher frequencies with relatively higher efficiency than traditional silicon-based circuits, since GaN transistors can have relatively lower reverse recovery charge compared to their silicon counterparts. Various inventive embodiments are described herein, including methods, processes, systems, apparatuses, and the like.

[0042] Figure 1 A simplified schematic of a power conversion circuit 100 receiving AC power input from an AC source Vac and providing power to a load 150 in accordance with embodiments of the present disclosure.

[0043] The power conversion circuit 100 includes a controller 110, an input inductor L, a high-side switch S1, a low-side switch S2, diodes D1, D2, and an output capacitor Co.

[0044] As understood by one of ordinary skill in the art, diodes D1 and D2 can be implemented using any current rectification structure, such as a pn-junction diode or a diode-connected transistor. Other current rectification structures can be used, as understood by one of ordinary skill in the art. In some embodiments, diodes D1 and D2 can be implemented with switches actively controlled by the controller 110, as understood by one of ordinary skill in the art.

[0045] The output capacitor Co can be implemented using any capacitor structure, such as two metal conductor plates separated by a dielectric or one or more transistors with drain and source terminals electrically shorted, where the drain / source terminals are used as the first plate of the capacitor and the gate of the transistor is used as the second plate of the capacitor, as understood by one of ordinary skill in the art. Other capacitor structures can be used, as understood by one of ordinary skill in the art.

[0046] The controller 110 is configured to receive a reference voltage Vref and an output voltage VO of the power conversion circuit 100. As understood by one of ordinary skill in the art, in some embodiments, the controller 110 can be configured to receive a voltage generated based on the output voltage VO rather than the output voltage VO itself. The controller 110 is also configured to receive a clock signal CLK. Based on the clock signal CLK, the reference voltage Vref, and the output voltage VO, the controller 110 is configured to generate a control signal for each of the high-side switch SI and the low-side switch S2. For example, the controller 110 can be configured to generate a pulse width modulation (PWM) signal that controls the conductive state of the high-side switch SI and the low-side switch S2. The controller 110 can be configured to generate control signals for the high-side switch SI and the low-side switch S2.

[0047] Each of the high-side switch SI and the low-side switch S2 can be configured to respond to a control signal received from the controller 110 by becoming conductive or non-conductive. In some embodiments, each of the high-side switch SI and the low-side switch S2 is configured to become conductive or non-conductive in response to a control signal and in response to an electrical condition of the high-side switch SI or the low-side switch S2. For example, either or both of the high-side switch SI and the low-side switch S2 can be configured to receive a control signal from the controller 110 and wait for a particular electrical condition to occur before becoming conductive or non-conductive according to the control signal.

[0048] As understood by one of ordinary skill in the art, a control signal includes an open control signal configured to cause the high-side switch SI or the low-side switch S2 to become non-conductive and a closed control signal configured to cause the high-side switch SI or the low-side switch S2 to become conductive.

[0049] An electrical condition can include, for example, that the high-side switch SI or the low-side switch S2 is conducting current, not conducting current, or specifically conducting current in either direction. In some embodiments, an electrical condition can include that the high-side switch SI or the low-side switch S2 is conducting current greater or less than a threshold current.

[0050] In some embodiments, an electrical condition can additionally or alternatively include that a voltage across the drain and source terminals of the high-side switch SI or the low-side switch S2 is greater or less than a threshold voltage.

[0051] In some embodiments, the high-side switch SI can be configured to receive an open control signal from the controller 110 and become non-conductive in response to an electrical condition that the current through the high-side switch SI is less than a threshold current. Thus, after the high-side switch SI receives an open control signal from the controller 110, a delay duration occurs before becoming non-conductive.

[0052] Additionally or alternatively, in some embodiments, low-side switch S2 can be configured to receive a turn-off control signal from controller 110 and become non-conductive in response to an electrical condition in which the current through low-side switch S2 is less than a threshold current. Thus, a delay duration occurs before low-side switch S2 becomes non-conductive after receiving the turn-off control signal from controller 110.

[0053] In the current approach, a controller can control the turn-on and turn-off times of the switches used in a power converter. In the present disclosure, a switch can automatically and autonomously detect the operating state in which it is, i.e., control mode or synchronization mode. Moreover, if the switch determines that it is operating in synchronization mode, it can turn off by itself independent of a control signal from the controller commanding the switch to turn off. Conversely, a synchronization switch can monitor the current flowing through its drain to source and turn off by itself when the current changes direction and reaches a magnitude determined by the instantaneous value of the input line voltage and the resistance value of the resistor.

[0054] Figure 2 A simplified schematic illustration of the operating conditions of the circuit of Figure 1 When operating in the conditions shown, the AC power input signal is positive, high-side switch S1 is non-conductive, and low-side switch S2 is conductive. Figure 2

[0055] Thus, as shown in Figure 2 the current flows from the positive terminal of the AC source of Vac, through inductor L, through low-side switch S2 in the positive direction, through diode D2, through the power conversion circuit 100 to the negative terminal of the AC source Vac.

[0056] When operating in the illustrated conditions, in response to receiving a turn-off control signal from controller 110, because the polarity of the AC power input signal is positive, the current flows in the indicated direction, and low-side switch S2 becomes non-conductive immediately or substantially immediately, or it becomes non-conductive regardless of the electrical state of low-side switch S2, which would cause a delay in the other operating conditions. The embodiments of a switch that can be used as low-side switch S2 are discussed below with reference to Figure 6

[0057] Figure 3 A simplified schematic illustration of the operating conditions of the circuit of Figure 1 When operating in the illustrated conditions, the AC power input signal is positive, high-side switch S1 is conductive, and low-side switch S2 is non-conductive. Figure 3

[0058] Thus, as shown in Figure 3 ​​​As shown, current flows from the positive terminal of the AC source of Vac, through the inductor L, through the power conversion circuit 100 in the negative direction to the positive plate of the capacitor Co via the high-side switch S1. In addition, current flows from the negative plate of the capacitor Co, through the diode D2 to the negative terminal of the AC source Vac.

[0059] When operating in the illustrated conditions, in response to receiving the off control signal from the controller 110, the high-side switch S1 does not immediately become non-conductive because the polarity of the AC power input signal is positive. Rather, the high-side switch S1 becomes non-conductive after additionally experiencing an electrical condition of a positive current flowing through the high-side switch S1 being greater than a threshold value. Alternatively, using the convention illustrated in Figure 2 the high-side switch becomes non-conductive after additionally experiencing an electrical condition of a negative current flowing through the high-side switch S1 being less than a threshold value.

[0060] Figure 4 A simplified schematic illustration of the operating conditions of the circuit of Figure 1 is shown in FIG. 2. When operating in the illustrated conditions, the AC power input signal is positive, the high-side switch S1 is conductive, and the low-side switch S2 is non-conductive. Figure 4

[0061] Thus, as shown, current flows from the negative terminal of the AC source of Vac, through the power conversion circuit 100 via the diode D1 to the positive plate of the capacitor Co via the high-side switch S1. In addition, current flows from the negative plate of the capacitor Co, through the inductor L to the positive terminal of the AC source Vac via the low-side switch S2. Figure 4 When operating in the illustrated conditions, in response to receiving the off control signal from the controller 110, current flows in the indicated direction and the high-side switch S1 immediately or substantially immediately becomes non-conductive, or becomes non-conductive regardless of the electrical state of the high-side switch S1, which would cause a delay in the other operating conditions. The following discusses embodiments of switches that can be used as the high-side switch S1.

[0062] Figure 6 A simplified schematic illustration of the operating conditions of the circuit of

[0063] is shown in FIG. 3. When operating in the illustrated conditions, the AC power input signal is negative, the high-side switch S1 is non-conductive, and the low-side switch S2 is conductive. Figure 5 Figure 1 Figure 5 Thus, as shown, current flows from the negative terminal of the AC source of Vac, through the power conversion circuit 100 via the diode D1 to the positive plate of the capacitor Co. In addition, current flows from the negative plate of the capacitor Co, through the inductor L to the positive terminal of the AC source Vac via the low-side switch S2.

[0064] Figure 5 Thus, as shown, current flows from the negative terminal of the AC source of Vac, through the power conversion circuit 100 via the diode D1 to the positive plate of the capacitor Co. In addition, current flows from the negative plate of the capacitor Co, through the inductor L to the positive terminal of the AC source Vac via the low-side switch S2.

[0065] ​​​​When operated under the conditions illustrated, in response to receiving a turn-off control signal from controller 110, low-side switch S2 does not immediately become non-conductive because the polarity of the AC power input signal is negative. Instead, low-side switch S2 becomes non-conductive after additionally experiencing an electrical condition of a positive current flowing through low-side switch S2 being greater than a threshold value. Alternatively, using Figure 2 The convention illustrated, low-side switch S2 becomes non-conductive after experiencing an electrical condition of a negative current flowing through low-side switch S2 being less than a threshold value.

[0066] Figure 6 A simplified schematic illustration of a variable current threshold switching circuit 600 according to embodiments of the present disclosure. In switching circuit 600, the threshold for detecting a current condition of a switch can be variable and is based on the input line voltage. In some embodiments, the threshold can be based on a difference between the value of the output voltage VO in circuit 100 and the input line voltage. Switching circuit 600 can include a drive circuit 610 and a current sense switching circuit 620. Current sense switching circuit 620 can include a first switch 630 and a second switch 622. In some embodiments, first switch 630 can be a power field effect transistor (FET) capable of carrying a relatively large current, while second switch 622 can be a sense FET capable of sensing a relatively small portion of the total current flowing through current sense switching circuit 620. The ratio of the active area size of switch 622 to the active area size of switch 630 can be less than 1.0. In various embodiments, first switch 630 and second switch 622 can be integrated on the same die. In some embodiments, first switch 630 and second switch 622 can be GaN-based transistors integrated on the same die. Switching circuit 600 can be used as either or both of high-side switch SI and low-side switch S2 in power conversion circuit 100. Figures 1 to 5

[0067] ​In some embodiments, the switching circuit 600 can be formed of silicon, GaN, or any other suitable semiconductor material. In various embodiments, both the drive circuit 610 and the switching circuit 620 can be formed in a silicon substrate. In some embodiments, both the drive circuit 610 and the switching circuit 620 can be formed in a GaN substrate. In some embodiments, the drive circuit 610 can be formed in a silicon substrate while the switching circuit 620 can be formed in a GaN substrate. In various embodiments, both the drive circuit 610 and the switching circuit 620 can be integrally integrated onto a single die. In some embodiments, the drive circuit 610 and the switching circuit 620 can be formed on separate individual dies. In various embodiments, the drive circuit 610 and the switching circuit 620 can be integrated into one electronic package, such as, but not limited to, into a quad flat no-lead (QFN) package or a dual flat no-lead (DFN) package, a ball grid array (BGA) package. In some embodiments, the drive circuit 610 and the switching circuit 620 can be individually packaged into an electronic package.

[0068] In some embodiments, the first switch 630 can have a first gate terminal 636, a first drain terminal 632, and a first source terminal 634. The second switch 622 can have a second gate terminal 628, a second drain terminal 624, and a second source terminal 626. The first gate terminal 636 can be connected to the second gate terminal 628, where both gates are connected to the GATE IN terminal, the first drain 632 can be connected to the second drain terminal 624, where both drains are connected to the drain terminal DRAIN, and the first source terminal 634 can be connected to the second source terminal 626, where both source terminals are connected to the source terminal SOURCE. In various embodiments,

[0069] The current sense switching circuit 620 selectively conducts between its drain terminal DRAIN and its source terminal SOURCE according to a gate control signal at its gate terminal GATE IN. The current sense switching circuit 620 is also configured to generate a current sense signal at its current sense terminal CS. The current sense signal can be generated by causing a sense current Isense flowing through the second switch 622 to flow through a current sense device 644. The current sense device 644 can be connected between the terminal CS IN and the SOURCE terminal. In this way, a voltage indicative of the value of the current conducted between the drain terminal DRAIN and the source terminal SOURCE can be generated. In some embodiments, the current sense device 644 can be a resistor, while in alternative embodiments, the current sense device 644 can be a FET.

[0070] The drive circuit 610 can include a logic and gate drive circuit 612, a comparator 614, and a zero current reference generator 616.

[0071] The zero-current reference generator 616 can receive the reference voltage at node ZCD. The zero-current reference generator 616 can further receive a PWM indication signal corresponding to the gate control signal of the current sense switch circuit 620. In some embodiments, the reference voltage at node ZCD can be generated based on a current provided by the zero-current reference generator 616 to a resistor (not shown), such as a resistor external to a chip on which the zero-current reference generator 616 is formed.

[0072] Based on the reference voltage at node ZCD and the PWM indication signal, the zero- current reference generator 616 can generate a reference voltage Vzcd. Embodiments of the zero-current reference generator 616 are discussed in more detail below in Figure 10

[0073] In some embodiments, the PWM indication signal can be generated at node 650. In alternative embodiments, the zero-current reference generator 616 can generate a current sense reference voltage that is not based on the PWM indication signal.

[0074] The comparator 614 can receive the current sense signal Vcs from the current sense switch circuit 620 and can receive the current sense reference voltage Vzcd from the zero- current reference generator 616. The comparator 614 can generate a current detection signal based on the current sense signal Vcs and the current sense reference voltage Vzcd. In response to the current sense signal Vcs being greater than the current sense reference voltage Vzcd, the comparator 614 can generate the current detection signal indicating that positive current is flowing from the drain to the source of the current sense switch circuit 620 and the current value is greater than a current threshold, or negative current is flowing from the drain to the source of the current sense switch circuit 620 and the current value is less than a current threshold. In response to the current sense signal Vcs being less than the current sense reference voltage Vzcd, the comparator 614 can generate the current detection signal indicating that positive current is flowing from the drain to the source of the current sense switch circuit 620 and the current value is less than a current threshold, or negative current is flowing from the drain to the source of the current sense switch circuit 620 and the current value is greater than a current threshold.

[0075] ​The logic and gate drive circuit 612 receives a PWM signal, for example, from a controller (e.g., controller 110). The logic and gate drive circuit 612 also receives a current detection signal from the comparator 614. In response to a PWM signal indicating that the switch circuit 600 is to be off, the logic and gate drive circuit 612 generates an off output signal for the current sense switch circuit 620 only after the current detection signal additionally indicates that positive current flowing from the drain to the source of the current sense switch circuit 620 is greater than a current threshold, or that negative current flowing from the drain to the source of the current sense switch circuit 620 is less than a current threshold. In response to a PWM signal indicating that the switch circuit 600 is to be on, the logic and gate drive circuit 612 generates an on output signal for the current sense switch circuit 620 such that the current sense switch circuit 620 is on, regardless of the state of the current detection signal.

[0076] In some embodiments, the drive circuit 610 is integrated on a first die or integrated circuit chip, and the current sense switch circuit 620 is integrated on a second die or integrated circuit chip. For example, the first die or integrated circuit chip can include a silicon semiconductor substrate, and the second die or integrated circuit chip can include a gallium nitride (GaN) semiconductor substrate.

[0077] In some embodiments, the reference voltage at node ZCD can be used to cause the logic and gate drive circuit 612 to generate the GATE_OUT signal that is a delayed version of the signal at node PWM. For example, the voltage at node ZCD can be such that the voltage at node Vzcd is equal to a ground voltage. In some embodiments, the drive circuit 610 can include a comparator 614 that provides a signal to the logic and gate drive circuit 612 that causes the logic and gate drive circuit 612 to generate the GATE_OUT signal that is a delayed version of the signal at node PWM in response to the voltage at node ZCD being greater than a reference voltage.

[0078] Figure 7 For Figure 6 A simplified schematic illustration of the operation of the threshold switching circuit 600, where the circuit 600 is operating in a control mode.

[0079] At time Tl, the PWM signal goes high, indicating that the switch circuit 600 is to be on. In response, the logic and gate drive circuit 612 generates a high GATE_OUT signal that can be received by the current sense switch circuit 620 at the GATE_IN node, causing the current sense switch circuit 620 to be on. The high GATE_OUT signal is generated regardless of the state of the current detection signal.

[0080] In response to the current sense switch circuit 620 turning on, the drain-to-source current Idrain of the current sense switch circuit 620 increases. In addition, the current sense signal Vcs generated by the current sense switch circuit 620 also increases. Furthermore, once the current sense signal Vcs is greater than the threshold voltage Vzcd generated by the zero current reference generator 616, the current sense signal indicates that the positive current flowing from the drain to the source of the current sense switch circuit 620 is greater than the current threshold.

[0081] At time T2, the PWM signal goes low, indicating that the switch circuit 600 will or has become non-conductive. In response, the logic and gate drive circuit 612 generates a low GATE_OUT signal for the current sense switch circuit 620, such that the current sense switch circuit 620 does not conduct. Since the current sense signal has indicated that the positive current flowing from the drain to the source of the current sense switch circuit 620 is greater than the current threshold, the high GATE_OUT signal is generated substantially immediately.

[0082] Thus, when the switch 600 is used as a high-side switch SI or a low-side switch S2 of the power conversion circuit 100 and operated as described above with reference to Figure 7 the high-side switch SI or the low-side switch S2 behaves as a control FET of the power conversion circuit 100.

[0083] Figure 8 For a simplified schematic illustration of the operation of the threshold switching switch circuit 600, where the circuit 600 operates in a synchronous mode. Figure 6

[0084] At time Tl, the PWM signal goes high, indicating that the switch circuit 600 will conduct. In response, the logic and gate drive circuit 612 generates a high GATE_OUT signal, which can be received by the current sense switch circuit 620 at the GATE_IN node, such that the current sense switch circuit 620 conducts. The high GATE_OUT signal is generated regardless of the state of the current sense signal.

[0085] In response to the current sense switch circuit 620 turning on, the drain-to-source current Idrain of the current sense switch circuit 620 increases from an initial negative value. In addition, the current sense signal Vcs generated by the current sense switch circuit 620 also increases.

[0086] At time T2, the PWM signal goes low, indicating that the switch circuit 600 will or has become non-conductive. The logic and gate drive circuit 612 does not generate a low GATE_OUT signal for the current sense switch circuit 620, such that the current sense switch circuit 620 does not conduct in response to the PWM signal going low, since the current sense signal Vcs is less than the threshold voltage Vzcd generated by the zero current reference generator 616. ​

[0087] At time T3, the current sense signal Vcs becomes greater than the threshold voltage Vzcd, and the current detection signal indicates that the positive current flowing from the drain to the source of the current sense switch circuit 620 is greater than the current threshold. In response to the low level of the PWM signal and the current detection signal, the logic and gate drive circuit 612 generates a low GATE_OUT signal for the current sense switch circuit 620, such that the current sense switch circuit 620 is not turned on.

[0088] Thus, when the switch 600 is used as the high-side switch SI or the low-side switch S2 of the power conversion circuit 100 and operates as described above with reference to Figure 8 The high-side switch SI or the low-side switch S2 behaves as a synchronous FET of the power conversion circuit 100.

[0089] Thus, when an instance of the switch 600 is used as the high-side switch SI and the low-side switch S2 of the power conversion circuit 100, each of the high-side switch SI and the low-side switch S2 operates automatically, as described above with reference to Figure 7 and Figure 8 Thus, in these embodiments, each of the high-side switch SI and the low-side switch S2 can automatically function or can be controlled to automatically function as a synchronous FET of the power conversion circuit 100 or as a control FET of the power conversion circuit 100.

[0090] For example, when the power conversion circuit 100 operates under the conditions described with reference to Figure 2 the low-side switch S2 can operate as a control FET and the high-side switch SI can operate as a synchronous FET. In addition, when the power conversion circuit 100 operates under the conditions described with reference to Figure 3 the low-side switch S2 can operate as a control FET and the high-side switch SI can operate as a synchronous FET. Furthermore, when the power conversion circuit 100 operates under the conditions described with reference to Figure 4 the low-side switch S2 can operate as a synchronous FET and the high-side switch SI can operate as a control FET, and when the power conversion circuit 100 operates under the conditions described with reference to Figure 5 the low-side switch S2 can operate as a synchronous FET and the high-side switch SI can operate as a control FET.

[0091] In some embodiments, based on the value of the input voltage across the AC source Vac and / or based on the value of the corresponding current sense signal Vcs, the controller 110 of the power conversion circuit 100 can ensure that the PWM signal goes low for or about when the switch operating as a control FET is turned off, as described above with reference toFigure 7 As explained. Moreover, the controller 110 of the power conversion circuit 100 can ensure that the PWM signal goes low for the switch operating as a synchronous FET before the switch is turned off as a synchronous FET operation, as Figure 8 As explained. For example, the controller 110 of the power conversion circuit 100 can ensure that the PWM signal goes low for the switch operating as a synchronous FET while the corresponding current sense signal Vcs indicates that the drain current is negative in the switch operating as a synchronous FET, as Figure 8 As explained.

[0092] Accordingly, in some embodiments, the pulse width of the PWM signal can differ depending on whether the switch turned on by the pulse of the PWM signal is operating as a synchronous FET or a control FET. For example, the pulse width of the PWM signal turning on a synchronous FET can be shorter than the pulse width of the PWM signal turning on a control FET. The pulse width of the PWM signal controlling a FET operating in synchronous mode can be shorter because the FET operating in synchronous mode can automatically and autonomously determine its turn-off time, i.e., the falling edge of the PWM signal received from the controller is not determinative for the synchronous FET. Instead, the synchronous FET can monitor the current flowing through its drain to source and turn off when the current changes direction, i.e., the current flows in reverse through the inductor L, and reaches a magnitude determined by the instantaneous value of the line voltage. In some embodiments, the magnitude of the current can be further determined by a resistor, e.g., an external resistor.

[0093] As understood by one of skill in the art, in various embodiments, the pulse width of the PWM signal can be the same or substantially the same regardless of whether the switch turned on by the pulse of the PWM signal is operating as a synchronous FET or a control FET.

[0094] In some embodiments, each of a series of consecutive PWM signals goes low before the corresponding current sense signal Vcs becomes greater than the threshold voltage Vzcd of the high-side switch S1 and the low-side switch S2 of the power conversion circuit 100. In these embodiments, the high-side switch S1 and the low-side switch S2 act as synchronous FETs of the power conversion circuit 100, as understood by one of skill in the art.

[0095] Figure 9A flowchart of an exemplary method 900 for determining the state of a power switch in a converter circuit and a power switch turn-off method according to embodiments of the present disclosure is illustrated. At block 910, the switch circuit receives a turn-off PWM signal, i.e., the PWM signal goes low. At block 920, the switch can generate a threshold signal (Vzcd) based on the input line voltage. This threshold signal varies with the input line voltage. For example, in a bridgeless PFC circuit, the input voltage Vac can vary, causing the threshold signal Vzcd to vary according to the instantaneous value of Vac. When the input voltage Vac has a relatively high value, e.g., 240V, the value of the signal Vzcd can be relatively high. In this way, the amount of energy used to bring the switch node Vs down to ground can depend on the input line voltage Vac, such that the optimal amount of current will be allowed to flow into the inductor L.

[0096] Determining the optimal amount of energy used to bring the switch node Vs down to ground can enable zero voltage switching (ZVS) in the power converter, improving the efficiency of the power converter. When the input line voltage Vac is at its peak, more current can be allowed to flow into the inductor L, such that a relatively higher charge in the inductor L can be used to transition the switch node Vs from a relatively high voltage, e.g., 400V, to ground. Embodiments of the present disclosure implement a variable threshold signal generator that can allow the switch circuit to determine the turn-off point of the current flowing into the inductor L in synchronous mode. The variable threshold signal can depend on the input line voltage. Thus, at relatively high input voltage Vac, the switch circuit can allow an increased amount of reverse current to flow into the inductor L, and at relatively low input line voltage, the switch circuit can allow a decreased amount of reverse current to flow into the inductor L.

[0097] At block 930, the switch circuit can generate a current sense signal based on at least one of the direction and magnitude of the current flowing through the switch. The current sense signal can be generated by sampling and feeding a relatively small amount of current passing through the switch circuit to the current sense device 644.

[0098] At block 940, the value of the current sense signal can be compared to the value of the threshold signal. In some embodiments, a comparator circuit can be used to perform this comparison. If the value of the current sense signal is greater than the value of the threshold signal, the switch circuit can turn off immediately in response to the PWM signal going low at block 950. If the value of the current sense signal is not greater than the value of the threshold signal, the switch circuit can not turn off immediately in response to the PWM signal going low at block 960. The switch circuit can wait until the value of the current sense signal becomes greater than the value of the threshold signal, at which point the switch circuit turns off at block 970.

[0099] It should be understood that Method 900 is illustrative, and variations and modifications are possible. The steps described in sequence can be performed in parallel, the order of the steps can be changed, and the steps can be modified, combined, added, or omitted.

[0100] Figure 10 This is a simplified schematic illustration of a zero-current reference voltage generator 1000 according to an embodiment of this disclosure. The zero-current reference voltage generator 1000 can be used as... Figure 6 A zero-current reference generator 616 is used to generate a reference voltage Vzcd. In some embodiments, a resistor 1080 may be used to set the value of Vzcd. In some embodiments, the resistor 1080 may not be integrated on the same die as other components of the zero-current reference voltage generator 1000. The zero-current reference voltage generator 1000 may include a resistor 1020 with a resistance of R, a low-pass filter circuit 1030, and switches 1040, 1050, and 1060. Switches 1040, 1050, and 1060 may be FETs. In various embodiments, switch 1040 may be an N-MOSFET, while switches 1050 and 1060 may be P-MOSFETs. Switches 1050 and 1060 may be arranged in a current mirror configuration. Alternative reference voltage generators may be used.

[0101] As will be understood by those skilled in the art, the low-pass filter circuit 1030 can be any low-pass filter circuit. The low-pass filter circuit 1030 can receive a PWM signal and can generate an output at node 1070 corresponding to the duty cycle of the received PWM signal. In some embodiments, such as in... Figure 6 As explained, the received PWM signal can be the GATE_OUT signal at node GATE_OUT. In an alternative embodiment, the received PWM signal can be... Figure 6 The PWM indication signal at the described node PWM. In some embodiments, a control signal may be used as the received PWM signal.

[0102] In the illustrated embodiment, an external ZCD resistor can be connected to switch 1050 arranged in a diode-connected configuration. Current through switch 1050 and resistor 1080 can be mirrored to produce current 1095 (I) through switch 1060 and resistor 1020. Voltage at node 1090 (Vzcd) will equal I*R. As the pulse width of the PWM signal gets longer, the voltage at node 1070 can increase. When the voltage at node 1070 exceeds a value equal to I*R plus the threshold voltage of switch 1040, the voltage at node 1090 can begin to increase. In this way, modulation of Vzcd with PWM duty cycle can be achieved. Further, Vzcd can track the input line voltage, as the PWM duty cycle can represent the input line voltage when the output voltage VO is fixed. In some embodiments, when the output voltage VO is not fixed, the PWM duty cycle can represent the difference between the output voltage VO and the input line voltage. Thus, Vzcd can vary with the input line voltage and the output voltage VO. Those skilled in the art with the benefit of this disclosure will appreciate that alternative methods can be used to affect modulation of Vzcd based on the input line voltage, and that such methods are within the scope of this disclosure.

[0103] Thus, in response to a PWM signal having a relatively low duty cycle, zero-current reference voltage generator 1000 can produce a relatively low reference voltage value at output node Vzcd. Similarly, in response to a PWM signal having a relatively high duty cycle, zero-current reference voltage generator 1000 can produce a relatively high reference voltage value at output node Vzcd.

[0104] A beneficial result of zero-current reference voltage generator 1000 producing a reference voltage value that depends on the PWM signal is that the reference voltage value can be modified to reduce or eliminate or substantially eliminate overcurrent used to charge or discharge node Vs, where node Vs is a connection node between switches SI and S2.

[0105] During a period when both switch SI and switch S2 are open, current through inductor L can cause the voltage at node Vs to increase or decrease, depending on the direction of the current. At least to reduce noise, switching loss, and conduction loss, switch S2 is best turned on when the voltage at node Vs decreases to equal the ground voltage. Similarly, at least to reduce noise, switching loss, and conduction loss, switch SI is best turned on once the voltage at node Vs increases to equal the output voltage at output node VO.

[0106] Insufficient current through inductor L can cause switch SI or switch S2 to turn on before the voltage at node Vs transitions to the best ground voltage or output voltage. Excessive current through inductor L can cause switch SI or switch S2 to turn on after the voltage at node Vs transitions beyond the best ground voltage or output voltage. Thus, insufficient or excessive current through inductor L is undesirable.

[0107] During a voltage transition at node Vs, the current value through inductor L is affected by the input voltage value across AC source Vac. Thus, the voltage value at node Vs when switch S2 or switch SI is subsequently turned on can depend on the value of the input voltage and the current through inductor L when switch SI or switch S2 is turned off. Thus, to reduce, eliminate, or substantially eliminate variations in the voltage value at node Vs when switch S2 or switch SI is subsequently turned on, the relative timing of when switch SI or switch S2 is turned off can be varied to adjust the current through inductor L when switch SI or switch S2 is turned off.

[0108] For example, if the value of the input voltage is relatively high, the relative timing of when either of switch SI or switch S2 is turned off can be delayed to allow the current through inductor L to be increased when either of switch SI or switch S2 is turned off. Similarly, if the value of the input voltage is relatively low, the relative timing of when either of switch SI or switch S2 is turned off can be advanced to reduce the current through inductor L when switch SI or switch S2 is turned off.

[0109] In some embodiments, controller 110 can vary the duty cycle of the PWM signal such that the duty cycle of the PWM signal corresponds to the voltage input value across AC source Vac. Thus, the duty cycle of the PWM signal can be used to affect the reference voltage value at node Vzcd such that the reference voltage value at node Vzcd is varied to modify the current through inductor L when switch SI or switch S2 is turned off to reduce, eliminate, or substantially eliminate variations in the voltage transition duration at node Vs caused by variations in the input voltage.

[0110] An advantageous result of zero-current reference voltage generator 1000 generating a reference voltage value that depends on the duty cycle of the PWM signal is that the reference voltage value can be modified to reduce or eliminate or substantially eliminate variations in the voltage value at node Vs when switch S2 or switch SI is turned on.

[0111] In some embodiments, controller 110 can vary the duty cycle of the PWM signal such that the duty cycle of the PWM signal corresponds to the voltage input value across AC source Vac. Thus, in some embodiments, the duty cycle of the PWM signal can be used to affect the reference voltage value at node Vzcd such that the reference voltage value at node Vzcd is varied to eliminate or substantially eliminate variations in the voltage value at node Vs when switch S2 or switch SI is turned on. As a result, energy in the output voltage at node Vo that occurs at the frequency of the input voltage across AC source Vac is reduced or eliminated or substantially eliminated.

[0112] Furthermore, because the reference voltage value at Vzcd can be based on I*R, the reference voltage value at the output node Vzcd can have a minimum value determined by the current of the current flowing through switch 1060 and resistor 1020.

[0113] Thus, in the illustrated embodiment, the reference voltage value generated at the output node Vzcd can be modified according to changes in the duty cycle of the PWM signal. In alternative embodiments, the reference voltage value generated at the output node Vzcd does not change with changes in the duty cycle of the PWM signal. For example, in alternative embodiments, the reference voltage generator can generate a fixed or substantially fixed reference voltage at the output node Vzcd.

[0114] When the power switch is operated in synchronous mode, embodiments of the disclosure can enable the power switch to determine its off time independently of the controller 110. This is in contrast to the current approach in which the controller can control the on and off times of the power switch. This places a relatively high computational load on the controller and increases the system cost in the current approach.

[0115] Embodiments of the disclosure can enable efficient operation of the power converter. The synchronous switch can be held beyond the point at which the current in the power conversion inductor can reach zero, so that some reverse current can be established in the power conversion inductor. In this way, when the synchronous power switch is turned off and some energy has accumulated in the power conversion inductor, the switch node can be soft transitioned from a relatively high voltage to a relatively low voltage, causing the control power switch to be turned on with zero or substantially zero voltage across it. This allows zero voltage switching (ZVS) operation and can improve the efficiency of operation of the power converter.

[0116] In some embodiments, the amount of energy accumulated in the power conversion inductor can vary with the instantaneous value of the input line voltage. In various embodiments, the amount of energy accumulated in the power conversion inductor can vary with the difference between the value of the output voltage and the instantaneous value of the input line voltage. In some embodiments, the amount of energy accumulated in the power conversion inductor can be optimized so that the efficiency of operation of the power converter is improved. The optimal amount of energy accumulated in the power conversion inductor can be determined by the optimal amount of current flowing through the synchronous power switch to the power conversion inductor. In various embodiments, the power switch can autonomously determine this optimal amount of current by turning off on its own when the current changes direction and when the current reaches an amount determined by the instantaneous line voltage.

[0117] In some embodiments, the automatic and autonomous determination of the turn-off time of the synchronous power switch can reduce the computational load on the controller 110, thereby increasing the control loop bandwidth and reducing the system cost. The controller 110 can obtain information about the synchronous mode of operation based on the polarity of the input AC line. The controller 110 can then send a relatively short PWM pulse to the synchronous power switch. When the power switch receives the PWM pulse before edge from the controller 110, it can turn off. When the PWM pulse after edge is received from the controller 110, the power switch can detect that it is in the synchronous mode and can not turn off by itself. The power switch can perform this detection by checking the direction of the current flowing from its drain to source. If this current is negative, the power switch can ignore the PWM pulse after edge. The power switch can monitor the current flowing from its drain to source and can turn off when the current changes direction, i.e., the current flows back to the power conversion inductor and reaches a value proportional to the instantaneous input line voltage. In various embodiments, this value can be proportional to the instantaneous input line voltage and a resistor, such as but not limited to an external resistor.

[0118] Once the synchronous power switch turns off, the switch node can soft transition to ground using the energy stored in the power conversion inductor. The synchronous power switch can send an indication signal to the controller 110 so that after the switch node has reached a value of zero or substantially zero volts, the controller 110 can know that the synchronous power switch turned off and can safely turn off the control power switch and start the next switching cycle.

[0119] As described in detail above, embodiments of the present disclosure can increase the control loop bandwidth of the power converter, thereby improving the performance of the power converter. In addition, a relatively simple controller can be used in the power converter, thereby reducing the system cost.

[0120] While various embodiments of the present application have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit of the application. Accordingly, the scope of the application is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0121] While this application has been disclosed through the use of specific embodiments, changes and modifications can be made to the embodiments disclosed without departing from the spirit and scope of the application.

Claims

1. A circuit comprising: a first circuit comprising: a first switch coupled between a power input node and a first terminal of a load; a first current sensing device arranged to transmit a first signal including at least one of a magnitude and a polarity of a first current passing through the first switch; and a first driver circuit arranged to transmit a first control signal to the first switch based at least in part on a voltage at the power input node and the first signal; and a second circuit comprising: a second switch coupled between the power input node and a second terminal of the load; a second current sensing device arranged to transmit a second signal including at least one of a magnitude and a polarity of a second current passing through the second switch, wherein the second current sensing device comprises a third switch coupled in parallel with the second switch; and a second driver circuit arranged to transmit a second control signal to the second switch based at least in part on the voltage at the power input node and the second signal.

2. The circuit of claim 1, wherein the first switch is a gallium nitride (GaN)-based switch.

3. The circuit of claim 1, wherein the second switch is a gallium nitride (GaN)-based switch.

4. The circuit of claim 1, wherein the first driver circuit comprises a first threshold generation circuit and the second driver circuit comprises a second threshold generation circuit.

5. The circuit of claim 4, wherein the first threshold generation circuit is arranged to generate a first threshold signal based on the voltage at the power input node.

6. The circuit of claim 5, wherein a value of the first threshold signal is based on a duty cycle of a pulse width modulated (PWM) signal received from a controller.

7. The circuit of claim 6, wherein the value of the first threshold signal is high when the duty cycle of the PWM signal is high.

8. The circuit of claim 6, wherein the value of the first threshold signal is low when the duty cycle of the PWM signal is low.

9. The circuit of claim 5, wherein the first driver circuit further comprises a first comparator arranged to receive the first threshold signal, and wherein the first comparator is further arranged to compare the first signal to the first threshold signal and generate a first current detection signal.

10. The circuit of claim 1, wherein the second driver circuit further comprises a second comparator arranged to receive a second threshold signal, and wherein the second comparator is further arranged to compare the second signal to the second threshold signal and generate a second current detection signal.

11. The circuit of claim 4, wherein the first threshold generation circuit comprises: a first transistor having a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is coupled to a first receive circuit; a first current mirror having a first input port and a first output port and arranged to replicate a first current of the first input port to the first output port; and a first resistor coupled to the first source terminal and the first output port.

12. The circuit of claim 11, wherein the first receive circuit comprises a low pass filter, and wherein the first drain terminal is coupled to a DC power source.

13. A method of operating a circuit, the method comprising: providing a first circuit comprising: a first power switch; a current sensor arranged to transmit a first signal indicative of at least one of a magnitude and a polarity of a first current passing through the first power switch; and a first driver circuit arranged to transmit a first control signal to the first power switch based at least in part on a voltage at a power input node and the first signal; providing a second circuit comprising: a second power switch; a second current sensor arranged to transmit a second signal indicative of at least one of a magnitude and a polarity of a second current passing through the second power switch, wherein the second current sensor comprises a third switch coupled in parallel with the second power switch; and a second driver circuit arranged to transmit a second control signal to the second power switch based at least in part on the voltage at the power input node and the second signal; and receiving a pulse width modulation (PWM) control signal for controlling operation of the first power switch and the second power switch; generating a first reference voltage based on a voltage of a power input node; and transmitting a first shutdown signal to the first power switch.

14. The method of claim 13, wherein transmitting the first shutdown signal to the first power switch occurs when the first signal is higher than the first reference voltage and when the first power switch receives a first controller shutdown signal.

15. The method of claim 14, further comprising: transmitting a second shutdown signal to the second power switch when the second signal is higher than a second reference voltage and when the second power switch receives a second controller shutdown signal.

16. The method of claim 13, wherein, the generating the first reference voltage based on the voltage of the power input node comprises: receiving the PWM control signal; and generating the first reference voltage based on a duty cycle of the PWM control signal and a resistance value of a first resistor.

17. The method of claim 16, wherein the generating the first reference voltage based on the voltage of the power input node further comprises: sending the received PWM control signal through a low pass filter and generating a first voltage corresponding to a duty cycle of the received PWM control signal; applying the first voltage to a gate terminal of a second transistor to modulate a first current passing through the second transistor; sending the modulated first current through the second transistor to the first resistor; and adding, by the first resistor, the modulated first current passing through the first resistor to a current from a first current mirror. ​ 18. The method of claim 17, further comprising selectively connecting the power input node to a first terminal of a load and a second terminal of the load.

19. The method of claim 18, wherein, the connection of the power input node to the first terminal of the load is performed when a drain terminal of the first power switch is approximately equal to a voltage at the first terminal of the load.

20. The method of claim 19, wherein, the connection of the power input node to the second terminal of the load is performed when a source terminal of the second power switch is approximately equal to a voltage at the second terminal of the load.

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