A ground comprehensive tester for measurement, control and communication

Abstract

The present invention provides a ground integrated tester for measurement and control communication, including: a host computer, used for configuring modulation and demodulation parameters and adjusting output signal power of an FPGA platform; used for sending baseband data streams to the FPGA platform and receiving and storing baseband data streams from the FPGA platform; and also used for monitoring and displaying the real-time status of the tester; an FPGA platform, used for completing the processing and modulation and demodulation of baseband data streams; used for configuring a radio frequency integrated platform, and also used for monitoring the link status; and a radio frequency integrated platform, used for completing up / down frequency conversion, filtering, low noise amplification and automatic gain control of signals. The advantages of the present invention are: the tester provided by the present invention has high integration, strong portability, and high reusability, and only needs simple additions, subtractions or changes to meet subsequent model requirements, reducing design difficulty and time cost.

Description

Technical Field

[0001] The invention belongs to the technical field of electronics, measurement, control and communication, and in particular relates to a ground comprehensive tester for measurement, control and communication. Background Art

[0002] While developing onboard equipment, it is often necessary to design or purchase ground detection equipment (referred to as ground detection) to cooperate with the debugging, testing and acceptance of onboard equipment.

[0003] In measurement and control communication tasks, the data format protocol, modulation method, data rate, and signal characteristics of each task are different, and even one task contains multiple modes.

[0004] The existing ground integrated tester for measurement, control and communication is large in size and not very convenient to carry, which is not conducive to field testing and on-site maintenance; the operation is relatively complicated and requires professional training to master the method of use, which increases the cost of use to a certain extent; moreover, the existing ground integrated tester for measurement, control and communication still has certain limitations in data processing and is difficult to meet the needs of complex testing tasks. The cost of using the existing ground integrated tester for measurement, control and communication is too high, and once the project requirements change, the workload of ground inspection developers will increase greatly. Therefore, it is very necessary to design a flexible, highly integrated, and highly portable ground integrated tester for measurement, control and communication to adapt to the work of various measurement, control and communication field model tasks. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the existing tester, such as inflexible configuration, poor versatility, weak portability and high cost.

[0006] In order to achieve the above-mentioned object, the present invention proposes a ground integrated tester for measurement, control and communication, which comprises: a host computer, an FPGA platform and a radio frequency integrated platform; wherein,

[0007] The host computer is used to configure the modulation and demodulation parameters and adjust the output signal power of the FPGA platform; to send the baseband data stream to the FPGA platform and to receive and store the baseband data stream from the FPGA platform; and to monitor and display the real-time status of the tester;

[0008] The FPGA platform is used to complete the processing and modulation and demodulation of the baseband data stream; to configure the RF integration platform, and to monitor the link status;

[0009] The RF integrated platform is used to receive the baseband data stream output by the FPGA platform, complete filtering, orthogonal up-conversion, and generate a RF analog signal; it is also used to complete low-noise amplification, orthogonal down-conversion, filtering and automatic gain control after receiving the RF signal, generate a digital intermediate frequency signal, and output it to the FPGA platform.

[0010] As an improvement of the above tester, the FPGA platform includes a PS end and a PL end;

[0011] The PS end includes data transmission modules DMA 0 and DMA 1, cache FIFO 0 and FIFO 1, and GPIO; wherein,

[0012] The data transmission module DMA 0 is used to receive the baseband data stream from the host computer and output it to the cache FIFO0;

[0013] The cache FIFO 0 is used to cache the baseband data stream received by the data transmission module DMA 0;

[0014] The data transmission module DMA 1 is used to obtain the baseband data stream from FIFO 1 and output it to the host computer;

[0015] The buffer FIFO 1 is used to buffer the baseband data stream output by the receiving subsystem;

[0016] The GPIO is used to exchange data between the host computer and the FPGA platform;

[0017] The PL end includes a transmitting terminal system and a receiving terminal system; wherein,

[0018] The transmitting subsystem is used to obtain the baseband data stream from the cache FIFO 0, perform frame synchronization, frame reorganization, encoding, scrambling and modulation, and then output it to the RF integration platform;

[0019] The receiving subsystem is used to receive the digital intermediate frequency signal sent by the radio frequency integration platform, perform demodulation, frame synchronization, descrambling and decoding, and then output it to the cache FIFO 1.

[0020] As an improvement of the above tester, the transmitting terminal system includes:

[0021] A frame synchronization module, used for receiving the baseband data stream sent by the PS end, completing the fixed frame length frame synchronization of the frame header shielding in the frame, and sending the processed baseband data stream to the reassembly frame module;

[0022] The reassembly frame module is used to identify the VCID of the current frame according to the frame format, count the current frame, fill the frame count into the corresponding position in the current frame, and output the frame enable signal, the identification to be encoded and the reassembly frame to the encoding module;

[0023] The encoding module is used to complete the encoding of the reassembled frame and output the encoded reassembled frame to the scrambling module;

[0024] a scrambling module, used to scramble the encoded recombined frame in units of frames, and output the scrambled data to the modulation module; and

[0025] The modulation module is used to complete the modulation of different modulation modes and different data rates in the corresponding mode for the scrambled data according to the modulation mode instruction sent by the host computer.

[0026] As an improvement of the above tester, the modulation module is also used to obtain the calibrated frequency deviation, sweep range, sweep rate, sweep zeroing and sweep start and stop parameters from the PS end to complete the frequency deviation and sweep setting of the data.

[0027] As an improvement of the above tester, the receiving terminal system includes:

[0028] A demodulation module, used for receiving a digital intermediate frequency signal sent by the radio frequency integration platform, demodulating the digital intermediate frequency signal, generating remote control log-likelihood ratio soft decision information, and outputting the information to a frame synchronization module;

[0029] A frame synchronization module is used to configure different frame synchronization parameters according to the demodulation mode provided by the host computer; perform fixed-length frame synchronization on the remote control log-likelihood ratio soft decision information, provide a frame synchronization identifier, and output the frame-synchronized data to the descrambling module;

[0030] A descrambling module, used to descramble the scrambled area of ​​the data after frame synchronization, and output the descrambled data to the pre-decoding processing module;

[0031] The pre-decoding processing module is used to remove the frame header of the valid frame of the descrambled data to generate a frame of fixed length, and after setting processing, it is output to the decoding module after serial-to-parallel conversion;

[0032] A decoding module, used to decode the data according to the decoding rules, and output the decoded data and the status indication of the decoding result to the post-decoding processing module;

[0033] The post-decoding processing module is used to perform parallel-to-serial conversion on the decoded data, and after setting processing, add a frame header according to the data frame format to form a transmission frame of fixed length and output it to the PS end.

[0034] As an improvement of the above-mentioned tester, when the decoding module performs decoding, if the decoding is correct, the correctly decoded frames are counted, and the good frame count is displayed in real time on the host computer; if the decoding is wrong, the incorrectly decoded frames are counted, and the bad frame count is displayed in real time on the host computer; if the decoding is correct and the data frame type is the proxy remote control reception count, the proxy remote control frames are counted.

[0035] As an improvement of the above-mentioned tester, the demodulation module is also used to output telemetry reflecting the current signal quality to the PS end, which is displayed in real time by the host computer; the telemetry includes frequency deviation telemetry, lock judgment value, demodulation lock indication, AGC gain and Eb / N0.

[0036] As an improvement of the above tester, the FPGA platform performs RF integrated platform configuration, including:

[0037] When the tester is powered on, the FPGA platform first completes a one-time configuration of the RF integration platform;

[0038] During the operation of the tester, the FPGA platform receives the dynamic parameter configuration sent by the host computer and dynamically configures the parameters of the RF integration platform.

[0039] The main configuration parameters include: modulation / demodulation mode, sweep range, sweep rate, sweep zero / start / stop, frequency deviation setting and AD9364 insertion loss setting.

[0040] As an improvement of the above tester, the host computer supports reading file import data and field configuration data.

[0041] As an improvement of the above tester, the tester supports selection of different baseband data sources, and supports a single baseband data source or multiple baseband data sources to send data simultaneously.

[0042] As an improvement of the above tester, the host computer communicates with the FPGA platform via an Ethernet interface; the FPGA platform and the RF integration platform are connected via an interconnection interface between FMC high-speed boards.

[0043] Compared with the prior art, the advantages of the present invention are:

[0044] 1. The present invention has high integration and strong flexibility. First, the present invention can support reading files (single file or multiple files) to import data and configure data on site; second, it has real-time storage function; third, it has mode switching function, and can switch modes through manual configuration (multiple modulation and demodulation modes, multiple data rates); fourth, it has real-time display of telemetry description of each state of the current link; fifth, parameters can be dynamically configured (sweep range, sweep rate, frequency deviation setting, sweep zeroing / start and stop, etc.); sixth, signal output power can be set in real time, with a power step of 0.25dB, an attenuation range of: 0 to -89.75dB, and the default setting is -40dB when powered on.

[0045] 2. The present invention has strong portability, high reusability, and IP-based functional modules. It only needs simple additions, subtractions or modifications to meet the needs of subsequent model tasks, greatly reducing the design difficulty and time cost of developers.

[0046] 3. The hardware used in the present invention is based on the ZYNQ+AD9364 platform, which has low cost, small size, light weight, and is easy to carry and transport during docking tests and other processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 The system structure block diagram of the ground integrated tester for measurement, control and communication is shown;

[0048] Figure 2 The following is the definition of the AOS frame format of the ground integrated tester for measurement, control and communication;

[0049] Figure 3 The figure shows the upper computer operation interface of the ground integrated tester for measurement, control and communication;

[0050] Figure 4 Shown is the software operation flow chart of the measurement, control and communication ground integrated tester. DETAILED DESCRIPTION

[0051] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0052] The present invention proposes a ground integrated tester for measurement and control communication, which can simulate the single-machine characteristics and behaviors of intersatellite link communication with the communication subsystem, and can also simulate the channel characteristics of the radio frequency link, and can be used as a general ground test for measurement and control communication type number tasks. The tester is connected to the communication subsystem in a radio frequency wired manner, and does not involve a wireless connection including an antenna.

[0053] The core components of the ground integrated tester include: FPGA platform, host computer and RF integration platform; among them, the FPGA platform is used to complete baseband data stream processing (frame synchronization, encoding and decoding, scrambling and descrambling, group deframing), modulation and demodulation, Ethernet communication, RF integration platform configuration and link status monitoring and other functions; the host computer is used to complete modulation and demodulation parameter configuration, output signal power adjustment, baseband data source sending and receiving storage, Ethernet communication and real-time monitoring and display of system status and other functions; the RF integration platform completes up / down conversion, filtering, low noise amplification (LNA), automatic gain control (AGC) and other functions.

[0054] At the transmitting end, FPGA receives data from the host computer, and the data transmission module DMA0 takes out the data from the PS end ARM, caches it through the first-in-first-out buffer FIFO 0, and outputs continuous data. The baseband data output by FIFO 0 is output to the modulation end for processing. The baseband data first passes through the frame synchronization module, the reframe module, the encoding module, and the scrambling module to complete the data link layer processing.

[0055] The frame synchronization module receives the data stream (in bytes) sent by the ARM end, completes the fixed frame length frame synchronization with the frame header masked in the frame, where the frame header is 1ACFFC1D and the frame length is 1024B, and outputs continuous frames starting with the frame header.

[0056] The reassembled frame module identifies the VCID of the current frame according to the frame format, counts the current frame, and then fills the frame count into the corresponding position in the current frame. The reassembled frame undergoes 8bit-1bit parallel-to-serial conversion, and outputs the frame enable signal, the identifier to be encoded, etc. The serial number corresponding to the VCID identifier sent by the host computer to the ARM end is received, and the frame count of this type of frame is returned to the ARM end to the host computer GPIO (General Purpose Input / Output) 18, and the host computer displays it in real time.

[0057] The encoding module completes the encoding of the reassembled frame.

[0058] The scrambling module scrambles the encoded data in frames, and all parts of the frame format except the synchronization header are scrambled.

[0059] The scrambled data is sent to the modulation module, which is divided into task mode and non-task mode. The modulation module completes the modulation algorithms of different modulation modes and different data rates in the corresponding mode according to the modulation mode instructions sent by the host computer.

[0060] At the receiving end, the FPGA receives the digital intermediate frequency signal received by the Rx data interface of the RF integration platform. The signal is first demodulated by the demodulation module. The demodulation module is divided into task mode and non-task mode. The demodulation module completes the demodulation algorithm of different modulation modes and different data rates in the corresponding mode according to the demodulation mode instruction sent by the host computer. And output telemetry reflecting the current signal quality, such as Eb / N0, AGC gain, frequency deviation telemetry, etc.

[0061] The demodulated baseband data is processed at the data link layer by the frame synchronization module, the descrambling module, the pre-decoding processing module, the decoding module, and the post-decoding processing module.

[0062] The frame synchronization module receives the remote control log-likelihood ratio soft decision information (remote control data stream) output by the demodulation module, performs fixed-length frame synchronization on the remote control data stream, and gives a frame synchronization identifier. Different frame synchronization parameters (number of error tolerance bits, number of checks, number of synchronization outages) are configured according to the demodulation mode switched by the host computer to the ARM end. In addition, the frame synchronization module can adapt to the situation where the remote control data stream is I / Q inverted; and perform phase ambiguity correction on frames with phase ambiguity.

[0063] The descrambling module receives the data transmission frame sent by the frame synchronization module and descrambles the original scrambled area.

[0064] The pre-decoding processing module removes the 32-bit frame header of the descrambled valid frame to convert it into a frame of 8160 length, and after processing, sends it to the decoding module through serial-to-parallel conversion.

[0065] The decoding module decodes according to the decoding rules, outputs the decoded data, and gives a status indication of the decoding result: idle state, correct decoding, and decoding error.

[0066] The post-decoding processing module converts the decoded data into parallel and serial data, and adds a 32-bit frame header according to the data frame format after processing to form an 8192-bit transmission frame. After the 1-bit-8-bit serial-to-parallel conversion, the transmission frame is sent to the first-in-first-out buffer FIFO 1 cache, and then sent to the ARM on the PS side through the data transmission module DMA 1. Finally, the host computer receives the data and completes the storage. The post-decoding processing module provides status information such as good frame count, bad frame count, and remote control reception frame count.

[0067] FPGA sends various working status information of the current link to the GPIO on the ARM side, and finally displays it on the host computer.

[0068] FPGA completes the configuration, transmission and reception of AD9364. Among them, when the device is powered on, the state machine in the FPGA first completes the one-time configuration of AD9364, and the configuration information is stored in the coe file in the ROM. The coe file includes the configuration information of all registers of AD9364 and the actions of the state machine (read, write, read back verification, monitoring). In addition to the one-time configuration at power-on, FPGA supports receiving the "AD9364 insertion loss setting" parameters sent by the host computer to complete the dynamic configuration of the transmission signal power. According to the AD9364 interface and characteristics, the timing control of the transmitter / receiver / SPI interface is completed to complete the transmission and reception of the signal.

[0069] The host computer supports dynamic parameter configuration, and the main configuration parameters include: modulation / demodulation mode, sweep range, sweep rate, sweep zeroing / start / stop, frequency deviation setting, AD9364 insertion loss setting, etc. These parameters are transmitted to FPGA through ARM's GPIO, and FPGA completes the corresponding configuration according to the pre-agreed protocol.

[0070] The host computer supports reading file import data and field configuration data. Multiple data sources can be sent separately or simultaneously.

[0071] The host computer supports the processing, detection, storage and display of the VCID (virtual channel identifier) ​​of the sent / received data. The host computer supports the real-time display of status telemetry and monitors the status of the current link.

[0072] The connection relationship between the various modules of the ground integrated tester for measurement, control and communication is as follows: the host computer communicates with the FPGA platform through the Ethernet interface to transmit the baseband data of remote control / telemetry, parameter configuration and monitor the system status. The FPGA platform and the RF integration platform are connected through the interconnection interface between the FMC (FPGA Mezzanine Card) high-speed boards.

[0073] The host computer can be any PC or laptop with an Ethernet interface.

[0074] The FPGA platform uses the XILINX Zynq7000 SOC chip XC7Z045 solution, which uses ARM+FPGASOC technology to integrate dual-core ARM Cortex-A9 and FPGA programmable logic on a single chip. The entire FPGA includes the ARM PS part and the conventional programmable logic PL part.

[0075] The RF integrated platform is used to receive the baseband data stream output by the FPGA platform, complete filtering, orthogonal up-conversion, and generate RF analog signals. It is also used to complete low-noise amplification, orthogonal down-conversion, filtering and automatic gain control after receiving the RF signal, generate a digital intermediate frequency signal, and output it to the FPGA platform.

[0076] The main chip of the RF integrated platform is AD9364, which is a high-performance, highly integrated RF agile transceiver. The device integrates the RF front end and the flexible mixed signal baseband part, and integrates the frequency synthesizer. The operating frequency range of AD9364 is 70MHz to 6.0GHz. The supported channel bandwidth range is below 200kHz to 56MHz.

[0077] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0078] Figure 1 The figure shows a system structure block diagram of a ground integrated tester for measurement, control and communication, which shows the connection relationship between various component modules and the connection relationship between various functional modules.

[0079] Figure 1 In the Vivado development environment, Xilinx provides ready-made IPs such as AXI-DMA and AXI-GPIO, which implement the corresponding interfaces. When using them, you can directly add them from the IP list of Vivado to implement the corresponding functions. Therefore, although the DMA, FIFO and GPIO in the figure are IP cores directly called by the PL side, the interconnection between the PS side and the PL side is realized through the AXI interface.

[0080] On the transmitting end, the host computer first configures the necessary parameters and selects the baseband data source to be sent.

[0081] (1) In order to detect the frequency deviation adaptability of the onboard equipment, the output frequency of the ground integrated tester needs to be adjustable. Since the ideal output frequency is fixed, the adjustable output frequency can be converted into an adjustable output frequency deviation.

[0082] The parameters configured by the host computer include: setting frequency deviation and frequency deviation after calibration.

[0083] Each time the value of "Frequency Deviation Before Calibration" changes, the host computer needs to save the value in the parameter configuration file, load the "Frequency Deviation Before Calibration" each time the computer is turned on, and display it in the "Frequency Deviation Before Calibration" value input box. If the value is not detected in the parameter configuration file, set the value to 0.

[0084] Each time the host computer is started, the default value of "set frequency deviation" is 0. At startup, or each time the value of "set frequency deviation" changes, the host computer calculates: "Frequency deviation after calibration" = "Set frequency deviation" - "Frequency deviation before calibration". "Frequency deviation after calibration" is a 16-bit signed integer, which is passed to the ARM side of the ZYNQ development board. After receiving the value, the ARM side transmits it to the modulation module of the PL side through GPIO 13.

[0085] (2) The onboard equipment needs to be able to adapt to a certain frequency deviation change rate (the source of the frequency deviation change rate is the relative motion between the two satellites and the change of the reference source). The ground-based integrated tester needs to provide such testing capabilities.

[0086] The parameters configured by the host computer include: sweep rate, sweep range, sweep zeroing, and sweep start and stop.

[0087] Frequency sweep range: Valid value range: 0~10kHz, step 1Hz, 16bit, unsigned integer.

[0088] Sweep rate: Valid range of values: 0 to 100 Hz, step 0.1 Hz, 10 bits, unsigned integer.

[0089] Sweep zero: 1 bit, the host computer interface uses a switch-like control to represent it. If it is 0, it means normal sweep; if it is 1, it means the frequency deviation will return to 0 and then stop sweeping.

[0090] Sweep start and stop: 1 bit, the host computer interface uses a switch-like control to represent it. If it is 1, it means normal sweep; if it is 0, it means the sweep will stop and the frequency deviation will be fixed.

[0091] Current frequency deviation: 16 bits, signed integer. Its meaning includes the set fixed frequency deviation + current sweep frequency deviation.

[0092] The ARM side transmits the frequency sweep parameters to the modulation module on the PL side through GPIO 22~GPIO 25, and transmits the "current frequency deviation" to GPIO 21, which is then transmitted by ARM to the host computer for real-time display.

[0093] (3) The ground integrated tester for measurement, control and communication supports the selection of baseband data sources and supports the simultaneous transmission of a single data source or multiple data sources.

[0094] Assuming that the selected data sources are A1, A2, and A3, the data format sent by the transmitter is: A1 frame 1, A2 frame 1, A3 frame 1, A1 frame 2, A2 frame 2, A3 frame 2, etc.

[0095] Table 1 gives an example of a specific baseband data source type. The baseband data source type can be increased, decreased or changed according to project requirements.

[0096] Table 1 Description of the transmitter baseband data source types

[0097]

[0098]

[0099] (4) The ground integrated tester for measurement, control and communication supports manual adjustment of the output signal power.

[0100] The parameters configured by the host computer include: AD9364 insertion loss setting.

[0101] The register address of the AD9364 configuration insertion loss is 0x74 / 0x73. 0x74[0](TxAtten[8]) and 0x73[7:0](TxAtten[7:0]) are combined to form a 9-bit value TxAtten[8:0]. The host computer outputs the 9-bit value to the ARM side through GPIO 20, and the ARM side transmits this value to the AD9364 configuration module on the PL side. After detecting that the spi_done signal of the one-time ROM configuration is pulled high at power-on, the state machine of the AD9364 configuration module detects the change of the GPIO 20 value. If a change is detected, the configuration of the insertion loss is started. The configuration process is: write 0x05 to the AD9364 register 0x14, write GPIO 20[8] to the AD9364 register 0x74, write GPIO 20[7:0] to the AD9364 register 0x73, and write 0x20 to the AD9364 register 0x14.

[0102] The legal range of the AD9364 insertion loss value is 0 to 359 (decimal), and the corresponding attenuation is: -Tx Atten[8:0] / 4 (dB), and the attenuation range is: 0 to -89.75dB. For example, TxAtten[8:0] = 359, which means that the internal attenuation of the AD9364 is: -89.75dB. The insertion loss defaults to -40dB when the integrated tester is turned on, and the value when the program is exited will be used as the default value for the next startup.

[0103] (5) Set the modulation mode of the transmitter to support different modulation modes and data rates. The working mode can be switched manually. Table 2 gives an example of a specific modulation mode. The modulation mode can be increased, decreased or changed according to project requirements.

[0104] Table 2 Transmitter modulation mode

[0105] Mode code Modulation rate Mission / non-mission mode 0 QPSK 40Mbps Mission Mode 1 QPSK 20Mbps Mission Mode 2 QPSK 2.5Mbps Mission Mode 3 SingleTone —— —— 4 BPSK 16Kbps Non-mission mode 5 BPSK 125bps Non-mission mode

[0106] At the transmitting end, the baseband data source output by the host computer is cached through DMA 0 and FIFO 0 on the ARM side to ensure data continuity. The baseband data output by FIFO 0 is output to the modulation side for processing. The baseband data first passes through the frame synchronization module, reframe module, encoding module, and scrambling module to complete the data link layer processing.

[0107] The frame synchronization module receives the data stream sent by the ARM end, with a bit width of 8 bits and a frame length of 1024B. Since the frame length is fixed and there is no bit error in the baseband data, the frame synchronization module completes the fixed frame length frame synchronization with the frame header masked in the frame in units of bytes, that is, after detecting the frame header 1ACFFC1D, the frame header is no longer searched in the frame, but the frame header is continued to be detected at the frame header position of the next frame.

[0108] The baseband data source sent by the host computer conforms to the AOS frame format. The AOS frame format is as follows: Figure 2 shown.

[0109] The frame count in the AOS frame of the baseband data source sent by the host computer is filled with all 0s. After receiving the frame after frame synchronization, the reassembly frame module identifies the VCID and counts the frames of the VCID. The frame count is filled into the corresponding position of the current frame type to complete the reassembly frame function. The reassembly frame module also monitors the frame count of the corresponding channel (VCID). For example, when a change is detected in GPIO 19 and the changed value is 4'b0001, it means that the current baseband data source type is data 1 (as shown in Table 1), and the frame count with VCID 6'b000101 is returned to GPIO 18, and sent to the host computer through the ARM end to display the count value of the current type of frame in real time. In this way, by comparing the frame type and frame count sent by the ground integrated tester with the frame type and frame count received by the communication subsystem, it can be determined whether the communication subsystem has frame loss behavior.

[0110] The encoding module completes the LDPC (8160, 7136) encoding of the reassembled frame.

[0111] The scrambling module scrambles the encoded information bits and check bits in frames according to the scrambling polynomial. All bits except the synchronization header in the AOS frame format are scrambled.

[0112] The modulation module receives the modulation mode control command GPIO 3 from the host computer and completes the modulation function of the scrambled data stream. The modulation module receives parameters: calibrated frequency deviation (GPIO 13), sweep range (GPIO 22), sweep rate (GPIO 23), sweep zero (GPIO 24), sweep start and stop (GPIO 25), and then completes the frequency deviation and sweep settings of the signal.

[0113] The I / Q baseband data output by the modulation module is sent to the transmitting module of AD9364, and AD9364 completes the transmission of the RF signal after filtering and orthogonal up-conversion.

[0114] At the receiving end, the host computer sets the demodulation mode of the receiving end, supports different demodulation methods and data rates, and the working mode can be switched manually. Table 3 gives a specific example, and the demodulation mode can be increased, decreased, or changed according to project requirements.

[0115] Table 3 Receiver demodulation mode

[0116]

[0117]

[0118] The RF signal passes through the AD9364's LNA, orthogonal down-conversion, filtering, and AGC to output a digital IF signal, which is sent to the AD9364's Rx module.

[0119] The digital intermediate frequency signal is sent to the demodulation module, and the demodulation function is completed according to the demodulation mode instruction GPIO 2 sent by the host computer. The demodulation module outputs telemetry reflecting the current signal quality, including frequency deviation telemetry, lock judgment value, demodulation lock indication, AGC gain, Eb / N0, which are sent to ARM's GPIO 4, GPIO 5, GPIO 6, GPIO 7, GPIO 8 respectively, and then sent to the host computer for real-time display.

[0120] The frame synchronization module receives the remote control log-likelihood ratio soft decision information output by the demodulation module and performs fixed-length frame synchronization on the remote control data stream, with a frame length of 8192.

[0121] In order to obtain better performance, the search frame header of the frame synchronization module is 32-bit 1ACFFC1D, and a frame protection mechanism is set. The frame protection mechanism is implemented by a state machine, which is divided into search state S0, verification state S1, and synchronization state S2. The frame synchronization working state is sent to GPIO 14 and sent to the host computer for real-time display via ARM.

[0122] Search state S0: The highest bit of the remote control log-likelihood information is shifted and stored in a 32-bit shift register. When the 32-bit shift register detects a frame header, it enters the search state.

[0123] Verification state S1: In the verification state, if the frame header is detected N times in succession and the upper and lower frames are consistent (phase and I / Q relationship are consistent), it enters the synchronization state; otherwise, it returns to the search state. That is, a total of N+1 frames are detected in the search state + verification state.

[0124] Synchronous state S2: If the synchronization is lost for M consecutive times in the synchronous state, it will return to the search state, otherwise it will maintain the synchronous state. That is, the synchronization is confirmed M times.

[0125] Due to different data rates and demodulation modes, the frame synchronization module receives the demodulation mode control (GPIO 2) and configures different frame synchronization parameters (number of error tolerance bits, number of checks, number of synchronization out-of-sync times) according to the current demodulation mode.

[0126] Since BPSK (Binary Phase Shift Keying) and QPSK (Quadrature Phase Shift Keying) have phase ambiguity during demodulation, BPSK has 2 types of ambiguous phases and QPSK has 4 types of ambiguous phases, so the frame synchronization module performs phase ambiguity correction on the frames with phase ambiguity. In addition, the frame synchronization module can adapt to the situation where the remote control data stream is I / Q inverted.

[0127] The descrambling module receives the transmission frame sent by the frame synchronization module and descrambles the original scrambled area.

[0128] The decoding pre-processing module removes the 32-bit frame header from the descrambled frame to convert it into a frame of length 8160, removes 2 clk data at the end of the frame of length 8160, and then adds 18 zeros at the beginning of the frame to finally form a frame of length 8176. In order to adapt to the decoding module interface, it is necessary to perform 7-way parallel conversion on the frame of length 8176 to obtain 7-way parallel data to be decoded with a length of 1168.

[0129] The decoding module decodes according to the decoding rules of LDPC (8160, 7136), outputs the decoded data, and gives the status indication of the decoding result: idle state, correct decoding, and decoding error.

[0130] The post-decoding processing module performs parallel-to-serial conversion (7bit to 1bit) on the parallel 7-way decoded data output by the LDPC decoding module. The frame length after parallel-to-serial conversion is 8176bit. Remove the 18bit 0 at the beginning of the 8176bit frame, and add 2bit 0 at the end of the frame. Finally, add a 32bit frame header according to the data frame format to form an 8192bit transmission frame. After the 1bit-8bit serial-to-parallel conversion, the transmission frame is sent to the FIFO 1 cache, and then sent to the ARM on the PS side through DMA 1. Finally, the host computer receives the data and completes real-time storage. If the decoding is correct, the correctly decoded frames are counted and sent to GPIO 15, and the good frame count is displayed in real time on the host computer; if the decoding is wrong, the frames with incorrect decoding are counted and sent to GPIO 16, and the bad frame count is displayed in real time on the host computer; if the decoding is correct and the data frame type is the remote control reception count, the remote control frames are counted and sent to GPIO 17.

[0131] Table 4 is a description of the GPIO meaning of the ground integrated tester for measurement, control and communication of the present invention, with a total of 26 GPIOs. Figure 1 The GPIO numbers in the table correspond one to one.

[0132] Table 4 GPIO meaning

[0133]

[0134]

[0135] Figure 3 The figure shows the upper computer operation interface of the ground integrated tester for measurement, control and communication of the present invention, including equipment startup function, instruction and parameter configuration function, baseband data source selection and transmission, baseband data real-time storage, system status real-time monitoring and judgment function. The upper computer performs real-time display every about 1s.

[0136] Click "Software Start" on the host computer interface to initiate a TCP / IP connection to the ARM end. If the connection is successful, the indicator light in the interface turns green. If the connection fails, the indicator light remains red. Click "Send Data" on the host computer interface, and the telemetry changes can be observed on the host computer interface, indicating that the device has started successfully.

[0137] Figure 4 The software operation flow chart of the ground integrated tester for measurement, control and communication of the present invention is shown. After the device is turned on, wait for 1 minute and start the upper computer software. After the device is successfully started, according to the requirements of the stand-alone subsystem, the function and performance test of the stand-alone subsystem is completed according to the test process. After the test is completed, disconnect and end the test.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the embodiments, it should be understood by those skilled in the art that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention and should be included in the scope of the claims of the present invention.

Claims

1. A ground integrated tester for measurement, control and communication, characterized in that: The tester includes: a host computer, an FPGA platform and a radio frequency integrated platform; wherein, The host computer is used to configure the modulation and demodulation parameters and adjust the output signal power of the FPGA platform; to send the baseband data stream to the FPGA platform and to receive and store the baseband data stream from the FPGA platform; and to monitor and display the real-time status of the tester; The FPGA platform is used to complete the processing and modulation and demodulation of the baseband data stream; to configure the RF integration platform, and to monitor the link status; The RF integrated platform is used to receive the baseband data stream output by the FPGA platform, complete filtering, orthogonal up-conversion, and generate a RF analog signal; it is also used to complete low-noise amplification, orthogonal down-conversion, filtering and automatic gain control after receiving the RF signal, generate a digital intermediate frequency signal, and output it to the FPGA platform; The FPGA platform includes a PS end and a PL end; The PS end includes data transmission modules DMA0 and DMA 1, cache FIFO 0 and FIFO 1, and GPIO; wherein, The data transmission module DMA0 is used to receive the baseband data stream from the host computer and output it to the cache FIFO 0; The cache FIFO 0 is used to cache the baseband data stream received by the data transmission module DMA0; The data transmission module DMA 1 is used to obtain the baseband data stream from FIFO 1 and output it to the host computer; The cache FIFO 1 is used to cache the baseband data stream output by the receiving subsystem; The GPIO is used to exchange data between the host computer and the FPGA platform; The PL end includes a transmitting terminal system and a receiving terminal system; wherein, The transmitting subsystem is used to obtain the baseband data stream from the cache FIFO 0, perform frame synchronization, frame reorganization, encoding, scrambling and modulation, and then output it to the RF integration platform; The receiving subsystem is used to receive the digital intermediate frequency signal sent by the radio frequency integration platform, perform demodulation, frame synchronization, descrambling and decoding, and then output it to the cache FIFO 1; The transmitter subsystem comprises: A frame synchronization module, used for receiving the baseband data stream sent by the PS end, completing the fixed frame length frame synchronization of the frame header shielding in the frame, and sending the processed baseband data stream to the reassembly frame module; The reassembly frame module is used to identify the VCID of the current frame according to the frame format, count the current frame, fill the frame count into the corresponding position in the current frame, and output the frame enable signal, the identification to be encoded and the reassembly frame to the encoding module; The encoding module is used to complete the encoding of the reassembled frame and output the encoded reassembled frame to the scrambling module; the encoding and decoding method supports LDPC (8160, 7136) code; a scrambling module, used to scramble the encoded recombined frame in units of frames, and output the scrambled data to the modulation module; and The modulation module is used to complete the modulation of different modulation modes and different data rates in the corresponding mode for the scrambled data according to the modulation mode instruction sent by the host computer; the modulation and demodulation mode supports BPSK and QPSK; the communication rate coverage range supports from 125bps to 40Mbps; The modulation module is also used to obtain the calibrated frequency deviation, sweep frequency range, sweep frequency rate, sweep frequency zeroing and sweep frequency start and stop parameters from the PS end to complete the frequency deviation and sweep frequency setting of the data; The receiving terminal system comprises: A demodulation module, used for receiving a digital intermediate frequency signal sent by the radio frequency integration platform, demodulating the digital intermediate frequency signal, generating remote control log-likelihood ratio soft decision information, and outputting the information to a frame synchronization module; A frame synchronization module is used to configure different frame synchronization parameters according to the demodulation mode provided by the host computer; perform fixed-length frame synchronization on the remote control log-likelihood ratio soft decision information, provide a frame synchronization identifier, and output the frame-synchronized data to the descrambling module; is used to adapt to the situation where the remote control data stream is I / Q inverted; and is also used to perform phase ambiguity correction on frames with phase ambiguity; A descrambling module, used to descramble the scrambled area of ​​the data after frame synchronization, and output the descrambled data to the pre-decoding processing module; The pre-decoding processing module is used to remove the frame header of the valid frame of the descrambled data to generate a frame of fixed length, and after setting processing, it is output to the decoding module after serial-to-parallel conversion; A decoding module, used to decode the data according to the decoding rules, and output the decoded data and the decoding result status indication to the post-decoding processing module; and The post-decoding processing module is used to perform parallel-to-serial conversion on the decoded data, and add a frame header according to the data frame format after setting processing to form a transmission frame of fixed length and output it to the PS end; The host computer supports reading file import data and field configuration data.

2. The ground integrated tester for measurement, control and communication according to claim 1, characterized in that: When the decoding module performs decoding, if the decoding is correct, the correctly decoded frames are counted, and the good frame count is displayed in real time on the host computer; if the decoding is wrong, the wrongly decoded frames are counted, and the bad frame count is displayed in real time on the host computer; If the decoding is correct and the data frame type is the remote control reception count, the remote control frames are counted.

3. The ground integrated tester for measurement, control and communication according to claim 1, characterized in that: The demodulation module is also used to output telemetry reflecting the current signal quality to the PS end, which is displayed in real time by the host computer; the telemetry includes frequency deviation telemetry, lock judgment value, demodulation lock indication, AGC gain and Eb / N0.

4. The ground integrated tester for measurement, control and communication according to claim 1, characterized in that: The FPGA platform performs radio frequency integrated platform configuration, including: When the tester is powered on, the FPGA platform first completes a one-time configuration of the RF integration platform; During the operation of the tester, the FPGA platform receives the dynamic parameter configuration sent by the host computer and dynamically configures the parameters of the RF integration platform; The main configuration parameters include: modulation / demodulation mode, sweep range, sweep rate, sweep zero / start / stop, frequency deviation setting and AD9364 insertion loss setting.

5. The ground integrated tester for measurement, control and communication according to claim 1, characterized in that: The tester supports the selection of different baseband data sources, and supports a single baseband data source or multiple baseband data sources sending data simultaneously.

6. The ground integrated tester for measurement, control and communication according to claim 1, characterized in that: The host computer communicates with the FPGA platform via an Ethernet interface; the FPGA platform and the RF integration platform are connected via an interconnection interface between FMC high-speed boards.

Images