Demand-based probe filter initialization after low power state

Abstract

A data fabric routes requests between multiple requesters. A probe filter tracks a state of a memory cache line at a probe filter coupled to the data fabric. In response to the data fabric leaving a non-operating power state while all requesters that are clients of the probe filter are in a non-operating power state, a power management controller delays a probe filter initialization state in which data about the cache line is initialized after the non-operating power state.

Description

Background Art

[0001] Computer systems utilize a variety of peripheral components for different input / output and communication functions. A system on a chip (SOC) combines data processing circuits such as a central processing unit (CPU) core and a graphics processing unit (GPU) with peripheral controllers and memory interfaces on a single integrated circuit chip and is well suited for portable battery-powered operation. For example, an SOC may incorporate a display controller, an image signal processor (ISP), and other peripheral controllers on the SOC to enable input and output of information to and from the computer system. In such large and complex SOCs, devices typically route access to transfer data between resources such as memory through large on-chip routing circuits or "data fabrics."

[0002] The diversity of circuits on a typical SOC poses a problem for implementing power saving modes. Many peripheral controllers operate in real time and are isochronous, requiring a certain amount of bandwidth to share memory resources during a specific time period. This requirement hinders the implementation of full chip low power states. For example, when the CPU core and GPU are idle, the peripheral controller may still be active and receive data that it can store in a buffer, but must send the data to memory before the buffer fills up.

[0003] On the other hand, CPUs and GPUs tend to have periods of high activity separated by idle periods. When idle periods are expected to be short, data fabrics, memory controllers, and memories are typically kept active so that they can quickly service requests from peripheral controllers to transfer more data. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An Advanced Configuration and Power Interface (ACPI) model for computer system power states known in the art is shown in block diagram form;

[0005] Figure 2 illustrates, in block diagram form, a data processing system according to some embodiments;

[0006] Figure 3 A block diagram is shown according to some embodiments. Figure 2 The data structure of

[0007] Figure 4 shows a flow chart of a process for entering a hold low power state according to an exemplary embodiment;

[0008] In the following description, the same reference numerals are used in different drawings to indicate similar or identical items. Unless otherwise specified, the word "couple" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise specified, any description of direct connection also means an alternative embodiment using an appropriate form of indirect electrical connection. DETAILED DESCRIPTION

[0009] The data processor includes a plurality of requesters, a plurality of responders, a data texture, and a power management controller. The data texture routes requests between the plurality of requesters and the plurality of responders. The data texture includes a probe filter that tracks a state of a memory cache line and has an initialization state. The power management controller operates to: delay the probe filter from entering the initialization state when the data texture leaves the non-operational power state while all requesters that are clients of the probe filter are in the non-operational power state; and allow the probe filter to enter the initialization state when at least one requester that is a client of the probe filter is in the operational power state.

[0010] A method includes: routing requests between a plurality of requesters and a plurality of responders at a data texture. Tracking a state of a memory cache line at a probe filter coupled to the data texture. In response to the data texture entering a non-operating power state, placing the probe filter in a non-operating power state. In response to the data texture leaving its non-operating power state while all requesters that are clients of the probe filter are in the non-operating power state, delaying a probe filter initialization state in which data about the cache line is initialized. In response to at least one requester that is a client of the probe filter leaving its non-operating power state, the probe filter enters its initialization state.

[0011] The data texture circuit routes requests between a plurality of requesters and a plurality of responders. The data texture circuit includes a probe filter that tracks a state of a memory cache line and has an initialization state. In response to a command from a power management controller, the data texture is operable to delay the probe filter initialization state when the data texture leaves the non-operational power state when each requester in a first set of requesters operating as clients of the probe filter is in the non-operational power state.

[0012] Figure 1 An Advanced Configuration and Power Interface (ACPI) model 100 known in the art for computer system power states is shown in block diagram form. The ACPI model 100 is part of the ACPI specification developed by various computer system, software, and component vendors to establish an industry standard interface for device configuration and power management of both devices and entire computer systems.

[0013] The ACPI model 100 defines a state hierarchy for various devices in a computer system organized around a set of global system states, including a G0 (S0) state 110 referred to as a "working" state, a G1 state 120 referred to as a "sleep" state, a G2 (S5) state 130 referred to as a "soft-off" state, and a G3 state 140 referred to as a "mechanical-off" state. In addition, the ACPI model 100 includes states 150 referred to as "legacy" states that accommodate pre-existing BIOS power management interfaces corresponding to basic input / output system (BIOS) operations prior to the loading of an ACPI-compliant operating system. The ACPI model 100 also defines a set of central processing unit (CPU) states 160, and a set of device states or "D" states 170 for devices such as modems, hard disk drives (HDDs), and compact disk read-only memories (CDROMs).

[0014] The ACPI model 100 is well known and most aspects will not be discussed further. However, certain aspects related to the power state of a central processing unit are relevant to understanding the present disclosure and will now be discussed.

[0015] In the G0 (S0) state 110, peripheral devices can dynamically change their power states, while the user can select various performance and power characteristics of the system through the user interface so that the software system can optimize the computer for desired performance or battery life. In this state, the computer system responds to external events in real time. The computer system can transition from the G0 (S0) state to the G1 state 120, which includes various power-saving sleep states or "S states", under the control of system firmware such as BIOS, and return to the working state in response to a wake-up event.

[0016] In the G0 (S0) state 110, the CPU is capable of operating in a variety of states including a "C0" state in which the processor executes instructions, and various lower power or "idle" states labeled "C1" through "Cn." In the C0 state, the CPU is capable of operating in various performance states or "P-states" in which dynamic voltage and frequency scaling (DVFS) can be used to increase or throttle the operating frequency to support the needs of the currently running application. In the idle states C1-Cn, the CPU is idle and not executing instructions, but has various combinations of power consumption and wake-up latency, where lower power consumption is weighed against longer wake-up latency. Thus, for example, in the C1 state, power consumption is highest but wake-up latency is shortest, while in the Cn state, power consumption is lowest but wake-up latency is longest.

[0017] Using ACPI model 100, each particular computer system may support different combinations of P-states and C-states appropriate for the application environment.Achieving a better tradeoff between reduced power consumption and low latency in a manner not specified by ACPI model 100 remains a desired goal.

[0018] Figure 2 A data processing system 200 according to some embodiments is shown in block diagram form. The data processing system 200 includes a data processor in the form of a SOC 210 and external memory in the form of low power double data rate synchronous dynamic random access memory (LPDDRx SDRAM) 273 and 283. Many other components of an actual data processing system are typically present but are not relevant to understanding the present disclosure and are not shown for ease of illustration. Figure 2 Shown in.

[0019] SOC 210 typically includes a system management unit (SMU) 211, a system management network (SMN) 212, a central processing unit (CPU) core complex 220 labeled "CCX", a graphics controller 230 labeled "GFX", a real-time client subsystem 240, a memory / client subsystem 250, a data fabric 260, memory channels 270 and 280, and a peripheral component interface express (PCIe) subsystem 290. As will be appreciated by one of ordinary skill in the art, SOC 210 may not have all of these elements present in every implementation, and may also have additional elements included therein.

[0020] The SMU 211 is bidirectionally connected to the major components in the SOC 210 through the SMN 212. The SMN 212 forms the control fabric of the SOC 210. The SMU 211 is a local controller that controls the operation of resources on the SOC 210 and synchronizes the communication between these resources. The SMU 211 manages the power-up sequencing of the various processors on the SOC 210, and controls a number of off-chip devices via reset, enable, and other signals. The SMU 211 includes one or more clock sources (not shown), such as a phase-locked loop (PLL), to provide clock signals for each component of the SOC 210. The SMU 211 also manages the power of the various processors and other functional blocks, and may receive measured power consumption values ​​from the CPU cores in the CPU core complex 220 and the graphics controller 230 to determine the appropriate P-state.

[0021] CPU core complex 220 includes a set of CPU cores, each of which is bidirectionally connected to SMU 211 via SMN 212. Each CPU core may be a single core that shares only a last level cache with other CPU cores, or may be grouped with some but not all other cores in the cluster.

[0022] Graphics controller 230 is bidirectionally connected to SMU 211 via SMN 212. Graphics controller 230 is a high-performance graphics processing unit that can perform graphics operations such as vertex processing, fragment processing, shading, texture blending, etc. in a highly integrated and parallel manner. In order to perform its operations, graphics controller 230 needs to periodically access external memory. Figure 2 In the embodiment shown in , graphics controller 230 shares a common memory subsystem with the CPU cores in CPU core complex 220, an architecture known as a unified memory architecture. Because SOC 210 includes both a CPU and a GPU, it is also referred to as an accelerated processing unit (APU).

[0023] The real-time client subsystem 240 includes a set of real-time clients such as representative real-time clients 242 and 243, and a memory management hub 241 labeled "MM Hub". Each real-time client is bidirectionally connected to the SMU 211 through the SMN 212, and is bidirectionally connected to the memory management hub 241. The real-time client can be any type of peripheral controller that requires periodic data movement, such as an image signal processor (ISP), an audio coder-decoder (codec), a display controller that renders and rasterizes objects generated by the graphics controller 230 for display on a monitor, etc.

[0024] The memory / client subsystem 250 includes a set of memory elements or peripheral controllers such as representative memory / client devices 252 and 253, and a system and input / output hub 251 labeled "SYS hub / IO hub." Each memory / client device is bidirectionally connected to the SMU 211 through the SMN 212, and to the system and input / output hub 251. The memory / client device is a circuit that stores data or requires access to data in a non-cyclic manner, such as non-volatile memory, static random access memory (SRAM), external disk controllers such as a serial advanced technology attachment (SATA) interface controller, a universal serial bus (USB) controller, a system management hub, etc.

[0025] The data fabric 260 is an interconnect that controls the flow of traffic in the SOC 210. The data fabric 260 is bidirectionally connected to the SMU 211 through the SMN 212, and is bidirectionally connected to the CPU core complex 220, the graphics controller 230, the memory management hub 241, and the system and input / output hub 251. The data fabric 260 includes a crossbar switch for routing memory-mapped access requests and responses between any of the various devices of the SOC 210. The data fabric includes a system memory map defined by a basic input / output system (BIOS) for determining the destination of a memory access based on the system configuration, and a buffer for each virtual connection.

[0026] Memory channels 270 and 280 are circuits that control data transfer to and from external memories 273 and 283. Memory channel 270 is formed by memory controller 271 and physical interface circuit 272 labeled “PHY” connected to external memory 273. Memory controller 271 is bidirectionally connected to SMU 211 through SMN 212 and has an upstream port bidirectionally connected to data fabric 260 and a downstream port. Physical interface circuit 272 has an upstream port bidirectionally connected to memory controller 271 and a downstream port bidirectionally connected to external memory 273. Similarly, memory channel 280 is formed by memory controller 281 and physical interface circuit 282 connected to external memory 283. Memory controller 281 is bidirectionally connected to SMU 211 through SMN 212 and has an upstream port bidirectionally connected to data fabric 260 and a downstream port. Physical interface circuit 282 has an upstream port bidirectionally connected to memory controller 281 and a downstream port bidirectionally connected to external memory 283.

[0027] The peripheral component interface express (PCIe) subsystem 290 includes a PCIe controller 291 and a PCIe physical interface circuit 292. The PCIe controller 291 is bidirectionally connected to the SMU 211 through the SMN 212, and has an upstream port bidirectionally connected to the system and input / output hub 251 and a downstream port. The PCIe physical interface circuit 292 has an upstream port bidirectionally connected to the PCIe controller 291 and a downstream port bidirectionally connected to the PCIe fabric ( Figure 2 The PCIe controller can form a PCIe root complex of a PCIe system for connecting to a PCIe network including PCIe switches, routers, and devices.

[0028] In operation, SOC 210 integrates a complex assortment of computing and storage devices on a single chip, including CPU core complex 220 and graphics controller 230. Most of these controllers are well known and will not be discussed further. SOC 210 also implements various system monitoring and power saving functions, including P-state promotion and suppression and C-state entry and exit under the control of SMU 211 and / or operating system software.

[0029] For example, the SOC 210 controls entry into and exit from various idle states of the CPU core complex 220 and the graphics controller 230 based on idle cycles when no instructions are being executed. As is well known, when both the CPU core complex 220 and the graphics controller 230 enter an idle state, other components of the SOC 210 may also be placed in appropriate idle states to save power. In one example, the CPU core complex 220 supports two idle states including a shallow idle state (C1) and a deep idle state (C6) state. The "packed C6" (PC6) state is a state in which all CCX cores are in the C6 state and all caches (including the level 3 cache inside the CCX) are flushed. Depending on the ACPI mode, the C1 state is the lightest C-state and may only involve clock gating and a reduction in supply voltage, which allows the SOC 210 to maintain its state and return to an active state with very low latency. On the other hand, the C6 state is a very deep C-state and reduces power consumption by gating clock signals and supply voltage, but it also has a very long exit latency. Since the expected dwell in the C6 state may be, for example, on the order of tens of microseconds, it still provides a net power saving despite the longer entry and exit latencies.

[0030] In some known systems, other components of the SOC 210 may also be placed in various idle states to correspond to the idle states of the data processing elements. In one specific example, when each CPU and GPU enters the C1 state, the data texture and memory system remain fully operational, but consume a large amount of power when they are not normally needed. However, when each CPU and GPU enters the C6 state, the data texture 260 is also placed in a corresponding idle power state with power and clock gating. Before the data texture enters this idle power state, the data texture places the external memory in a self-refresh state and places the memory controller and PHY in a similar low-power state.

[0031] Figure 3 A block diagram is shown according to some embodiments. Figure 2 The data fabric 260 includes a group of master ports 310, a group of slave ports 320, a crossbar router 330 and a power controller circuit 350.

[0032] The master port 310 includes ports for each device capable of generating a memory access request, including representative coherent master ports 311 and 312 and representative master ports 313 and 314. Each of the ports 311, 312, 313, and 314 is adapted to bidirectionally connect to a device such as Figure 2 2 and 3. The master ports 311 and 312 are connected to the corresponding requesting devices shown in the figure, and have bidirectional downstream ports. Each master port has an internal FIFO buffer for temporary storage access. In various embodiments, the coherent master ports 311 and 312 are connected to the coherent requesters such as CCX 220, GFX 230 or other CPU or GPU requesters in the upstream direction. The master ports 313 and 314 are connected to the main non-coherent requesters such as display controllers or multimedia controllers through MM hub 241 and IO hub 251 respectively in the upstream direction.

[0033] The slave ports 320 include ports for each device capable of responding to a memory access request, including a representative non-coherent slave port 321 and representative coherent slave ports 322 and 323. Each of the slave ports 321, 322, and 323 has a bidirectional upstream port and is adapted to bidirectionally connect to a memory access request. Figure 2 The corresponding responding devices shown. Each slave port has an internal FIFO buffer for temporary storage access. The consistency slave ports 322 and 323 are each bidirectionally connected to a corresponding probe filter 360 for tracking the state of the memory cache line. Each consistency slave port includes a consistency slave controller for that port.

[0034] The crossbar router 330 has a bidirectional connection for downstream bidirectional connection to the master port 310 and a bidirectional connection for upstream bidirectional connection to the slave port 320. The crossbar router 330 is the core of the data fabric 260 and forms a virtual connection between the master port and the slave port based on the destination address of the requester by routing access between the master port and the corresponding slave port.

[0035] The power controller circuit 350 includes a local C-state controller 351, a clock gating circuit 352, a power gating circuit 353, and a probe filter clock gating 345. The local C-state controller 351 has a first input terminal for receiving a signal labeled "SOC state", a first output terminal connected to the probe filter power gating 355, a second output terminal, and a third output terminal. The clock gating circuit 352 has a first input terminal for receiving a signal labeled "F CLK The power gating circuit 353 has an input terminal for receiving a data texture clock signal marked as "V DD″ has an input terminal for a data line texture supply voltage, a control input terminal connected to a third output terminal of the local C state controller 351, and an output terminal for providing a selective gating power supply voltage to the data line texture 260.

[0036] Probe filter power gate 355 has an input terminal (not shown) that receives a supply voltage from power gate circuit 353 and an output terminal connected to probe filter 360. Probe filter power gate 355 operates to selectively gate the power supply to probe filter 360 under the control of C-state controller 351 to provide a low power state, such as with respect to Figure 4 Further described.

[0037] In general, data fabric 260 routes memory access requests and responses between requesters (such as CPU cores, GPUs, real-time client controllers, etc.) and responders (such as external memory through memory controllers and PHYs, on-chip memory, etc.). The local C-state controller activates both clock gating 352 and power gating 353 in C-states. In addition, it can perform Figure 3 Additional steps not shown in FIG. 1, such as disabling the generation of the texture clock signal F when entering the C state CLK Phase-locked loop.

[0038] In this embodiment, C-state controller 351 and probe filter power gating 355 include power state control circuitry that operates to provide a probe filter low power state and a probe filter initialization state. When exiting the probe filter low power state, the power state control circuitry is operable to: delay the probe filter from entering the probe filter initialization state when data texture leaves the non-operational power state while all first requesters are in the non-operational power state; and allow the probe filter to enter the probe filter initialization state when at least one first requester is in the operational power state, as further described below.

[0039] Figure 4A flow chart 400 showing a process of entering and exiting a low power state at a probe filter is shown according to an exemplary embodiment. The depicted process is suitable for implementation with data texture 260 under the control of local C-state controller 351, or with other suitable data texture circuitry including probe filter clock gating capability and suitable power state controller power state control circuitry similar to that of local C-state controller 351. While in this embodiment, the process handles requests from CCX clients and non-CCX clients, in other embodiments, these two groups of clients are generalized as probe filter clients and non-probe filter clients, respectively. A probe filter client is a cacheable coherent client whose cache lines are tracked by the probe filter, so that a request of another coherent client that misses in the probe filter does not require a probe to be sent to the cacheable coherent probe filter client. All other clients are non-probe filter clients, some of which may also be cacheable and coherent, in which case their cache lines are not tracked in the probe filter, so a request from another coherent client requires unconditionally sending a probe to said cacheable coherent non-probe filter client, resulting in no filtering being performed.

[0040] The process begins at block 402, where CCX 220 and GFX 230 become idle with CCX cache flushed, and enter a low power state such as the PC6 state described above. In response, at block 404, local C-state controller 351 determines that the data texture should enter a low power state. The low power state of the data texture includes clock gating 352 to gate the clock signal to the data texture 260, and power gating 353 to remove power supply to the data texture 260. This determination may be made by a local power state controller for data texture, such as local C-state controller 351, or a system power state controller, such as SMU 211 ( Figure 2 )conduct.

[0041] At block 406, the process determines that the data texture should leave the low power state. Exiting the low power state may be done for a variety of reasons. For example, the low power state may be exited to service a direct memory access (DMA) request of a requestor on the data texture.

[0042] At block 408, the process determines whether any CCX client, or any probe filter client in other embodiments, has exited their low power state. If not, the process proceeds to block 410 where it delays the probe filter initialization state and waits for the CCX client to exit its low power state. In this embodiment, the determination at block 408 is made by the local C-state controller 351 based on information in the SOC state signal. When the CCX client exits the low power state at block 408, the process proceeds to block 412.

[0043] At block 412, the probe filter enters an initialization state in parallel with the initialization of the CCX. (Although the CCX is discussed herein, the same process behavior is employed for embodiments of the requestor having a single CPU core rather than a core complex design.) During the initialization state of the probe filter, the data of the probe filter, including one or more arrays of state data for memory locations, is initialized to change the array contents from the random or unpredictable data present after the memory is powered up to an initial state. Typically, the initial state reflects an "invalid" indication for each tracked row in the probe filter, which reflects that cache state tracking data for the associated memory row has not yet been received at the probe filter. The desired data is written to each array entry for tracking the corresponding memory row in the probe filter.

[0044] As shown at block 412, probe filter initialization is performed in parallel with certain steps in the initialization process of the CCX. For example, to initialize from a low power state, the CCX performs certain steps such as repair, fuse propagation, and initialization microcode as well as restoring the CCX state to the state it exited. These CCX initialization steps have design specific latencies, as does probe filter initialization. Thus, in some embodiments, probe filter initialization will be completed before CCX initialization, while in other embodiments, CCX initialization will be completed first. Thus, in some embodiments, it is possible that the CCX will begin making requests to the coherence slave controller before the probe filter is initialized to handle coherence and cacheable requests. Furthermore, CCX requests such as state restore requests made during CCX initialization may include cacheable but non-coherent requests that may be fulfilled without accessing the probe filter. Other requestors may also make requests to the coherence slave controller during the probe filter's initialization state. Thus, the coherence slave controller includes the ability to handle such requests in an appropriate manner during the probe filter initialization state as shown at blocks 414-421.

[0045] Blocks 414-421 depict the coherence slave controller's responses to various types of requests if such requests occur during the probe filter's initialization state.

[0046] At block 414, if a cacheable coherency request is received from a CCX client or a probe filter client, the process at block 415 blocks such request until probe filter initialization is complete. This functionality of the coherency slave controller handles scenarios where CCX initialization completes before probe filter initialization completes.

[0047] At block 416, if a request is made that is dependent on a previous request that was blocked at block 415, the process at block 417 also blocks that request until the request it depends on completes. Such requests include requests made by a CCX requestor, a GFX requestor, or a real-time client requestor to the same address as the blocked request. This functionality allows the coherency slave controller to handle such requests and maintain coherency.

[0048] At block 418, if a coherency request is received from a non-CCX client requestor, such as a GFX requestor or a real-time client requestor, the request is fulfilled by the coherency slave controller that received the request and treated as a cache miss at block 419. Note that address conflicts are handled according to block 416 regardless of whether they are coherency requests. This functionality allows the coherency slave controller to fulfill certain requests without waiting for probe filter initialization to complete.

[0049] At block 420, if a non-cacheable coherence request is received from a CCX client, the request is fulfilled by the coherence slave controller receiving the request and treated as a cache miss at block 421. Likewise, if such a request is dependent on a previously blocked request, such a request is blocked at 417.

[0050] At block 422, if a non-coherent request is received from any requestor, the request is fulfilled at block 423 as would normally be fulfilled by the coherent slave controller receiving the request. Likewise, if such a request is dependent on a previously blocked request, such a request is blocked at 417.

[0051] Requests that are not cacheable or coherent typically do not require a probe filter and are processed normally by the coherent slave controller during the probe filter initialization state unless a dependency on the request is discovered at block 416 .

[0052] At block 424, when all data arrays in the probe filter are initialized with appropriate data, the probe filter initialization is complete, thereby ending the probe filter initialization state.Then at block 426, the consistency slave controller begins creating a process probe filter lookup.

[0053] Figure 2The SOC 210 or any part thereof, such as the data texture 260, may be described or represented by a computer accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture the integrated circuit. For example, the data structure may be a behavioral level description or a register transfer level (RTL) description of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool, which may synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates, which also represent the functionality of the hardware comprising the integrated circuit. The netlist may then be placed and routed to produce a data set describing a geometry to be applied to a mask. The mask may then be used in various semiconductor manufacturing steps to produce the integrated circuit. Alternatively, the database on the computer accessible storage medium may be a netlist (with or without a synthesis library) or a data set (as desired) or a Graphic Data System (GDS) II data.

[0054] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. Various techniques used in conjunction with the C-states of the data texture disclosed herein may be used independently or in conjunction with other techniques. In addition, different techniques and circuits may be used to detect the idle traffic state through data texture.

[0055] Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A data processor, comprising: Multiple requestors; Multiple responders; A data texture, the data texture being used to route requests between the plurality of requesters and the plurality of responders, the data texture comprising: a probe filter that tracks a state of a memory cache line, the probe filter having an initialized state; and A power management controller, the power management controller being operable to: delay the probe filter from entering the initialization state when the data texture leaves the non-operational power state while all requesters that are clients of the probe filter are in the non-operational power state, and allow the probe filter to enter the initialization state when at least one requester that is a client of the probe filter is in the operational power state.

2. The data processor according to claim 1, wherein the data texture further comprises: Crossbar router; and One or more coherence slave controllers are coupled to the crossbar router and are operable to block cacheable coherence requests from requestors that are probe filter clients during the initialization state.

3. The data processor of claim 2, wherein the coherency slave controller is operable to block requests that are dependent on the blocked cacheable coherency requests during the initialization state.

4. The data processor of claim 2, wherein the coherence slave controller is operable to cause, during the initialization state, coherence requests from requestors that are not probe filter clients to be classified as cache misses and to fulfill the coherence requests.

5. The data processor of claim 1 , wherein the power management controller causes the probe filter to enter its initialization state in response to at least one of the requestors that is a probe filter client leaving its non-operational power state and entering an initialization state.

6. The data processor of claim 1, wherein the requestor as a probe filter client comprises a central processing unit (CPU) core.

7. The data processor according to claim 6, further comprising: A requestor that is not a probe filter client includes one or more of: a graphics processing unit (GPU) core, a neural processing unit (NPU) core, and an input / output (I / O) interface controller.

8. A method comprising: At the data fabric, routing requests between multiple requesters and multiple responders; tracking a state of a memory cache line at a probe filter coupled to the data fabric; responsive to the data texture entering a non-operational power state, placing the probe filter in a non-operational power state; In response to the data texture leaving its non-operating power state while all requesters that are clients of the probe filter are in the non-operating power state, delaying a probe filter initialization state in which data about a cache line is initialized after the non-operating power state; as well as In response to at least one of the requestors that is a probe filter client leaving its non-operational power state, the probe filter is caused to enter its initialization state.

9. The method according to claim 8, further comprising: Cacheable coherent requests from the requestor as a probe filter client on the data fabric are blocked during the probe filter initialization state.

10. The method according to claim 8, further comprising: Requests that are dependent on the blocked cacheable coherency requests on the data fabric during the probe filter initialization state are blocked.

11. The method according to claim 8, further comprising: During the initialization state, coherency requests from requesters on the data fabric that are not probe filter clients are fulfilled as cache misses.

12. The method of claim 11, wherein the requestor that is not a probe filter client comprises one or more of: a graphics processing unit (GPU) core, a neural processing unit (NPU) core, and an input / output (I / O) interface controller.

13. The method according to claim 8, further comprising: During the probe filter initialization state, a non-cacheable coherent request from the requestor as a probe filter client is fulfilled as a cache miss.

14. The method of claim 8, wherein the requestor as a probe filter client comprises a central processing unit (CPU) core.

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