Liquid crystal display device and its control module, integrated board card

Abstract

The present disclosure provides a liquid crystal display device and a control module (CTR) and an integrated board card (C-Mult) thereof, and belongs to the technical field of display. The integrated board card (C-Mult) comprises a field programmable logic gate array (FPGA) and a backlight driving unit (LEDD) arranged on the same circuit board; the field programmable logic gate array (FPGA) is configured to receive picture data, generate picture synchronization data according to the picture data and send the picture synchronization data to a liquid crystal display panel (PNL), and generate backlight driving data according to the picture data and send the backlight driving data to the backlight driving unit (LEDD); and the backlight driving unit (LEDD) is configured to have a delay time of the received backlight driving data and picture synchronization data less than the time of one frame of picture. The integrated board card (C-Mult) can make the liquid crystal display panel (PNL) and the backlight module (BLU) synchronously respond to the synchronization data.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a liquid crystal display device and its control module and integrated circuit board. Background Technology

[0002] Local dimming can significantly improve the display effect of LCD devices. However, the LCD panel and backlight module do not respond synchronously to synchronization data, which causes a certain flickering effect when displaying some images, such as when switching between black and white images.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a liquid crystal display device and its control module and integrated board to reduce screen flicker.

[0005] According to one aspect of this disclosure, an integrated board for a liquid crystal display device is provided, the integrated board including a field-programmable gate array and a backlight driving unit disposed on the same circuit board;

[0006] The field-programmable gate array is configured to receive screen data, generate screen synchronization data based on the screen data, and send it to the liquid crystal display panel; and to generate backlight driving data based on the screen data and send it to the backlight driving unit.

[0007] The backlight driving unit is configured such that the delay time between the received backlight driving data and the screen synchronization data is less than the time of one frame.

[0008] According to one embodiment of this disclosure, the integrated board further includes a storage module, which is a storage circuit located on the circuit board, or the storage module is a storage unit of a field-programmable gate array, or the storage module is composed of a storage unit of a field-programmable gate array and a storage circuit located on the circuit board;

[0009] The storage module is configured to store configuration information of the backlight driving unit, debugging interface configuration, and at least a portion of the program of the field-programmable gate array.

[0010] The field-programmable gate array is configured to generate the screen synchronization data and the backlight synchronization data according to the screen data, and cache the screen synchronization data and the backlight synchronization data in the storage module.

[0011] The field-programmable gate array is also configured to forward the screen synchronization data in the storage module to the liquid crystal display panel, generate the backlight driving data according to the backlight synchronization data in the storage module and the configuration information of the backlight driving unit, and send it to the backlight driving unit.

[0012] The field-programmable gate array is also configured to invoke the debugging interface configuration in response to a debugging signal, and to cause the display device to display the debugging interface.

[0013] According to one embodiment of the present disclosure, the storage circuit includes a first storage sub-circuit located on the circuit board, the first storage sub-circuit storing configuration information of the backlight driving unit;

[0014] The field-programmable gate array is configured to generate the screen synchronization data and the backlight synchronization data according to the screen data, and cache the screen synchronization data and the backlight synchronization data in the first storage sub-circuit.

[0015] The field-programmable gate array is also configured to forward the screen synchronization data in the first storage sub-circuit to the liquid crystal display panel, generate the backlight driving data according to the backlight synchronization data in the first storage sub-circuit and the configuration information of the backlight driving unit, and send it to the backlight driving unit.

[0016] According to one embodiment of the present disclosure, the storage circuit includes a second storage sub-circuit located on the circuit board, the second storage sub-circuit storing a debugging interface configuration;

[0017] The field-programmable gate array is also configured to invoke the debugging interface configuration in response to a debugging signal, and to cause the display device to display the debugging interface.

[0018] According to one embodiment of the present disclosure, the storage circuit includes a third storage sub-circuit located on the circuit board, the third storage sub-circuit storing at least a portion of the program of the field-programmable gate array.

[0019] According to one embodiment of the present disclosure, the field-programmable gate array includes a first field-programmable gate array and a second field-programmable gate array;

[0020] The first field-programmable gate array is configured to receive the screen data and forward it to the second field-programmable gate array;

[0021] The second field-programmable gate array is configured to generate the screen synchronization data and the backlight driving data based on the screen data; the second field-programmable gate array is also configured to send the screen synchronization data to the liquid crystal display panel and the backlight driving data to the backlight driving unit within the same frame time.

[0022] According to one embodiment of this disclosure, the integrated board includes a first storage sub-circuit and a third storage sub-circuit located on the circuit board;

[0023] The first storage sub-circuit stores the configuration information of the backlight driving unit; the third storage sub-circuit stores at least a portion of the program of the second field-programmable gate array.

[0024] The second field-programmable gate array is configured to generate the screen synchronization data and backlight synchronization data based on the screen data, and cache the screen synchronization data and backlight synchronization data in the first storage sub-circuit; the second field-programmable gate array is also configured to forward the screen synchronization data in the first storage sub-circuit to the liquid crystal display panel within the same frame time, and generate the backlight driving data based on the backlight synchronization data in the first storage sub-circuit and the configuration information of the backlight driving unit and send it to the backlight driving unit.

[0025] According to one embodiment of the present disclosure, the integrated board further includes a second storage sub-circuit located on the circuit board, the second storage sub-circuit storing a debugging interface configuration;

[0026] The first field-programmable gate array is also configured to receive and respond to a debugging signal to invoke the debugging interface configuration, generate a debugging screen, and transmit the debugging screen as screen data to the second field-programmable gate array.

[0027] According to one embodiment of this disclosure, the circuit board is further provided with a power module, a power management unit, and a gamma voltage unit;

[0028] The power module is used to connect to an external power source and supply power to the power management unit and the backlight driving unit;

[0029] The power management unit is configured to provide a variety of different power supply voltages to the liquid crystal display panel and to power the gamma voltage unit.

[0030] The gamma voltage unit is configured to provide the liquid crystal display panel with a common voltage and gamma binding point voltages corresponding to the grayscale of each gamma binding point.

[0031] The power for the field-programmable gate array comes from the power module or the power management unit.

[0032] According to one embodiment of this disclosure, the integrated board further includes a power supply selection unit; the power supply selection unit is configured to select one of the power module and the power management unit to supply power to the field-programmable gate array.

[0033] According to one embodiment of the present disclosure, the integrated board further includes a communication module located on the circuit board, the communication module being configured to perform at least one of receiving video signals, receiving control signals, and transmitting signals.

[0034] According to one embodiment of this disclosure, the communication module includes a video signal port and a signal conversion unit; the video signal port is configured to receive a video signal and forward it to the signal conversion unit;

[0035] The signal conversion unit is configured to transcode the video signal into the image data and forward the image data to the field-programmable gate array.

[0036] According to one embodiment of this disclosure, the video signal port includes at least one of an HDMI port, a DVI port, a VGA port, and a DP port.

[0037] According to one embodiment of this disclosure, the communication module includes a serial input port and a serial output port;

[0038] The serial input port is configured to transmit control signals to the field-programmable gate array;

[0039] The serial output port is configured to send out signals generated by the field-programmable gate array.

[0040] According to one embodiment of this disclosure, the communication module includes an infrared sensor;

[0041] The infrared sensor is configured to receive infrared signals to generate control signals and transmit the control signals to the field-programmable gate array.

[0042] According to one embodiment of this disclosure, the communication module includes a microprocessor and at least one of a serial input port, a serial output port, and an infrared sensor.

[0043] The microprocessor interacts with the field-programmable gate array;

[0044] The serial input port is configured to transmit control signals to the microprocessor or the field-programmable gate array.

[0045] The serial output port is configured to send signals generated by the field-programmable gate array or the microprocessor.

[0046] The infrared sensor is configured to receive an infrared control signal, generate a control signal, and transmit the control signal to the field-programmable gate array or the microprocessor.

[0047] According to one embodiment of this disclosure, the integrated board is provided with a system board interface module disposed on the circuit board, and the system board interface module is used to connect to the system board.

[0048] According to one embodiment of this disclosure, the system board interface module includes:

[0049] The video data port is configured to receive video data from the system board and send it to the field-programmable gate array; the video data is generated by the system board based on the video signal.

[0050] According to one embodiment of this disclosure, the integrated board includes a power module located on the circuit board;

[0051] The system board interface module includes a system board power port, which is electrically connected to the power module and configured to supply power to the system board.

[0052] According to one embodiment of the present disclosure, the system board interface module includes a backlight control port, which is used to receive a backlight control signal from the system board and transmit it to the field programmable gate array.

[0053] According to one embodiment of this disclosure, the integrated board further includes a microprocessor located on the circuit board, the microprocessor being configured to interact with the field-programmable gate array;

[0054] The system board interface module includes a backlight control port, which is used to receive backlight control signals from the system board and transmit them to the field-programmable gate array or the microprocessor.

[0055] According to one embodiment of the present disclosure, the backlight driving unit is configured to directly drive the backlight module according to the backlight driving data.

[0056] According to another aspect of this disclosure, a control module for a liquid crystal display device is provided, including the aforementioned integrated board.

[0057] According to another aspect of this disclosure, a liquid crystal display device is provided, including the control module described above; the liquid crystal display device further includes a liquid crystal display panel and a backlight module; the integrated board is electrically connected to the liquid crystal display panel and the backlight module.

[0058] According to one embodiment of this disclosure, the backlight module includes multiple arrayed lamp zones configured to be driven by local dimming.

[0059] According to one embodiment of this disclosure, the liquid crystal display panel is a splicing display panel and includes multiple sub-display panels.

[0060] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0061] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0062] Figure 1 This is a schematic diagram of the architecture of the control module in related technologies.

[0063] Figure 2 This is a schematic diagram of the driving process of the control module in related technologies.

[0064] Figure 3 This is a schematic diagram of the structure of a liquid crystal display device according to one embodiment of the present disclosure.

[0065] Figure 4 This is a schematic diagram of the structure of a liquid crystal display panel in one embodiment of the present disclosure.

[0066] Figure 5 This is a schematic diagram of the structure of a backlight module in one embodiment of the present disclosure.

[0067] Figure 6 This is a partial structural diagram of an integrated board in one embodiment of the present disclosure.

[0068] Figure 7 This is a schematic diagram of an integrated board directly receiving video signals in one embodiment of this disclosure.

[0069] Figure 8 This is a schematic diagram illustrating the interaction between an integrated board and a system board in one embodiment of this disclosure.

[0070] Figure 9 This is a schematic diagram of the driving process of the control module in one embodiment of the present disclosure.

[0071] Figure 10 This is a schematic diagram illustrating the interaction between the FPGA and the storage circuit in an integrated board according to one embodiment of this disclosure.

[0072] Figure 11 This is a schematic diagram of an integrated board with a communication module in one embodiment of the present disclosure.

[0073] Figure 12 This is a schematic diagram of an integrated board with a communication module in one embodiment of the present disclosure.

[0074] Figure 13 This is a schematic diagram of the structure of an integrated board with a system board interface module in one embodiment of this disclosure.

[0075] Figure 14 This is a schematic diagram of the structure of an integrated board with a communication module and a system board interface module in one embodiment of this disclosure.

[0076] Figure 15 This is a schematic diagram of the power module structure in one embodiment of the present disclosure.

[0077] Explanation of reference numerals in the attached figures:

[0078] PNL, LCD panel; C-TCON, screen driver board; C-SOC, system board; C-Power, voltage board; C-CONV, conversion board; BLU, backlight module; LEDD, backlight driver unit; MCU, microprocessor; SiC, source driver circuit; CTR, control module; AA, display area; BB, peripheral area; B1, first peripheral area; B2, second peripheral area; GOA, gate driver circuit; GTW, gate line; DataW, data line; LEDA, lamp area; MIC, microchip; PM, power module; PMIC, power management unit; GMIC, gamma voltage unit; STR1, first memory sub-circuit; STR2, second memory sub-circuit; STR3, third memory sub-circuit; TRU, signal conversion unit; RSIN, serial input port; RSOU T, Serial output port; IRM, Infrared sensor; CA, Rectifier and filter unit; CB, Voltage regulation unit; CC, Backlight driver unit; CD, Board power supply unit; C100, Filter; C200, Rectifier bridge; C300, PFC circuit; C400, LLC switching transformer; C500, First control circuit; C501, First rectifier and filter circuit; C502, First feedback circuit; C503, First optocoupler isolation circuit; C601, Flyback switching transformer; C602, Second rectifier and filter circuit; C603, Voltage conversion circuit; C604, Second feedback circuit; C605, Second optocoupler isolation circuit; C606, Second control circuit; FPGA, Field Programmable Gate Array; FPGA1, First Field Programmable Gate Array; FPGA2, Second Field Programmable Gate Array. Detailed Implementation

[0079] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0080] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0081] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0082] Figure 1 This diagram illustrates the architecture of a control module for a liquid crystal display device in related technologies. In these technologies, the control module includes four boards: a conversion board C-CONV, a system board C-SOC, a voltage board C-Power, and a screen driver board C-TCON. The voltage board C-Power supplies power to the system board C-SOC and the conversion board C-CONV. Upon receiving a video signal, the system board C-SOC transcodes it into image data and transmits it to the screen driver board C-TCON. The screen driver board C-TCON generates image synchronization data and transmits it to the source drive circuit of the liquid crystal display panel (PNL), enabling the source drive circuit to drive the liquid crystal display panel (PNL) according to the image data. On the other hand, the screen driver board C-TCON also needs to calculate the local dimming data of the backlight module BLU based on the screen data, and send the local dimming data to the microprocessor MCU on the conversion board C-CONV. The microprocessor MCU generates backlight driving data based on the local dimming data and sends it to the backlight driving unit LEDD on the conversion board C-CONV. The backlight driving unit LEDD drives each light source of the backlight module BLU according to the backlight driving data.

[0083] Generally, after receiving image data, the C-TCON screen driver board can send image synchronization data in as little as 0.5 frames, but it needs 2.5 frames to generate local dimming data. The microprocessor (MCU) needs 1 frame to receive the local dimming data and send backlight drive data, and the backlight drive unit (LEDD) needs 0.5 frames to refresh the duty cycle of each light source based on the backlight drive data. This causes the brightness change of the backlight module (BLU) to lag behind the image change of the LCD panel (PNL) by 3.5 frames. See also... Figure 2 After accelerating the processing speed of local dimming data, when the system board C-SOC sends the data of the Nth frame (Frame N) to the screen driver board C-TCON, the screen driver board C-TCON can send the data of the (N-1)th frame (Frame N-1) (this data is frame synchronization data) to the source driver circuit SiC and the (N-1)th frame (Frame N-1) (this data is local dimming data) to the microprocessor MCU. The microprocessor MCU sends the data of the (N-2)th frame (Frame N-1) (this data is backlight driving data) to the backlight driver unit LEDD. Therefore, even with accelerated processing of local dimming data, the brightness change of the backlight module BLU is still delayed by one frame compared to the image change of the liquid crystal display panel PNL. In this case, the response speed of the liquid crystal display panel PNL is greater than the response speed of the backlight module BLU, which may affect the display quality of the display device. For example, when a display device shows a small white block in a dynamic crosstalk (white block in the center with a black border) image, the user may perceive a delayed darkening at the edges of the white block, causing eye discomfort. In some implementations, the screen synchronization data can be the same as the screen data, i.e., a vertical or horizontal synchronization signal with synchronization signals emitted by the screen driver board C-TCON. See also Figure 3 This disclosure provides a liquid crystal display device and its control module CTR. The liquid crystal display device includes a liquid crystal display panel (PNL), a backlight module (BLU), and a control module (CTR). See also... Figure 4 and Figure 5 The liquid crystal display panel (PNL) has a source drive circuit (SIC) for driving pixels, and the backlight module (BLU) has multiple arrayed lamp areas (LEDA). An integrated board is provided in the control module (CTR) of this disclosure.

[0084] In some exemplary embodiments, the liquid crystal display panel (PNL) can be a modular liquid crystal display panel. Specifically, it is composed of multiple sub-display panels joined together.

[0085] See Figure 6The integrated board C-Mult includes an FPGA (Field-Programmable Gate Array) and a backlight driver unit (LEDD) mounted on the same circuit board. The FPGA is configured to receive image data, generate image synchronization data based on the image data, and send it to the liquid crystal display panel (PNL); and to generate backlight driving data based on the image data and send it to the backlight driver unit (LEDD). The backlight driver unit (LEDD) is configured such that the delay time between receiving the backlight driving data and directly driving the backlight module according to the backlight driving data, and the delay time between receiving the image synchronization data and the delay time between receiving the backlight driving data and the delay time between receiving the image synchronization data, is less than the time of one frame. For example, the delay time can be zero, or half a frame, one-third of a frame, etc.

[0086] In some implementations, the backlight driving unit LEDD is configured to directly drive the backlight module BLU according to the backlight driving data.

[0087] In the liquid crystal display device disclosed herein, an FPGA is used to replace some functions of the traditional screen driver board C-TCON. The FPGA can generate backlight driving data that directly drives the backlight driving unit LEDD based on the screen data. Thus, the FPGA sends screen synchronization data to the source driver circuit SiC and backlight driving data to the backlight driving unit LEDD simultaneously, based on the screen data. The source driver circuit SiC drives the liquid crystal display panel PNL according to the screen synchronization data, and the backlight driving unit LEDD drives the backlight module BLU according to the backlight driving data. This ensures synchronized responses between the liquid crystal display panel PNL and the backlight module BLU, overcoming the problem of low display quality (e.g., flickering) caused by the liquid crystal display panel PNL responding faster than the backlight module BLU.

[0088] In related technologies, the local dimming data sent by the screen driver board C-TCON cannot be directly used by the backlight driver unit LEDD. The local dimming data needs to be processed by the microprocessor to generate backlight driver data that can be directly used by the backlight driver unit LEDD.

[0089] In this disclosure, the backlight driving unit (LEDD) directly drives the backlight module (BLU) based on the backlight driving data. This means that the backlight driving data can be directly applied to the LEDD without further processing by a microprocessor or other processing unit. Specifically, the backlight module is driven based on the backlight driving data. It is understood that the FPGA and the LEDD can be directly connected via traces (e.g., data lines or serial data lines on a circuit board) or via other devices (e.g., drivers), ensuring that the backlight driving data generated by the FPGA can be transmitted to the LEDD. In this disclosure, the backlight driving data received by the LEDD and the backlight driving data output by the FPGA can have the same electrical signal. Specifically, the backlight driving data output by the FPGA is transmitted to the LEDD without delay.

[0090] The structure, principle, and effects of the display device disclosed herein will be further explained and illustrated below with reference to the accompanying drawings.

[0091] From a structural perspective, a liquid crystal display panel (PNL) may include an array substrate and a color filter substrate stacked sequentially. A liquid crystal cell, encapsulated with adhesive, is disposed between the array substrate and the color filter substrate, and liquid crystal is disposed within the liquid crystal cell. The PNL also includes a first polarizer located on the side of the array substrate away from the color filter substrate and a second polarizer located on the side of the color filter substrate away from the array substrate. Pixel electrodes and pixel driving circuits for applying data voltage to the pixel electrodes are disposed on the array substrate. A common electrode is disposed on either the array substrate or the color filter substrate. By controlling the electric field strength between the pixel electrode and the common electrode, the degree of twisting or collapsing of the liquid crystal within the corresponding range of the pixel electrode can be adjusted, thereby adjusting the polarization direction of the polarized light passing through the liquid crystal, and ultimately adjusting the light extraction efficiency of the PNL within the corresponding range of the pixel electrode.

[0092] Figure 4A schematic diagram of a liquid crystal display panel (PNL) according to an embodiment of the present disclosure is shown. From a planar perspective, the liquid crystal display panel (PNL) may include a display area AA and a peripheral area BB surrounding the display area AA. In the display area AA, an array substrate is provided with gate lines GTW extending in the row direction and data lines DataW extending in the column direction. The gate lines GTW and data lines DataW define a plurality of pixel areas, and pixel electrodes and pixel driving circuits may be located in the pixel areas. In the example, the pixel driving circuit may be a thin-film transistor as a switching transistor. One end of the switching transistor is electrically connected to the data line DataW, and the other end of the switching transistor is connected to the pixel electrode. The gate of the switching transistor is connected to the gate line GTW. The peripheral area BB of the array substrate has a first peripheral area B1 with a source driving circuit SIC bonded thereon, and a second peripheral area B2 with a gate driving circuit GOA disposed thereon. The first peripheral area B1 is located at one end of the array substrate in the column direction, and the second peripheral area B2 is located at one end of the array substrate in the row direction. The gate driving circuit GOA is electrically connected to each gate line GTW and is used to load a scan signal to the gate line GTW to turn on the switching transistor. The source drive circuit SiC is electrically connected to the data line DataW and is used to generate a data voltage based on the screen synchronization data and apply it to the data line DataW.

[0093] See Figure 4 In this example, the liquid crystal display panel (PNL) has multiple source driver circuits (SICs), each of which can drive multiple data lines (DataW). Furthermore, the source driver circuits (SICs) are chips; the array substrate has an FPC bonding area and a source driver circuit (SIC) bonding area in the first peripheral area B1. Source driver circuits (SICs) can be bonded within the source driver circuit (SIC) bonding area, and these bonding areas are electrically connected to the data lines (DataW) and the FPC bonding area via traces. The FPC bonding area can be bonded to the integrated circuit board via an FPC. Thus, signals and voltages on the integrated circuit board can be transmitted to the source driver circuits (SICs) via the FPC. Furthermore, the signal between the source driver circuits (SICs) and the integrated circuit board can be an LVDS (Low Voltage Differential) signal or a mini LVDS signal to reduce signal crosstalk.

[0094] Of course, in other embodiments of this disclosure, the liquid crystal display panel PNL can also have other structures. For example, the gate driving circuit GOA can be additionally bonded to the array substrate instead of being provided on it; for another example, gate driving circuits GOA can be provided on both sides of the array substrate in the row direction to reduce the scanning signal voltage drop or increase the scanning frequency; for yet another example, source driving circuits SiC can be provided at both ends of the array substrate in the column direction to drive the liquid crystal display panel PNL on both sides, reducing the voltage drop on the data lines DataW in large-size liquid crystal display panel PNLs, especially reducing the voltage drop on the data lines DataW in splicing screens. For yet another example, the source driving circuit SiC can be provided on the COF (chip-on-film) instead of on the liquid crystal display panel PNL. This disclosure does not limit the relative positional relationship and arrangement of the source driving circuit SiC and the display panel PNL, as long as the source driving circuit SiC can directly drive each pixel of the display area of ​​the PNL.

[0095] In this embodiment of the disclosure, the backlight module (BLU) is a direct-lit backlight. See also... Figure 5 The direct-lit backlight includes a lamp panel with an array of LED zones (LEDA). Each LED zone contains one or more synchronously controlled light-emitting elements (e.g., Mini LEDs or Micro LEDs). Under the control of the backlight driving unit (LEDD), the brightness of each LED zone can be independently controlled to coordinate with the image displayed on the liquid crystal display panel (PNL), thereby improving the display effect of the display device. In one example, the backlight driving unit (LEDD) controls the brightness of each LED zone by controlling the duty cycle of each light-emitting element during emission.

[0096] In one example, see Figure 5 The LED board can be equipped with microchips (MICs), each of which can control one or more LED zones (LEDA). For example, one microchip MIC can control one LED zone or four LED zones. The backlight driver unit (LEDD) can send LED zone data for each controlled LED zone to each microchip MIC. Based on the LED zone data, the microchip MIC determines the on-time of each controlled LED zone, thereby controlling the duty cycle of each LED zone. In other words, the backlight driver unit (LEDD) can refresh the duty cycle of each LED zone by loading LED zone data into each microchip MIC. Furthermore, when the light-emitting elements of each LED zone emit light, the brightness is basically the same, meaning the current flowing through each light-emitting element is basically the same.

[0097] For example, in one embodiment, the lamp board is provided with control units, lamp area power supply traces, lamp area grounding traces, and data traces. Each control unit may include a microchip (MIC) and lamp areas (LEDA) controlled by the microchip. Each LEDA includes one or more light-emitting elements, which can be connected in parallel, in series, or in a hybrid parallel / series connection. The first power supply terminal of each LEDA is electrically connected to the lamp area power supply trace, and the second power supply terminal of each LEDA is electrically connected to the control pin of the microchip. The lamp area power supply trace can be loaded with a relatively stable driving voltage (ACC), and the lamp area grounding trace can be loaded with a ground voltage (GND). When the microchip controls multiple LEDA areas, the control pins connected to each LEDA area are different. The microchip connects to the data trace and the lamp area grounding trace to receive lamp area data from the backlight driver unit (LEDD) via the data trace, and controls the electrical connection between each control pin and the lamp area grounding trace based on the received lamp area data. Under the control of the microchip MIC, when the control pin is electrically connected to the lamp area grounding trace, each light-emitting element in the LEDA lamp area connected to the control pin is in a conductive state. The current on the lamp area power supply trace flows through the light-emitting elements to the lamp area grounding trace, thus causing each light-emitting element to emit light under a basically constant current. Under the control of the microchip MIC, when the control pin is electrically disconnected from the lamp area grounding trace, each light-emitting element in the LEDA lamp area connected to the control pin is in an open-circuit state. The current on the lamp area power supply trace cannot flow through the light-emitting elements to the lamp area grounding trace, thus causing each light-emitting element to not emit light. In this way, under the control of the lamp area data, the microchip MIC can control the duty cycle of each light-emitting element in the LEDA lamp area by controlling the proportion of electrical conduction and disconnection of each control pin, which ultimately manifests as control of the macroscopic brightness of each LEDA lamp area. In this embodiment, the backlight driving unit LEDD also needs to apply an operating voltage to the microchip MIC to enable the microchip MIC to operate. The lamp board can be additionally equipped with chip power lines to apply operating voltage to the microchip MIC, or it can apply operating voltage to the microchip MIC via data traces. For example, the data traces can be reused as chip power lines, thereby using power line carrier communication technology to simultaneously apply operating voltage and lamp zone data to the microchip MIC.

[0098] In one example, sensors, such as temperature sensors and brightness sensors, can also be installed on the light board. The sensing signals generated by these sensors can be sent directly to the backlight driver unit (LEDD) or forwarded to the backlight driver unit (LEDD) via the microchip (MIC). The backlight driver unit (LEDD) can directly adjust the working state or process of the backlight module (BLU) based on these sensing signals, or feed these sensing signals back to the FPGA and have the FPGA adjust the backlight driving data based on these sensing signals.

[0099] In one example, the light board may include a substrate, a driving layer, and a component layer stacked sequentially. The driving layer has at least two wiring metal layers, such as two copper-containing wiring metal layers. The wiring metal layers are isolated by an insulating layer, which may be an inorganic insulating layer (e.g., silicon nitride or silicon oxide) or an organic insulating layer (e.g., resin), or a combination of stacked inorganic and organic insulating layers. The wiring metal layers can be connected vias penetrating the insulating layer. The surface of the wiring metal layer furthest from the substrate may have bonding pads for bonding electronic components, such as light-emitting elements, microchips (MICs), and sensors.

[0100] In one example, the substrate of the lamp panel can be a glass substrate. Furthermore, the lamp panel can be composed of multiple sub-lamp panels spliced ​​together; the sub-lamp panels are electrically connected to each other, or each sub-lamp panel is independent and directly controlled by the backlight driving unit LEDD.

[0101] In one example, all the light-emitting elements emit the same color, for example, all are blue light-emitting elements. A photoluminescent layer, such as a quantum dot film, is also provided on the lamp panel to convert the blue light into a more uniform white light.

[0102] In some examples, the backlight module (BLU) may also be provided with one or more of the following: collimating film, bandpass filter, diffuser, brightness enhancement film, or other optical film materials, without limitation in this disclosure.

[0103] It is understood that the backlight module (BLU) of the present disclosure may also adopt other structures, such as using light strips to form a light panel. These methods will not be described in detail in this disclosure.

[0104] In some implementations, see Figure 6In addition to the FPGA and backlight driver unit LEDD, which are mounted on the same circuit board, the integrated board also includes a power module PM, a power management unit PMIC, and a gamma voltage unit GMIC. The power module PM connects to an external power supply and supplies power to the power management unit PMIC and the backlight driver unit LEDD. The power management unit PMIC is configured to provide various power voltages to the liquid crystal display panel PNL and to power the gamma voltage unit GMIC. The gamma voltage unit GMIC is configured to provide the liquid crystal display panel PNL with a common voltage VCOM and gamma binding point voltages VGamma corresponding to each gamma binding point grayscale. The FPGA is powered by either the power module PM or the power management unit PMIC. Thus, the integrated board of this disclosure can at least realize the functions of the screen driver board C-TCON, voltage board C-Power, and conversion board C-CONV in related technologies. This reduces the number of boards in the control module CTR, thereby improving the integration of the control module CTR and increasing the assembly efficiency of the display device.

[0105] Furthermore, units with the same function, originally located on boards such as the screen driver board C-TCON, voltage board C-Power, and conversion board C-CONV, can be merged or reused. This avoids resource waste and cost increases caused by setting up units with the same function in the control module CTR, effectively simplifying the structure of the control module CTR and reducing its cost. For example, in related technologies, the screen driver board C-TCON and conversion board C-CONV may both have units related to local dimming functions, which overlap in function and lead to resource waste. Similarly, the voltage board C-Power and conversion board C-CONV both have units related to the lamp area power supply voltage (ACC, used to provide drive voltage to the lamp area), which overlap in function and also lead to resource waste. In this embodiment, these functionally overlapping or related units, originally distributed on different boards, can be merged, simplified, or implemented using an FPGA, thereby reducing the number of functional units in the control module CTR and minimizing waste and cost increases caused by functional overlap.

[0106] In related technologies, individual boards need to be connected via wires and connectors (ports), which is not only complex but also costly. The integrated board of this disclosure has all units located on the same circuit board, eliminating the need for wires to connect individual functional units. This offers advantages such as high integration and low cost, resulting in a cleaner overall design and improved assembly efficiency of the control module (CTR). Furthermore, compared to previous multi-board designs, the integrated board of this disclosure has a smaller board area, which helps reduce the size and cost of the display device, facilitating its thinner and lighter design.

[0107] See Figure 6 In some embodiments of this disclosure, the power management unit (PMIC) can supply power to the FPGA, for example, by providing 3.3V as the FPGA's operating voltage. Of course, in other embodiments of this disclosure, the FPGA's power can come from the power module (PM) instead of the PMIC; that is, the power module (PM) can directly supply power to the FPGA (e.g., ...). Figure 11 (As shown by the dashed arrow in the image).

[0108] In one embodiment, the integrated board further includes a power selection unit configured to select either the power module PM or the power management unit PMIC to power the FPGA. For example, the power selection unit can monitor the power consumption of the power management unit PMIC; when the power consumption of the power management unit PMIC is greater than a preset power consumption, the power module PM is selected to power the FPGA. When the power consumption of the power management unit PMIC is less than the preset power consumption, the power management unit PMIC is selected to power the FPGA.

[0109] In one embodiment of this disclosure, see Figure 6The integrated board includes a circuit board and an FPGA, a power management unit (PMIC), a gamma voltage unit (GMIC), a power module (PM), and a backlight driver unit (LEDD) mounted on the circuit board. The circuit board also has a panel port (PNL-CNT) for connecting to the liquid crystal display panel (PNL), a backlight port (BLU-CNT) for connecting to the backlight module (BLU), and a power port (AC-CNT) for connecting to an external power supply. Depending on the distribution of the bonding pads on the liquid crystal display panel (PNL), there can be one or more panel ports; for example, there can be two panel ports. Depending on the distribution of the bonding pads on the lamp board of the backlight module (BLU), there can be one or more backlight ports; for example, nine panel ports can be provided. Each panel port can control one or more signal channels on the backlight module (BLU), and each signal channel has multiple LED areas (LEDA), for example, multiple LED areas controlled by cascaded microchips (MICs). Optionally, the panel ports and backlight ports can be sequentially arranged pads or connectors for insertion, or other feasible structures.

[0110] See Figure 6 and Figure 9 FPGAs can improve the response synchronization of the LCD panel PNL and the backlight module BLU by employing a strategy of buffering and sending one frame at a time. Specifically, when the FPGA receives the (N-1)th frame of image data, it can buffer and process it first; when it receives the Nth frame of image data, it can send out the data of the (N-1)th frame. During transmission, the image synchronization data of the (N-1)th frame can be sent to the source driver circuit SiC, so that the source driver circuit SiC can directly drive the LCD panel PNL according to the image synchronization data of the (N-1)th frame; the backlight driving data of the (N-1)th frame can be sent to the backlight driver unit LEDD, so that the backlight driver unit LEDD can directly drive the backlight module BLU according to the backlight driving data of the (N-1)th frame. In this way, the LCD panel PNL and the backlight module BLU process the data of the (N-1)th frame simultaneously, achieving response synchronization. In this method, the FPGA does not need to send the backlight synchronization data first and then have other units generate the backlight driving data based on the backlight synchronization data, thus avoiding the response asynchrony caused by the above method.

[0111] In some embodiments of this disclosure, the integrated board further includes a storage module for storing programs, configuration information, and buffered data. In one example, the storage module is a storage circuit located on the circuit board. In another example, the storage module is a storage cell of a field-programmable gate array (FPGA). In yet another example, the storage module consists of a storage cell of the FPGA and a storage circuit located on the circuit board. In the examples where a storage circuit is provided, by introducing the storage circuit outside the FPGA as part of the storage module, the limitation of the FPGA's functionality on the size of its storage cells can be reduced, and space can be reserved for future functional upgrades of the integrated board.

[0112] In some embodiments of this disclosure, the storage module is configured to store configuration information of the backlight driving unit, debugging interface configuration, and at least a portion of the program of the field-programmable gate array.

[0113] The field-programmable gate array is configured to generate the screen synchronization data and the backlight synchronization data according to the screen data, and cache the screen synchronization data and the backlight synchronization data in the storage module.

[0114] The field-programmable gate array is also configured to forward the screen synchronization data in the storage module to the liquid crystal display panel, generate the backlight driving data according to the backlight synchronization data in the storage module and the configuration information of the backlight driving unit, and send it to the backlight driving unit.

[0115] The field-programmable gate array is also configured to invoke the debugging interface configuration in response to a debugging signal, and to cause the display device to display the debugging interface.

[0116] In one embodiment of this disclosure, see Figure 10The storage circuit includes a first storage sub-circuit STR1 located on the circuit board, which interacts with the FPGA. The first storage sub-circuit STR1 stores synchronization data and configuration information of the backlight driver unit (LEDD). The FPGA is configured to generate screen synchronization data and backlight synchronization data based on the screen data, and cache these data in the first storage sub-circuit STR1. The FPGA is also configured to forward the screen synchronization data from the first storage sub-circuit STR1 to the liquid crystal display panel (PNL), and generate backlight driving data based on the backlight synchronization data and LEDD configuration information in the first storage sub-circuit STR1, and send it to the LEDD. Thus, after receiving screen data, the FPGA can generate synchronization data (including screen synchronization data and backlight synchronization data) and cache it in the first storage sub-circuit STR1. Then, it can read the screen synchronization data (in some cases, the screen synchronization data is the same as the screen data) from the first storage sub-circuit STR1 and send it to the panel port on the integrated circuit board, thereby transmitting the screen synchronization data to the source driver circuit (SIC). The FPGA can also call the backlight synchronization data and configuration information of the backlight driver unit LEDD stored in the first storage sub-circuit STR1, thereby generating backlight driver data that can directly control the backlight driver unit LEDD, and sending the backlight driver data to the backlight driver unit LEDD.

[0117] In one embodiment of this disclosure, see Figure 10 The storage circuit includes a second storage sub-circuit STR2 located on the circuit board, which stores the debugging interface configuration of the display device. The FPGA is also configured to invoke the debugging interface configuration in response to a debugging signal and cause the display device to display the debugging interface. When the FPGA receives a debugging signal, in addition to debugging the display device in response to the signal, it can also invoke the debugging interface configuration to generate a debugging interface and control the backlight module BLU and the liquid crystal display panel PNL to display the debugging interface.

[0118] In one embodiment of this disclosure, see Figure 10 The storage circuit includes a third storage sub-circuit STR3 located on the circuit board. The third storage sub-circuit STR3 can be used to store part or all of the FPGA's programming data (program) to avoid the limitation of FPGA's function by insufficient storage capacity of the FPGA's internal static storage unit.

[0119] It is understood that the storage circuit of this disclosure may include one, two, or all of the first storage sub-circuit STR1, the second storage sub-circuit STR2, and the third storage sub-circuit STR3 described above. For example, in Figure 10 In the example implementation, the storage circuit includes a first storage sub-circuit STR1, a second storage sub-circuit STR2, and a third storage sub-circuit STR3. In other examples of this disclosure, the storage circuit may also include other storage sub-circuits to implement other functions or reserve storage redundancy for upgrades to the integrated board's functions. In this disclosure, the various storage sub-circuits may be different locations within the same memory (e.g., different partitions) or the same memory; this disclosure does not limit this. In some other implementations, the storage sub-circuit may also be an external memory connected to the FPGA via an interface; this allows for hardware upgrades to the integrated board by replacing the external memory, providing versatility to the integrated board.

[0120] In some embodiments of this disclosure, two or more interactive FPGAs can be configured on the integrated board to avoid insufficient functionality of a single FPGA. When multiple FPGAs are configured, any two FPGAs can be identical or different. Furthermore, when multiple FPGAs are configured, each FPGA can perform different tasks. In one example, along the information transmission direction of the screen data, the last-stage FPGA is used to load screen synchronization data to the panel port and to load backlight driving data to the backlight driving unit LEDD.

[0121] In one example, the integrated board has two FPGAs: a first field-programmable gate array (FPGA1) and a second field-programmable gate array (FPGA2). FPGA1 is connected to a second storage sub-circuit STR2; FPGA1 is configured to receive screen data and forward it to FPGA2. FPGA1 can also be configured to receive debug signals, and upon receiving a debug signal, it can invoke the debug interface configuration stored in the second storage sub-circuit STR2 and generate debug interface data, which is sent to FPGA2 as screen data. FPGA2 is configured to generate screen synchronization data and backlight driving data based on the screen data; FPGA2 is also configured to send the screen synchronization data to the liquid crystal display panel (PNL) and the backlight driving data to the backlight driving unit (LEDD) within the same frame time.

[0122] For example, after receiving the screen data, FPGA2 can parse the synchronization data (including screen synchronization data and backlight synchronization data) and cache it in the first storage sub-circuit STR1. FPGA2 can also send the screen synchronization data to the panel port (e.g., in the form of a MiniLVDS signal). The source driver circuit SIC can receive the signal sent by the panel port (e.g., a MiniLVDS signal) to obtain the screen synchronization data. Within the same frame, FPGA2 can also call the configuration information and backlight synchronization data of the backlight driver unit LEDD stored in the first storage sub-circuit STR1 to generate backlight driver data for directly controlling the backlight driver unit LEDD. This backlight driver data is sent to the backlight driver unit LEDD (e.g., via a serial peripheral interface SPI). It is understood that in the above example, FPGA2 and the source driver circuit SIC can also communicate using other signal methods, such as using LVDS signals. FPGA2 and the backlight driver unit LEDD can also communicate using other signal methods, such as using TTL (transistor-to-transistor logic level) signals.

[0123] Optional, see Figure 10 The third storage sub-circuit STR3 can interact with FPGA2, enabling FPGA2 to perform more complex calculations and process screen data and generate backlight drive data more efficiently and quickly.

[0124] Optional, see Figure 10 FPGA2 can also send a clock signal CLK to FPGA1, for example, to the digital clock management module of FPGA1, so that the clocks of FPGA1 and FPGA2 are synchronized.

[0125] Optionally, FPGA1 and FPGA2 can interact using either SPI or TTL signals. For example, when FPGA1 receives screen data as a TTL signal, FPGA1 can forward the screen data to FPGA2 via the TTL signal. In one example, screen data is transmitted using a 24-channel TTL signal.

[0126] Optionally, the FPGA can use an SPI signal to send backlight driving data to the backlight driving unit LEDD.

[0127] In the example above, the integrated board was exemplarily described with two FPGAs and three storage sub-circuits. In other embodiments of this disclosure, the number of FPGAs may be three or more, or even just one. The number of storage sub-circuits may be more or less, for example, four or five.

[0128] See Figure 6 The power module PM can be connected to a power port to receive external power (such as commercially available AC power) and power the components on the integrated board.

[0129] Optionally, the power module PM can be a wide-voltage power supply component, capable of adapting to a large input voltage range, such as 70V to 300V. In one example, the input voltage adaptation range of the power module PM is 90V to 264V.

[0130] Optionally, the power module PM can be adapted to a rated input current of no more than 3A, for example, the rated input current adapted to the power module PM is around 2A.

[0131] Optionally, the power module PM can provide power to the power management unit (PMIC), for example, by providing a constant voltage of approximately 12V. Furthermore, the rated current supplied to the PMIC does not exceed 1.5A.

[0132] Optionally, the power module PM can provide power to the backlight driver unit LEDD, for example, by providing a constant voltage in the range of 10V to 20V. Furthermore, the rated current of the power supplied by the power module PM to the backlight driver unit LEDD does not exceed 8.5A.

[0133] In one example, the power module PM provides power to the backlight driver unit LEDD, a portion of which can be directly transferred to the backlight port to directly power the backlight module BLU's lamp board. In other words, the power module PM can supply power to the lamp board via the backlight port through the wiring of the backlight driver unit LEDD; the backlight driver unit LEDD is used to directly or indirectly control the duty cycle of each light-emitting device on the lamp board.

[0134] Optionally, the backlight driver unit LEDD can collect the voltage at the output terminal of the backlight module BLU and adjust the voltage applied to the input terminal of the backlight module BLU by the power module PM according to the voltage at the output terminal of the backlight module BLU, thereby ensuring that the driving voltage (ACC) applied to the lamp area LEDA of the backlight module BLU is stable, which is conducive to realizing constant current driving of the light-emitting element.

[0135] The following example illustrates one implementation of the power module PM on the integrated board according to embodiments of this disclosure. It should be understood that the power module PM according to embodiments of this disclosure is not limited to the following example.

[0136] See in this example. Figure 15 The power module PM includes a rectifier and filter unit CA, a voltage regulator unit CB, a backlight power supply unit CC, and a board power supply unit CD.

[0137] See Figure 15 The rectifier and filter unit CA may include a filter C100 connected to the power supply port and a rectifier bridge C200 cascaded with the filter C100 to shape the external AC power into DC power. Optionally, the filter C100 is an EMI filter.

[0138] The voltage regulation unit CB includes a PFC circuit C300, an LLC switching transformer C400, and a first control circuit C500. The input terminal of the PFC circuit C300 is connected to the output terminal of the rectifier bridge C200. The first control circuit C500 samples the output terminal of the PFC circuit C300 or a node within the circuit to obtain a feedback signal, and generates a first drive signal based on the feedback signal provided by the PFC circuit C300 to regulate the PFC circuit C300, thereby enabling the PFC circuit C300 to output a stable DC voltage V1 under the regulation of the first control circuit C500. The input terminal of the LLC switching transformer C400 is electrically connected to the output terminal of the PFC circuit C300, and its control terminal is connected to the first control circuit C500. The LLC switching transformer C400 is used to output voltage to the backlight power supply unit CC under the control of the second drive signal issued by the first control circuit C500. In one example, the DC voltage V1 can be in the range of 350 to 450V, for example, 400V.

[0139] The backlight power supply unit CC includes a first rectifier and filter circuit C501, a first feedback circuit C502, and a first optocoupler isolation circuit C503. The input terminal of the first rectifier and filter circuit C501 is connected to the output terminal of the LLC switching transformer C400, and is used to shape the voltage signal input to the LLC switching transformer C400 into a DC voltage V2. In one example, the DC voltage V2 is in the range of 10–20V, for example, 13.4V. The first control circuit C500 can adjust the output of the LLC switching transformer C400 through a second drive signal, thereby adjusting the DC voltage V2 after being filtered and shaped by the first rectifier and filter circuit C501. The output terminal of the first rectifier and filter circuit C501 can be connected to the backlight module BLU, particularly to the upstream (closer to the positive terminal of the battery) of the lamp area power supply trace of the backlight module BLU (the lamp area power supply trace is used to apply drive voltage to the light-emitting elements in the lamp area), thereby providing drive voltage (ACC) to each light-emitting element of the backlight module BLU. The backlight driving unit LEDD can sample the voltage on the backlight module BLU to obtain a sampled voltage. The first feedback circuit C502 can compare the sampled voltage with the DC voltage V2 to generate a feedback signal. This feedback signal is fed back to the first control circuit C500 through the first optocoupler isolation circuit C503. The first control circuit C500 adjusts the second driving signal based on the feedback from the first optocoupler isolation circuit C503. In this way, the operating state of the LLC switching transformer C400 can be matched with the load changes on the backlight module BLU, improving the operating stability and backlight accuracy of the backlight module BLU.

[0140] The DD circuit includes a flyback switching transformer C601, a second rectifier and filter circuit C602, a voltage conversion circuit C603, a second feedback circuit C604, a second optocoupler isolation circuit C605, and a second control circuit C606. The input of the flyback switching transformer C601 is connected to the output of the PFC circuit C300, and under the control of the third drive signal provided by the second control circuit C606, it outputs a voltage signal to the second rectifier and filter circuit C602. The second rectifier and filter circuit C602 shapes and filters the voltage signal output from the flyback switching transformer C601 to form a DC voltage V3. This DC voltage V3 can be directly supplied to the power management unit (PMIC) as its power supply. The voltage conversion circuit C603 can step down the DC voltage V3 to a DC voltage V4, which can then be used as the power supply for the FPGA. Of course, in other embodiments of this disclosure, the FPGA can also be powered by a power management unit (PMIC). In this case, the output of the voltage conversion circuit C603 may not be electrically connected to the FPGA, or the power module PM may not have a voltage conversion circuit C603. The second feedback circuit C604 can sample the DC voltage V3 to generate a feedback signal. This feedback signal is fed back to the second control circuit C606 via the second optocoupler isolation circuit C605, thereby enabling the second control circuit C606 to adjust the third drive signal according to the feedback signal, thereby maintaining the stability of the DC voltage V3. In one example, the DC voltage V3 can be in the range of 10V to 18V, for example, 12V. In one example, the DC voltage V4 can be in the range of 2V to 6V, for example, 3.3V.

[0141] In the examples described above in this disclosure, the power management unit (PMIC) may not supply power to the FPGA; instead, the power supply module (PM) may directly power the FPGA to avoid excessive power consumption by the PMIC. See other examples in this disclosure. Figure 6 The power module (PM) can supply power to the power management unit (PMIC), which in turn can supply power to the FPGA.

[0142] See Figure 11The Power Management Unit (PMIC) generates AVDD and provides it to the Liquid Crystal Display (PNL) via the panel connector to power some components within the PNL, such as the source driver circuit SiC. The PMIC also generates and provides VGL (gate drive low level) and VGH (gate drive high level) voltages to the PNL via the panel connector. Furthermore, the PMIC generates HAVDD (half of the AVDD voltage) and provides it to the Gamma Voltage Unit (GMIC) as its operating voltage. Powered by the PMIC, the Gamma Voltage Unit generates the gamma binding point voltage VGamma corresponding to each gamma binding point grayscale based on stored gamma register data and transmits VGamma to the source driver circuit SiC. Thus, the source driver circuit SiC determines the gamma voltage of each pixel based on the synchronized image data and the gamma binding point voltage VGamma. In this way, the source driver circuit SiC achieves gamma compensation for the displayed image. (See also...) Figure 11 In this example, the Gamma Voltage Unit (GMIC) can also generate a common voltage (VCOM) and transmit it to the LCD panel (PNL).

[0143] In some embodiments of this disclosure, the integrated board further includes a communication module located on the circuit board, the communication module being configured to perform at least one of the functions of receiving video signals, receiving control signals, and transmitting signals. See also... Figure 7 The integrated board can directly receive video signals and provide image data to the FPGA based on the video signals.

[0144] In one embodiment of this disclosure, see Figure 11 The communication module includes at least one video signal port and a signal conversion unit (TRU). The video signal port is configured to receive video signals and forward them to the TRU. The TRU is configured to transcode the video signals into the image data and forward the image data to the FPGA. In this way, the communication module can receive video signals and provide image data to the FPGA based on the video signals, enabling the integrated board to also achieve the functionality of a system-on-a-chip (C-SOC) board in related technologies. This can further reduce the number of boards in the control module (CTR).

[0145] In one example, see Figure 11The signal conversion unit (TRU) can forward screen data to the FPGA in the form of TTL signals, for example, in the form of 24-channel TTL signals. It is understood that in other examples of this disclosure, the TRU may also use other signals to forward screen data, such as SPI signals, LVDS signals, or Mini LVDS signals.

[0146] Optionally, the video signal port is selected from one or more of the following: HDMI port, DVI port, VGA port, and DP port. In one example, the integrated board is equipped with both HDMI and DVI ports.

[0147] In one embodiment of this disclosure, see Figure 11 The communication module of the integrated board may also include a serial communication port to enable the integrated board to communicate with external devices. Further, the serial communication port may include a serial input port RSIN and a serial output port RSOUT. The serial input port RSIN can receive external communication signals, for example, it is configured to receive external control signals and transmit them to the FPGA; the serial output port RSOUT is used to send communication signals to the outside, for example, it is configured to send signals generated by the FPGA. In one example, the serial input port RSIN and the serial output port RSOUT are RS-232 standard interfaces (asynchronous transfer standard interfaces).

[0148] In one example, see Figure 11 The serial input port RSIN forwards communication signals to the FPGA, which then responds to them. For example, a debugging device can send a debugging signal (as a communication signal) to the FPGA via RSIN. The FPGA responds to this signal by adjusting the display state of the display device, such as adjusting the color temperature, resolution, or displaying the debugging interface. The serial output port RSOUT receives communication signals from the FPGA and forwards them.

[0149] In some embodiments of this disclosure, see Figure 11 The communication module further includes an infrared sensor (IRM); the infrared sensor (IRM) is configured to receive infrared signals to generate control signals and transmit the control signals to the FPGA.

[0150] In another embodiment of this disclosure, see [link to relevant documentation]. Figure 12The communication module of the integrated board may also include a microprocessor (MCU), which interacts with the FPGA; the serial input port RSIN is configured to transmit control signals to the microprocessor (MCU) or the FPGA; the serial output port RSOUT is configured to send signals generated by the FPGA or the microprocessor (MCU) to the outside; the infrared sensor (IRM) is configured to receive infrared control signals, generate control signals, and transmit the control signals to the FPGA or the microprocessor (MCU).

[0151] In this way, the microprocessor (MCU) can communicate with the serial input port RSIN, the serial output port RSOUT, and the FPGA. Communication signals received at the serial input port RSIN can be forwarded to the microprocessor (MCU), which can directly respond to the communication signal, or preprocess the signal before forwarding it to the FPGA for further response. The microprocessor (MCU) can directly forward the communication signal received at the serial input port RSIN through the serial output port RSOUT, or generate a relay signal based on the communication signal received at the serial input port RSIN and forward it through the serial output port RSOUT, or generate a communication signal in response to FPGA instructions and forward it through the serial output port RSOUT.

[0152] In one embodiment, the display device includes multiple integrated boards cascaded in sequence. After the serial input port RSIN of the upper-level integrated board receives a communication signal, the upper-level integrated board can respond to the communication signal on the one hand, and forward the communication signal to the serial input port RSIN of the lower-level integrated board through the serial output port RSOUT on the other hand. Alternatively, it can generate a relay signal (as the communication signal of the lower-level integrated board) based on the communication signal and forward it to the serial input port RSIN of the lower-level integrated board through the serial output port RSOUT.

[0153] In another implementation, the FPGA or MCU of the integrated board can send its own operating parameters or feedback signals outward as communication signals through the serial output port RSOUT.

[0154] It is understood that the integrated board disclosed herein may or may not have a microprocessor (MCU). The FPGA can be adjusted, for example, by selecting a more powerful FPGA, so that the integrated board does not require a microprocessor (MCU). Alternatively, a microprocessor (MCU) can be included as a supplement to the FPGA to share the FPGA's workload or to reserve hardware redundancy for future upgrades of the integrated board.

[0155] In some embodiments of this disclosure, see Figure 13 and Figure 14 The integrated board includes a system board interface module mounted on the circuit board, which is used to connect to the system board. See also... Figure 8 This integrated board can be connected to a system board C-SOC. When the integrated board is connected to the system board C-SOC, it can perform the functions of the voltage board C-Power, the screen driver board C-TCON, and the conversion board C-CONV in related technologies, and can realize the response synchronization of the LCD panel PNL and the backlight module BLU.

[0156] In one embodiment of this disclosure, see Figure 13 The system board interface module may include a screen data port, which is configured to receive screen data from the system board and send it to the FPGA; the screen data is generated by the system board based on the video signal. In this embodiment, the system board C-SOC can receive the video signal, decode the video signal into screen data, and transmit it to the FPGA through the screen data port. In one example, the screen data can be transmitted via LVDS signals.

[0157] In one embodiment of this disclosure, see Figure 13 The integrated board includes a power module PM located on the circuit board; the system board interface module includes a system board power port, which is electrically connected to the power module PM and configured to supply power to the system board. Thus, the system board power port is connected to the power port of the system board C-SOC, allowing the power module PM to supply power to the system board C-SOC through the system board power port. In one example, the power module PM can provide multiple different voltages to the system board C-SOC through the system board power port, such as 5V and 12V, to meet the different voltage requirements of the system board C-SOC.

[0158] In one embodiment of this disclosure, see Figure 13 The system board interface module includes a backlight control port, which receives backlight control signals from the system board and transmits them to the FPGA. Alternatively, if the integrated board has a microprocessor (MCU), the backlight control signals can also be sent to the MCU.

[0159] See Figure 14The C-SOC system board can input backlight control signals to the microprocessor (MCU) or FPGA via the backlight control port. These backlight control signals can include at least one of a backlight power-on signal (BLON) and a backlight brightness signal. When the display device is powered on, the C-SOC system board inputs the backlight power-on signal to the MCU or FPGA via the backlight control port, thereby illuminating the backlight module (BLU). The C-SOC system board can respond to external controls, such as user screen brightness adjustments, by inputting a backlight brightness signal to the FPGA or MCU via the backlight control port. The FPGA or MCU then adjusts the maximum display brightness of the display device in response to this backlight brightness signal.

[0160] See some examples in this disclosure. Figure 11 and Figure 12 The integrated board can be configured with a communication module without requiring a system board interface module. In this way, the integrated board itself can function as a system board (C-SOC), a screen driver board (C-TCON), a voltage board (C-Power), and a conversion board (C-CONV) in related technologies, significantly improving the integration of the control module (CTR) and increasing the assembly efficiency of the display device, while reducing the cost of the display device.

[0161] See also some other examples in this disclosure. Figure 13 The integrated board can be configured without a communication module but instead have a system board interface module. This allows the integrated board to function as the screen driver board C-TCON, voltage board C-Power, and conversion board C-CONV in related technologies. The control module CTR of the display device includes the integrated board and the system board C-SOC that works with it. In this example, the system board C-SOC can be flexibly selected according to different needs, improving the flexibility of the control module CTR in terms of configuration and functionality, thereby expanding the applicability of the integrated board.

[0162] Of course, in other embodiments of this disclosure, see [link to other embodiments]. Figure 14 The integrated board can be configured with both a communication module and a system board interface module. Therefore, this integrated board can be used independently or in conjunction with the C-SOC system board, thus broadening its applicability.

[0163] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An integrated board for a liquid crystal display device, the integrated board comprising a field-programmable gate array and a backlight driving unit disposed on the same circuit board; The field-programmable gate array is configured to receive screen data, generate screen synchronization data based on the screen data, and send it to the liquid crystal display panel; and to generate backlight driving data based on the screen data and send it to the backlight driving unit. The backlight driving unit is configured such that the delay time between the received backlight driving data and the screen synchronization data is less than the time of one frame. The integrated board also includes a storage module, which is a storage circuit located on the circuit board, or the storage module is a storage unit of a field-programmable gate array, or the storage module is composed of a storage unit of a field-programmable gate array and a storage circuit located on the circuit board; The storage module is configured to store configuration information of the backlight driving unit and at least a portion of the program of the field-programmable gate array. The field-programmable gate array is configured to generate the screen synchronization data and the backlight synchronization data according to the screen data, and cache the screen synchronization data and the backlight synchronization data in the storage module. The field-programmable gate array is also configured to forward the screen synchronization data in the storage module to the liquid crystal display panel, generate the backlight driving data according to the backlight synchronization data in the storage module and the configuration information of the backlight driving unit, and send it to the backlight driving unit.

2. The integrated board according to claim 1, wherein, The storage module is configured to store the debugging interface configuration; The field-programmable gate array is configured to generate the screen synchronization data and the backlight synchronization data according to the screen data, and cache the screen synchronization data and the backlight synchronization data in the storage module. The field-programmable gate array is also configured to invoke the debugging interface configuration in response to a debugging signal, and to cause the display device to display the debugging interface.

3. The integrated board according to claim 2, wherein, The storage circuit includes a first storage sub-circuit located on the circuit board, the first storage sub-circuit storing configuration information of the backlight driving unit; The field-programmable gate array is configured to generate the screen synchronization data and the backlight synchronization data according to the screen data, and cache the screen synchronization data and the backlight synchronization data in the first storage sub-circuit. The field-programmable gate array is also configured to forward the screen synchronization data in the first storage sub-circuit to the liquid crystal display panel, generate the backlight driving data according to the backlight synchronization data in the first storage sub-circuit and the configuration information of the backlight driving unit, and send it to the backlight driving unit.

4. The integrated board according to claim 2, wherein, The storage circuit includes a second storage sub-circuit located on the circuit board, and the second storage sub-circuit stores the debugging interface configuration. The field-programmable gate array is also configured to invoke the debugging interface configuration in response to a debugging signal, and to cause the display device to display the debugging interface.

5. The integrated board according to claim 2, wherein, The storage circuit includes a third storage sub-circuit located on the circuit board, the third storage sub-circuit storing at least a portion of the program of the field-programmable gate array.

6. The integrated board according to claim 1, wherein, The field-programmable gate array includes a first field-programmable gate array and a second field-programmable gate array; The first field-programmable gate array is configured to receive the screen data and forward it to the second field-programmable gate array; The second field-programmable gate array is configured to generate the screen synchronization data and the backlight drive data based on the screen data; The second field-programmable gate array is also configured to send the image synchronization data to the liquid crystal display panel and the backlight driving data to the backlight driving unit within the same frame time.

7. The integrated board according to claim 6, wherein, The integrated board includes a first storage sub-circuit and a third storage sub-circuit located on the circuit board; The first storage sub-circuit stores the configuration information of the backlight driving unit; the third storage sub-circuit stores at least a portion of the program of the second field-programmable gate array. The second field-programmable gate array is configured to generate the screen synchronization data and backlight synchronization data based on the screen data, and cache the screen synchronization data and backlight synchronization data in the first storage sub-circuit; the second field-programmable gate array is also configured to forward the screen synchronization data in the first storage sub-circuit to the liquid crystal display panel within the same frame time, and generate the backlight driving data based on the backlight synchronization data in the first storage sub-circuit and the configuration information of the backlight driving unit and send it to the backlight driving unit.

8. The integrated board according to claim 6, wherein, The integrated board also includes a second storage sub-circuit located on the circuit board, the second storage sub-circuit storing the debugging interface configuration; The first field-programmable gate array is also configured to receive and respond to a debugging signal to invoke the debugging interface configuration, generate a debugging screen, and transmit the debugging screen as screen data to the second field-programmable gate array.

9. The integrated circuit board according to any one of claims 1 to 8, wherein, The circuit board is also equipped with a power module, a power management unit, and a gamma voltage unit; The power module is used to connect to an external power source and supply power to the power management unit and the backlight driving unit; The power management unit is configured to provide a variety of different power supply voltages to the liquid crystal display panel and to power the gamma voltage unit. The gamma voltage unit is configured to provide the liquid crystal display panel with a common voltage and gamma binding point voltages corresponding to the grayscale of each gamma binding point. The power for the field-programmable gate array comes from the power module or the power management unit.

10. The integrated board according to claim 9, wherein, The integrated board also has a power supply selection unit; the power supply selection unit is configured to select one of the power module and the power management unit to supply power to the field programmable gate array.

11. The integrated circuit board according to any one of claims 1 to 8, wherein, The integrated board also includes a communication module located on the circuit board, the communication module being configured to perform at least one of the functions of receiving video signals, receiving control signals, and sending signals to the outside.

12. The integrated board according to claim 11, wherein, The communication module includes a video signal port and a signal conversion unit; the video signal port is configured to receive video signals and forward them to the signal conversion unit. The signal conversion unit is configured to transcode the video signal into the image data and forward the image data to the field-programmable gate array.

13. The integrated board according to claim 12, wherein, The video signal port includes at least one of the following: HDMI port, DVI port, VGA port, and DP port.

14. The integrated board according to claim 11, wherein, The communication module includes a serial input port and a serial output port; The serial input port is configured to transmit control signals to the field-programmable gate array; The serial output port is configured to send out signals generated by the field-programmable gate array.

15. The integrated board according to claim 11, wherein, The communication module includes an infrared sensor; The infrared sensor is configured to receive infrared signals to generate control signals and transmit the control signals to the field-programmable gate array.

16. The integrated board according to claim 11, wherein, The communication module includes a microprocessor and at least one of a serial input port, a serial output port, and an infrared sensor. The microprocessor interacts with the field-programmable gate array; The serial input port is configured to transmit control signals to the microprocessor or the field-programmable gate array. The serial output port is configured to send signals generated by the field-programmable gate array or the microprocessor. The infrared sensor is configured to receive an infrared control signal, generate a control signal, and transmit the control signal to the field-programmable gate array or the microprocessor.

17. The integrated circuit board according to any one of claims 1 to 8, wherein, The integrated board is provided with a system board interface module on the circuit board, and the system board interface module is used to connect to the system board.

18. The integrated board according to claim 17, wherein, The system board interface module includes: The video data port is configured to receive video data from the system board and send it to the field-programmable gate array; the video data is generated by the system board based on the video signal.

19. The integrated board according to claim 17, wherein, The integrated board includes a power module located on the circuit board; The system board interface module includes a system board power port, which is electrically connected to the power module and configured to supply power to the system board.

20. The integrated board according to claim 17, wherein, The system board interface module includes a backlight control port, which is used to receive backlight control signals from the system board and transmit them to the field programmable gate array.

21. The integrated board according to claim 17, wherein, The integrated board also includes a microprocessor located on the circuit board, and the microprocessor interacts with the field-programmable gate array. The system board interface module includes a backlight control port, which is used to receive backlight control signals from the system board and transmit them to the field-programmable gate array or the microprocessor.

22. The integrated circuit board according to any one of claims 1 to 8, wherein, The backlight driving unit is configured to directly drive the backlight module according to the backlight driving data.

23. A control module for a liquid crystal display device, comprising the integrated board according to any one of claims 1 to 22.

24. A liquid crystal display device, comprising the control module of claim 23; the liquid crystal display device further comprising a liquid crystal display panel and a backlight module; the integrated board being electrically connected to the liquid crystal display panel and the backlight module.

25. The liquid crystal display device according to claim 24, wherein, The backlight module includes multiple arrayed lamp zones, which are configured to be driven by local dimming.

26. The liquid crystal display device according to claim 24 or 25, wherein, The liquid crystal display panel is a splicing display panel and includes multiple sub-display panels.

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