Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a first substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a first transparent conductive layer, a third insulating layer and a second transparent conductive layer. The first transparent conductive layer comprises a lateral common electrode line, and the second transparent conductive layer comprises a capacitor electrode. The first storage capacitor is formed by the capacitor electrode and the lateral common electrode line. Compared with the prior art, the substrate common electrode line (Acom) is arranged on the side of the third insulating layer away from the substrate and is stacked with the pixel electrode to form the storage capacitor. The area of the capacitor electrode and the lateral common electrode line is larger, and the capacity of the first storage capacitor is larger. Furthermore, the storage capacitor is formed by two transparent conductive layers, and part of the substrate common electrode line can be omitted, so that the light transmittance and brightness are improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Most liquid crystal displays (LCDs) are backlit LCDs, which consist of a housing, a liquid crystal display panel housed within the housing, and a backlight module within the housing. LCDs require a light source provided by the backlight module to display their images properly.

[0003] Typically, a liquid crystal display panel is made by bonding an array glass substrate and a color filter glass substrate together, with liquid crystal injected between the two substrates. Pixel electrodes and common electrodes are set on the opposite inner sides of the two substrates. The rotation direction of the liquid crystal molecules is controlled by a voltage field, which refracts the light from the backlight module to produce an image.

[0004] Improving brightness and reducing power consumption have always been goals pursued by LCD monitors. On the one hand, LCD monitors are currently achieving increasingly higher resolutions, which reduces light transmittance due to increased pixel density; on the other hand, LCD monitors require higher brightness outdoors. Therefore, improving the light transmittance and brightness of LCD monitors while reducing power consumption requires new technologies. Summary of the Invention

[0005] This application provides an array substrate and display panel with higher light transmittance and brightness.

[0006] A first aspect of this application provides an array substrate, comprising: a first substrate; a first metal layer disposed on the first substrate, including a plurality of gate lines extending along a first direction; a first insulating layer covering the first metal layer; a second metal layer disposed on the first insulating layer, including a plurality of data lines, source electrodes, and drain electrodes extending along a second direction; the second direction intersecting the first direction; a second insulating layer covering the first metal layer; a first transparent conductive layer disposed on the side of the second insulating layer away from the substrate, including a lateral common electrode line and a first pixel electrode layer; the lateral common electrode line covering the data lines; further comprising: a third insulating layer covering the lateral common electrode line and the gate lines, and having an opening for exposing a pixel electrode; a second transparent conductive layer; wherein the second transparent conductive layer includes a capacitor electrode and a pixel electrode extension connected to each other; the capacitor electrode is disposed on the side of the third insulating layer away from the substrate and stacked with the lateral common electrode line to form a first storage capacitor, and the pixel electrode extension is disposed within the opening and electrically connected to the first pixel electrode layer.

[0007] Furthermore, the third insulating layer is a black matrix layer.

[0008] Furthermore, the array substrate also includes a filter layer disposed between the second insulating layer and the first transparent conductive layer.

[0009] Furthermore, the edge of the pixel electrode extension is stacked with the edge of the first pixel electrode layer.

[0010] Furthermore, the second transparent conductive layer also includes a second pixel electrode layer electrically connected to the pixel electrode extension; the second pixel electrode layer is stacked with the first pixel electrode layer and has the same pattern; the first pixel electrode layer has a plurality of first slits and the second pixel electrode layer has a plurality of second slits; the plurality of first slits and the plurality of second slits correspond one-to-one and are partially staggered.

[0011] Furthermore, the two capacitor electrodes corresponding to two adjacent pixels are spaced apart on the black matrix layer between the two adjacent pixels, and the gap between the two capacitor electrodes corresponding to two adjacent pixels is filled with the material of the alignment layer.

[0012] Furthermore, the first metal layer includes only the substrate common electrode line extending along the first direction.

[0013] Furthermore, the substrate common electrode line is electrically connected to the lateral common electrode line; the substrate common electrode line and the first pixel electrode layer are at least partially stacked to form a second storage capacitor.

[0014] Furthermore, the first metal layer does not include any common electrode lines.

[0015] A second aspect of this application provides a display substrate, comprising: an array substrate; a counter substrate disposed at a distance from the array substrate; the counter substrate comprising a second substrate and a third transparent conductive layer; and a liquid crystal layer disposed between the array substrate and the counter substrate; wherein the array substrate is an array substrate according to any one of the above embodiments.

[0016] The beneficial effects of this application are as follows: The array substrate of this application includes a first substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a first transparent conductive layer, a third insulating layer, and a second transparent conductive layer. The first transparent conductive layer includes a lateral common electrode line, and the second transparent conductive layer includes a capacitor electrode. A first storage capacitor is formed by stacking the capacitor electrode and the lateral common electrode line. Compared to the prior art storage capacitor where the substrate common electrode line (Acom) is disposed on the side of the third insulating layer away from the substrate and stacked with the pixel electrode, the overlapping area of ​​the capacitor electrode and the lateral common electrode line in this application is larger, resulting in a larger first storage capacitor capacity. Furthermore, since the storage capacitor is formed through two transparent conductive layers, some substrate common electrode lines can be eliminated, thereby improving light transmittance and brightness. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A top view of one embodiment of the array substrate provided in this application;

[0019] Figure 2 for Figure 1 Cross-sectional view at point AA;

[0020] Figure 3 for Figure 1 Cross-sectional view at point BB;

[0021] Figure 4 A top view of another embodiment of the array substrate provided in this application;

[0022] Figure 5 for Figure 4 Cross-sectional view at point AA;

[0023] Figure 6 for Figure 4 Cross-sectional view at point BB;

[0024] Figure 7 for Figure 4 A magnified view of a section at point C;

[0025] Figure 8 This is a schematic diagram of one embodiment of the display panel provided in this application.

[0026] Explanation of icon numbers:

[0027] 1-Array substrate, 11-First substrate, 12-First metal layer, 13-First insulating layer, 14-Second metal layer, 15-Second insulating layer, 16-First transparent conductive layer, 17-Third insulating layer, 18-Second transparent conductive layer, 121-Gate line, 122-Substrate common electrode line, 141-Data line, 142-Source electrode, 143-Drain electrode, 144-Active layer, 161-Side common electrode line, 162-First pixel electrode layer, 164-Pixel electrode, 181-Capacitor electrode, 182-Pixel electrode extension, 183-Second pixel electrode layer, 2-Pairing substrate, 3-Liquid crystal layer, 4-Filter layer, 5-Via, 6-Alignment layer, 100-Display panel. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0029] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0030] The term "A is placed on B" in this application does not mean that A and B must be in direct contact. It can also mean that A and B are not in direct contact. For example, A is in direct contact with C, and B is in direct contact with C but not with A.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] The inventors of this application have discovered that in commonly used liquid crystal display panels, pixels typically have a substrate common electrode line (Acom) surrounding the pixel electrode. Therefore, common electrode lines are located on both sides of the data lines. These substrate common electrode lines are used to stack with the edge of the pixel electrode to form a storage capacitor. However, to increase the aperture ratio, the width of the substrate common electrode line needs to be as small as possible; therefore, the storage capacitor of existing liquid crystal display panels is relatively small. Furthermore, since the common electrode line blocks some light, the transmittance and brightness of existing liquid crystal display panels are relatively low.

[0033] Therefore, in order to solve the problems of the prior art, this application provides an array substrate and a liquid crystal display panel using such an array substrate.

[0034] Please see Figures 1 to 3 In one embodiment, the array substrate 1 provided in this application includes a first substrate 11, a first metal layer 12, a first insulating layer 13, a second metal layer 14, a second insulating layer 15, a first transparent conductive layer 16, a third insulating layer 17, and a second transparent conductive layer 18.

[0035] The first metal layer 12 is disposed on the first substrate 11 and includes a plurality of gate lines 121 extending along the first direction X. The first insulating layer 13 covers the first metal layer 12. The second metal layer 14 is disposed on the first insulating layer 13 and includes a plurality of data lines 141, source electrodes 142 and drain electrodes 143 extending along the second direction Y. The second direction Y intersects with the first direction X.

[0036] Specifically, multiple gate lines 121 are arranged parallel to each other, multiple data lines 141 are arranged parallel to each other, and the multiple data lines 141 and multiple gate lines 121 are arranged to intersect each other to form multiple pixel regions. For example, the array substrate 1 includes multiple sub-pixels arranged in an array, the first direction X is the row direction of the sub-pixel array, the second direction Y is the column direction of the sub-pixel array, and the second direction Y is perpendicular to the first direction X.

[0037] The shape and size of the substrate 11 are not limited, and the material can be glass. The gate line 121 and the data line 141 can be made of metallic materials, such as copper, molybdenum, aluminum and titanium, to ensure good conductivity, but are not limited to these, and can also be made of other materials with good conductivity.

[0038] Each pixel region contains a driving transistor, and each driving transistor has three nodes: a source electrode 142, a gate electrode (not shown), and a drain electrode 143. These three nodes are electrically connected to the corresponding data line 141, the corresponding gate line 121, and the individual pixel electrode, respectively. An active layer 144 is disposed between the source electrode 142 and the drain electrode 143. The active layer 144 can be formed by patterning using a semiconductor material. For example, the active layer 144 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc.

[0039] The second insulating layer 15 covers the second metal layer 14, and the materials of the first insulating layer 13 and the second insulating layer 15 include at least one of silicon dioxide, silicon nitride, and silicon oxide.

[0040] Please continue reading. Figure 2 and Figure 3 A first transparent conductive layer 16 is disposed on the side of the second insulating layer 15 away from the first substrate 11. The first transparent conductive layer 16 includes a lateral common electrode line 161; the lateral common electrode line 161 covers the data line 141. The lateral common electrode line 161 is also called a DBS (Data Line BM Less) common electrode line, which is used to shield the disordered electric field of the data line 141 and prevent the liquid crystal near the data line 141 from tilting randomly.

[0041] The third insulating layer 17 covers the lateral common electrode line 161 and the gate line 121, and has an opening that exposes the pixel electrode. The material of the third insulating layer 17 may be resin.

[0042] Please see Figures 2 to 4 The first transparent conductive layer 16 further includes a first pixel electrode layer 162, which serves as a pixel electrode 164. The second transparent conductive layer 18 includes a capacitor electrode 181 and a pixel electrode extension 182 connected to each other. The capacitor electrode 181 is disposed on the side of the third insulating layer 17 away from the substrate and is stacked with the lateral common electrode line 161 to form a first storage capacitor. The pixel electrode extension 182 is disposed in the opening and is electrically connected to the first pixel electrode layer 162. The materials of the first transparent conductive layer 16 and the second transparent conductive layer 18 may include at least one of indium tin oxide (ITO) and indium zinc oxide (IZO). In this application, ITO is used as an example of a transparent conductive layer for illustration.

[0043] Specifically, the first pixel electrode layer 162 and the lateral common electrode line 161 are disposed in the same transparent conductive layer. The third insulating layer 17 covers the lateral common electrode line 161. The capacitor electrode 181 is disposed on the side of the third insulating layer 17 away from the substrate 11 and is stacked with the lateral common electrode line 161 to form a first storage capacitor. Compared with the prior art where the substrate common electrode line (Acom) is disposed on the side of the third insulating layer 17 away from the substrate and stacked with the pixel electrode to form a storage capacitor, the overlapping area of ​​the capacitor electrode 181 and the lateral common electrode line 161 is larger, resulting in a larger first storage capacitor capacity, which positively contributes to crosstalk and variable refresh rate (VRR). The pixel electrode extension 182 is disposed in the opening and electrically connected to the first pixel electrode layer 162. By applying an electric field, the alignment of liquid crystal molecules is controlled, thereby realizing image display. Furthermore, since the storage capacitor is formed by two transparent conductive layers, at least some of the common electrode lines of the substrate between the first pixel electrode layer 162 and the data line 141 can be eliminated, thereby improving light transmittance and brightness.

[0044] In one embodiment, the third insulating layer 17 is a black matrix layer that covers the lateral common electrode line 161 and the gate line 121 to block light emitted by the backlight module, thereby preventing incorrect color mixing and light leakage. The black matrix layer is disposed on the array substrate 1, which can effectively improve the alignment accuracy of the gate line 121 and the black matrix layer, as well as the data line 141 and the black matrix layer. The black matrix layer can be made narrower, thereby increasing the aperture ratio.

[0045] In another embodiment, the third insulating layer 17 is a PFA planarization layer, in which case the black matrix layer can be disposed on the substrate 2.

[0046] Please continue reading. Figure 3 In one embodiment, the array substrate 1 further includes a filter layer 4, which is disposed between the second insulating layer 15 and the first transparent conductive layer 16. The filter layer 4 is used to filter light so that the light passing through the color filter layer 4 is visible light of a specific color. The light passing through the red, blue, and green filter units becomes red light, blue light, and green light, respectively. In this way, by mixing these three primary colors of light, various colors of light can be synthesized to display the desired image.

[0047] In another embodiment, the filter layer 4 may be disposed on the substrate 2, and this application does not limit this.

[0048] Please continue reading. Figure 3 In one embodiment, the edge of the pixel electrode extension 182 is stacked with the edge of the first pixel electrode layer 162, making the electrical connection between the edge of the pixel electrode extension 182 and the first pixel electrode layer 162 more stable.

[0049] In another embodiment, the edge of the pixel electrode extension 182 and the edge of the first pixel electrode layer 162 can also be disposed on the same layer, as long as they are electrically connected to each other. This application does not limit this.

[0050] Please see Figures 5 to 7 In another embodiment, the second transparent conductive layer 18 further includes a second pixel electrode layer 183 electrically connected to the pixel electrode extension 182; the capacitor electrode 181 is disposed on the side of the third insulating layer 17 away from the substrate and is stacked with the lateral common electrode line 161 to form a first storage capacitor, and the second pixel electrode layer 183 is disposed in the opening.

[0051] Specifically, the capacitor electrode 181 and the lateral common electrode line 161 are stacked to form a first storage capacitor. The increased capacity of the first storage capacitor has a positive effect on crosstalk and variable refresh rate (VRR). The second pixel electrode layer 183 and the first pixel electrode layer 162 are stacked to form a pixel electrode 164.

[0052] In this design, the second pixel electrode layer 183 is stacked on top of the first pixel electrode layer 162 and has the same pattern. The first pixel electrode layer 162 has multiple first slits 1621, and the second pixel electrode layer 183 has multiple second slits 1831. The multiple first slits 1621 and the multiple second slits 1831 correspond one-to-one and are partially staggered. It is understood that, due to the limitation of single-layer ITO process, the slit width of the pixel electrode cannot be further reduced when the pixel electrode is formed using the same transparent conductive layer in the prior art. In this application, by stacking the second pixel electrode layer 183 on top of the first pixel electrode layer 162, and by having the multiple first slits 1621 and the multiple second slits 1831 correspond one-to-one and are partially staggered, the overlapping area of ​​the first slits 1621 and the second slits 1831 forms the slit of the pixel electrode 164. Therefore, the second pixel electrode layer 183 and the first pixel electrode layer 162 are stacked together to form a pixel electrode 164 with a narrower slit, which improves the liquid crystal deflection efficiency and makes the liquid crystal panel have higher light transmittance.

[0053] Please continue reading. Figure 4 In one embodiment, the pixel electrode extension 182 is electrically connected to the drain electrode 143 through a via 5 that passes through the black matrix layer and the filter layer 4. The via 5 passes through the black matrix layer and the filter layer 4, and the pixel electrode extension 182 is electrically connected to the drain electrode 143 through the via 5, thereby driving the transistor to drive the pixel electrode.

[0054] In other embodiments, the pixel electrode extension 182 is electrically connected to the drain electrode 143 through a via 5 penetrating the third insulating layer 17, which may be a planarization layer (PFA).

[0055] Please continue reading. Figure 2 and Figure 3 In one embodiment, two capacitor electrodes 181 corresponding to two adjacent pixels are spaced apart on the black matrix layer between the two adjacent pixels, and the gap between the two capacitor electrodes 181 corresponding to two adjacent pixels is filled with the material of the alignment layer 6 to increase the insulation effect.

[0056] Specifically, the black matrix layer covers the lateral common electrode line 161, and the capacitor electrode 181 is stacked on the lateral common electrode line 161. The two capacitor electrodes 181, which are spaced apart, form two first storage capacitors with the lateral common electrode line 161, and the two first storage capacitors are used to drive two adjacent pixels respectively.

[0057] In other embodiments, two capacitive electrodes 181 corresponding to two adjacent pixels are spaced apart on a third insulating layer 17 between the two adjacent pixels. The third insulating layer 17 may be, for example, a planarization layer (PFA).

[0058] Please continue reading. Figure 4 In one embodiment, the first metal layer 12 includes only a substrate common electrode line 122 extending along the first direction X. The substrate common electrode line 122 and the gate line 121 are parallel to each other, meaning that the substrate common electrode line 122 is not disposed on both sides of the data line 141. By omitting the substrate common electrode line 122 on both sides of the data line 141, the aperture ratio of the display panel 100 can be improved. Furthermore, by disposing of the black matrix layer on the array substrate 1, the alignment accuracy of the gate line 121 and the black matrix layer, as well as the data line 141 and the black matrix layer, can be effectively improved. The black matrix layer can be made narrower, thereby increasing the aperture ratio.

[0059] In one embodiment, the substrate common electrode line 122 is electrically connected to the lateral common electrode line 161; the substrate common electrode line 122 and the first pixel electrode layer 162 are at least partially stacked to form a second storage capacitor. The first storage capacitor and the second storage capacitor are used together to further increase the storage capacitor capacity.

[0060] In other embodiments, the first metal layer 12 does not include any common electrode lines, and the pixel aperture ratio can be improved by reducing the black matrix layer used to block common electrode lines.

[0061] Please see Figure 8 This application further provides a display panel 100, which includes an array substrate 1, a counter substrate 2, and a liquid crystal layer 3. The counter substrate 2 is disposed at a distance from the array substrate 1. The counter substrate 2 includes a second substrate 21 and a third transparent conductive layer 22. The liquid crystal layer 3 is disposed between the array substrate 1 and the counter substrate 2. The third transparent conductive layer 22 serves as a common electrode that cooperates with the pixel electrode 164 to drive the liquid crystal deflection of the liquid crystal layer 3.

[0062] Specifically, the array substrate 1 can be any of the aforementioned TFT array substrates. The substrate 2 can be a color filter substrate, meaning it further includes a color filter layer; alternatively, the substrate 2 may not include a color filter layer, and the color filter layer may be disposed on the array substrate 1. If the array substrate 1 does not include a black matrix layer, the substrate 2 may still include a black matrix layer. The substrate 2 also includes other functional layers, such as an alignment layer and a polarizing layer. The liquid crystal layer 3 acts as a light valve in the display panel 100, controlling the brightness of the transmitted light to achieve the information display effect. The material of the third transparent conductive layer 22 may include at least one of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0063] The second substrate 21 can be a flat plate or a curved surface. In this embodiment, the second substrate 21 is a flat plate. The second substrate 21 is a transparent substrate; in this embodiment, the second substrate 21 is a glass substrate, generally made of alkali-free borosilicate glass with excellent mechanical properties, heat resistance, and chemical corrosion resistance.

[0064] Preferably, in one embodiment, the array substrate 1 includes a black matrix layer and a color filter layer, while the substrate 2 does not include a black matrix layer and a color filter layer.

[0065] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An array substrate, comprising: a first substrate; a first metal layer disposed on the first substrate, comprising a plurality of gate lines extending in a first direction; a first insulating layer covering the first metal layer; a second metal layer disposed on the first insulating layer, comprising a plurality of data lines extending in a second direction, source electrodes and drain electrodes; the second direction intersects the first direction; a second insulating layer covering the first metal layer; a first transparent conductive layer disposed on a side of the second insulating layer away from the substrate, comprising a lateral common electrode line and a first pixel electrode layer; the lateral common electrode line covers the data lines; characterized in that further comprising: a third insulating layer covering the lateral common electrode line and the gate lines, and having an opening exposing a pixel electrode; a second transparent conductive layer; wherein the second transparent conductive layer comprises a capacitor electrode and a pixel electrode extension connected to each other; the capacitor electrode is disposed on a side of the third insulating layer away from the substrate and is stacked with the lateral common electrode line to form a first storage capacitor, and the pixel electrode extension is disposed in the opening and is electrically connected to the first pixel electrode layer.

2. The array substrate of claim 1, wherein, the third insulating layer is a black matrix layer.

3. The array substrate of claim 2, wherein, the array substrate further comprises a filter layer disposed between the second insulating layer and the first transparent conductive layer.

4. The array substrate of claim 3, wherein, an edge of the pixel electrode extension is stacked with an edge of the first pixel electrode layer.

5. The array substrate of claim 4, wherein, the second transparent conductive layer further comprises a second pixel electrode layer electrically connected to the pixel electrode extension; the second pixel electrode layer is stacked with the first pixel electrode layer and has the same pattern; the first pixel electrode layer has a plurality of first slits, and the second pixel electrode layer has a plurality of second slits; the plurality of first slits and the plurality of second slits are one-to-one corresponding and partially misaligned.

6. The array substrate according to any one of claims 2 to 5, wherein, two capacitor electrodes corresponding to two adjacent pixels are disposed on the black matrix layer between the two adjacent pixels, and a gap between the two capacitor electrodes corresponding to the two adjacent pixels is filled with a material of an alignment layer.

7. The array substrate of claim 1, wherein, the first metal layer only comprises a substrate common electrode line extending in the first direction.

8. The array substrate of claim 7, wherein, the substrate common electrode line is electrically connected to the lateral common electrode line; the substrate common electrode line is at least partially stacked with the first pixel electrode layer to form a second storage capacitor.

9. The array substrate of claim 1, wherein, the first metal layer does not comprise any common electrode line. 10.A display panel, comprising: an array substrate; a counter substrate disposed apart from the array substrate; the counter substrate comprises a second substrate and a third transparent conductive layer; a liquid crystal layer disposed between the array substrate and the counter substrate; characterized in that the array substrate is the array substrate according to any one of claims 1-9.

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