LDO linear transient enhancement circuit, chip and electronic device

Abstract

The application discloses an LDO linear transient enhancement circuit, a chip and electronic equipment, and relates to the technical field of integrated circuits.The technical scheme points are as follows: including a low-dropout linear voltage regulator, a current mirror bias circuit and a transient enhancement circuit; the transient enhancement circuit includes a one-way conductive component, a capacitor CP1, a resistor RES1 and a MOS tube PM2; the input end of the one-way conductive component is connected with a power supply voltage VIN, and the output end is connected with the source electrode of the MOS tube PM2; the gate electrode of the MOS tube PM2 is connected with the power supply voltage VIN through the resistor RES1, and the drain electrode is connected with the current mirror bias circuit; one end of the capacitor CP1 is connected with the output end of the one-way conductive component, and the other end is grounded.The application does not need to use additional operational amplifiers and always-on current mirror bias circuits, and only uses resistors, capacitors, MOS tubes and diodes to realize an LDO linear transient enhancement circuit with low power consumption, low cost, high reliability and easy expansion.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to an LDO linear transient enhancement circuit, chip, and electronic device. Background Technology

[0002] In integrated circuit chips, to prevent abnormal LDO (Low Dropout Linear Regulator) output due to insufficient or excessive transient current in a branch during power supply voltage transients (such as excessively high or low output), an LDO linear transient boosting circuit is typically designed to compensate for or shunt the transient current, thereby stabilizing the branch current and the LDO output. The function of this circuit is to provide additional transient compensation current when the power supply voltage changes instantaneously, driving the gate of the LDO power transistor to promptly turn it on or off to provide appropriate load current. This stabilizes the LDO output during rapid power supply fluctuations, shortens the stabilization time, and prevents the LDO output from becoming too high or too low, which could affect the normal operation of subsequent circuits.

[0003] Existing LDO linear transient enhancement circuits typically use multiple capacitors, current mirror circuits, and operational amplifiers to achieve voltage detection, such as... Figure 1 As shown. When the power supply voltage VIN decreases instantaneously, the gate-source voltage difference Vgs of the power transistor MP decreases, thus reducing the on-state current provided by the power transistor, i.e., reducing the external output load current IL, and causing VOUT to drop. At this time, the op-amp detects that VOUT is less than VREF, amplifies the difference between the two, and generates VPLUSE. VPLUSE is then coupled to the gate of the PM2 transistor through capacitor CP1, increasing the source-gate difference Vgs, and thus IDS... PM2 Increase, and mirror it as IDS through current mirror circuits NM2 and NM3. NM2 IDS NM2 Increasing the capacitance CP at the gate of the power transistor MP will increase the discharge current IDS. NM1 Increasing the voltage across the gate of the power transistor MP can accelerate the drop in voltage, increase its Vgs, increase the on-state current, and provide sufficient load current IL, thereby preventing the LDO output VOUT voltage from being too low. This is in accordance with the IDS described above. PM2 IDS NM2 IDS NM1 These refer to the current flowing through MOSFETs PM2, NM2, and NM1, respectively.

[0004] However, the aforementioned LDO linear transient enhancement circuit has the following drawbacks: 1. It requires an additional operational amplifier (amp) to amplify the change in VOUT and normally conducting current mirror branches PM2 and NM3. This not only increases circuit complexity but also continuously consumes quiescent current, resulting in significant power waste. 2. The LDO transient response time is limited by the op-amp's operating bandwidth and slew rate, which cannot provide sufficient drive current to the power transistor in a timely manner, thus increasing the LDO transient response time. Therefore, researching and designing an LDO linear transient enhancement circuit, chip, and electronic device that can overcome the above-mentioned defects is a problem that urgently needs to be solved. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide an LDO linear transient enhancement circuit, chip, and electronic device that does not require additional operational amplifiers and normally open current mirror bias circuits. It uses only resistors, capacitors, MOSFETs, and diodes to achieve a low-power, low-cost, high-reliability, and easily expandable LDO linear transient enhancement circuit, which is particularly suitable for transient slew rate enhancement circuits of LDO chips.

[0006] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0007] In a first aspect, an LDO linear transient enhancement circuit is provided, including a low dropout linear regulator and a current mirror bias circuit, wherein a transient enhancement circuit is provided between the power supply voltage VIN of the low dropout linear regulator and the current mirror bias circuit.

[0008] The transient enhancement circuit includes a unidirectional conductive element, a capacitor CP1, a resistor RES1, and a MOSFET PM2;

[0009] The input terminal of the unidirectional conductive element is connected to the power supply voltage VIN, and the output terminal is connected to the source of the MOS transistor PM2.

[0010] The gate of the MOSFET PM2 is connected to the power supply voltage VIN through resistor RES1, and the drain is connected to the current mirror bias circuit.

[0011] One end of the capacitor CP1 is connected to the output terminal of the unidirectional conductive element, and the other end is grounded.

[0012] Furthermore, when the power supply voltage VIN rises instantaneously, the MOS transistor PM2 is turned off, and the capacitor CP1 is charged and stored through the unidirectional conductive component, so there is no current in the current mirror bias circuit.

[0013] When the power supply voltage VIN drops instantaneously, MOSFET PM2 turns on, and capacitor CP1 discharges current to ground through MOSFET PM2. A large instantaneous current is generated in the current mirror bias circuit, which increases the discharge current of capacitor CP to ground through MOSFET NM1 in the low dropout linear regulator, and accelerates the increase of the gate-source voltage Vgs of power transistor MP, so as to provide sufficient load current IL to maintain the stability of the output voltage VOUT of the low dropout linear regulator.

[0014] Furthermore, when the power supply voltage VIN is in static operation, MOSFETs PM2, NM2, and NM3 are in the off state, consuming zero static current.

[0015] Furthermore, the unidirectional conductive element is a diode or a MOS transistor containing a diode;

[0016] The positive terminal of the diode corresponds to the input terminal of the unidirectional conductive element, and the negative terminal of the diode corresponds to the output terminal of the unidirectional conductive element.

[0017] Furthermore, the current mirror bias circuit is composed of MOSFET NM2 and MOSFET NM3, and the midpoint of the connection between MOSFET NM2 and MOSFET NM3 is grounded through resistor RES3.

[0018] Furthermore, the ratio of the mirrored current between MOS transistor NM2 and MOS transistor NM3 is determined based on compensation parameters.

[0019] Furthermore, a resistor RES2 is connected between the output terminal of the unidirectional conductive element and the source of the MOS transistor PM2;

[0020] The midpoint of the current mirror bias circuit is grounded through resistor RES3;

[0021] The resistors RES1 and RES3 and the capacitor CP1 together form an RC delay circuit to adjust the discharge time.

[0022] Furthermore, the low dropout linear regulator is composed of MOSFETs NM1, NM4, PM1 and MP, as well as bias sources idc, VBIASE1, VBIASE2 and VSET.

[0023] Furthermore, when the power supply voltage VIN is in static operation, the MOS transistor PM2 is in the off state, and the static current consumption is 0.

[0024] In a second aspect, an integrated circuit chip is provided, the chip including at least one LDO linear transient enhancement circuit as described in the first aspect.

[0025] Thirdly, an electronic device is provided, which is configured with at least one integrated circuit chip as described in the second aspect.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] 1. The present invention provides an LDO linear transient enhancement circuit that does not require additional operational amplifiers and normally open current mirror bias circuits. It only uses resistors, capacitors, MOSFETs and diodes to achieve a low-power, low-cost, high-reliability and easily expandable LDO linear transient enhancement circuit, which is particularly suitable for transient slew rate enhancement circuits of LDO chips.

[0028] 2. This invention saves circuit area and power consumption, and the transient response time is not limited by the operational amplifier settling time, enabling faster response to LDO transient changes;

[0029] 3. This invention does not require a constantly conducting current mirror bias circuit, which can avoid current consumption during LDO steady-state operation, especially in high-voltage circuits, which can greatly save power consumption.

[0030] 4. This invention addresses the different transient compensation current requirements of LDOs by simply adjusting the ratio of MOSFETs NM2 and NM3 and the value of CP1 in the current mirror structure. It eliminates the need for the complex circuit structure of additional operational amplifier adjustments required in previous LDO linear transient enhancement circuit structures, making it simple and easy to migrate. Attached Figure Description

[0031] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0032] Figure 1 This is a circuit schematic of an existing LDO linear transient enhancement circuit;

[0033] Figure 2 This is a circuit diagram of the LDO linear transient enhancement circuit in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0035] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly or indirectly attached to that other component. When a component is referred to as being "connected to" another component, it can be directly or indirectly connected to that other component.

[0036] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0038] Example: An LDO linear transient enhancement circuit, such as Figure 2 As shown, it includes a low-dropout linear regulator and a current mirror bias circuit. A transient enhancement circuit is provided between the power supply voltage VIN of the low-dropout linear regulator and the current mirror bias circuit.

[0039] The transient enhancement circuit includes a diode, a capacitor CP1, and a MOSFET PM2. The positive terminal of the diode is connected to the power supply voltage VIN, and the negative terminal is connected to the source of the MOSFET PM2. The gate of the MOSFET PM2 is connected to the power supply voltage VIN, and the drain is connected to the current mirror bias circuit. One end of the capacitor CP1 is connected to the negative terminal of the diode, and the other end is grounded.

[0040] During the rising phase of the power supply voltage VIN, capacitor CP1 is charged through the diode, while MOSFET PM2 is in the off state. During the falling phase of the power supply voltage VIN, MOSFET PM2 is turned on, and capacitor CP1 discharges through resistor RES2, MOSFET PM2, and MOSFET NM3. When the power supply voltage VIN is in a steady state, there is no current in this circuit structure. The diode can be any unidirectional conductive component, with the anode corresponding to the input terminal of the unidirectional conductive component and the cathode corresponding to the output terminal, such as a diode connected to a MOSFET.

[0041] A resistor RES2 is connected between the output terminal of the unidirectional conductive component and the source of the MOSFET PM2; the midpoint of the current mirror bias circuit is grounded through a resistor RES3; among them, resistors RES1 and RES3 and capacitor CP1 together form an RC delay circuit to adjust the discharge time.

[0042] The low dropout linear regulator consists of MOSFETs NM1, NM4, PM1, and MP, as well as bias sources idc, VBIASE1, VBIASE2, and VSET.

[0043] Specifically, the source of MOSFET MP is connected to the power supply voltage VIN, and its drain is connected to both the output voltage VOUT and the source of MOSFET PM1. The gate of MOSFET NM1 is connected to the drain of MOSFET NM1, and the power supply voltage VIN is connected to the drain of MOSFET NM1 via a bias source idc. The gate of MOSFET NM1 is grounded via a bias source VBIASE1. The source of MOSFET NM1 is connected to the drains of MOSFETs PM1 and NM4. The gate of MOSFET NM4 is grounded via a bias source VBIASE2, and the source of MOSFET NM4 is also grounded. Furthermore, the gate of MOSFET PM1 is grounded via a bias source VSET. The capacitor CP is equivalent to the parasitic capacitance of the MP gate, and IL is the load current of the LDO; however, this LDO is not limited to this specific structure.

[0044] This invention utilizes a unidirectional conductive diode, ensuring that current can only flow from the power supply voltage VIN through the diode portion to the capacitor CP1, but not through the diode portion back to the power supply voltage VIN. The capacitor CP1 and the diode also constitute a delayed charging mechanism. Therefore, during the rising phase of the power supply voltage VIN, the source voltage of MOSFET PM2 is less than the gate voltage, and MOSFET PM2 is off. During the falling phase of the power supply voltage VIN, MOSFET PM2 is turned on, and capacitor CP1 discharges current, injecting current into MOSFETs NM3 and NM2 in the current mirror structure, generating a compensation current.

[0045] Specifically, when the power supply voltage VIN rises instantaneously, MOSFET PM2 is turned off, and capacitor CP1 is charged and stored through diode, resulting in no current in the current mirror bias circuit. When the power supply voltage VIN drops instantaneously, MOSFET PM2 is turned on, and capacitor CP1 discharges current to ground through MOSFET PM2, generating a large instantaneous current in the current mirror bias circuit. This increases the discharge current of capacitor CP to ground through MOSFET NM1 in the low dropout linear regulator, accelerating the increase of the gate-source voltage Vgs of power transistor MP, thus providing sufficient load current IL to maintain the stability of the output voltage VOUT of the low dropout linear regulator. During static operation, MOSFETs PM2, NM2, and NM3 are in the off state, consuming zero static current.

[0046] This invention eliminates the need for additional operational amplifiers and normally open current mirror bias circuits. It utilizes only resistors, capacitors, MOSFETs, and diodes to achieve a low-power, low-cost, high-reliability, and easily scalable LDO linear transient enhancement circuit, making it particularly suitable for transient slew rate enhancement circuits in LDO chips. This invention saves circuit area and power consumption; the transient response time is not limited by the operational amplifier settling time, enabling faster response to LDO transient changes. The elimination of a normally conducting current mirror bias circuit avoids current consumption during LDO steady-state operation, significantly saving power, especially in high-voltage circuits. For different LDO transient compensation current requirements, this invention only requires adjusting the ratio of MOSFETs NM2 and NM3 and the value of CP1 in the current mirror structure, eliminating the need for complex operational amplifier adjustments found in previous LDO linear transient enhancement circuits, making it simple and easily adaptable.

[0047] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0048] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0049] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0050] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0051] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An LDO linear transient enhancement circuit, comprising a low dropout linear regulator and a current mirror bias circuit, characterized in that, A transient enhancement circuit is provided between the power supply voltage VIN of the low dropout linear regulator and the current mirror bias circuit. The transient enhancement circuit includes a unidirectional conductive element, a capacitor CP1, a resistor RES1, and a MOSFET PM2; The input terminal of the unidirectional conductive element is connected to the power supply voltage VIN, and the output terminal is connected to the source of the MOS transistor PM2. The gate of the MOSFET PM2 is connected to the power supply voltage VIN through resistor RES1, and the drain is connected to the current mirror bias circuit. One end of the capacitor CP1 is connected to the output terminal of the unidirectional conductive element, and the other end is grounded; wherein, the current mirror bias circuit is composed of MOSFET NM2 and MOSFET NM3, and the midpoint of the connection between MOSFET NM2 and MOSFET NM3 is grounded through resistor RES3.

2. The LDO linear transient enhancement circuit according to claim 1, characterized in that, When the power supply voltage VIN rises instantaneously, the MOSFET PM2 is turned off, and the capacitor CP1 is charged and stored through the unidirectional conductive component, and there is no current in the current mirror bias circuit. When the power supply voltage VIN drops instantaneously, MOSFET PM2 turns on, and capacitor CP1 discharges current to ground through MOSFET PM2. A large instantaneous current is generated in the current mirror bias circuit, which increases the discharge current of capacitor CP to ground through MOSFET NM1 in the low dropout linear regulator, and accelerates the increase of the gate-source voltage Vgs of power transistor MP, so as to provide sufficient load current IL to maintain the stability of the output voltage VOUT of the low dropout linear regulator. Furthermore, when the power supply voltage VIN is in static operation, MOSFETs PM2, NM2, and NM3 are in the off state, consuming zero static current.

3. The LDO linear transient enhancement circuit according to claim 1, characterized in that, The unidirectional conductive component is a diode or a MOS transistor containing a diode. The positive terminal of the diode corresponds to the input terminal of the unidirectional conductive element, and the negative terminal of the diode corresponds to the output terminal of the unidirectional conductive element.

4. The LDO linear transient enhancement circuit according to claim 1, characterized in that, The ratio of the mirrored current between MOS transistors NM2 and NM3 is determined based on compensation parameters.

5. The LDO linear transient enhancement circuit according to claim 1, characterized in that, A resistor RES2 is connected between the output terminal of the unidirectional conductive component and the source of the MOS transistor PM2. The midpoint of the current mirror bias circuit is grounded through resistor RES3; The resistors RES1 and RES3 and the capacitor CP1 together form an RC delay circuit to adjust the discharge time.

6. The LDO linear transient enhancement circuit according to claim 1, characterized in that, The low-dropout linear regulator consists of MOSFETs NM1, NM4, PM1, and MP, as well as bias sources idc, VBIASE1, VBIASE2, and VSET.

7. An integrated circuit chip, characterized in that, The chip includes at least one LDO linear transient enhancement circuit as described in any one of claims 1-6.

8. An electronic device, characterized in that, The electronic device is equipped with at least one integrated circuit chip as described in claim 7.

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