Goa circuit and display panel

Abstract

The application discloses a GOA circuit and a display panel, wherein the GOA circuit is additionally provided with a second anti-leakage unit, an output end of the second anti-leakage unit is connected with an output end of a first anti-leakage unit, an input end of the second anti-leakage unit is connected with a pull-up control unit, a first control end of the second anti-leakage unit is connected with a first node, and the second anti-leakage unit is used for blocking a leakage path of the first node when a potential of the first node is at a low potential, so that the first node is charged to a high potential; the first anti-leakage unit starts to work when the first node is at the high potential, the leakage path of the first node is blocked, and the first node is charged to the high potential. The application improves the stability of a charging process of the GOA circuit, and enables the display panel to normally display.

Description

Technical Field

[0001] The present application relates to the technical field of display panel driving, and in particular to a GOA circuit and a display panel. Background Art

[0002] GOA (Gate Driver on Array) technology, also known as array substrate row drive technology, utilizes a thin film transistor liquid crystal display array process to fabricate a gate scan drive circuit on a thin film transistor array substrate to achieve a row-by-row scan drive mode.

[0003] GOA driver circuits offer advantages such as low cost (no gate-IC required), borderless design, and high product yield (gate-driver defects during assembly are avoided). However, GOA circuits place high demands on the stability of thin-film transistors (TFTs). GOA circuits are prone to leakage, which can cause GOA circuit stage failure and display anomalies. Summary of the Invention

[0004] The embodiments of the present application provide a GOA circuit and a display panel to solve the technical problem of display abnormality caused by leakage protection failure of the GOA circuit.

[0005] In a first aspect, the present application provides a GOA circuit, comprising:

[0006] a pull-up control unit, connected to the first node, and configured to pull up the potential of the first node;

[0007] a first anti-leakage unit, wherein a control end of the first anti-leakage unit is connected to the first node, an output end of the first anti-leakage unit is connected to an output end of a second anti-leakage unit, and an input end of the first anti-leakage unit is connected to a high-potential signal end, and the first anti-leakage unit is configured to start operating when the potential of the first node is at a high potential, thereby blocking a leakage path of the first node and charging the first node to a high potential;

[0008] a pull-up unit connected to the first node, and configured to pull up the potentials of the stage transmission signal terminal and the output signal terminal;

[0009] a pull-down unit, wherein an output end of the pull-down unit is connected to the first node, and is used to pull down the potential of the first node;

[0010] A second anti-leakage unit, wherein the first control end of the second anti-leakage unit is connected to the first node, the input end of the second anti-leakage unit is connected to the pull-up control unit, the second anti-leakage unit is used to turn on when the potential of the first node is at a low potential to block the leakage path of the first node, so that the first node is charged to a high potential, and the second anti-leakage unit is used to turn off when the potential of the first node is at a high potential.

[0011] In some embodiments, the second anti-leakage unit includes:

[0012] a first transistor and a second transistor, wherein a channel type of the first transistor is opposite to a channel type of the second transistor;

[0013] The drain of the first transistor is the output terminal of the second anti-leakage unit, the source of the first transistor is connected to the drain of the second transistor, and the gate of the first transistor is the first control terminal of the second anti-leakage unit;

[0014] The source of the second transistor is the input terminal of the second anti-leakage unit, and the gate of the second transistor is connected to the pull-up control signal terminal.

[0015] In some embodiments, the first transistor is a P-type MOS transistor, and the second transistor is an N-type MOS transistor.

[0016] In some embodiments, the first anti-leakage unit includes:

[0017] a third transistor and a fourth transistor, wherein the gate of the third transistor and the gate of the fourth transistor serve as control terminals of the first anti-leakage unit;

[0018] The drain of the third transistor is the output end of the first anti-leakage unit, and the source of the third transistor is connected to the drain of the fourth transistor;

[0019] The source of the fourth transistor is connected to the high potential signal terminal.

[0020] In some embodiments, the pull-down unit includes:

[0021] a fifth transistor and a sixth transistor;

[0022] The gate of the fifth transistor and the gate of the sixth transistor are both connected to the pull-down control signal terminal;

[0023] The source of the fifth transistor is connected to the first node, and the drain of the fifth transistor and the source of the sixth transistor are connected to the output end of the first anti-leakage unit;

[0024] The drain of the sixth transistor is connected to the first low potential signal terminal.

[0025] In some embodiments, the pull-up control unit includes:

[0026] a seventh transistor and an eighth transistor;

[0027] The gate of the seventh transistor and the gate of the eighth transistor are both connected to the pull-up control signal terminal;

[0028] The source of the seventh transistor is connected to the high potential signal terminal, and the drain of the seventh transistor is connected to the source of the eighth transistor;

[0029] A drain of the eighth transistor is connected to the first node.

[0030] In some embodiments, the pull-up unit includes:

[0031] a ninth transistor and a tenth transistor, wherein a gate of the ninth transistor and a gate of the tenth transistor are both connected to the first node;

[0032] The source of the ninth transistor is connected to the first clock signal terminal, the source of the tenth transistor is connected to the second clock signal terminal, the drain of the ninth transistor is connected to the stage transfer signal terminal, and the drain of the tenth transistor is connected to the output signal terminal.

[0033] In some embodiments, the GOA circuit further includes a first pull-down maintaining unit, wherein the first pull-down maintaining unit includes:

[0034] an eleventh transistor and a twelfth transistor, wherein a gate of the eleventh transistor and a gate of the twelfth transistor are both connected to the second node;

[0035] The source of the eleventh transistor is connected to the first node, and the drain of the eleventh transistor and the source of the twelfth transistor are connected to the output end of the first anti-leakage unit;

[0036] The drain of the twelfth transistor is connected to the first low-potential signal terminal.

[0037] In some embodiments, the GOA circuit further includes a reset unit connected to the first node, wherein the reset unit includes:

[0038] a thirteenth transistor and a fourteenth transistor;

[0039] The gate of the thirteenth transistor and the gate of the fourteenth transistor are both connected to the global reset signal terminal VS;

[0040] The source of the thirteenth transistor is connected to the first node, and the drain of the thirteenth transistor and the source of the fourteenth transistor are connected to the output end of the first leakage protection unit;

[0041] The drain of the fourteenth transistor is connected to the first low-potential signal terminal.

[0042] In a second aspect, the present application further provides a display panel comprising the GOA circuit described in the first aspect.

[0043] The present application provides a GOA circuit and display panel, which are connected to a first node through a pull-up control unit to pull up the potential of the first node, the control end of the pull-up unit is connected to the first node to pull up the potential of the stage transmission signal end and the output signal end, the output end of the pull-down unit is connected to the first node to pull down the potential of the first node, the output end of the first anti-leakage unit is connected to the output end of the second anti-leakage unit, the first anti-leakage unit is used to start working when the first node is at a high potential to block the leakage path of the first node, so that the first node is charged to a high potential, the first control end of the second anti-leakage unit is connected to the first node, the input end of the second anti-leakage unit is connected to the pull-up control unit, the second anti-leakage unit is used to start working when the potential of the first node is at a low potential to block the leakage path of the first node, so that the first node is charged to a high potential, thereby improving the stability of the charging process of the GOA circuit and enabling the display panel to display normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 A schematic diagram of the structure of the GOA circuit provided in an embodiment of the present application.

[0046] Figure 2 A timing diagram provided for an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0048] In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "one end" and "the other end" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of this application, "" means two or more, unless otherwise clearly and specifically defined.

[0049] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0050] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0051] The disclosure below provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0052] The present application provides a GOA circuit and display panel. The display panel in the embodiments of the present application can be used in mobile phones, tablet computers, desktop computers, laptop computers, e-readers, handheld computers, electronic display screens, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) and virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.

[0053] The display panel may be a liquid crystal display panel. This application does not limit the type of liquid crystal display panel. The liquid crystal display panel provided in this application may be a horizontal electric field type liquid crystal display panel, such as a Fringe Field Switching (FFS) type liquid crystal display panel or an In-Plane Switching (IPS) type liquid crystal display panel, or a vertical electric field type liquid crystal display panel, such as a twisted nematic (TN) type liquid crystal display panel or a multi-domain vertical alignment (MVA) type liquid crystal display panel.

[0054] See also Figure 1 A schematic diagram of the structure of a GOA circuit provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the GOA circuit includes:

[0055] A pull-up control unit 10 is connected to the first node Q and is used to pull up the potential of the first node Q;

[0056] a first anti-leakage unit 20, wherein a control terminal of the first anti-leakage unit 20 is connected to the first node Q, an output terminal of the first anti-leakage unit 20 is connected to the output terminal of the second anti-leakage unit 50, and an input terminal of the first anti-leakage unit 20 is connected to the high-potential signal terminal VGH. The first anti-leakage unit 20 is configured to start working when the potential of the first node Q is at a high potential, so as to block the leakage path of the first node Q, thereby charging the first node Q to a high potential;

[0057] A pull-up unit 30, wherein a control terminal of the pull-up unit 30 is connected to the first node Q, and is used to pull up the potential of the stage transmission signal terminal Cout[n] and the output signal terminal WR[n];

[0058] a pull-down unit 40 , wherein an output end of the pull-down unit 40 is connected to the first node Q, and is configured to pull down the potential of the first node Q;

[0059] A second anti-leakage unit 50, a first control end of the second anti-leakage unit 50 is connected to the first node Q, an input end of the second anti-leakage unit 50 is connected to the pull-up control unit 10, and the second anti-leakage unit 50 is used to turn on when the potential of the first node Q is at a low potential to block the leakage path of the first node Q, so that the first node Q is charged to a high potential, and the second anti-leakage unit 50 is used to turn off when the potential of the first node Q is at a high potential.

[0060] Specifically, the first node Q can be Figure 1 The path of the pull-down unit 40 shown is leaking. For the GOA circuit provided with the first anti-leakage unit 20, there will be a stage where the potential of the first node Q is pulled high. When the transistor in the first anti-leakage unit 20 is not turned on, it will cause the transistor connected to the first node Q to leak in advance. The present application adds a second anti-leakage unit 50 to the GOA circuit, the control end of the second anti-leakage unit 50 is connected to the first node Q, and the output end of the second anti-leakage unit 50 is connected to the output end of the first anti-leakage unit 20, the control end of the first anti-leakage unit 20 is connected to the first node Q, and the input end of the second anti-leakage unit 50 is connected to the pull-up control unit 10. When the first node Q is at a high potential, the first anti-leakage unit 20 can start working, and when the first node Q is at a high potential, the second anti-leakage unit 50 does not start working. Of course, the threshold voltage Vth of the transistor in the circuit is negatively biased, which may cause the first node Q to start leaking before the first anti-leakage unit 20 starts working. At this time, because the first anti-leakage unit 20 starts leaking before starting working, the first node Q is at a low potential. Then, the second anti-leakage unit 50 blocks the path for the first node Q to leak from the pull-down unit 40 when the potential of the first node Q is at a low potential, so that the transistor in the pull-down unit 40 cannot leak. That is, when the potential of the first node Q is at a low potential, the second anti-leakage unit 50 connects the input end of the first anti-leakage unit 20 to the high potential signal end VGH, and the high voltage connected to the high potential signal end VGH is input to the second node N[n] through the second anti-leakage unit 50, ensuring that the first node Q is normally charged to the specified high potential, blocking the leakage path of the first node Q, and ensuring that the first node Q is normally charged to the specified high potential, so that the display panel can display normally.

[0061] In some embodiments of the present application, Figure 1 As shown, the second anti-leakage unit 50 includes:

[0062] a first transistor T8-1 and a second transistor T8-2, wherein a channel type of the first transistor T8-1 is opposite to a channel type of the second transistor T8-2;

[0063] The drain of the first transistor T8-1 is the output terminal of the second anti-leakage unit 50, the source of the first transistor T8-1 is connected to the drain of the second transistor T8-2, and the gate of the first transistor T8-1 is the first control terminal of the second anti-leakage unit 50;

[0064] The source of the second transistor T8 - 2 is the input terminal of the second anti-leakage unit 50 , and the gate of the second transistor T8 - 2 is connected to the pull-up control signal terminal Cout-PU.

[0065] Specifically, the drain of the first transistor T8-1 is connected to the second node N[n], the source of the first transistor T8-1 is connected to the drain of the second transistor T8-2, the gate of the first transistor T8-1 is connected to the first node Q, the source of the second transistor T8-2 is connected to the pull-up control unit 10, and the gate of the second transistor T8-2 is connected to the pull-up control signal terminal Cout-PU. Since the output terminal of the first leakage prevention unit 20 is connected to the second node N[n] and the control terminal of the first leakage prevention unit 20 is connected to the first node Q, the gate of the first transistor T8-1 is connected to the control terminal of the first leakage prevention unit 20, and the drain of the first transistor T8-1 is connected to the output terminal of the first leakage prevention unit 20.

[0066] Figure 2 A timing diagram provided for an embodiment of the present application, Figure 1 As can be seen in FIG, when the second anti-leakage unit 50 is not provided, the control end of the pull-up control unit 10 is connected to the pull-up control signal end Cout-PU, such as Figure 2 As shown, when the pull-up control signal terminal Cout-PU outputs a high potential in the T1 phase, the pull-up control unit 10 can pull up the potential of the first node Q. Figure 1 As shown, the control terminal of the pull-down unit 40 is connected to the pull-down control signal terminal Cout-PD, as shown in FIG. Figure 2 As shown, when the pull-down control signal terminal Cout-PD outputs a low potential in the T1 stage, the transistor in the pull-down unit 40 is in the off state at this time. However, since the threshold voltage of the transistor is negatively biased, when the transistor in the first anti-leakage unit 20 is not yet turned on or turned on, leakage occurs at the first node Q, so that the level at the first node Q fails to rise normally to the specified high potential, thereby making the first anti-leakage unit 20 unable to work normally, that is, the first anti-leakage unit 20 fails due to the premature leakage of the first node Q, and thus cannot effectively prevent the GOA circuit from leaking.

[0067] The present application sets up a second anti-leakage unit 50. Since the second anti-leakage unit 50 uses the pull-up control signal terminal Cout-PU to control the second transistor T8-2, when the potential of the first node Q is pulled down due to leakage, the first transistor T8-1 can be turned on and input a high potential to the second node N[n], blocking the first node Q from leaking through the leakage path of the pull-down unit 20, so that the first node Q is normally charged to the specified high potential. After the potential of the first node Q is pulled high, the output end of the first anti-leakage unit 20 outputs a high potential. Even if the threshold voltage is negatively biased, it can still ensure that the voltage difference between the gate voltage Vg and the source voltage Vs is less than the threshold voltage, thereby preventing the pull-down unit 30 from being abnormally turned on in advance, causing the first node Q to leak, blocking the leakage path of the first node Q, and ensuring that the first node Q is normally charged to the specified high potential, so that the display panel can display normally.

[0068] It should be noted that Figure 1 Multiple signal terminals use the same label, but in reality these signal terminals with the same label are the same signal terminal. Figure 1 In order to facilitate the illustration and description of the connection of each component in the circuit, each connection terminal will be separately indicated. In fact, the signal terminals with the same label are the same signal terminal. For example Figure 1 All Cout-PUs in the diagram are pull-up control signal terminals. Similarly, other signal terminals with the same label are the same signal terminal. However, it is understandable that each signal terminal may exist in multiple units, but in practice, each signal terminal is not limited to belonging to a specific unit.

[0069] It should be noted that Figure 1 The black dot in the figure indicates that the two lines of the cross setting are connected at this point, but Figure 1 Not all conduction points are marked in the figure, and the actual connection is described in the following embodiments.

[0070] It should be noted that Figure 1 N[n] includes multiple connection ends, but in reality, the multiple connection ends of N[n] are one point. For the convenience of illustration and description, N[n] is divided into multiple connection ends, and in reality, the multiple connection ends are the same point.

[0071] In some embodiments of the present application, the first transistor T8-1 is a P-type MOS transistor, and the second transistor T8-2 is an N-type MOS transistor. Thus, by setting the first transistor T8-1 as a P-type MOS transistor and the second transistor T8-2 as an N-type MOS transistor, the leakage protection capability of the first node Q can be improved, and the circuit stability can be improved.

[0072] In some embodiments of the present application, the first anti-leakage unit 20 includes:

[0073] a third transistor T7_1 and a fourth transistor T7_2, wherein the gate of the third transistor T7_1 and the gate of the fourth transistor T7_2 serve as control terminals of the first anti-leakage unit 20;

[0074] The drain of the third transistor T7_1 is the output end of the first anti-leakage unit 20, and the source of the third transistor T7_1 is connected to the drain of the fourth transistor T7_2;

[0075] The source of the fourth transistor T7_2 is connected to the high potential signal terminal VGH.

[0076] Specifically, by connecting the gate of the first anti-leakage unit 20 to the first node Q, the first anti-leakage unit 20 outputs a high potential signal, and the first node Q is respectively connected to the pull-down unit, the first pull-down maintaining unit and the reset unit, so that the gate of the third transistor T7_1 and the gate of the fourth transistor T7_2 in the first anti-leakage unit 20 are connected to the pull-down unit 40, so that the transistors in the first anti-leakage unit 20 are not turned on, the first anti-leakage unit 20 cannot work normally, that is, the first anti-leakage unit 20 fails and cannot effectively prevent the GOA circuit from leaking, resulting in leakage at the first node Q. The pull-up control signal terminal Cout-PU is used to control the first anti-leakage unit 50. Transistor T8-1 and the second transistor T8-2, when the potential of the first node Q is pulled low, the first transistor T8-1 can be turned on and input a high potential to the second node N[n], blocking the first node Q from leaking through the leakage path of the pull-down unit 40, thereby reducing the leakage current of the first node Q, so that the first node Q is normally charged to the specified high potential, avoiding the failure of the first anti-leakage unit 20, after the potential of the first node Q is pulled high, the first anti-leakage unit 20 can be normally turned on to realize the anti-leakage function of the first anti-leakage unit 20, thereby preventing at least one transistor in the pull-down unit 20 from being abnormally turned on to cause leakage of the first node Q, so that GOA can output signals normally, and the display panel can display normally.

[0077] In some embodiments of the present application, the pull-down unit 40 includes:

[0078] a fifth transistor T41 and a sixth transistor T42;

[0079] The gate of the fifth transistor T41 and the gate of the sixth transistor T42 are both connected to the pull-down control signal terminal Cout-PD;

[0080] The source of the fifth transistor T41 is connected to the first node Q, and the drain of the fifth transistor T41 and the source of the sixth transistor T42 are connected to the output end of the first anti-leakage unit 20;

[0081] The drain of the sixth transistor T42 is connected to the first low potential signal terminal VGL1 .

[0082] Specifically, the problem of leakage may occur in the transistor of the pull-down unit 40 before the first anti-leakage unit 20 works. Figure 1 For example, from Figure 1 It can be seen that when the second anti-leakage unit 50 is not set, the pull-up control signal terminal Cout-PU outputs a high potential. When the potential of the first node Q is pulled up, the pull-down control signal terminal Cout-PD is a low potential, and the transistor in the pull-down unit 40 is in the off state. However, since the threshold voltage of the first transistor T41 and / or the second transistor T42 may be negatively biased, the voltage difference between the gate voltage Vg and the source voltage Vs is greater than the threshold voltage. At this time, the transistor in the first anti-leakage unit 20 has not yet been turned on, and the first anti-leakage unit 20 cannot work normally, that is, the first anti-leakage unit 20 fails and cannot effectively prevent the GOA circuit from leaking, resulting in leakage at the first node Q. In the present application, a second anti-leakage unit 50 is provided. Since the second anti-leakage unit 50 uses a pull-up control signal terminal Cout-PU to control the second transistor T8-2, when the potential of the first node Q is pulled low, the first transistor T8-1 can be turned on and input a high potential to the second node N[n], blocking the first node Q from leaking through the leakage path of the first transistor T41 and / or the second transistor T42, thereby reducing the leakage current of the first node Q, allowing the first node Q to be normally charged to a specified high potential, avoiding failure of the first anti-leakage unit 20. After the potential of the first node Q is pulled high, the output terminal of the first anti-leakage unit 20 outputs a high potential. Even if the threshold voltage is negatively biased, it can still ensure that the voltage difference between the gate voltage Vg and the source voltage Vs is less than the threshold voltage, thereby preventing the first transistor T41 and / or the second transistor T42 from being abnormally turned on, causing leakage of the first node Q, allowing the GOA to output signals normally, and allowing the display panel to display normally.

[0083] In some embodiments of the present application, the pull-up control unit 10 includes:

[0084] a seventh transistor T11 and an eighth transistor T12;

[0085] The gate of the seventh transistor T11 and the gate of the eighth transistor T12 are both connected to the pull-up control signal terminal Cout-PU;

[0086] The source of the seventh transistor T11 is connected to the high potential signal terminal VGH, and the drain of the seventh transistor T11 is connected to the source of the eighth transistor T12;

[0087] A drain of the eighth transistor T12 is connected to the first node Q.

[0088] Specifically, the pull-up control unit controls the potential of the first node Q, thereby controlling whether the GOA circuit outputs a signal.

[0089] In some embodiments of the present application, the pull-up unit 30 includes:

[0090] a ninth transistor T21 and a tenth transistor T22, wherein a gate of the ninth transistor T21 and a gate of the tenth transistor T22 are both connected to the first node Q;

[0091] The source of the ninth transistor T21 is connected to the first clock signal terminal CKa, the source of the tenth transistor T22 is connected to the second clock signal terminal CKb, the drain of the ninth transistor T21 is connected to the stage transfer signal terminal Cout[n], and the drain of the tenth transistor T22 is connected to the output signal terminal WR[n].

[0092] Specifically, by adopting the clock signal input, the GOA circuit can be controlled to control the display of the display panel.

[0093] In some embodiments of the present application, the GOA circuit further includes a first pull-down maintaining unit 70, and the first pull-down maintaining unit 70 includes:

[0094] an eleventh transistor T43 and a twelfth transistor T44, wherein the gate of the eleventh transistor T43 and the gate of the twelfth transistor T44 are both connected to the second node QB;

[0095] The source of the eleventh transistor T43 is connected to the first node Q, and the drain of the eleventh transistor T43 and the source of the twelfth transistor T44 are connected to the output end of the first anti-leakage unit 20;

[0096] The drain of the twelfth transistor T44 is connected to the first low potential signal terminal VGL1 .

[0097] Specifically, the transistor in the first pull-down maintaining unit 70 may leak before the first anti-leakage unit 20 works. Figure 1 For example, from Figure 1It can be seen that when the second anti-leakage unit 50 is not set, the pull-up control signal terminal Cout-PU outputs a high potential. When the potential of the first node Q is pulled up, the output terminal of the first anti-leakage unit 20 is a low potential, and the transistor in the first pull-down maintaining unit 70 is in an off state. However, since the threshold voltage of the eleventh transistor T43 and / or the twelfth transistor T44 may be negatively biased, the voltage difference between the gate voltage Vg and the source voltage Vs is greater than the threshold voltage. At this time, the transistor in the first anti-leakage unit 20 has not yet been turned on, and the first anti-leakage unit 20 cannot work normally, that is, the first anti-leakage unit 20 fails and cannot effectively prevent the GOA circuit from leaking, resulting in leakage at the first node Q. The present application provides a second anti-leakage unit 50. Since the second anti-leakage unit 50 uses a pull-up control signal terminal Cout-PU to control the second transistor T8-2, when the potential of the first node Q is pulled low, the first transistor T8-1 can be turned on and input a high potential to the second node N[n], blocking the first node Q from leaking through the leakage path of the eleventh transistor T43 and / or the twelfth transistor T44, thereby reducing the leakage current of the first node Q, allowing the first node Q to be normally charged to a specified high potential, avoiding failure of the first anti-leakage unit 20. After the potential of the first node Q is pulled high, the output terminal of the first anti-leakage unit 20 outputs a high potential. Even if the threshold voltage is negatively biased, it can still ensure that the voltage difference between the gate voltage Vg and the source voltage Vs is less than the threshold voltage, thereby preventing the eleventh transistor T43 and / or the twelfth transistor T44 from being abnormally turned on, causing leakage of the first node Q, allowing the GOA to output signals normally, and allowing the display panel to display normally.

[0098] In some embodiments of the present application, the GOA circuit further includes a reset unit 60 connected to the first node Q, and the reset unit includes:

[0099] a thirteenth transistor T45 and a fourteenth transistor T46;

[0100] The gate of the thirteenth transistor T45 and the gate of the fourteenth transistor T46 are both connected to the global reset signal terminal VST;

[0101] The source of the thirteenth transistor T45 is connected to the first node Q, and the drain of the thirteenth transistor T45 and the source of the fourteenth transistor T46 are connected to the output end of the first anti-leakage unit 20;

[0102] The drain of the fourteenth transistor T46 is connected to the first low potential signal terminal VGL1 .

[0103] Specifically, the transistor in the reset unit may leak electricity before the first anti-leakage unit 20 works. Figure 1 For example, from Figure 1It can be seen that when the second anti-leakage unit 50 is not set, the pull-up control signal terminal Cout-PU outputs a high potential. When the potential of the first node Q is pulled up, the output terminal of the first anti-leakage unit 20 is a low potential, and the transistor in the reset unit is in a closed state. However, since the threshold voltage of the thirteenth transistor T45 and / or the fourteenth transistor T46 may be negatively biased, the voltage difference between the gate voltage Vg and the source voltage Vs is greater than the threshold voltage. At this time, the transistor in the first anti-leakage unit 20 has not yet been turned on, and the first anti-leakage unit 20 cannot work normally, that is, the first anti-leakage unit 20 fails and cannot effectively prevent the GOA circuit from leaking, resulting in leakage at the first node Q. In the present application, a second anti-leakage unit 50 is provided. Since the second anti-leakage unit 50 uses a pull-up control signal terminal Cout-PU to control the first transistor T8-1 and the second transistor T8-2, when the potential of the first node Q is pulled low, the first transistor T8-1 and the second transistor T8-2 can be turned on and input a high potential to the second node N[n], blocking the first node Q from leaking through the leakage path of the thirteenth transistor T45 and / or the fourteenth transistor T46, thereby reducing the leakage current of the first node Q, allowing the first node Q to be normally charged to a specified high potential, and avoiding failure of the first anti-leakage unit 20. After the potential of the first node Q is pulled high, the output terminal of the first anti-leakage unit 20 outputs a high potential. Even if the threshold voltage is negatively biased, it can still ensure that the voltage difference between the gate voltage Vg and the source voltage Vs is less than the threshold voltage, thereby preventing the thirteenth transistor T45 and / or the fourteenth transistor T46 from being abnormally turned on, causing leakage of the first node Q, allowing the GOA to output signals normally, and allowing the display panel to display normally.

[0104] In some embodiments, after a frame ends, the reset unit may output a high potential via the global reset signal terminal VST to turn on the thirteenth transistor T45 and the fourteenth transistor T46 , thereby pulling down the first node Q of the GOA circuit.

[0105] In some embodiments of the present application, Figure 1As shown, the inverter 80 includes a fifteenth transistor T51A, a sixteenth transistor T51B, a seventeenth transistor T52, an eighteenth transistor T53, a nineteenth transistor T54, and a twentieth transistor T56. The gate of the fifteenth transistor T51A, the drain of the fifteenth transistor T51A, the gate of the sixteenth transistor T51B, and the drain of the eighteenth transistor T53 are connected to the low-frequency clock signal LC. The source of the fifteenth transistor T51A is connected to the drain of the sixteenth transistor T51B, the source of the sixteenth transistor T51B and the drain of the seventeenth transistor T52 are connected to the gate of the eighteenth transistor T53, the gate of the seventeenth transistor T52 and the gate of the nineteenth transistor T54 are connected to the first node Q, the source of the seventeenth transistor T52 is connected to the third low-potential signal terminal VGL3, the source of the eighteenth transistor T53, the drain of the nineteenth transistor T54, and the drain of the twentieth transistor T56 are connected to the third node QB, the source of the nineteenth transistor T54 and the source of the twentieth transistor T56 are connected to the first low-potential signal terminal VGL1, and the gate of the twentieth transistor T56 is connected to the pull-up control signal terminal Cout-PU. By providing an inverter 80, the potentials of the first node Q and the third node QB are reversed, so that the circuit operates normally.

[0106] In some embodiments of the present application, the GOA circuit further includes a second pull-down maintaining unit 90, which includes a twenty-first transistor T31 and a twenty-second transistor T32. The gate of the twenty-first transistor T31 and the gate of the twenty-second transistor T32 are connected to the third node QB, the drain of the twenty-first transistor T31 is connected to the stage transmission signal terminal Cout[n], and the source of the twenty-first transistor T31 is connected to the first low-potential signal terminal VGL1. The drain of the twenty-second transistor T32 is connected to the output signal terminal WR[n], and the source of the twenty-second transistor T32 is connected to the second low-potential signal terminal VGL2. By providing the second pull-down maintaining unit 90, the potentials of the stage transmission signal terminal Cout[n] and the output signal terminal WR[n] can be maintained at a low potential.

[0107] Specifically, Figure 1 This is the nth level GOA circuit in the gate drive circuit provided in the embodiment of the present application. Therefore, the output signal terminal is indicated by WR[n]. It can be understood that according to different values ​​of n, different levels of GOA circuits are designed.

[0108] Specifically, Figure 1 The GOA circuit shown, Figure 2The working process of the GOA circuit is explained by taking the timing diagram of each signal terminal and each point in the GOA circuit as an example. Figure 1 、 Figure 2 As shown:

[0109] In the first phase T1, a high voltage is input to the pull-up control signal terminal Cout-PU, turning on the seventh transistor T11 and the tenth transistor T12. After the high voltage is input to the pull-up control signal terminal Cout-PU, the negative Vth bias of the transistors in the pull-down unit may cause leakage of the first node Q before the third transistors T7_1 and T7_2 are turned on, thus rendering the first leakage prevention unit 20 inoperable. The newly added second leakage prevention unit 50 in this application assists in charging the first node Q, ensuring that the first leakage prevention unit 20 properly outputs a high voltage. T8_1 is a PMOS transistor, and T8_2 is a NOSM transistor. When the first node Q can be normally charged to a high voltage, T8_1 is turned off. If Q leaks through other pathways (for example, premature leakage caused by the pull-down unit 40, the first pull-down control unit 70, and the reset unit 60 in the above embodiment), the first leakage prevention unit 20 fails, and the first node Q is at a low potential, which controls T8_1 to turn on. VGH is input to point N[n] through T8_2 and T8_1, blocking the leakage path of the first node Q and ensuring that the first node Q is normally charged to the specified high potential. After the first leakage prevention unit 20 is normally activated, the first node Q is charged to a high potential, and T8_1 and T8_2 are turned off. The first node Q is pulled to a high potential, the third transistor T7_1 and the fourth transistor T7_2 are turned on, and the first leakage prevention unit 20 is normally turned on. The output terminal of the first leakage prevention unit 20 outputs a high potential to point N[n], blocking the leakage path of the first node Q and ensuring that the first node Q is normally charged to the specified high potential.

[0110] In the second phase T2, the first clock signal terminal CKa ( Figure 2 The first node Q is coupled to a higher potential due to the first capacitor C1.

[0111] In the third stage T3, after the signal output of the stage transfer signal terminal Cout[n] and the output signal terminal WR[n] is completed, the pull-down control signal terminal Cout-PD inputs a high potential, the first transistor T41 and the second transistor T42 are turned on, and the potential of the first node Q is pulled down. At the same time, the third transistor T7_1 and the fourth transistor T7_2 are turned off, and the output terminal of the first leakage protection unit 20 has no high potential output.

[0112] In an embodiment, the transistor described above can be a low-temperature polysilicon thin-film transistor, an oxide thin-film transistor, and a hydrogenated polycrystalline thin-film transistor grown by a low-temperature solid-phase crystallization process.

[0113] The newly added second anti-creeping unit 50 can utilize the switching characteristics of NMOS and PMOS to ensure that the first node Q is charged to a high potential when the anti-creeping function fails, so that the first anti-creeping unit 20 can be normally started, that is, the second anti-creeping unit 50 is used to ensure that the first node Q is charged to a specified high potential, and the subsequent first anti-creeping unit 20 normally operates, thereby ensuring the charging stability of the boosting circuit.

[0114] The output end of the first anti-creeping unit 20 is connected to the pull-up control unit 10, so that the high potential signal accessed through the pull-up control unit 10 flows through the output end of the first anti-creeping unit to charge the first node Q, thereby reducing the leakage current of the first node Q and enabling the display panel to normally display.

[0115] The above embodiment takes the first pull-down unit 30 how to prevent leakage as an example for detailed description. It can be understood that for the abnormal opening of at least one transistor in the first pull-down maintenance unit 70 and the reset unit 60 to cause the leakage of the first node Q, the second anti-creeping unit 50 is opened when the potential of the first node Q is at a low potential to block the leakage path of the first node Q, so as to ensure that the first node Q is charged to a high potential, so that the first anti-creeping unit 20 is normally started, and the principle of avoiding the leakage of the GOA circuit is the same, which will not be described here.

[0116] The embodiment of the present application also provides a display panel, which comprises a GOA circuit as Figure 1 The embodiment shown in the figure corresponds to a GOA circuit.

[0117] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0118] The above describes in detail the GOA circuit and the display panel provided by the embodiment of the present application. The specific examples are applied to explain the principle and implementation manner of the present application. The above embodiment is only used to help understand the method and core idea of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range can be changed. In summary, the content of the specification should not be understood as a limitation of the present application. Moreover, for those skilled in the art, some improvements and refinements can be made without departing from the principle of the present application, and these improvements and refinements are also regarded as the protection scope of the present application.

Claims

1. A GOA circuit, characterized in that: include: A pull-up control unit (10), connected to the first node (Q), and configured to pull up the potential of the first node (Q); a first anti-leakage unit (20), wherein a control end of the first anti-leakage unit (20) is connected to the first node (Q), an output end of the first anti-leakage unit (20) is connected to an output end of a second anti-leakage unit (50), an input end of the first anti-leakage unit (20) is connected to a high potential signal end (VGH), and the first anti-leakage unit (20) is configured to start working when the potential of the first node (Q) is at a high potential, so as to block a leakage path of the first node (Q), thereby charging the first node (Q) to a high potential; A pull-up unit (30), wherein a control terminal of the pull-up unit (30) is connected to the first node (Q) and is used to pull up the potentials of the stage transmission signal terminal (Cout[n]) and the output signal terminal (WR[n]); a pull-down unit (40), wherein an output end of the pull-down unit (40) is connected to the first node (Q) and is used to pull down the potential of the first node (Q); A second anti-leakage unit (50), wherein a first control end of the second anti-leakage unit (50) is connected to the first node (Q), an input end of the second anti-leakage unit (50) is connected to the pull-up control unit (10), the second anti-leakage unit (50) is used to turn on when the potential of the first node (Q) is at a low potential, so as to block the leakage path of the first node (Q), so that the first node (Q) is charged to a high potential, and the second anti-leakage unit (50) is used to turn off when the potential of the first node (Q) is at a high potential.

2. The GOA circuit according to claim 1, wherein: The second anti-leakage unit (50) comprises: a first transistor (T8-1) and a second transistor (T8-2), wherein a channel type of the first transistor (T8-1) is opposite to a channel type of the second transistor (T8-2); The drain of the first transistor (T8-1) is the output terminal of the second anti-leakage unit (50), the source of the first transistor (T8-1) is connected to the drain of the second transistor (T8-2), and the gate of the first transistor (T8-1) is the first control terminal of the second anti-leakage unit (50); The source of the second transistor (T8-2) is the input terminal of the second anti-leakage unit, and the gate of the second transistor (T8-2) is connected to the pull-up control signal terminal (Cout-PU).

3. The GOA circuit according to claim 2, characterized in that The first transistor (T8-1) is a P-type MOS transistor, and the second transistor (T8-2) is an N-type MOS transistor.

4. The GOA circuit according to claim 2, wherein: The first anti-leakage unit (20) comprises: a third transistor (T7_1) and a fourth transistor (T7_2), wherein the gate of the third transistor (T7_1) and the gate of the fourth transistor (T7_2) serve as control terminals of the first anti-leakage unit (20); The drain of the third transistor (T7_1) is the output end of the first anti-leakage unit (20), and the source of the third transistor (T7_1) is connected to the drain of the fourth transistor (T7_2); The source of the fourth transistor (T7_2) is connected to the high potential signal terminal (VGH).

5. The GOA circuit according to claim 4, characterized in that The pull-down unit (40) comprises: a fifth transistor (T41) and a sixth transistor (T42); The gate of the fifth transistor (T41) and the gate of the sixth transistor (T42) are both connected to the pull-down control signal terminal (Cout-PD); The source of the fifth transistor (T41) is connected to the first node (Q), and the drain of the fifth transistor (T41) and the source of the sixth transistor (T42) are connected to the output end of the first anti-leakage unit; The drain of the sixth transistor (T42) is connected to the first low potential signal terminal (VGL1).

6. The GOA circuit according to claim 5, characterized in that The pull-up control unit (10) comprises: a seventh transistor (T11) and an eighth transistor (T12); The gate of the seventh transistor (T11) and the gate of the eighth transistor (T12) are both connected to the pull-up control signal terminal (Cout-PU); The source of the seventh transistor (T11) is connected to the high potential signal terminal (VGH), and the drain of the seventh transistor (T11) is connected to the source of the eighth transistor (T12); The drain of the eighth transistor (T12) is connected to the first node (Q).

7. The GOA circuit according to claim 6, wherein: The pull-up unit (30) comprises: a ninth transistor (T21) and a tenth transistor (T22), wherein a gate of the ninth transistor (T21) and a gate of the tenth transistor (T22) are both connected to the first node (Q); The source of the ninth transistor (T21) is connected to the first clock signal terminal (CKa), the source of the tenth transistor (T22) is connected to the second clock signal terminal (CKb), the drain of the ninth transistor (T21) is connected to the stage transfer signal terminal (Cout[n]), and the drain of the tenth transistor (T22) is connected to the output signal terminal (WR[n]).

8. The GOA circuit according to claim 7, wherein: The GOA circuit further comprises a first pull-down maintaining unit (70), wherein the first pull-down maintaining unit (70) comprises: an eleventh transistor (T43) and a twelfth transistor (T44), wherein a gate of the eleventh transistor (T43) and a gate of the twelfth transistor (T44) are both connected to the second node (QB); The source of the eleventh transistor (T43) is connected to the first node (Q), and the drain of the eleventh transistor (T43) and the source of the twelfth transistor (T44) are connected to the output end of the first anti-leakage unit (20); The drain of the twelfth transistor (T44) is connected to the first low potential signal terminal (VGL1).

9. The GOA circuit according to claim 8, characterized in that The GOA circuit further comprises a reset unit (60) connected to the first node (Q), wherein the reset unit (60) comprises: a thirteenth transistor (T45) and a fourteenth transistor (T46); The gate of the thirteenth transistor (T45) and the gate of the fourteenth transistor (T46) are both connected to the global reset signal terminal (VST); The source of the thirteenth transistor (T45) is connected to the first node (Q), and the drain of the thirteenth transistor (T45) and the source of the fourteenth transistor (T46) are connected to the output end of the first anti-leakage unit (20); The drain of the fourteenth transistor (T46) is connected to the first low potential signal terminal (VGL1).

10. A display panel, characterized in that: The GOA circuit comprises the GOA circuit according to any one of claims 1 to 9.

Images