Semiconductor package
By employing a cross-arranged wiring layer and insulating region structure in semiconductor packaging, the stability and characteristics of semiconductor devices are solved, resulting in reduced losses, uniform operation, and suppression of malfunctions, thereby improving the reliability and mechanical strength of the package.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KK TOSHIBA
- Filing Date
- 2023-02-20
- Publication Date
- 2026-06-26
AI Technical Summary
In existing semiconductor packaging, the stability and characteristics of semiconductor devices such as IGBTs are difficult to guarantee, especially when the control signal is uneven, the loss is large, and the parasitic inductance and mutual inductance differences lead to malfunctions and current oscillations.
A specific wiring structure is adopted, including a first conductive component, a second conductive component, multiple semiconductor devices, wiring components, a first connecting component, and a second connecting component. Through the cross-arranged wiring layers and insulation areas, the uniformity of wiring length is ensured, parasitic inductance and mutual inductance differences are reduced, and current control is stabilized.
It improves the stability and reliability of semiconductor packaging, reduces losses during shutdown, homogenizes the operation of semiconductor devices, enhances mechanical strength and capacitance consistency, and suppresses malfunctions and current oscillations.
Smart Images
Figure CN117594543B_ABST
Abstract
Description
[0001] This application is based on Japanese Patent Application No. 2022-127742 (filed on August 10, 2022), from which it enjoys priority benefits. This application incorporates the entire contents of that application by reference. Technical Field
[0002] Embodiments of the present invention relate to semiconductor packaging. Background Technology
[0003] Stable characteristics are desired in semiconductor packages containing semiconductor devices such as IGBTs (insulated gate bipolar transistors). Summary of the Invention
[0004] Embodiments of the present invention provide a semiconductor package that yields stable properties.
[0005] Methods for solving problems
[0006] According to an embodiment of the present invention, a semiconductor package includes a first conductive component, a second conductive component, a plurality of semiconductor devices, a wiring component, a first connection component, and a second connection component. The plurality of semiconductor devices are disposed between the first conductive component and the second conductive component. One of the plurality of semiconductor devices includes a semiconductor component, a first electrode disposed between the first conductive component and the semiconductor component, a first control electrode disposed between the first conductive component and the semiconductor component, a second control electrode disposed between the first conductive component and the semiconductor component, and a second electrode disposed between the semiconductor component and the second conductive component. The first conductive component is electrically connected to the first electrode. The second conductive component is electrically connected to the second electrode. A direction from the second control electrode to the first control electrode intersects a first direction from the first conductive component to the second conductive component. The wiring component includes a first wiring layer, a second wiring layer, a third wiring layer, and an insulating region. Directions from the first wiring layer to the second wiring layer and from the first wiring layer to the third wiring layer are along the first direction. At least a portion of the insulating region is located between the first wiring layer and the third wiring layer, and between the third wiring layer and the second wiring layer. The second wiring layer is positioned in the first direction between the position of the insulating region in the first direction and the positions of the plurality of semiconductor devices in the first direction. The second wiring layer includes a first connection region and a second connection region. The first connection region is electrically connected to the first wiring layer. The third wiring layer is electrically connected to the first conductive component. The first connection component is disposed between the first connection region and the first control electrode, electrically connecting the first connection region to the first control electrode. The second connection component is disposed between the second connection region and the second control electrode, electrically connecting the second connection region to the second control electrode.
[0007] The semiconductor package with the above structure can provide a semiconductor package with stable characteristics. Attached Figure Description
[0008] Figure 1 This is a cross-sectional schematic diagram illustrating the semiconductor package of the first embodiment.
[0009] Figure 2 This is a top view schematic diagram illustrating the semiconductor package of the first embodiment.
[0010] Figure 3 This is a cross-sectional schematic diagram illustrating the semiconductor package of the first embodiment.
[0011] Figure 4 This is a cross-sectional schematic diagram illustrating a portion of the semiconductor package according to the first embodiment.
[0012] Figure 5 This is a circuit diagram illustrating the semiconductor package of the first embodiment.
[0013] Figure 6 (a) and Figure 6 (b) is a schematic diagram illustrating the operation of the semiconductor packaging according to the first embodiment.
[0014] Figure 7 This is a circuit diagram illustrating a portion of the semiconductor package according to the first embodiment.
[0015] Figure 8 This is a cross-sectional schematic diagram illustrating the semiconductor package of the second embodiment.
[0016] Figure 9 This is a cross-sectional schematic diagram illustrating the semiconductor package of the second embodiment.
[0017] Figure 10 This is a cross-sectional schematic diagram illustrating the semiconductor package of the second embodiment.
[0018] Figure 11 This is a top view schematic diagram illustrating the semiconductor package of the second embodiment.
[0019] Figure 12 This is a top view schematic diagram illustrating the semiconductor package of the second embodiment.
[0020] Figure 13 (a) and Figure 13 (b) is a cross-sectional schematic diagram illustrating the semiconductor package of the second embodiment.
[0021] Figure 14 This is a cross-sectional schematic diagram illustrating the semiconductor package of the second embodiment.
[0022] Figure 15 This is a cross-sectional schematic diagram illustrating the semiconductor package of the second embodiment.
[0023] Figure 16 This is a top view schematic diagram illustrating a portion of a semiconductor package according to an embodiment.
[0024] Figure 17 This is a top view schematic diagram illustrating a portion of a semiconductor package according to an embodiment.
[0025] Figure 18 This is a top view schematic diagram illustrating a portion of a semiconductor package according to an embodiment.
[0026] Figure 19This is a side view schematic diagram illustrating the usage state of the semiconductor package in the embodiment.
[0027] Explanation of reference numerals in the attached figures
[0028] 11a~11f…First semiconductor region~sixth semiconductor region; 11i…Component insulating portion; 15…Semiconductor device; 15a, 15b…First control electrode, second control electrode; 15i…Component insulating part; 15p, 15q…First electrode, second electrode; 15s…Semiconductor part; 20…Wiring part; 20h…Wiring part hole; 21~24…First wiring layer~fourth wiring layer; 21f~23f…Fixing part; 22a~22c…First connection region~third connection region; 23h…Second wiring layer hole; 25i…Insulating region; 27a~27c…First connection portion~third connection portion; 28…Fixing part; 28p…First fixing portion; 28e…First fixing extension portion; 31, 32…First connecting part, second connecting part; 35a, 35b…First conductive plate, second conductive plate Plate; 45…Insulating plate; 51~54…First conductive part~Fifth conductive part; 61, 62…First conductive component, second conductive component; 61b…First base part; 61p…First protrusion; 65…Insulating component; 81, 82…First plate, second plate; 83…Fixing component; 84…Cooling fin; 85, 86…Insulator; 87…Spring; 110~114, 120…Semiconductor package; D1, D2…First direction, second direction; De1~De3…First element direction~Third element direction; L1~L3, Lg1, Lg2…Parasitic inductance; T1~T3…First terminal~Third terminal; V1~V4…First potential~Fourth potential; Vc1, Vc2…Potential; f1, f2…First surface, second surface; r1~r4…First part region~Fourth part region; t1…First moment; tm…Time Detailed Implementation
[0029] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.
[0030] The accompanying drawings are schematic or conceptual, and the relationships between the thicknesses and widths of the parts, as well as the ratios between the sizes of the parts, may not be the same as in reality. Even when representing the same parts, the dimensions and ratios may sometimes be shown differently depending on the accompanying drawings.
[0031] In the specification and figures of this application, elements that are the same as those described in previously existing figures are labeled with the same reference numerals and detailed descriptions are omitted where appropriate.
[0032] (First Implementation)
[0033] Figure 1This is a cross-sectional schematic diagram illustrating the semiconductor package of the first embodiment.
[0034] Figure 2 This is a top view schematic diagram illustrating the semiconductor package of the first embodiment.
[0035] Figure 3 This is a cross-sectional schematic diagram illustrating the semiconductor package of the first embodiment.
[0036] Figure 1 yes Figure 2 A1-A2 line cross-section view. Figure 3 yes Figure 2 The cross-sectional view along line B1-B2.
[0037] like Figure 1 As shown, the semiconductor package 110 of the embodiment includes a first conductive component 61, a second conductive component 62, a plurality of semiconductor devices 15, a wiring component 20, a first connection component 31 and a second connection component 32.
[0038] Multiple semiconductor devices 15 are disposed between the first conductive member 61 and the second conductive member 62. A first direction D1 from the first conductive member 61 to the second conductive member 62 is defined as the Z-axis direction. A direction perpendicular to the Z-axis direction is defined as the X-axis direction. A direction perpendicular to both the Z-axis and X-axis directions is defined as the Y-axis direction. Figure 2 As shown, multiple semiconductor devices 15 are arranged, for example, in the XY plane. Figure 2 The image shows a state in which the second conductive component 62 has been removed.
[0039] like Figure 1 As shown, one of the plurality of semiconductor devices 15 includes a semiconductor component 15s, a first electrode 15p, a first control electrode 15a, a second control electrode 15b, and a second electrode 15q.
[0040] The first electrode 15p is disposed between the first conductive component 61 and the semiconductor component 15s. The first control electrode 15a is disposed between the first conductive component 61 and the semiconductor component 15s. The second control electrode 15b is disposed between the first conductive component 61 and the semiconductor component 15s. The second electrode 15q is disposed between the semiconductor component 15s and the second conductive component 62.
[0041] For example, one of the plurality of semiconductor devices 15 includes a first surface f1 and a second surface f2. The first surface f1 is located between the first conductive member 61 and the second surface f2. The second surface f2 is located between the first surface f1 and the second conductive member 62. The first surface f1 is opposite to the first conductive member 61. The second surface f2 is opposite to the second conductive member 62.
[0042] For example, the first electrode 15p, the first control electrode 15a, and the second control electrode 15b are disposed on the first surface f1. The second electrode 15q is disposed on the second surface f2.
[0043] The first conductive component 61 is electrically connected to the first electrode 15p. The second conductive component 62 is electrically connected to the second electrode 15q.
[0044] like Figure 1 and Figure 2 As shown, the direction from the second control electrode 15b to the first control electrode 15a intersects the first direction D1 (the direction from the first conductive member 61 to the second conductive member 62). Figure 1 and Figure 2 In the example, in one of the plurality of semiconductor devices 15 of interest, the direction from the second control electrode 15b to the first control electrode 15a is along a second direction D2. The second direction D2 intersects the first direction D1. In one example, the second direction D2 may be the X-axis direction.
[0045] like Figure 1 As shown, the wiring component 20 includes a first wiring layer 21, a second wiring layer 22, a third wiring layer 23, and an insulation region 25i. The direction from the first wiring layer 21 to the second wiring layer 22 and the direction from the third wiring layer 23 to the second wiring layer 22 are along a first direction D1. In this example, the third wiring layer 23 is located between the first wiring layer 21 and the second wiring layer 22.
[0046] At least a portion of the insulating region 25i is located between the first wiring layer 21 and the second wiring layer 22, and between the third wiring layer 23 and the second wiring layer 22. The insulating region 25i insulates these wiring layers from each other.
[0047] In the wiring component 20, the first wiring layer 21, the second wiring layer 22, the third wiring layer 23, and the insulation region 25i can also be in contact with each other and integrated as one unit. Alternatively, the first wiring layer 21, the second wiring layer 22, the third wiring layer 23, and the insulation region 25i can also be separated from each other.
[0048] The second wiring layer 22 is positioned in the first direction D1 between the position of the insulating region 25i in the first direction D1 and the position of the plurality of semiconductor devices 15 in the first direction D1. The second wiring layer 22 is opposite to the plurality of semiconductor devices 15.
[0049] like Figure 1 As shown, the second wiring layer 22 includes a first connection area 22a and a second connection area 22b.
[0050] The first connection region 22a is electrically connected to the first wiring layer 21. In this example, the wiring component 20 also includes a first connection portion 27a. The first connection portion 27a electrically connects the first wiring layer 21 to the second connection region 22b. At least a portion of the first connection portion 27a extends in the insulating region 25i along a first direction D1 (Z-axis direction). In this example, the third wiring layer 23 includes a third wiring layer hole 23h. The first connection portion 27a passes through the third wiring layer hole 23h.
[0051] As will be described later, the third wiring layer 23 is electrically connected to the first conductive component 61.
[0052] like Figure 1 As shown, the first connecting component 31 is disposed between the first connecting region 22a and the first control electrode 15a. The first connecting component 31 electrically connects the first connecting region 22a and the first control electrode 15a.
[0053] like Figure 1 As shown, the second connecting member 32 is disposed between the second connecting region 22b and the second control electrode 15b. The second connecting member 32 electrically connects the second connecting region 22b and the second control electrode 15b.
[0054] like Figure 1 As shown, the semiconductor package 110 may include a first terminal T1, a second terminal T2, and a third terminal T3. The first terminal T1 is electrically connected to the first wiring layer 21. The second terminal T2 is electrically connected to the second wiring layer 22. The third terminal T3 is electrically connected to the third wiring layer 23.
[0055] In the semiconductor package 110, the current (e.g., main current) flowing between the first conductive component 61 and the second conductive component 62 can be controlled by a signal supplied to at least one of the first terminal T1 and the second terminal T2. This current can be controlled by the potential of at least one of the first terminal T1 and the second terminal T2. The signal (or potential) can be a signal (potential) referenced to the potential of the third terminal T3.
[0056] The plurality of semiconductor devices 15 are transistors. For example, the plurality of semiconductor devices 15 may be IGBTs (Insulated Gate Bipolar Transistors). The first electrode 15p corresponds, for example, to the emitter. The second electrode 15q corresponds, for example, to the collector. The first control electrode 15a corresponds to the gate. The second control electrode 15b corresponds to the electrode used for control operation.
[0057] As described later, the second terminal T2 receives a control signal different from that received by the first terminal T1. This, for example, reduces losses during turn-off. However, reducing these losses is more difficult when the control signals input to the multiple semiconductor devices 15 are not uniform.
[0058] For example, consider a reference example where the wiring connected to the first control electrode 15a and the wiring connected to the second control electrode 15b are located in the same plane. In this case, the lengths of these wirings differ significantly across the multiple semiconductor devices 15. Therefore, in the reference example, the reduction in losses is insufficient.
[0059] In one embodiment, the first wiring layer 21 connected to the first control electrode 15a and the second wiring layer 22 connected to the second control electrode 15b may overlap in the first direction D1. Therefore, the length difference of these wiring layers can be suppressed in the plurality of semiconductor devices 15. According to the embodiment, in each of the plurality of semiconductor devices 15, the desired reduction in loss can be effectively and stably achieved.
[0060] According to the implementation method, losses can be reduced. For example, a semiconductor package with stable characteristics can be provided. For example, the operation of multiple semiconductor devices 15 is uniformized. For example, higher reliability is easily obtained.
[0061] like Figure 1 As shown, in this example, the position of the second wiring layer 22 in the first direction D1 is between the position of the first wiring layer 21 in the first direction D1 and the positions of the plurality of semiconductor devices 15 in the first direction D1. The position of the third wiring layer 23 in the first direction D1 is between the position of the first wiring layer 21 in the first direction D1 and the position of the second wiring layer 22 in the first direction D1.
[0062] For example, the first wiring layer 21, the third wiring layer 23, and the second wiring layer 22 are arranged side by side in this order. Therefore, for example, the parasitic capacitance between the first wiring layer 21 and the third wiring layer 23 is substantially the same as the parasitic capacitance between the second wiring layer 22 and the third wiring layer 23. For example, the distortion of the signal supplied to the first wiring layer 21 is similar to the distortion of the signal supplied to the second wiring layer 22. This allows for more stable loss reduction.
[0063] The distance along the first direction D1 between the first wiring layer 21 and the third wiring layer 23 (the first distance) can be substantially the same as the distance along the first direction D1 between the third wiring layer 23 and the second wiring layer 22 (the second distance). This allows the parasitic capacitances to be substantially the same. In one example, the second distance can be more than 0.5 times and less than 1.5 times the first distance. In another example, the second distance can be more than 0.3 times and less than 3.0 times the first distance. For example, in the wiring component 20, it is easy to obtain higher mechanical strength.
[0064] In this embodiment, the first connecting member 31 and the second connecting member 32 are preferably elastic members. These wiring members are, for example, spring pins. A stable connection is possible.
[0065] like Figure 3 As shown, the first conductive member 61 may include a first base portion 61b and a first protrusion 61p. The first protrusion 61p is connected to the first base portion 61b. The first protrusion 61p protrudes toward the second conductive member 62 with reference to the first base portion 61b.
[0066] like Figure 3 As shown, the wiring component 20 includes, for example, a wiring component hole 20h. A first protrusion 61p passes through the wiring component hole 20h. The end of the first protrusion 61p is opposed to a plurality of semiconductor devices 15.
[0067] like Figure 1 and Figure 3 As shown, in this example, the semiconductor package 110 includes a first conductive plate 35a and a second conductive plate 35b. The first conductive plate 35a is located between a first protrusion 61p and a first electrode 15p. The second conductive plate 35b is located between a second electrode 15q and a second conductive component 62. The first conductive plate 35a electrically connects the first protrusion 61p and the first electrode 15p. The second conductive plate 35b electrically connects the second electrode 15q and the second conductive component 62.
[0068] At least one of the first conductive plate 35a and the second conductive plate 35b contains, for example, Mo. The first conductive plate 35a and the second conductive plate 35b are, for example, Mo plates. At least one of the first conductive component 61 and the second conductive component 62 contains, for example, Cu.
[0069] like Figure 3 As shown, the second wiring layer 22 may further include a third connection region 22c. On the other hand, the wiring component 20 may further include a second connection portion 27b and a fourth wiring layer 24. An insulating region 25i is located between the fourth wiring layer 24 and the third connection region 22c in a first direction D1. The second connection portion 27b extends in the insulating region 25i along the first direction D1. The second connection portion 27b electrically connects the fourth wiring layer 24 and the third connection region 22c.
[0070] In this example, the wiring component 20 also includes a third connection portion 27c. The third connection portion 27c extends along a first direction D1 in the insulation region 25i. The third connection portion 27c electrically connects the third connection region 22c to the third wiring layer 23.
[0071] With this structure, the third wiring layer 23 is electrically connected to the fourth wiring layer 24 via the third connection portion 27c, the third connection area 22c, and the second connection portion 27b. The fourth wiring layer 24 is electrically connected to the first conductive component 61.
[0072] like Figure 3 As shown, in this example, the semiconductor package 110 further includes a fixing member 28. The fixing member 28 includes a first fixing portion 28p and a first fixing extension portion 28e. The first fixing extension portion 28e is connected to the first fixing portion 28p. For example, the width of the first fixing portion 28p along the second direction D2 is greater than the width of the first fixing extension portion 28e along the second direction D2. The fixing member 28 may be, for example, a screw.
[0073] The fourth wiring layer 24, the second connection portion 27b, and the third connection region 22c are located between a portion of the first conductive member 61 and the first fixing portion 28p in the first direction D1. The first fixing extension portion 28e passes through the fourth wiring layer 24, the second connection portion 27b, and the third connection region 22c along the first direction D1. The first fixing extension portion 28e is fixed to the aforementioned portion of the first conductive member 61. For example, the wiring member 20 is fixed to the first conductive member 61 by means of a fixing member 28 (e.g., a screw). The third wiring layer 23 is electrically connected to the first conductive member 61 by means of the fixing member 28.
[0074] like Figure 1 and Figure 3 As shown, the semiconductor package 110 may further include an insulating plate 45. The insulating plate 45 is disposed between the first base portion 61b and the wiring component 20. The insulating plate 45 electrically insulates the portions of the first conductive component 61b and the wiring component 20 that should be insulated. The insulating plate 45 may, for example, comprise glass epoxy.
[0075] like Figure 1 and Figure 3 As shown, the semiconductor package 110 may further include an insulating component 65. For example... Figure 2 As shown, an insulating member 65 is disposed around a plurality of semiconductor devices 15 in a plane (e.g., an XY plane) intersecting the first direction D1. At least a portion of the insulating member 65 is located between the first conductive member 61 and the second conductive member 62. The insulating member 65 may, for example, comprise ceramic. The insulating member 65 may, for example, be an insulator. Stable insulation can be obtained.
[0076] In one embodiment, stresses are applied to the plurality of semiconductor devices 15 in a direction from the first conductive member 61 toward the plurality of semiconductor devices 15 and in a direction from the second conductive member 62 toward the plurality of semiconductor devices 15. The semiconductor package 110 is, for example, a press-pack semiconductor device (press-pack IGBT).
[0077] Thus, in this embodiment, one of the plurality of semiconductor devices 15 is an IGBT. The first electrode 15p functions as the emitter. The second electrode 15q functions as the collector. The current flowing between the first electrode 15p and the second electrode 15q can be controlled by the potential of at least one of the first control electrode 15a and the second control electrode 15b.
[0078] Figure 4 This is a cross-sectional schematic diagram illustrating a portion of the semiconductor package according to the first embodiment. Figure 4 One of a plurality of semiconductor devices 15 is illustrated. For example... Figure 4 As shown, one of the plurality of semiconductor devices 15 includes a first conductive portion 51, a second conductive portion 52, a third conductive portion 53, a fourth conductive portion 54, and a component insulating portion 11i. A second component direction De2 from the third conductive portion 53 to the fourth conductive portion 54 intersects a first component direction De1 from the first conductive portion 51 to the second conductive portion 52. The first component direction De1 may, for example, be the opposite direction to the aforementioned first direction D1. The third conductive portion 53 and the fourth conductive portion 54 extend along the third component direction De3. The third component direction De3 intersects a plane that includes the first component direction De1 and the second component direction De2.
[0079] As already described, one of the plurality of semiconductor devices 15 includes a semiconductor component 15s. Figure 4 As shown, the semiconductor component 15s includes a first semiconductor region 11a of a first conductivity type, a second semiconductor region 11b of a second conductivity type, a third semiconductor region 11c of a first conductivity type, and a fourth semiconductor region 11d of a second conductivity type.
[0080] The fourth semiconductor region 11d is located between the first conductive portion 51 and the first semiconductor region 11a in the first element direction De1. The first semiconductor region 11a includes a first partial region r1, a second partial region r2, a third partial region r3, and a fourth partial region r4. The first partial region r1 is located between the fourth semiconductor region 11d and the third conductive portion 53 in the first element direction De1. The second partial region r2 is located between the fourth semiconductor region 11d and the fourth conductive portion 54 in the first element direction De1.
[0081] The third region r3 lies between the first region r1 and the second region r2 in the second element direction De2. The fourth region r4 lies between the third region r3 and the third semiconductor region 11c in the first element direction De1. The second semiconductor region 11b lies between the fourth region r4 and the third semiconductor region 11c in the first element direction De1.
[0082] The direction from the third conductive portion 53 toward the fourth portion region r4, the second semiconductor region 11b, and the third semiconductor region 11c is along the second element direction De2. The second semiconductor region 11b is located between the third conductive portion 53 and the fourth conductive portion 54 in the second element direction De2.
[0083] The first conductive part 51 is electrically connected to the fourth semiconductor region 11d. The second conductive part 52 is electrically connected to the third semiconductor region 11c.
[0084] The component insulating portion 11i is disposed between the semiconductor component 15s and the third conductive portion 53, between the semiconductor component 15s and the fourth conductive portion 54, between the third conductive portion 53 and the second semiconductor region 11b, and between the second semiconductor region 11b and the fourth conductive portion 54. The component insulating portion 11i may be disposed between the third conductive portion 53 and the third semiconductor region 11c.
[0085] The first conductive part 51 is electrically connected to the first electrode 15p. The second conductive part 52 is electrically connected to the second electrode 15q. The third conductive part 53 is electrically connected to the first control electrode 15a. The fourth conductive part 54 is electrically connected to the second control electrode 15b.
[0086] The first conductivity type is either n-type or p-type. The second conductivity type is either n-type or p-type. Hereinafter, we assume the first conductivity type is n-type and the second conductivity type is p-type.
[0087] The first semiconductor region 11a, for example, includes n - Region. An n-region may also be provided between the first semiconductor region 11a and the second semiconductor region 11b. The second semiconductor region 11b, for example, includes a p-region. The third semiconductor region 11c, for example, includes an n-region. + Region. The fourth semiconductor region 11d, for example, includes a p-region. The impurity concentration (e.g., carrier concentration) of the first conductivity type in the third semiconductor region 11c is higher than the impurity concentration (e.g., carrier concentration) of the first conductivity type in the first semiconductor region 11a.
[0088] In this example, a fifth semiconductor region 11e of a second conductivity type is provided. The fifth semiconductor region 11e is located between the second semiconductor region 11b and the second conductive portion 52. The impurity concentration (e.g., carrier concentration) of the second conductivity type in the fifth semiconductor region 11e is higher than the impurity concentration (e.g., carrier concentration) of the second conductivity type in the second semiconductor region 11b. The fifth semiconductor region 11e is, for example, p... + The area provides a good electrical connection.
[0089] In this example, a sixth semiconductor region 11f of a first conductivity type is provided. The sixth semiconductor region 11f is located between the fourth semiconductor region 11d and the first semiconductor region 11a. The impurity concentration (e.g., carrier concentration) of the first conductivity type in the sixth semiconductor region 11f is higher than that in the first semiconductor region 11a. The sixth semiconductor region 11f is, for example, an n-region. Good electrical connection can be obtained.
[0090] like Figure 4 As shown, a plurality of third conductive parts 53 and a plurality of fourth conductive parts 54 are provided. The number (density) of the plurality of fourth conductive parts 54 can be greater than the number (density) of the plurality of third conductive parts 53.
[0091] Figure 5 This is a circuit diagram illustrating the semiconductor package of the first embodiment.
[0092] like Figure 5 As shown, multiple semiconductor devices 15 are connected in parallel. The current flowing between the first conductive component 61 and the second conductive component 62 is controlled by signals supplied to the first terminal T1 and the second terminal T2.
[0093] Figure 6 (a) and Figure 6 (b) is a schematic diagram illustrating the operation in the semiconductor package of the first embodiment.
[0094] Figure 6 (a) illustrates the potential Vc1 of the first terminal T1. Figure 6 Figure (b) illustrates the potential Vc2 at the second terminal T2. These potentials can be referenced to the potential at the third terminal T3. The horizontal axis of these graphs represents time tm.
[0095] like Figure 6As shown in (a), when the potential Vc1 of the first terminal T1, referenced to the potential of the third terminal T3, is the second potential V2, it corresponds to the off state. When the potential Vc1 is the first potential V1, it corresponds to the on state. The second potential V2 is lower than the first potential V1. For example, the second potential V2 is negative and the first potential V1 is positive. The change in potential Vc1 from the first potential V1 to the second potential V2 forms the off state.
[0096] During the cutoff operation where the potential Vc1 of the first terminal T1 changes from the first potential V1 to the second potential V2, the moment when the potential changes from the first potential V1 to the second potential V2 is set as the first moment t1.
[0097] like Figure 6 As shown in (b), the potential Vc2 of the second terminal T2, referenced to the potential of the third terminal T3, can change from the third potential V3 to the fourth potential V4. The fourth potential V4 is lower than the third potential V3. For example, the fourth potential V4 is negative and the third potential is positive.
[0098] like Figure 6 (a) and Figure 6 As shown in (b), before the first time t1, the potential Vc2 of the second terminal T2 changes from the third potential V3 to the fourth potential V4. Therefore, for example, it is possible to effectively discharge the charge carriers accumulated in the semiconductor component for 15s. Therefore, for example, it is possible to reduce losses during turn-off.
[0099] Such potential control (signal control) can be performed by a control unit connected to the semiconductor package 110. The semiconductor package 110 may contain a control unit that performs such potential control (signal control).
[0100] Figure 7 This is a circuit diagram illustrating a portion of the semiconductor package according to the first embodiment.
[0101] Figure 7 One of a plurality of semiconductor devices 15 is illustrated. For example... Figure 7 As shown, the first electrode 15p is electrically connected to the first conductive component 61. The second electrode 15q is electrically connected to the second conductive component 62. The first control electrode 15a is electrically connected to the first terminal T1. The second control electrode 15b is electrically connected to the second terminal T2. The first electrode 15p is electrically connected to the third terminal T3.
[0102] For example, a parasitic inductance L1 exists in the current path between the first electrode 15p and the first conductive component 61. For example, a parasitic inductance L2 exists in the current path between the second electrode 15q and the second conductive component 62. A parasitic inductance Lg1 exists in the current path between the first control electrode 15a and the first terminal T1. A parasitic inductance Lg2 exists in the current path between the second control electrode 15b and the second terminal T2. A parasitic inductance L3 exists in the current path between the first electrode 15p and the third terminal T3.
[0103] Mutual inductance occurs between parasitic inductances Lg1 and Lg2. Mutual inductance occurs between parasitic inductances Lg1 and L3. Mutual inductance occurs between parasitic inductances Lg2 and L3.
[0104] Furthermore, mutual inductance occurs between parasitic inductance Lg1 and parasitic inductance L2. Mutual inductance also occurs between parasitic inductance Lg1 and parasitic inductance L2.
[0105] Mutual inductance occurs between parasitic inductance Lg2 and parasitic inductance L1. Mutual inductance is generated between parasitic inductance Lg2 and parasitic inductance L2.
[0106] In the multiple semiconductor devices 15, uniform operation can be easily obtained by making these parasitic inductances and mutual inductances uniform. In the embodiment, by using the wiring component 20 described above, these inductances can be easily reduced and made uniform. For example, signal delay can be made uniform.
[0107] For example, parasitic inductance Lg1 causes a transmission delay in the control signal supplied to the first control electrode 15a. Parasitic inductance Lg2 causes a transmission delay in the control signal supplied to the second control electrode 15b. The difference in these parasitic inductances results in a difference in the transmission delay of these control signals. Due to this difference in transmission delay, malfunctions may sometimes occur.
[0108] In this embodiment, by using the wiring component 20 described above, it is easy to make the wiring length uniform in a plurality of semiconductor devices 15. For example, it is possible to reduce the difference in parasitic inductance.
[0109] Mutual inductance results in an induced voltage caused by the change in the signal supplied to the control electrode over time (dI / dt). This induced voltage can sometimes cause malfunctions or current oscillations.
[0110] For example, when the third wiring layer 23 is provided between the first wiring layer 21 and the second wiring layer 22, the magnetic field generated by the current flowing into the first wiring layer 21 and the magnetic field generated by the current flowing into the second wiring layer 22 cancel each other out. As a result, mutual inductance can be effectively suppressed.
[0111] According to the embodiment, in multiple semiconductor devices 15, it is easy to make the wiring length uniform. The deviation of parasitic inductance can be reduced. For example, mutual inductance can be suppressed. Malfunctions can be further suppressed.
[0112] (Second Implementation)
[0113] Figure 8 and Figure 9 This is a cross-sectional schematic diagram illustrating the semiconductor package of the second embodiment.
[0114] Figure 8 Is with Figure 2 The cross-sectional view corresponding to line A1-A2. Figure 9 Is with Figure 2 The cross-sectional view corresponding to line B1-B2.
[0115] like Figure 8 As shown, in the semiconductor package 120 of this embodiment, the structure of the wiring component 20 differs from that of the wiring component 20 in the semiconductor package 110. Otherwise, the structure of the semiconductor package 120 may be the same as that of the semiconductor package 110.
[0116] like Figure 8 As shown, in the semiconductor package 120, the wiring component 20 includes a first wiring layer 21, a second wiring layer 22, a third wiring layer 23, and an insulating region 25i. Figure 8 As shown, the position of the second wiring layer 22 in the first direction D1 is between the position of the third wiring layer 23 in the first direction D1 and the positions of the plurality of semiconductor devices 15 in the first direction D1. The position of the first wiring layer 21 in the first direction D1 is between the position of the third wiring layer 23 in the first direction D1 and the position of the second wiring layer 22 in the first direction D1.
[0117] In such a semiconductor package 120, it is also easy to achieve uniform wiring lengths across multiple semiconductor devices 15. Parasitic inductance deviations can be reduced. A semiconductor package with stable characteristics can be provided.
[0118] Such as about Figure 6 As explained, before the first moment t1 of the cutoff operation, the potential Vc2 of the second terminal T2 is changed from the third potential V3 to the fourth potential V4. This, for example, allows for the efficient removal of charge carriers accumulated in the semiconductor component for 15s, reducing losses during turn-off. By making the number of the plurality of fourth conductive portions 54 greater than the number of the plurality of third conductive portions 53, charge carrier removal can be more efficient.
[0119] When the number of the plurality of fourth conductive portions 54 is greater than the number of the plurality of third conductive portions 53, the capacitance of the second control electrode 15b is greater than the capacitance of the first control electrode 15a. In this case, by bringing the second wiring layer 22, which is connected to the second control electrode 15b with the larger capacitance, closer to the semiconductor device 15, waveform distortion can be further suppressed. For example, the second wiring layer 22 is located between the first wiring layer 21 and the plurality of semiconductor devices 15. More stable operation can be obtained.
[0120] Hereinafter, examples of semiconductor packaging in the embodiments will be described.
[0121] Figures 10-15 This is a schematic diagram illustrating a semiconductor package according to an embodiment.
[0122] Figure 10 , Figure 13 , Figure 14 and Figure 15 It is a cross-sectional view. Figure 11 and Figure 12 It is a top view.
[0123] like Figure 10 As shown, semiconductor package 111 has the same structure as semiconductor package 110. The second terminal T2 passes through the insulating member 65 and is exposed to the outside.
[0124] Figure 11 An example is shown of a first surface f1 in a semiconductor package 111. On the first surface f1, a first electrode 15p, a first control electrode 15a, and a second control electrode 15b are provided. These electrodes are not covered by the component insulating member 15i. Multiple first electrodes 15p can be provided.
[0125] Figure 12 A second surface f2 in a semiconductor package 111 is illustrated. A second electrode 15q is provided on the second surface f2.
[0126] Figures 13-15 A portion of the outer edge of the semiconductor package 111 is illustrated below. For example... Figure 13 As shown, the second terminal T2 is electrically connected to the second wiring layer 22 via the fixing component 22f. For example... Figure 14 As shown, the third terminal T3 is electrically connected to the third wiring layer 23 via the fixing component 23f. (As indicated...) Figure 15 As shown, the first terminal T1 is electrically connected to the first wiring layer 21 via the fixing component 21f. The fixing components 21f, 22f, and 23f are, for example, conductive screws.
[0127] Figures 16-18 This is a top view schematic diagram illustrating a portion of a semiconductor package according to an embodiment.
[0128] These diagrams illustrate the first face f1. For example... Figure 16 As shown, in the semiconductor package 112, the second control electrode 15b is located next to the first control electrode 15a. These control electrodes are located at the corners of the semiconductor device 15.
[0129] like Figure 17 As shown, in the semiconductor package 113, the second control electrode 15b is disposed along one side of the semiconductor device 15 in a manner separate from the first control electrode 15a.
[0130] like Figure 18 As shown, in the semiconductor package 114, the second control electrode 15b is disposed next to the first control electrode 15a. These control electrodes are disposed at the center of one side of the semiconductor device 15.
[0131] Figure 19 This is a side view schematic diagram illustrating the usage state of the semiconductor package in the embodiment.
[0132] like Figure 19 As shown, multiple semiconductor packages 110 may also overlap. Multiple semiconductor packages 110 are disposed between the first plate 81 and the second plate 82. Cooling fins 84 may be disposed between the multiple semiconductor packages 110. For example, an insulator 85 may be disposed between the first plate 81 and the cooling fins 84. For example, an insulator 86 may be disposed between the cooling fins 84 and the second plate 82. A spring 87 may be disposed between the insulator 86 and the second plate 82. The first plate 81 and the second plate 82 may be fixed in a pressure-applied state by a fixing member 83 (e.g., a screw).
[0133] The implementation methods may also include the following technical solutions.
[0134] (Technical Solution 1)
[0135] A semiconductor package, wherein:
[0136] First conductive component;
[0137] Second conductive component;
[0138] A plurality of semiconductor devices are disposed between a first conductive component and a second conductive component. One of the plurality of semiconductor devices includes a semiconductor component, a first electrode disposed between the first conductive component and the semiconductor component, a first control electrode disposed between the first conductive component and the semiconductor component, a second control electrode disposed between the first conductive component and the semiconductor component, and a second electrode disposed between the semiconductor component and the second conductive component. The first conductive component is electrically connected to the first electrode, and the second conductive component is electrically connected to the second electrode. The direction from the second control electrode to the first control electrode intersects a first direction from the first conductive component to the second conductive component.
[0139] A wiring component includes a first wiring layer, a second wiring layer, a third wiring layer, and an insulating region. Along a first direction, from the first wiring layer to the second wiring layer and from the first wiring layer to the third wiring layer, at least a portion of the insulating region is located between the first wiring layer and the third wiring layer, and between the third wiring layer and the second wiring layer. The position of the second wiring layer in the first direction is between the position of the insulating region in the first direction and the positions of the plurality of semiconductor devices in the first direction. The second wiring layer includes a first connection region and a second connection region. The first connection region is electrically connected to the first wiring layer, and the third wiring layer is electrically connected to the first conductive component.
[0140] A first connecting component is disposed between the first connecting region and the first control electrode, electrically connecting the first connecting region and the first control electrode; and
[0141] The second connecting component is disposed between the second connecting region and the second control electrode, and electrically connects the second connecting region and the second control electrode.
[0142] (Technical Solution 2)
[0143] According to the semiconductor package described in technical solution 1, wherein,
[0144] The position of the second wiring layer in the first direction is located between the position of the first wiring layer in the first direction and the positions of the plurality of semiconductor devices in the first direction.
[0145] The position of the third wiring layer in the first direction is between the position of the first wiring layer in the first direction and the position of the second wiring layer in the first direction.
[0146] (Technical Solution 3)
[0147] According to the semiconductor package described in technical solution 2, wherein,
[0148] The distance between the first wiring layer and the third wiring layer along the first direction is more than 0.3 times and less than 3.0 times the distance between the third wiring layer and the second wiring layer along the first direction.
[0149] (Technical Solution 4)
[0150] According to the semiconductor package described in technical solution 2 or 3, wherein,
[0151] The wiring component also includes a first connecting part.
[0152] The first connection portion electrically connects the first wiring layer to the first connection area.
[0153] At least a portion of the first connection extends along the first direction in the insulating region.
[0154] (Technical Solution 5)
[0155] According to the semiconductor package described in technical solution 4, wherein...
[0156] The third wiring layer includes third wiring layer vias.
[0157] The first connection portion passes through the hole in the third wiring layer.
[0158] (Technical Solution 6)
[0159] According to the semiconductor package described in technical solution 1, wherein,
[0160] The position of the second wiring layer in the first direction is located between the position of the third wiring layer in the first direction and the position of the plurality of semiconductor devices in the first direction.
[0161] The position of the first wiring layer in the first direction is between the position of the third wiring layer in the first direction and the position of the second wiring layer in the first direction.
[0162] (Technical Solution 7)
[0163] According to the semiconductor package described in technical solution 6, wherein...
[0164] The capacitance of the second control electrode is greater than that of the first control electrode.
[0165] (Technical Solution 8)
[0166] The semiconductor package according to any one of technical solutions 1 to 7, wherein,
[0167] The first conductive component includes a first base portion and a first protrusion connected to the first base portion.
[0168] The wiring component includes a wiring component hole.
[0169] The first protrusion passes through the hole in the wiring component.
[0170] (Technical Solution 9)
[0171] According to the semiconductor package described in technical solution 8, wherein...
[0172] The semiconductor package also includes a first conductive plate and a second conductive plate.
[0173] The first conductive plate is located between the first protrusion and the first electrode.
[0174] The second conductive plate is located between the second electrode and the second conductive component.
[0175] (Technical Solution 10)
[0176] According to the semiconductor package described in technical solution 8 or 9, wherein,
[0177] The semiconductor package also includes an insulating plate.
[0178] The insulating plate is disposed between the first base portion and the wiring component.
[0179] (Technical Solution 11)
[0180] The semiconductor package according to any one of technical solutions 1 to 10, wherein,
[0181] The wiring component further includes a second connector and a fourth wiring layer.
[0182] The first wiring layer also includes a third connection area.
[0183] The insulating region is located between the fourth wiring layer and the third connection region in the first direction.
[0184] The second connection portion extends along the first direction in the insulating region.
[0185] The second connection portion electrically connects the fourth wiring layer to the third connection area.
[0186] (Technical Solution 12)
[0187] According to the semiconductor package described in technical solution 11, wherein,
[0188] The semiconductor package also includes a fixing component.
[0189] The fixing component includes a first fixing portion and a first fixing extension portion.
[0190] The first fixed extension portion is connected to the first fixed portion.
[0191] The fourth wiring layer, the second connection portion, and the third connection area are located in the first direction between a portion of the first conductive component and the first fixing portion.
[0192] The first fixed extension portion passes through the fourth wiring layer, the second connection portion, and the third connection region along the first direction.
[0193] The first fixed extension portion is fixed to the portion of the first conductive component.
[0194] (Technical Solution 13)
[0195] According to the semiconductor package described in technical solution 12, wherein,
[0196] The fixing component is a screw.
[0197] (Technical Solution 14)
[0198] The semiconductor package according to any one of technical solutions 1 to 13, wherein,
[0199] The first connecting component and the second connecting component are elastic components.
[0200] (Technical Solution 15)
[0201] The semiconductor package according to any one of technical solutions 1 to 14, wherein,
[0202] One of the plurality of semiconductor devices is an IGBT.
[0203] The first electrode functions as the emitter.
[0204] The second electrode functions as a collector.
[0205] The current flowing between the first electrode and the second electrode can be controlled by the potential of at least one of the first control electrode and the second control electrode.
[0206] (Technical Solution 16)
[0207] The semiconductor package according to any one of technical solutions 1 to 15, wherein,
[0208] The semiconductor package also includes insulating components.
[0209] The insulating component is disposed around the plurality of semiconductor devices in a plane intersecting the first direction.
[0210] At least a portion of the insulating component is located between the first conductive component and the second conductive component.
[0211] (Technical Solution 17)
[0212] The semiconductor package according to technical solution 16 further comprises:
[0213] The first terminal electrically connected to the first wiring layer;
[0214] The second terminal electrically connected to the second wiring layer; and
[0215] The third terminal is electrically connected to the third wiring layer;
[0216] At least one of the first terminal, the second terminal, and the third terminal passes through the insulating member in a direction intersecting the first direction.
[0217] (Technical Solution 18)
[0218] According to the semiconductor package described in technical solution 17, wherein,
[0219] During the cutoff operation where the potential of the first terminal, based on the potential of the third terminal, changes from a first potential to a second potential, before the first moment of the change from the first potential to the second potential, the potential of the second terminal, based on the potential of the third terminal, can change from a third potential to a fourth potential.
[0220] The second potential is lower than the first potential.
[0221] The fourth potential is lower than the third potential.
[0222] (Technical Solution 19)
[0223] The semiconductor package according to any one of technical solutions 1 to 18, wherein,
[0224] One of the plurality of semiconductor devices includes a first conductive portion, a second conductive portion, a third conductive portion, a fourth conductive portion, and a component insulating portion.
[0225] The direction from the third conductive portion to the fourth conductive portion, towards the second element, intersects with the direction from the first conductive portion to the second conductive portion, towards the first element.
[0226] The semiconductor component includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type.
[0227] The fourth semiconductor region is located between the first conductive portion and the first semiconductor region in the direction of the first element.
[0228] The first semiconductor region includes a first partial region, a second partial region, a third partial region, and a fourth partial region.
[0229] The first portion of the region is located between the fourth semiconductor region and the third conductive portion in the direction of the first element.
[0230] The second portion of the region is located between the fourth semiconductor region and the fourth conductive portion in the direction of the first element.
[0231] The third region is located between the first region and the second region in the direction of the second element.
[0232] The fourth region is located between the third region and the third semiconductor region in the direction of the first element.
[0233] The second semiconductor region is located between the fourth portion region and the third semiconductor region in the direction of the first element.
[0234] The direction from the third conductive portion toward the fourth portion region, the second semiconductor region, and the third semiconductor region along the direction of the second element.
[0235] The second semiconductor region is located between the third conductive portion and the fourth conductive portion in the direction of the second element.
[0236] The first conductive portion is electrically connected to the fourth semiconductor region.
[0237] The second conductive portion is electrically connected to the third semiconductor region.
[0238] The insulating portion of the element is disposed between the semiconductor component and the third conductive portion, between the semiconductor component and the fourth conductive portion, between the third conductive portion and the second semiconductor region, and between the second semiconductor region and the fourth conductive portion.
[0239] (Technical Solution 20)
[0240] The semiconductor package according to any one of technical solutions 1 to 19, wherein,
[0241] Stress is applied to the plurality of semiconductor devices in a direction from the first conductive component toward the plurality of semiconductor devices and in a direction from the second conductive component toward the plurality of semiconductor devices.
[0242] According to the implementation method, a semiconductor package with stable characteristics can be provided.
[0243] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, any specific structure of the various elements included in a semiconductor package, such as conductive components, semiconductor devices, wiring components, and connection components, is included within the scope of the present invention, as long as the present invention can be similarly implemented and the same effects obtained by appropriate selection by those skilled in the art from the known scope.
[0244] Furthermore, any solution obtained by combining any two or more elements in each specific example within the technically possible range is included within the scope of this invention, as long as it contains the spirit of this invention.
[0245] Furthermore, all semiconductor packages that can be implemented by those skilled in the art based on the semiconductor package described as an embodiment of the present invention with appropriate design modifications, as long as they contain the spirit of the present invention, are also included within the scope of the present invention.
[0246] Furthermore, it is understood that within the scope of the present invention, those skilled in the art can conceive of various modifications and alterations, which also fall within the scope of the present invention.
[0247] Some embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention as set forth in the claims and its equivalents.
Claims
1. A semiconductor package, characterized in that, have: First conductive component; Second conductive component; A plurality of semiconductor devices are disposed between a first conductive component and a second conductive component. One of the plurality of semiconductor devices includes a semiconductor component, a first electrode disposed between the first conductive component and the semiconductor component, a first control electrode disposed between the first conductive component and the semiconductor component, a second control electrode disposed between the first conductive component and the semiconductor component, and a second electrode disposed between the semiconductor component and the second conductive component. The first conductive component is electrically connected to the first electrode, and the second conductive component is electrically connected to the second electrode. The direction from the second control electrode to the first control electrode intersects a first direction from the first conductive component to the second conductive component. A wiring component includes a first wiring layer, a second wiring layer, a third wiring layer, and an insulating region. Along a first direction, from the first wiring layer to the second wiring layer and from the first wiring layer to the third wiring layer, at least a portion of the insulating region is located between the first wiring layer and the third wiring layer, and between the third wiring layer and the second wiring layer. The position of the second wiring layer in the first direction is between the position of the insulating region in the first direction and the positions of the plurality of semiconductor devices in the first direction. The second wiring layer includes a first connection region and a second connection region. The first connection region is electrically connected to the first wiring layer, and the third wiring layer is electrically connected to the first conductive component. A first connecting component is disposed between the first connecting region and the first control electrode, and electrically connects the first connecting region and the first control electrode. as well as A second connecting component is disposed between the second connecting region and the second control electrode, electrically connecting the second connecting region and the second control electrode.
2. The semiconductor package according to claim 1, characterized in that, The position of the second wiring layer in the first direction is located between the position of the first wiring layer in the first direction and the positions of the plurality of semiconductor devices in the first direction. The position of the third wiring layer in the first direction is between the position of the first wiring layer in the first direction and the position of the second wiring layer in the first direction.
3. The semiconductor package according to claim 2, characterized in that, The distance between the first wiring layer and the third wiring layer along the first direction is more than 0.3 times and less than 3.0 times the distance between the third wiring layer and the second wiring layer along the first direction.
4. The semiconductor package according to claim 2, characterized in that, The wiring component also includes a first connecting part. The first connection portion electrically connects the first wiring layer to the first connection area. At least a portion of the first connection extends along the first direction in the insulating region.
5. The semiconductor package according to claim 4, characterized in that, The third wiring layer includes third wiring layer vias. The first connection portion passes through the hole in the third wiring layer.
6. The semiconductor package according to claim 1, characterized in that, The position of the second wiring layer in the first direction is located between the position of the third wiring layer in the first direction and the position of the plurality of semiconductor devices in the first direction. The position of the first wiring layer in the first direction is between the position of the third wiring layer in the first direction and the position of the second wiring layer in the first direction.
7. The semiconductor package according to claim 1, characterized in that, The first conductive component includes a first base portion and a first protrusion connected to the first base portion. The wiring component includes a wiring component hole. The first protrusion passes through the hole in the wiring component.
8. The semiconductor package according to claim 1, characterized in that, The wiring component further includes a second connector and a fourth wiring layer. The first wiring layer also includes a third connection area. The insulating region is located between the fourth wiring layer and the third connection region in the first direction. The second connection portion extends along the first direction in the insulating region. The second connection portion electrically connects the fourth wiring layer to the third connection area.
9. The semiconductor package according to claim 8, characterized in that, The semiconductor package also includes a fixing component. The fixing component includes a first fixing portion and a first fixing extension portion. The first fixed extension portion is connected to the first fixed portion. The fourth wiring layer, the second connection portion, and the third connection area are located in the first direction between a portion of the first conductive component and the first fixing portion. The first fixed extension portion passes through the fourth wiring layer, the second connection portion, and the third connection region along the first direction. The first fixed extension portion is fixed to the portion of the first conductive component.
10. The semiconductor package according to claim 1, characterized in that, One of the plurality of semiconductor devices is an IGBT. The first electrode functions as the emitter. The second electrode functions as a collector. The current flowing between the first electrode and the second electrode can be controlled by the potential of at least one of the first control electrode and the second control electrode.