Power semiconductor components and processing equipment

Abstract

An embodiment of the present specification provides a power semiconductor element and a processing device thereof, wherein the power semiconductor element includes: a first semiconductor layer forming a field stop layer, a second semiconductor layer formed on the first semiconductor layer, a charge storage layer formed between the first semiconductor layer and the second semiconductor layer, and the doping concentration is higher than that of the first semiconductor layer and the first gate and the second gate; a first groove portion and a second groove portion penetrate the second semiconductor layer, extend to the first semiconductor layer, and are spaced a certain distance apart from each other; an emitter is formed above the second semiconductor layer; an emitter layer is formed between the first groove portion and the second groove portion, and is in contact with the first groove portion and the second groove portion; and the structure can enhance the soundness of the power semiconductor element by limiting the maximum current capacity of the short-circuit circuit, thereby preventing the power semiconductor element from being damaged before the protection circuit operates and the short-circuit current from flowing when a short circuit occurs.

Description

Technical Field

[0001] The embodiments of the present specification relate to the field of semiconductor technology, and in particular, to power semiconductor elements and processing devices thereof. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) has higher input impedance than power field effect transistor and higher current flow capacity than bipolar transistor, and is mainly used as power switching element. This type of insulated gate bipolar transistor can be roughly divided into planar gate and trench gate. Recently, the research and development of trench gate, which can simultaneously increase current density and reduce size, has been active.

[0003] Generally speaking, an insulated gate bipolar transistor has: an emitter layer of the first conductivity type and a base layer of the second conductivity type, a drift layer (base layer) of the first conductivity type, a collector layer and a base layer of the second conductivity type, and a gate formed by an insulating film resisting the drift layer. 2 Through the allowable voltage of the gate, a channel is formed on the base layer, and a small amount of carriers (holes) are injected from the collector layer to the drift layer, so that the conductivity on the drift layer is changed, the resistance value is reduced, and thus all voltages during conduction can be reduced. At the same time, the problem of the insulated gate bipolar transistor is that in the short circuit circuit (Short circuit), the load is connected for switching, and when a short circuit occurs after the external load disappears to '0', the collector layer and the emitter layer are immediately supplied with an external voltage. In the case of such a short circuit, a large amount of current will flow instantly to the insulated gate bipolar transistor, so there is a problem of having to withstand a high power within a few μs to start the protection circuit. Therefore, a better solution is urgently needed. Summary of the invention

[0004] In view of this, the embodiments of this specification provide a power semiconductor element and a processing device thereof. One or more embodiments of this specification also relate to a power semiconductor element processing device, a computing device, a computer-readable storage medium and a computer program to solve the technical defects existing in the prior art.

[0005] According to a first aspect of an embodiment of the present specification, there is provided a power semiconductor element, comprising: a first semiconductor layer 110 forming a field stop layer 111, a second semiconductor layer 120 formed on the first semiconductor layer 110, a charge accumulation layer 130 formed between the first semiconductor layer 110 and the second semiconductor layer 120, wherein the doping concentration of the charge accumulation layer 130 is higher than that of the first semiconductor layer 110 and the first gate 142 and the second gate 142a;

[0006] The first groove portion 140 and the second groove portion 140a penetrate the second semiconductor layer 120, extend to the first semiconductor layer 110, and are spaced a certain distance apart from each other;

[0007] The emitter 150 is formed on the second semiconductor layer 120;

[0008] The first emission layer 160 and the second emission layer 160a are formed between the first groove portion 140 and the second groove portion 140a, and are in contact with the first groove portion 140 and the second groove portion 140a;

[0009] The first barrier layer 170 and the second barrier layer 170a are arranged in parallel below the first groove portion 140 and the second groove portion 140a, are spaced a certain distance apart from each other, and vertically intersect the first groove portion 140 and the second groove portion 140a, so as to prevent electrons from flowing from the first emission layer 160 and the second emission layer 160a to the collector 180;

[0010] The collector electrode 180 is connected to a collector layer 181 formed under the first semiconductor layer 110 .

[0011] In a possible implementation, the first emission layer 160 and the second emission layer 160a are respectively formed directly above the space separated by the first barrier layer 170 and the second barrier layer 170a;

[0012] The characteristic of the maximum current amount is adjusted according to the length dimensions of the first emission layer 160 and the second emission layer 160 a and the spacing distance between the first barrier layer 170 and the second barrier layer 170 a .

[0013] In a possible implementation, the first groove portion 140 and the second groove portion 140a form insulating films 141, 141a on the inner walls; and the first gate 142 and the second gate 142a are buried by the insulating films 141, 141a and insulated from the second semiconductor layer 120 and the emission layer.

[0014] In a possible implementation, the emitter 150 forms an emitter contact 152 between the first trench portion 140 and the second trench portion 140 a and extends to the second semiconductor layer 120 .

[0015] In a possible implementation, the first barrier layer and the second barrier layer cover the bottom surface of the charge storage layer 130, the bottom surfaces of the first groove portion 140 and the second groove portion 140a, and part of the lower side surface of the first groove portion 140 and the second groove portion 140a.

[0016] In a possible implementation, the first barrier layer and the second barrier layer are spaced a certain distance from the bottom surface of the charge storage layer 130 and cover the bottom surfaces of the first groove portion 140 and the second groove portion 140a and part of the side surfaces of the first groove portion 140 and the second groove portion 140a.

[0017] In a possible implementation, it includes:

[0018] The first barrier layer and the second barrier layer are spaced a certain distance from the bottom surface of the charge storage layer, and are formed below the bottom surfaces of the first groove portion 140 and the second groove portion 140 a at a certain distance.

[0019] According to a second aspect of an embodiment of the present specification, a power semiconductor element is provided, comprising: a first semiconductor layer 110 forming a field stop layer 111, a second semiconductor layer 120 formed on the first semiconductor layer 110, a charge storage layer 130 formed between the first semiconductor layer 110 and the second semiconductor layer 120, wherein the doping concentration of the charge storage layer 130 is higher than that of the first semiconductor layer 110;

[0020] The first groove portion 140 and the second groove portion 140a penetrate the second semiconductor layer 120, extend to the first semiconductor layer 110, and are spaced a certain distance apart from each other;

[0021] The emitter 150 is formed on the second semiconductor layer 120;

[0022] The third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a are formed between the first groove portion 140 and the second groove portion 140a, and are in contact with the first groove portion 140 and the second groove portion 140a;

[0023] The first barrier layer 170 and the second barrier layer 170a are arranged in parallel below the first groove portion 140 and the second groove portion 140a, are spaced a certain distance apart from each other, and vertically intersect the parallel first groove portion 140 and the second groove portion, so as to prevent electrons from flowing from the third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a to the collector 180;

[0024] The third emission layer 160 ′, the fourth emission layer 160 ′a, the fifth emission layer 161 ′ and the sixth emission layer 161 ′a are formed directly above the first barrier layer 170 and the second barrier layer 170 a , respectively.

[0025] In one possible implementation, the maximum current characteristic is adjusted according to the distances between the third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a to the first barrier layer 170 and the second barrier layer 170a and the spacing distance between the first barrier layer 170 and the second barrier layer 170a.

[0026] In a possible implementation, the first groove portion 140 and the second groove portion 140a form insulating films 141, 141a on the inner walls; and the first gate 142 and the second gate 142a are buried by the insulating films 141, 141a and insulated from the second semiconductor layer 120 and the emission layer.

[0027] In a possible implementation, the emitter 150 forms an emitter contact 152 between the first trench portion 140 and the second trench portion 140 a and extends to the second semiconductor layer 120 .

[0028] In a possible implementation, the first barrier layer and the second barrier layer cover the bottom surface of the charge storage layer 130, the bottom surfaces of the first groove portion 140 and the second groove portion 140a, and part of the lower side surface of the first groove portion 140 and the second groove portion 140a.

[0029] In a possible implementation, the first barrier layer and the second barrier layer are spaced a certain distance from the bottom surface of the charge storage layer 130 and cover the bottom surfaces of the first groove portion 140 and the second groove portion 140a and part of the side surfaces of the first groove portion 140 and the second groove portion 140a.

[0030] In a possible implementation, it includes:

[0031] The first barrier layer and the second barrier layer are spaced a certain distance from the bottom surface of the charge storage layer, and are formed below the bottom surfaces of the first groove portion 140 and the second groove portion 140 a at a certain distance.

[0032] According to a third aspect of an embodiment of the present specification, there is provided a power semiconductor element processing device, wherein the power semiconductor element processing device is used to process the power semiconductor element mentioned above.

[0033] The embodiments of the present specification provide a power semiconductor element and a processing device thereof, wherein the power semiconductor element includes: a first semiconductor layer forming a field stop layer, a second semiconductor layer formed on the first semiconductor layer, a charge storage layer formed between the first semiconductor layer and the second semiconductor layer, and the doping concentration is higher than that of the first semiconductor layer and the first gate and the second gate; a first groove portion and a second groove portion penetrate the second semiconductor layer, extend to the first semiconductor layer, and are spaced a certain distance apart from each other; an emitter is formed above the second semiconductor layer; an emitter layer is formed between the first groove portion and the second groove portion, and is in contact with the first groove portion and the second groove portion; and the structure can enhance the soundness of the power semiconductor element by limiting the maximum current capacity of the short-circuit circuit, thereby preventing the power semiconductor element from being damaged before the protection circuit operates and the short-circuit current from flowing when a short circuit occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a first schematic diagram of a power semiconductor element provided by an embodiment of this specification;

[0035] Figure 2 is a second schematic diagram of a power semiconductor element provided by an embodiment of this specification;

[0036] Figure 3 is a third schematic diagram of a power semiconductor element provided by an embodiment of this specification;

[0037] Figure 4 is a fourth schematic diagram of a power semiconductor element provided by an embodiment of this specification;

[0038] Figure 5 is a fifth schematic diagram of a power semiconductor element provided by an embodiment of this specification;

[0039] Figure 6 is a sixth schematic diagram of a power semiconductor element provided by an embodiment of this specification;

[0040] Figure 7 is a seventh schematic diagram of a power semiconductor element provided by an embodiment of this specification;

[0041] Figure 8 is an eighth schematic diagram of a power semiconductor element provided by an embodiment of this specification;

[0042] Fig. 9 is a ninth schematic diagram of a power semiconductor element provided by an embodiment of this specification;

[0043] Fig.10 is a tenth schematic diagram of a power semiconductor element provided by an embodiment of this specification;

[0044] Fig.11 is an eleventh schematic diagram of a power semiconductor element provided by an embodiment of this specification;

[0045] Fig.12 This is the twelfth schematic diagram of a power semiconductor element provided by an embodiment of this specification. DETAILED DESCRIPTION

[0046] Many specific details are described in the following description to facilitate a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of this specification, so this specification is not limited to the specific implementation disclosed below.

[0047] The terms used in one or more embodiments of this specification are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of this specification. The singular forms of "a" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0048] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of this specification, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0049] According to a first aspect of an embodiment of the present specification, a power semiconductor element is provided, the power semiconductor element comprising a first semiconductor layer 110 forming a field stop layer 111, a second semiconductor layer 120 formed on the first semiconductor layer 110, a charge storage layer 130 formed between the first semiconductor layer 110 and the second semiconductor layer 120, and having a higher doping concentration than the first semiconductor layer 110 and a first gate 142 and a second gate 142a; a first groove portion 140 and a second groove portion 140a penetrate the second semiconductor layer 120, extend to the first semiconductor layer 110, and are spaced a certain distance apart from each other; an emitter 150 is formed in the second semiconductor layer 120 0; the first emission layer 160 and the second emission layer 160a are formed between the first groove portion 140 and the second groove portion 140a, and are in contact with the first groove portion 140 and the second groove portion 140a; the first barrier layer 170 and the second barrier layer 170a are arranged in parallel below the first groove portion 140 and the second groove portion 140a, are spaced a certain distance apart from each other, and are perpendicularly intersected with the first groove portion 140 and the second groove portion 140a, thereby preventing electrons from flowing from the first emission layer 160 and the second emission layer 160a to the collector 180; the collector 180 is connected to the collector layer 181 formed below the first semiconductor layer 110.

[0050] like Figures 1 to 5 As shown, in the embodiment of the present invention, the power semiconductor element 100 may be formed of a silicon substrate, on the surface of which a gate wiring and an emitter 150 may be formed.

[0051] Specifically, the power semiconductor element 100 may be formed into a first semiconductor layer 110 coated with a low-concentration first conductive type n-type dopant; for example, the coating concentration of the n-type dopant may be 10 13 ~10 16 / cm 3 In view of the coating concentration of the n-type dopant, the first semiconductor layer 110 can be called an n-type drift layer. Further, the first semiconductor layer 110 can sequentially form a field stop layer 111 (fields to player) and a collector layer 181 (collector layer) under the n-type base layer, and a collector electrode 180 can be further formed under the collector layer 181. The field stop layer 111 can be a layer coated with an n-type dopant, and the concentration of the n-type dopant coated thereon can be higher than the concentration of the n-type dopant of the first semiconductor layer 110, and the dopant concentration can be 10 14 ~10 18 / cm 3That is, the first semiconductor layer 110 is a low-concentration n-type semiconductor layer as a drift layer, and in the off state, most of the collector-emitter voltage is introduced to the first semiconductor layer 110, and the field stop layer 111 suppresses the expansion of the depletion layer when a reverse voltage is applied.

[0052] In this way, the field stop layer 111 can obtain a higher breakdown voltage by only passing through a shorter drift region, thereby improving the forward operation characteristics. Further, the semiconductor element 100 can form a second semiconductor layer 120 below the first semiconductor layer 110. The second semiconductor layer 120 can be a region coated with a p-type dopant, and the concentration of the p-type dopant can be 10 15 ~10 19 / cm 3 or so; when considering the coating concentration of the P-type dopant, it can be P0 or P+. Furthermore, in order to accumulate charges between the first semiconductor layer 110 and the second semiconductor layer 120, a charge storage layer (Carrier Storage) 130 coated with an n-type dopant can be formed, and its concentration is higher than the concentration of the dopant in the first semiconductor layer 110. That is, the charge storage layer 130 is arranged between the first semiconductor layer 110 and the second semiconductor layer 120. When the element is in the on state, holes can pass through the second semiconductor layer 120, hindering the flow to the emitter, thereby increasing the carrier concentration of the first semiconductor layer 110 directly below the charge storage layer 130, thereby achieving the purpose of reducing the overall voltage. The first groove portion 140 and the second groove portion 140a can penetrate the second semiconductor layer 120 and the charge storage layer 130 and extend to the first semiconductor layer 110.

[0053] Further, the first groove portion 140 and the second groove portion 140a may be spaced a certain distance apart from each other to form parallel stripes. The first groove portion 140 and the second groove portion 140a may form insulating films 141, 141a on the inner walls, respectively. The first groove portion 140 and the second groove portion 140a may form a first gate 142 and a second gate 142a, which are buried by the insulating films 141, 141a, and are insulated from the second semiconductor layer 120 and the first emission layer 160 and the second emission layer 160a.

[0054] Furthermore, the second semiconductor layer 120 and the first and second trenches 140 and 140a may form a gate wiring and an emitter 150 together with the insulating film 151. The emitter 150 may form an emitter contact 152 extending to the second semiconductor layer 120 between the first and second trenches 140 and 140a.

[0055] Further, the insulating film 151 may be formed in other regions except the emission contact 152 region, so that the first gate 142 and the second gate 142a of the first groove portion 140 and the second groove portion 140a are electrically separated from the emitter 150. The first emission layer 160 and the second emission layer 160a may be formed on both sides of the emission contact 152 as the center, that is, they may be formed in the second semiconductor layer 120, and they are in contact with the first groove portion 140 and the second groove portion 140a divided by the emission contact 152. The first emission layer 160 and the second emission layer 160a may be formed between the first groove portion 140 and the second groove portion 140a parallel to each other, and have a square shape of a certain size. The first emission layer 160 and the second emission layer 160a may be n-type emission layers coated with n-type dopants. The first emission layer 160 and the second emission layer 160a may be formed in the space between the first barrier layer 170 and the second barrier layer 170a which are spaced apart and parallel to each other, that is, they may be formed directly above the space between the first barrier layer 170 and the second barrier layer 170a. The length of the first emission layer 160 and the second emission layer 160a may be equal to but not limited to the distance W1 between the first barrier layer 170 and the second barrier layer 170a; as required, it may be less than or greater than the distance W1 between the first barrier layer 170 and the second barrier layer 170a. The first barrier layer 170 and the second barrier layer 170a, as a component that hinders the flow of electrons from the first emission layer 160 and the second emission layer 160a to the collector 180, may be composed of a P+ type carrier coated with a high concentration of p-type dopant. The first barrier layer 170 and the second barrier layer 170a may be disposed below the charge storage layer 130 and the first groove portion 140 and the second groove portion 140a. At this time, the first barrier layer 170 and the second barrier layer 170a can wrap the charge storage layer 130 and the bottom of the first groove portion 140 and the second groove portion 140a. That is, the first barrier layer 170 and the second barrier layer 170a can cover the bottom surface of the charge storage layer 130, the bottom surface of the first groove portion 140 and the second groove portion 140a, and cover part of the lower side surface of the first groove portion 140 and the second groove portion 140a.

[0056] Furthermore, if Figure 6 As shown, the third barrier layer 170' and the second barrier layer may be spaced a certain distance from the bottom surface of the charge storage layer 130, and cover the bottom surfaces of the first groove portion 140 and the second groove portion 140a, and part of the lower side surfaces of the first groove portion 140 and the second groove portion 140a. Figure 7 As shown, the fourth barrier layer 170 ″ and the second barrier layer may be formed below the bottom surfaces of the first trench portion 140 and the second trench portion 140 a at a certain distance.

[0057] Reference Figures 1 to 5The first barrier layer 170 and the second barrier layer 170a may intersect the first groove portion 140 and the second groove portion 140a perpendicularly and be spaced a certain distance W1 from each other, forming a parallel band shape. Further, the first barrier layer 170 and the second barrier layer 170a may pass through an area equal to the distance W1 between them, so that electrons flow from the first emission layer 160 and the second emission layer 160a to the collector layer 181. At the same time, the collector layer 181 may be a p+ layer coated with a p-type dopant, and the concentration of the coated p-type dopant may be 10 17 ~10 21 / cm 3 The operation process of the power semiconductor element 100 in one embodiment of the present invention is described below. When a voltage is applied to the first gate 142 and the second gate 142a, the first emission layer 160 and the second emission layer 160a emit electrons to the first semiconductor layer 110 through the channel; thereafter, when the conductivity changes after the hole injection in the p+ collector layer 181, the insulated gate bipolar transistor (IGBT) is operated. At this time, the electron flow injected from the first emission layer 160 and the second emission layer 160a flowing into the collector layer 181 is intercepted and blocked by the first barrier layer 170 and the second barrier layer 170a formed under the first groove portion 140 and the second groove portion 140a.

[0058] Furthermore, since the flow of electrons is hindered by the first barrier layer 170 and the second barrier layer 170a, the electrons flow through the channel formed by the spacing between the first barrier layer 170 and the second barrier layer 170a, thereby limiting the amount of current that can flow. Therefore, due to the limitation of the size of the first emission layer 160 and the second emission layer 160a, and the limitation of the spacing distance W1 between the first barrier layer 170 and the second barrier layer 170a that hinders the flow of electrons, the maximum current capacity when a short circuit occurs can be limited, thereby increasing the tolerance when a short circuit occurs, that is, the bearing capacity. Further, by adjusting the size of the first emission layer 160 and the second emission layer 160a in the length direction and the spacing distance W1 between the first barrier layer 170 and the second barrier layer 170a, the required maximum current capacity can be adjusted. Figures 8 to 12 FIG. 1 is a diagram illustrating a power semiconductor device according to another embodiment of the present invention. First, the same components are not described in detail, and the same reference numerals are used for the same components.

[0059] Reference Figures 8 to 12In the second embodiment of the present invention, the power semiconductor element 100' comprises: a first semiconductor layer 110 with a field stop layer 111 formed below; a second semiconductor layer 120 formed on the first semiconductor layer 110; and a charge storage layer 130 formed between the first and second semiconductor layers 110, 120, and having a higher doping concentration than the first semiconductor layer 110. Furthermore, in the second embodiment, the power semiconductor element 100' comprises a gate 142, which can penetrate the second semiconductor layer 120 and extend to the first semiconductor layer 110; a first groove portion 140, namely a second groove portion 140a, which are spaced a certain distance apart from each other and are in the shape of parallel strips. Further, the power semiconductor element 100' in the second embodiment may form an emitter 150 formed on the second semiconductor layer 120; a third emitter layer 160', a fourth emitter layer 160'a, a fifth emitter layer 161' and a sixth emitter layer 161'a formed on the second semiconductor layer 120 and in contact with the first trench portion 140 and the second trench portion 140a between the first trench portion 140 and the second trench portion 140a. Further, the power semiconductor element 100' in the second embodiment may form a first barrier layer 170 and a second barrier layer 170a formed under the first trench portion 140 and the second trench portion 140a. The first barrier layer 170 and the second barrier layer 170a may cover the bottom surface of the charge storage layer 130, the bottom surfaces of the first trench portion 140 and the second trench portion 140a, and may cover a portion of the lower side surface of the first trench portion 140 and the second trench portion 140a.

[0060] Further, the third barrier layer 170', referring to Figure 6 The second barrier layer may be spaced apart from the bottom surface of the charge storage layer 130 by a certain distance, and may cover the bottom surfaces of the first and second groove portions 140 and 140 a , and a portion of the lower side surfaces of the first and second groove portions 140 and 140 a .

[0061] Further, the fourth barrier layer 170", referring to Figure 7The first barrier layer 170 and the second barrier layer 170a may be formed below the bottom surface of the first groove portion 140 and the second groove portion 140a at a certain distance. The first barrier layer 170 and the second barrier layer 170a may intersect perpendicularly with the first groove portion 140 and the second groove portion 140a which are parallel to each other. The first barrier layer 170 and the second barrier layer 170a may be spaced a certain distance W1 from each other and be in the shape of parallel bands. The first barrier layer 170 and the second barrier layer 170a hinder the flow of electrons injected from the third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a in the process of flowing to the collector 180. The electrons injected from the third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a by the first barrier layer 170 and the second barrier layer 170a can flow to the collector layer 181 through an area equal to the distance W1 between each other.

[0062] Further, the power semiconductor element 100' in the second embodiment may form a collector 180, which contacts the collector layer 181 formed below the first semiconductor layer 110. The power semiconductor element 100' in the second embodiment of the present invention has a third emission layer 160', a fourth emission layer 160'a, a fifth emission layer 161' and a sixth emission layer 161'a, which have certain differences from the above-mentioned embodiments. The third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a in the second embodiment may be an n-type emission layer coated with an n-type dopant, and may be formed in the region between the first groove portion 140 and the second groove portion 140a divided by the emission contact 152.

[0063] Further, the third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a in the second embodiment can be formed in the second semiconductor layer 120 at intervals and in contact with the first groove portion 140 and the second groove portion 140a between the first groove portion 140 and the second groove portion 140a. That is, a pair of emission layers 160', 160'a can be formed in a partial region in a direction parallel to the first groove portion 140 and the second groove portion 140a, and another pair of emission layers 161', 161'a can be formed.

[0064] Further, the third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a which are spaced apart from each other may be formed directly above the first barrier layer 170 and the second barrier layer 170a, respectively. That is, the third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a in the second embodiment of the present invention may be formed in the upper region of the first barrier layer 170 and the second barrier layer 170a, respectively, and they intersect vertically below the first groove portion 140 and the second groove portion 140a, thereby hindering the flow of electrons. There is a certain difference in the structure of the third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a in the second embodiment and the first emission layer 160 and the second emission layer 160a in the first embodiment which are formed in the area just above the gap between the first barrier layer 170 and the second barrier layer 170a. In this way, the electrons injected from the third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a at the two side ends are blocked from moving by the first barrier layer 170 and the second barrier layer 170a formed below, thereby hindering the flow.

[0065] Furthermore, when electrons move through the channel formed by the spacing distance W1 between the first barrier layer 170 and the second barrier layer 170a, the channel resistance increases, thereby hindering the flow of electrons. Therefore, when a short circuit occurs, the maximum current capacity can be limited by the distance from the third emission layer 160', the fourth emission layer 160'a, the fifth emission layer 161' and the sixth emission layer 161'a to the channel between the first barrier layer 170 and the second barrier layer 170a, and the spacing distance W1 between the first barrier layer 170 and the second barrier layer 170a, thereby increasing the tolerance (or bearing capacity) during a short circuit. Therefore, when a short circuit occurs, the soundness of the power semiconductor element can be enhanced by limiting the structure of the maximum current capacity of the short-circuit circuit, so as to ensure that the power semiconductor element is not damaged and that a short-circuit current flows before the protection circuit is operated. Furthermore, by improving the soundness of the power semiconductor element, the time required to start the protection circuit during a short circuit can be increased.

[0066] The embodiments of the present specification also provide a power semiconductor element processing device, which is used to process the power semiconductor element mentioned above.

[0067] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of this specification are not limited by the order of the actions described, because according to the embodiments of this specification, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the embodiments of this specification.

[0068] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0069] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The optional embodiments do not describe all the details in detail, nor do they limit the invention to only the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of the embodiments of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of this specification, so that technicians in the relevant technical field can well understand and use this specification. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. A power semiconductor element, characterized in that: include: A first semiconductor layer (110) forming a field stop layer (111), a second semiconductor layer (120) formed on the first semiconductor layer (110), a charge accumulation layer (130) formed between the first semiconductor layer (110) and the second semiconductor layer (120), and a doping concentration of the charge accumulation layer (130) being higher than a doping concentration of the first semiconductor layer (110); The first groove portion (140) and the second groove portion (140a) penetrate the second semiconductor layer (120), extend to the first semiconductor layer (110), and are spaced a certain distance apart from each other; An emitter (150) is formed above the second semiconductor layer (120); A first emission layer (160) and a second emission layer (160a) are formed between the first groove portion (140) and the second groove portion (140a), and are in contact with the first groove portion (140) and the second groove portion (140a); The first barrier layer (170) and the second barrier layer (170a) are arranged in parallel below the first groove portion (140) and the second groove portion (140a), are spaced a certain distance apart from each other, and are perpendicularly intersected with the first groove portion (140) and the second groove portion (140a), thereby preventing electrons from flowing from the first emission layer (160) and the second emission layer (160a) to the collector (180); The collector electrode (180) is connected to a collector layer (181) formed below the first semiconductor layer (110); The first emission layer (160) and the second emission layer (160a) are respectively formed directly above the space separated by the first barrier layer (170) and the second barrier layer (170a); The maximum current amount is adjusted according to the length dimensions of the first emission layer (160) and the second emission layer (160a) and the spacing distance between the first barrier layer (170) and the second barrier layer (170a).

2. The power semiconductor element according to claim 1, characterized in that: The first groove part (140) and the second groove part (140a) form an insulating film (141, 141a) on the inner wall; and a first gate (142) and a second gate (142a) are buried by the gate insulating film (141, 141a) and insulated from the second semiconductor layer (120) and the emission layer.

3. The power semiconductor element according to claim 1, characterized in that: The emitter (150) forms an emitter contact (152) between the first groove portion (140) and the second groove portion (140a) and extends to the second semiconductor layer (120).

4. The power semiconductor element according to claim 1, characterized in that: The first barrier layer and the second barrier layer are formed on the bottom surface of the charge storage layer (130), the bottom surfaces of the first groove portion (140) and the second groove portion (140a), and part of the lower side surfaces of the first groove portion (140) and the second groove portion (140a).

5. The power semiconductor element according to claim 1, characterized in that: include: The first barrier layer and the second barrier layer are spaced a certain distance from the bottom surface of the charge storage layer (130) and cover the bottom surfaces of the first groove portion (140) and the second groove portion (140a) and part of the side surfaces of the first groove portion (140) and the second groove portion (140a).

6. The power semiconductor element according to claim 1, characterized in that: include: The first barrier layer and the second barrier layer are spaced a certain distance from the bottom surface of the charge storage layer, and are formed below the bottom surfaces of the first groove portion (140) and the second groove portion (140a) at a certain distance.

7. A power semiconductor element, characterized in that: include: A first semiconductor layer (110) forming a field stop layer (111), a second semiconductor layer (120) formed on the first semiconductor layer (110), a charge accumulation layer (130) formed between the first semiconductor layer (110) and the second semiconductor layer (120), and a doping concentration of the charge accumulation layer (130) being higher than a doping concentration of the first semiconductor layer (110); The first groove portion (140) and the second groove portion (140a) penetrate the second semiconductor layer (120), extend to the first semiconductor layer (110), and are spaced a certain distance apart from each other; An emitter (150) is formed above the second semiconductor layer (120); A third emission layer (160'), a fourth emission layer (160'a), a fifth emission layer (161') and a sixth emission layer (161'a) are formed between the first groove portion (140) and the second groove portion (140a), and are in contact with the first groove portion (140) and the second groove portion (140a); The first barrier layer (170) and the second barrier layer (170a) are arranged in parallel below the first groove portion (140) and the second groove portion (140a), are spaced a certain distance apart from each other, and are perpendicularly intersected with the parallel first groove portion (140) and the second groove portion, thereby preventing electrons from flowing from the third emission layer (160'), the fourth emission layer (160'a), the fifth emission layer (161') and the sixth emission layer (161'a) to the collector (180); The third emission layer (160'), the fourth emission layer (160'a), the fifth emission layer (161') and the sixth emission layer (161'a) are respectively formed directly above the first barrier layer (170) and the second barrier layer (170a); The characteristic of adjusting the maximum current amount according to the distance between the third emission layer (160'), the fourth emission layer (160'a), the fifth emission layer (161') and the sixth emission layer (161'a) to the first barrier layer (170) and the second barrier layer (170a) and the spacing distance between the first barrier layer (170) and the second barrier layer (170a).

8. The power semiconductor element according to claim 7, characterized in that: The first groove part (140) and the second groove part (140a) form an insulating film (141, 141a) on the inner wall; and a first gate (142) and a second gate (142a) are buried by the gate insulating film (141, 141a) and insulated from the second semiconductor layer (120) and the emission layer.

9. The power semiconductor element according to claim 7, characterized in that: The emitter (150) forms an emitter contact (152) between the first groove portion (140) and the second groove portion (140a) and extends to the second semiconductor layer (120).

10. The power semiconductor element according to claim 7, characterized in that: The first barrier layer and the second barrier layer are formed on the bottom surface of the charge storage layer (130), the bottom surfaces of the first groove portion (140) and the second groove portion (140a), and part of the lower side surfaces of the first groove portion (140) and the second groove portion (140a).

11. The power semiconductor element according to claim 7, characterized in that: include: The first barrier layer and the second barrier layer are spaced a certain distance from the bottom surface of the charge storage layer (130) and cover the bottom surfaces of the first groove portion (140) and the second groove portion (140a) and part of the side surfaces of the first groove portion (140) and the second groove portion (140a).

12. The power semiconductor element according to claim 7, characterized in that: include: The first barrier layer and the second barrier layer are spaced a certain distance from the bottom surface of the charge storage layer, and are formed below the bottom surfaces of the first groove portion (140) and the second groove portion (140a) at a certain distance.

13. A power semiconductor element processing device, characterized in that: The power semiconductor element processing device is used for processing the power semiconductor element according to any one of claims 1 to 12.

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