Three-phase e-type hybrid-level dual-output integrated converter and carrier pwm modulation method thereof

Abstract

The application discloses a three-phase E-type hybrid level double-output integrated converter and a carrier PWM modulation method thereof, and belongs to the technical field of power electronic conversion devices. The three-phase E-type hybrid level double-output integrated converter comprises one DC input power supply, two capacitors on the DC input side, 15 switch modules, and one set of three-phase inductive load on each output end of the bridge arm of each phase. The carrier PWM modulation method with added DC offset and zero sequence component is given for the proposed converter. Two sets of modulation waves with added DC offset and zero sequence component are compared with anti-phase stacked carriers respectively. According to the switch state and the comparison result, the logic operation for generating the driving signals of each switch module is derived. One set of DC input voltage is converted into three-level AC voltage on the upper end and two-level AC voltage on the lower end through the inverter circuit, and the frequency and amplitude of the three-phase AC voltage can be adjusted. The three-phase E-type hybrid level double-output integrated converter can be widely applied to the double-motor driving application scene of one master and one slave, and has the advantages of reasonable structure, scientific modulation method, outstanding performance and the like.

Description

Technical Field

[0001] This invention belongs to the technical field of power electronic conversion devices, and particularly relates to a three-phase E-type hybrid level dual-output integrated converter and its carrier PWM modulation method. Background Technology

[0002] An inverter, as a converter that directly converts direct current (DC) to alternating current (AC), can power AC loads. However, it can only convert DC to a single three-phase AC output. With the widespread use and development of motor drives in industrial production and daily life, inverters with only one output are gradually becoming insufficient for applications requiring dual AC power, such as wind power systems, electric vehicles, and rail locomotive traction. Much research is increasingly focusing on how to use a single power converter to power multiple electrical devices.

[0003] Currently, three-phase three-level dual-output converters have seen some development. In applications where dual motors must be controlled independently, integrated three-level dual-output converters offer the advantage of low harmonic content. However, in some dual-motor drive scenarios requiring only one master and one slave motor, such as scraper conveyors, hybrid-level dual-output converters are more suitable than three-level dual-output converters. Therefore, this paper proposes a three-phase E-type hybrid-level dual-output integrated converter and its carrier PWM modulation method. The hybrid level retains the advantages of three-level control of the main motor while also meeting the engineering requirements of the auxiliary motor with two levels, further reducing size and cost compared to integrated three-level dual-output converters. The proposed three-phase E-type hybrid-level dual-output integrated converter has a higher DC link voltage utilization rate and lower voltage stress on the switching transistors. The carrier PWM modulation method adds DC offset and zero-sequence components to the modulation wave. This modulation method is simple to implement, has lower harmonic distortion rate, and higher efficiency. To date, there are no literature reports or practical applications of three-phase E-type hybrid-level dual-output integrated converters and their carrier PWM modulation methods. Summary of the Invention

[0004] The purpose of this invention is to propose a small-sized, low-cost, and structurally reasonable three-phase E-type hybrid-level dual-output integrated converter for dual-motor drive applications with one master and one slave, from the perspective of saving costs and reducing converter size; and to provide a scientific, reasonable, highly applicable, and effective modulation method.

[0005] To achieve the above objectives, the specific technical solution of the three-phase E-type hybrid-level dual-output integrated converter and its carrier PWM modulation method of the present invention is as follows:

[0006] A three-phase E-type mixed-level dual-output integrated converter, characterized in that: it includes a capacitor C connected to the DC side. U C LPhase A, Phase B, and Phase C bridge arms, each phase bridge arm consists of 5 switching modules S 1x ~S 5x Composition, where x∈{a, b, c};

[0007] Each of the switching modules consists of an insulated gate bipolar transistor T. kx With a diode D connected in antiparallel kx Composition, symbol T kx and symbol D kx subscript symbol k x This indicates the switch module to which it belongs, where x∈{a, b, c}, k∈{1, 2, 3, 4, 5}; the switch module S kx Diode D kx The anode of the diode is connected to the emitter of the insulated-gate bipolar transistor Tkx, and the diode D is connected to the emitter of the insulated-gate bipolar transistor Tkx. kx Anode and Insulated Gate Bipolar Transistor T kx The point where the emitters are connected is defined as the switching module S. kx The emitter of the diode D kx Cathode and Insulated Gate Bipolar Transistor T kx The collector of the diode is connected, and the diode D is connected to the collector of the diode. kx Cathode and Insulated Gate Bipolar Transistor T kx The point where the collectors are connected is defined as the switching module S. kx The collectors of the inverter are given by the following: x∈{a,b,c}, k∈{1,2,3,4,5}; phase A arm has two output terminals, namely upper output terminal A1 and lower output terminal A2; phase B arm has two output terminals, namely upper output terminal B1 and lower output terminal B2; phase C arm has two output terminals, namely upper output terminal C1 and lower output terminal C2; the three upper output terminals A1, B1 and C1 together form inverter stage 1; the three lower output terminals A2, B2 and C2 together form inverter stage 2; the three-phase load driven by inverter stage 1 is Z. LA1 Z LB1 Z LC1 The three-phase load driven by inverter stage 2 is Z. LA2 Z LB2 Z LC2 ;

[0008] Two capacitors are connected to the DC side, and they are called capacitors C. U and capacitor C L Capacitor C U The positive terminal of the capacitor is connected to the positive terminal P of the DC bus, and the capacitor C U The negative terminal and capacitor C L The positive terminal is connected, and the capacitor C L The negative terminal of the capacitor is connected to the negative terminal N of the DC bus, and the capacitor C is connected to the negative terminal N of the DC bus. U The negative terminal and capacitor CL The point where the positive terminals are connected is defined as the DC neutral point O; the voltage between the positive terminal P and the negative terminal N is U. dc The potential of neutral point O is 0, and the voltage between the positive terminal P and neutral point O is U. dc / 2, the voltage between the neutral point O and the negative terminal N is U dc / 2;

[0009] Switch module S 1a The collector is connected to the positive terminal P of the DC bus, and the switching module S 1a emitter and switch module S 2a The collectors are connected, and the switching module S 2a emitter and switch module S 4a The collectors are connected, and the switching module S 4a emitter and switch module S 5a The collectors are connected, and the switching module S 5a The emitter is connected to the negative terminal N of the DC bus; the switch module S is connected. 1a emitter and switch module S 2a The point where the collectors of the circuit are connected is defined as the AC output terminal A1; the switching module S... 4a emitter and switch module S 5a The point where the collectors are connected is defined as the AC output terminal A2;

[0010] Switch module S 1b The collector is connected to the positive terminal P of the DC bus, and the switching module S 1b emitter and switch module S 2b The collectors are connected, and the switching module S 2b emitter and switch module S 4b The collectors are connected, and the switching module S 4b emitter and switch module S 5b The collectors are connected, and the switching module S 5b The emitter is connected to the negative terminal N of the DC bus; the switch module S is connected. 1b emitter and switch module S 2b The point where the collectors of the circuit are connected is defined as the AC output terminal B1; the switching module S... 4b emitter and switch module S 5b The point where the collectors are connected is defined as the AC output terminal B2;

[0011] Switch module S 1c The collector is connected to the positive terminal P of the DC bus, and the switching module S 1c emitter and switch module S 2c The collectors are connected, and the switching module S 2c emitter and switch module S4c The collectors are connected, and the switching module S 4c emitter and switch module S 5c The collectors are connected, and the switching module S 5c The emitter is connected to the negative terminal N of the DC bus; the switch module S is connected. 1c emitter and switch module S 2c The point where the collectors of the circuit are connected is defined as the AC output terminal C1; the switching module S... 4c emitter and switch module S 5c The point where the collectors are connected is defined as the AC output terminal C2;

[0012] Switch module S 3a The collector of the switch module S is connected to the DC neutral point 0. 3a emitter and switch module S 2a The emitters are connected;

[0013] Switch module S 3b The collector of the switch module S is connected to the DC neutral point 0. 3b emitter and switch module S 2b The emitters are connected;

[0014] Switch module S 3c The collector of the switch module S is connected to the DC neutral point 0. 3c emitter and switch module S 2c The emitters are connected;

[0015] Three-phase resistive load Z LA1 Z LB1 Z LC1 One end is connected to output terminals A1, B1, and C1 respectively, and the three-phase resistive-inductive load Z LA1 Z LB1 Z LC1 The other end is connected together; three-phase resistive-inductive load Z LA2 Z LB2 Z LC2 One end is connected to output terminals A2, B2, and C2 respectively, and the three-phase resistive-inductive load Z LA2 Z LB2 Z LC2 The other end is connected together.

[0016] This invention also provides a carrier PWM modulation method for a three-phase E-type mixed-level dual-output integrated converter, which includes the following steps:

[0017] Step 1: Set the number of switching modules and appropriate switching states for the A, B, and C phase bridge arms of the three-phase E-type mixed-level dual-output integrated converter. For each phase bridge arm of the three-phase E-type mixed-level dual-output integrated converter, there is a constraint relationship between the output potential of the upper output terminal and the lower output terminal, and they are identical. For the A phase bridge arm, the upper output terminal A1 output potential V... A1 ≥ Output potential V at lower output terminal A2 A2 And the output potential V of A1 A1 For U dc / 2, Lower output A2 output potential V A2 Cannot be U dc / 2, the A-phase bridge arm, the B-phase bridge arm, and the C-phase bridge arm each have 5 switching modules and 5 reasonable switching states. For the A-phase bridge arm:

[0018] Operating state 1: Switch module S 1a Switch module S 3a Switch module S 4a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 For U dc / 2, Lower output A2 output potential V A2 =0;

[0019] Operating state 2: Switch module S 1a Switch module S 4a Switch module S 5a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 For U dc / 2, Lower output A2 output potential V A2 For -U dc / 2;

[0020] Operating state 3: Switch module S 2a Switch module S 3a Switch module S 4a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 When the value is 0, the output potential V of A2 is 0. A2 =0;

[0021] Operating status 4: Switch module S 2a Switch module S 3a Switch module S 5a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 When the value is 0, the output potential V of A2 is 0. A2 For -U dc / 2;

[0022] Operating Status 5: Switch Module S 2aSwitch module S 4a Switch module S 5a When the circuit is turned on, the output potential V at the upper output terminal A1 is... A1 For -U dc / 2, Lower output A2 output potential V A2 For -U dc / 2;

[0023] The states of the B-phase bridge arm switches and the C-phase bridge arm switches are similar to those of the A-phase bridge arm switches.

[0024] Step 2: Employ carrier PWM modulation with added DC offset and zero-sequence component, using two triangular carriers u c1 and u c2 It adopts an anti-phase stacking method, that is, two triangular carriers u c1 u c2 Their phases differ by 180°, but their frequencies are the same, and u c1 The variation range is 0 to 1, u c2 The range of variation is -1 to 0;

[0025] Define two sets of sinusoidal modulation waves u x1 and u x2 Where x∈{A, B, C}, the first group of sinusoidal modulation waves u x1 The expression is:

[0026]

[0027] The second group of sinusoidal modulation waves u x2 The expression is:

[0028]

[0029] Where m1 and m2 are the modulation intensities of the first and second modulated waves, respectively, and the values ​​of m1 and m2 both range from 0 to 1.15; ω1, ω2, These are the angular frequency and initial phase angle of the first and second modulated waves, respectively. The value range is from -π / 2 to π / 2; the periods of the two sets of modulation waves are set as T1 and T2 respectively, that is, T1=2π / ω1 and T2=2π / ω2;

[0030] Define u max1 u min1 and u mid1 These represent the maximum, minimum, and median values ​​of the first group of modulated waves, u. max2 u min2 and u mid2 These represent the maximum, minimum, and median values ​​of the second group of modulated waves, and the maximum, minimum, and median values ​​of the first group of modulated waves, respectively. max1 umin1 and u mid1 The expressions are as follows:

[0031]

[0032] The maximum, minimum, and median values ​​of the second group of modulated waves, u max2 u min2 and u mid2 The expressions are as follows:

[0033]

[0034] Define u 01 and u 02 The zero-sequence components of the superposition of the first and second sinusoidal modulated waves, respectively, u 01 and u 02 The expressions are as follows:

[0035]

[0036]

[0037] Using two sets of modulation waves mx1 and u mx2 Two sets of three-level AC outputs are controlled respectively, where x∈{A, B, C}, and the first set of modulation wave u mx1 The expression is:

[0038]

[0039] The second group of modulation waves u mx2 The expression is:

[0040]

[0041] Among them, U offset1 and U offset2 These are the DC offsets of the upper output modulated wave and the lower output modulated wave, respectively. offset1 The value range is from 0 to 1-m1 / 1.15, U offset2 The value range is from 0 to 1-m² / 1.15;

[0042] Modulated wave u mx1 u mx2 and two triangular carriers u respectively c1 u c2 Comparing the magnitudes determines the potentials v at the two output terminals. x1 v x2 Where x∈{A, B, C}, the specific comparison method is as follows:

[0043] ①If umx1 >u c1 v x1 For U dc / 2; if u mx1 ≤u c2 v x1 For -U dc / 2; if u c2 ≤u mx1 ≤u c1 v x1 =0;

[0044] ②If u mx2 >u c2 v x2 If u is 0; mx2 ≤u c2 v x2 For -U dc / 2;

[0045] Step 3: Define the line voltage amplitudes between phase A and phase B of the two sets of AC outputs as U. AB1 U AB2 AC output line voltage amplitude U AB1 U AB2 The relationship between the modulation intensities m1 and m2 of the two sets of sinusoidal modulated waves is as follows:

[0046]

[0047]

[0048] Step 4: Combining the analysis conclusions of Steps 1 to 3 and the 5 reasonable switching states, further analyze the logical operations of generating the drive signals for each switch module; a drive signal value of 1 indicates that the switch module is turned on; a drive signal value of 0 indicates that the switch module is turned off.

[0049] The first group of modulation waves u mx1 With carrier u c1 The comparison is performed, and based on the result, signal e1 is generated. The specific expression is as follows:

[0050]

[0051] The first group of modulation waves u mx1 With carrier u c2 The comparison is performed, and based on the comparison result, signal e2 is generated. The specific expression is as follows:

[0052]

[0053] The second group of modulation waves u mx2 With carrier u c1The comparison is performed, and based on the result, signal e3 is generated. The specific expression is as follows:

[0054]

[0055] The second group of modulation waves u mx2 With carrier u c2 The comparison is performed, and based on the result, signal e4 is generated. The specific expression is as follows:

[0056]

[0057] Signal e5 is generated from signals e1 and e2, expressed as:

[0058]

[0059] Where u represents the logical NOT operation on u, and the symbol “&” represents the logical AND operation;

[0060] Signal e6 is generated from signals e3 and e4, expressed as:

[0061]

[0062] Signal e5 generates signal e7, expressed as:

[0063]

[0064] Signal e6 generates signal e8, expressed as:

[0065]

[0066] Based on the signals e1 to e8 and the five reasonable switching states of the three-phase E-type mixed-level dual-output integrated converter, the five switching modules S of each phase bridge arm are analyzed. 1x ~S 5x drive signal s 1x ~s 5x Where x∈{a, b, c}:

[0067] ① The potential v at the upper output terminal x1 For U dc / 2, lower output terminal potential v x2 The voltage at the upper output terminal is 0; x1 For U dc / 2, lower output terminal potential v x2 For -U dc / 2, switch module S 1x When the circuit is turned on, analysis of the relationship between the switch state and the output potential at the output terminal shows that the switch module S... 1x drive signal s 1x The expression is:

[0068] s 1x =e1

[0069] ② The potential v at the upper output terminal x1 The lower output terminal potential v is 0. x2 The voltage at the upper output terminal is 0; x1 The lower output terminal potential v is 0. x2 For -U dc / 2; Upper output terminal potential v x1 For -U dc / 2, lower output terminal potential v x2 For -U dc / 2, switch module S 2x When the circuit is turned on, analysis of the relationship between the switch state and the output potential at the output terminal shows that the switch module S... 2x drive signal s 2x The expression is:

[0070]

[0071] The symbol “∨” represents the logical OR operation.

[0072] ③ The potential v at the upper output terminal x1 For U dc / 2, lower output terminal potential v x2 The voltage at the upper output terminal is 0; x1 The lower output terminal potential v is 0. x2 The voltage at the upper output terminal is 0; x1 The lower output terminal potential v is 0. x2 For -U dc / 2, switch module S 3x When the circuit is turned on, analysis of the relationship between the switch state and the output potential at the output terminal shows that the switch module S... 3x drive signal s 3x The expression is:

[0073]

[0074] ④ The potential v at the upper output terminal x1 For U dc / 2, lower output terminal potential v x2 The voltage at the upper output terminal is 0; x1 For U dc / 2, lower output terminal potential v x2 For -U dc / 2; Upper output terminal potential v x1 The lower output terminal potential v is 0. x2 The voltage at the upper output terminal is 0; x1 For -U dc / 2, lower output terminal potential v x2For -U dc / 2, switch module S 4x When the circuit is turned on, analysis of the relationship between the switch state and the output potential at the output terminal shows that the switch module S... 4x drive signal s 4x The expression is:

[0075] s 4x =e4&e7

[0076] ⑤ The potential v at the upper output terminal x1 For U dc / 2, lower output terminal potential v x2 For -U dc / 2; Upper output terminal potential v x1 The lower output terminal potential v is 0. x2 For -U dc / 2; Upper output terminal potential v x1 For -U dc / 2, lower output terminal potential v x2 For -U dc / 2, switch module S 5x When the circuit is turned on, analysis of the relationship between the switch state and the output potential at the output terminal shows that the switch module S... 5x drive signal s 5x The expression is:

[0077]

[0078] Step 5: Through steps 1 to 4, the drive signals of the 15 switching modules of the three-phase E-type mixed-level dual-output integrated converter can be obtained, and carrier PWM modulation can be completed to enable the three-phase E-type mixed-level dual-output integrated converter to output two sets of three-phase mixed-level AC outputs with adjustable frequency and amplitude.

[0079] The three-phase E-type hybrid-level dual-output integrated converter and its carrier PWM modulation method of the present invention have the following advantages:

[0080] 1. The present invention provides a three-phase E-type hybrid level dual-output integrated converter, which enables a set of DC input voltages to output two sets of three-phase AC voltages with adjustable frequency and amplitude through an inverter circuit. It has a simple structure, low cost, and wide range of applications.

[0081] 2. Compared to two-level converters, hybrid level converters have lower voltage stress on a single switch and the output waveform is closer to a sine wave; compared to three-level converters, they are more suitable for dual-motor drive applications with one master and one slave.

[0082] 3. The three-phase E-type hybrid level dual-output integrated converter of the present invention has a large DC link voltage utilization rate, and the switching devices are subjected to low voltage stress, with a simple structure and low cost;

[0083] 4. The carrier PWM modulation method used adds DC offset and zero-sequence component to the modulated wave, which is simple to implement, has lower harmonic distortion rate and higher efficiency, and is scientifically sound, highly applicable and has outstanding performance. Attached Figure Description

[0084] Figure 1 This is a topology diagram of a three-phase E-type hybrid-level dual-output integrated converter according to the present invention;

[0085] Figure 2 The schematic diagram is for switch state 1;

[0086] Figure 3 The schematic diagram is for switch state 2;

[0087] Figure 4 The schematic diagram is for switch state 3;

[0088] Figure 5 The schematic diagram is for switch state 4;

[0089] Figure 6 The schematic diagram is for switch state 5;

[0090] Figure 7 This is a schematic diagram comparing the modulated wave and the carrier wave;

[0091] Figure 8 The logic diagram for generating drive signals;

[0092] Figure 9 The line voltage V of the output inverter stage 1 of the upper group. a1b1 Waveform diagram;

[0093] Figure 10 Line voltage v a1b1 Plot the results of the Fourier analysis;

[0094] Figure 11 The line voltage V output of inverter stage 2 in the next group. a2b2 Waveform diagram;

[0095] Figure 12 Line voltage v a2b2 Plot the results of the Fourier analysis;

[0096] Figure 13 The output shows the three-phase load current waveform.

[0097] Figure 14 The following is a waveform diagram of the three-phase load current output. Detailed Implementation

[0098] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides an explanation of a three-phase E-type hybrid-level dual-output integrated converter and its carrier PWM modulation method.

[0099] Reference Figure 1 The present invention provides a three-phase E-type mixed-level dual-output integrated converter, comprising: a capacitor C connected to the DC side. U C L Phase A, Phase B, and Phase C bridge arms, each phase bridge arm consists of 5 switching modules S 1x ~S 5x The inverter is composed of three phases, where x∈{a, b, c}. Phase A has two output terminals, A1 and A2; Phase B has two output terminals, B1 and B2; Phase C has two output terminals, C1 and C2. The three upper output terminals A1, B1, and C1 together form inverter stage 1; the three lower output terminals A2, B2, and C2 together form inverter stage 2. The three-phase load of inverter stage 1 is Z. LA1 Z LB1 Z LC1 The three-phase load driven by inverter stage 2 is Z. LA2 Z LB2 Z LC2 ;

[0100] Each of the switching modules consists of an insulated gate bipolar transistor T. kx It consists of a diode Dkx connected in antiparallel, symbol T. kx and symbol D kx The subscript symbol kx indicates the switch module to which it belongs, where x∈{a, b, c}, k∈{1, 2, 3, 4, 5}; the switch module S kx Diode D kx Anode and Insulated Gate Bipolar Transistor T kx Connect the emitter of the diode to the diode D. kx Anode and Insulated Gate Bipolar Transistor T kx The point where the emitters are connected is defined as the switching module S. kx The emitter of the diode D kx Cathode and Insulated Gate Bipolar Transistor T kx The collector of the diode is connected, and the diode D is connected to the collector of the diode. kx Cathode and Insulated Gate Bipolar Transistor T kx The point where the collectors are connected is defined as the switching module S. kx The collector of, where x∈{a, b, c}, k∈{1, 2, 3, 4, 5};

[0101] Two capacitors are connected to the DC side, and they are called capacitors C. U and capacitor C L Capacitor C U The positive terminal of the capacitor is connected to the positive terminal P of the DC bus, and the capacitor C U The negative terminal and capacitor C L The positive terminal is connected, and the capacitor C L The negative terminal of the capacitor is connected to the negative terminal N of the DC bus, and the capacitor C is connected to the negative terminal N of the DC bus. U The negative terminal and capacitor C L The point where the positive terminals are connected is defined as the DC neutral point O; the voltage between the positive terminal P and the negative terminal N is U. dc The potential of neutral point O is 0, and the voltage between the positive terminal P and neutral point O is U. dc / 2, the voltage between the neutral point O and the negative terminal N is U dc / 2;

[0102] Switch module S 1a The collector is connected to the positive terminal P of the DC bus, and the switching module S 1a emitter and switch module S 2a The collectors are connected, and the switching module S 2a emitter and switch module S 4a The collectors are connected, and the switching module S 4a emitter and switch module S 5a The collectors are connected, and the switching module S 5a The emitter is connected to the negative terminal N of the DC bus; the switch module S is connected. 1a emitter and switch module S 2a The point where the collectors of the circuit are connected is defined as the AC output terminal A1; the switching module S... 4a emitter and switch module S 5a The point where the collectors are connected is defined as the AC output terminal A2;

[0103] Switch module S 1b The collector is connected to the positive terminal P of the DC bus, and the switching module S 1b emitter and switch module S 2b The collectors are connected, and the switching module S 2b emitter and switch module S 4b The collectors are connected, and the switching module S 4b emitter and switch module S 5b The collectors are connected, and the switching module S 5b The emitter is connected to the negative terminal N of the DC bus; the switch module S is connected. 1b emitter and switch module S 2b The point where the collectors of the circuit are connected is defined as the AC output terminal B1; the switching module S...4b emitter and switch module S 5b The point where the collectors are connected is defined as the AC output terminal B2;

[0104] Switch module S 1c The collector is connected to the positive terminal P of the DC bus, and the switching module S 1c emitter and switch module S 2c The collectors are connected, and the switching module S 2c emitter and switch module S 4c The collectors are connected, and the switching module S 4c emitter and switch module S 5c The collectors are connected, and the switching module S 5c The emitter is connected to the negative terminal N of the DC bus; the switch module S is connected. 1c emitter and switch module S 2c The point where the collectors of the circuit are connected is defined as the AC output terminal C1; the switching module S... 4c emitter and switch module S 5c The point where the collectors are connected is defined as the AC output terminal C2;

[0105] Switch module S 3a The collector of the switch module S is connected to the DC neutral point 0. 3a emitter and switch module S 2a The emitters are connected; switch module S 3b The collector of the switch module S is connected to the DC neutral point 0. 3b emitter and switch module S 2b The emitters are connected; switch module S 3c The collector of the switch module S is connected to the DC neutral point 0. 3c emitter and switch module S 2c The emitters are connected; the three-phase resistive-inductive load Z LA1 Z LB1 Z LC1 One end is connected to output terminals A1, B1, and C1 respectively, and the three-phase resistive-inductive load Z LA1 Z LB1 Z LC1 The other end is connected together; three-phase resistive-inductive load Z LA2 Z LB2 Z LC2 One end is connected to output terminals A2, B2, and C2 respectively, and the three-phase resistive-inductive load Z LA2 Z LB2 Z LC2 The other end is connected together.

[0106] like Figure 1As shown, by applying a reasonable drive signal to the switching module, the three-phase E-type hybrid level dual-output integrated converter of the present invention can realize the conversion of a single DC input voltage into two sets of three-phase AC voltages with adjustable frequency and amplitude.

[0107] Reference Figures 1-7 The present invention discloses a carrier PWM modulation method for a three-phase E-type hybrid-level dual-output integrated converter, comprising the following steps:

[0108] Step 1: Set the number of switching modules and appropriate switching states for the A, B, and C phase bridge arms of the three-phase E-type mixed-level dual-output integrated converter. For each phase bridge arm of the three-phase E-type mixed-level dual-output integrated converter, there is a constraint relationship between the output potential of the upper output terminal and the lower output terminal, and they are identical. For the A phase bridge arm, the upper output terminal A1 output potential V... A1 ≥ Output potential V at lower output terminal A2 A2 And the output potential V of A1 A1 For U dc / 2, Lower output A2 output potential V A2 Cannot be U dc / 2, the A-phase bridge arm, the B-phase bridge arm, and the C-phase bridge arm each have 5 switching modules and 5 reasonable switching states. For the A-phase bridge arm:

[0109] Operating state 1: Switch module S 1a Switch module S 3a Switch module S 4a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 For U dc / 2, Lower output A2 output potential V A2 =0, such as Figure 2 As shown;

[0110] Operating state 2: Switch module S 1a Switch module S 4a Switch module S 5a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 For U dc / 2, Lower output A2 output potential V A2 For -U dc / 2, as Figure 3 As shown;

[0111] Operating state 3: Switch module S 2a Switch module S 3a Switch module S 4a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 When the value is 0, the output potential V of A2 is 0. A2=0, such as Figure 4 As shown;

[0112] Operating status 4: Switch module S 2a Switch module S 3a Switch module S 5a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 When the value is 0, the output potential V of A2 is 0. A2 For -U dc / 2, as Figure 5 As shown;

[0113] Operating Status 5: Switch Module S 2a Switch module S 4a Switch module S 5a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 For -U dc / 2, Lower output A2 output potential V A2 For -U dc / 2, as Figure 6 As shown;

[0114] The states of the B-phase bridge arm switches and the C-phase bridge arm switches are similar to those of the A-phase bridge arm switches.

[0115] Step 2: Employ carrier PWM modulation with added DC offset and zero-sequence component, using two triangular carriers u c1 and u c2 It adopts an anti-phase stacking method, that is, two triangular carriers u c1 u c2 Their phases differ by 180°, but their frequencies are the same, and u c1 The variation range is 0 to 1, u c2 The variation range is -1 to 0; two carrier waves, such as Figure 7 As shown;

[0116] Define two sets of sinusoidal modulation waves u x1 and u x2 Where x∈{A, B, C}, the first group of sinusoidal modulation waves u x1 The expression is:

[0117]

[0118] The second group of sinusoidal modulation waves u x2 The expression is:

[0119]

[0120] Where m1 and m2 are the modulation intensities of the first and second modulated waves, respectively, and the values ​​of m1 and m2 both range from 0 to 1.15; ω1, ω2, These are the angular frequency and initial phase angle of the first and second modulated waves, respectively. The value range is from π / 2 to π / 2; the periods of the two sets of modulation waves are set as T1 and T2 respectively, that is, T1=2π / ω1 and T2=2π / ω2;

[0121] Define u max1 u min1 and u mid1 These represent the maximum, minimum, and median values ​​of the first group of modulated waves, u. max2 u min2 and u mid2 These represent the maximum, minimum, and median values ​​of the second group of modulated waves, and the maximum, minimum, and median values ​​of the first group of modulated waves, respectively. max1 u min1 and u mid1 The expressions are as follows:

[0122]

[0123] The maximum, minimum, and median values ​​of the second group of modulated waves, u max2 u min2 and u mid2 The expressions are as follows:

[0124]

[0125] Define u 01 and u 02 The zero-sequence components of the superposition of the first and second sinusoidal modulated waves, respectively, u 01 and u 02 The expressions are as follows:

[0126]

[0127]

[0128] Using two sets of modulation waves mx1 and u mx2 Two sets of three-level AC outputs are controlled respectively, where x∈{A, B, C}, and the first set of modulation wave u mx1 The expression is:

[0129]

[0130] The second group of modulation waves u mx2 The expression is:

[0131]

[0132] Among them, U offset1 and U offset2These are the DC offsets of the upper output modulated wave and the lower output modulated wave, respectively. offset1 The value range is from 0 to 1-m1 / 1.15, U offset2 The value range is from 0 to 1-m² / 1.15; the two sets of modulation waves are as follows: Figure 7 As shown;

[0133] Modulated wave u mx1 u mx2 and two triangular carriers u respectively c1 u c2 Comparing the magnitudes determines the potentials v at the two output terminals. x1 v x2 Where x∈{A, B, C}, the specific comparison method is as follows:

[0134] ①If u mx1 >u c1 v x1 For U dc / 2; if u mx1 ≤uc2,v x1 For -U dc / 2; if u c2 ≤u mx1 ≤u c1 v x1 The value is 0; the potential at the AC output terminal of inverter 1 is v. x1 like Figure 7 As shown;

[0135] ②If u mx2 >u c2 v x2 If u is 0; mx2 ≤u c2 v x2 For -U dc / 2; Inverter 2 AC output terminal potential v x2 like Figure 7 As shown;

[0136] Step 3: Define the line voltage amplitudes between phase A and phase B of the two sets of AC outputs as U. AB1 U AB2 AC output line voltage amplitude U AB1 U AB2 The relationship between the modulation intensities m1 and m2 of the two sets of sinusoidal modulated waves is as follows:

[0137]

[0138]

[0139] Step 4: Combining the analysis conclusions of Steps 1 to 3 and the 5 reasonable switching states, further analyze the logical operations of generating the drive signals for each switch module; a drive signal value of 1 indicates that the switch module is turned on; a drive signal value of 0 indicates that the switch module is turned off.

[0140] The first group of modulation waves u mx1 With carrier u c1 The comparison is performed, and based on the result, signal e1 is generated. The specific expression is as follows:

[0141]

[0142] The first group of modulation waves u mx1 With carrier u c2 The comparison is performed, and based on the comparison result, signal e2 is generated. The specific expression is as follows:

[0143]

[0144] The second group of modulation waves u mx2 With carrier u c1 The comparison is performed, and based on the result, signal e3 is generated. The specific expression is as follows:

[0145]

[0146] The second group of modulation waves u mx2 With carrier u c2 The comparison is performed, and based on the result, signal e4 is generated. The specific expression is as follows:

[0147]

[0148] Signal e5 is generated from signals e1 and e2, expressed as:

[0149]

[0150] in, This indicates a logical NOT operation on u, while the symbol "&" indicates a logical AND operation.

[0151] Signal e6 is generated from signals e3 and e4, expressed as:

[0152]

[0153] Signal e5 generates signal e7, expressed as:

[0154]

[0155] Signal e6 generates signal e8, expressed as:

[0156]

[0157] Based on the signals e1 to e8 and the five reasonable switching states of the three-phase E-type mixed-level dual-output integrated converter, the five switching modules S of each phase bridge arm are analyzed. 1x ~S 5x drive signal s 1x ~s 5x Where x∈{a, b, c}:

[0158] ① The potential v at the upper output terminal x1 For U dc / 2, lower output terminal potential v x2 The voltage at the upper output terminal is 0; x1 For U dc / 2, lower output terminal potential v x2 For -U dc / 2, switch module S 1x When the circuit is turned on, analysis of the relationship between the switch state and the output potential at the output terminal shows that the switch module S... 1x drive signal s 1x The expression is:

[0159] s 1x =e1

[0160] ② The potential v at the upper output terminal x1 The lower output terminal potential v is 0. x2 The voltage at the upper output terminal is 0; x1 The lower output terminal potential v is 0. x2 For -U dc / 2; Upper output terminal potential v x1 For -U dc / 2, lower output terminal potential v x2 For -U dc / 2, switch module S 2x When the circuit is turned on, analysis of the relationship between the switch state and the output potential at the output terminal shows that the switch module S... 2x drive signal s 2x The expression is:

[0161]

[0162] The symbol “∨” represents a logical OR operation;

[0163] ③ The potential v at the upper output terminal x1 For U dc / 2, lower output terminal potential v x2 The voltage at the upper output terminal is 0; x1 The lower output terminal potential v is 0. x2 The voltage at the upper output terminal is 0; x1 The lower output terminal potential v is 0.x2 For -U dc / 2, switch module S 3x When the circuit is turned on, analysis of the relationship between the switch state and the output potential at the output terminal shows that the switch module S... 3x drive signal s 3x The expression is:

[0164]

[0165] ④ The potential v at the upper output terminal x1 For U dc / 2, lower output terminal potential v x2 The voltage at the upper output terminal is 0; x1 For U dc / 2, lower output terminal potential v x2 For -U dc / 2; Upper output terminal potential v x1 The lower output terminal potential v is 0. x2 The voltage at the upper output terminal is 0; x1 For -U dc / 2, lower output terminal potential v x2 For -U dc / 2, switch module S 4x When the circuit is turned on, analysis of the relationship between the switch state and the output potential at the output terminal shows that the switch module S... 4x drive signal s 4x The expression is:

[0166]

[0167] ⑤ The potential v at the upper output terminal x1 For U dc / 2, lower output terminal potential v x2 For -U dc / 2; Upper output terminal potential v x1 The lower output terminal potential v is 0. x2 For -U dc / 2; Upper output terminal potential v x1 For -U dc / 2, lower output terminal potential v x2 For -U dc / 2, switch module S 5x When the circuit is turned on, analysis of the relationship between the switch state and the output potential at the output terminal shows that the switch module S... 5x drive signal s 5x The expression is:

[0168]

[0169] Based on the above analysis, the logic circuit for generating the power switch drive signal can be obtained, such as... Figure 8 As shown in the figure, the symbols This indicates a comparison operation. When the positive "+" input signal is greater than the negative "-" input signal, the output is a high level "1"; otherwise, the output is a low level "0".

[0170] Step 5: By following Steps 1 to 4, the drive signals of the 15 switching modules of the three-phase E-type mixed-level dual-output integrated converter can be obtained, and carrier PWM modulation is completed, so that the three-phase E-type mixed-level dual-output integrated converter outputs two sets of three-phase mixed-level AC outputs with adjustable frequency and amplitude.

[0171] To verify the effectiveness of the carrier PWM modulation method for a three-phase E-type hybrid-level dual-output integrated converter proposed in this invention, a simulation circuit was built using MATLAB / Simulink. The simulation parameters are as follows: DC link voltage 100V, DC link capacitance C... U =C L =500uF, carrier frequency is 10kHz, the first group of AC outputs is connected to a three-phase resistive-inductive load with a resistance of 30Ω and an inductance of 10mH; the second group of AC outputs is connected to a three-phase resistive-inductive load with a resistance of 30Ω and an inductance of 10mH; the modulation index m1 of the first group of modulation waves is 0.6 and the frequency is 50Hz; the modulation index m2 of the second group of modulation waves is 0.4 and the frequency is 150Hz.

[0172] Simulation results are as follows Figure 9-14 As shown, Figure 9 The line voltage V of the output inverter stage 1 of the upper group. a1b1 The waveform diagram shows that the load line voltage has five levels: 100V, 50V, 0V, -50V, and -100V. Figure 10 For line voltage v a1b1 The Fourier analysis results show that the fundamental component amplitude is 59.75V; Figure 11 The line voltage V of the output of the lower output inverter stage 2 a2b2 The waveform diagram shows that the load line voltage has three levels: 50V, 0V, and -50V. Figure 12 For line voltage v a2b2 The Fourier analysis results show that the fundamental component amplitude is 39.75V; Figure 13 The waveform of the three-phase load current at the upper output is shown. The fundamental amplitude is 1A and the frequency is 50Hz. Figure 14 The waveform of the three-phase load current at the lower output is shown. The fundamental amplitude is 0.64A and the frequency is 150Hz.

[0173] The simulation results above demonstrate that the carrier modulation method for a three-phase E-type hybrid-level dual-output integrated converter of the present invention enables the amplitude, phase, and frequency of the two sets of output voltages of the three-phase E-type hybrid-level dual-output integrated converter to be independently adjusted.

[0174] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A three-phase E-type mixed-level dual-output integrated converter, characterized in that, It includes the capacitor C connected on the DC side. U C L Phase A, Phase B, and Phase C bridge arms, each phase bridge arm consists of 5 switching modules S 1x ~S 5x Composition, where x∈{a, b, c}; Each of the switching modules consists of an insulated gate bipolar transistor T. kx With a diode D connected in antiparallel kx Composition, symbol T kx and symbol D kx The subscript symbol kx indicates the switch module to which it belongs, where x∈{a, b, c}, k∈{1, 2, 3, 4, 5}; the switch module S kx Diode D kx Anode and Insulated Gate Bipolar Transistor T kx Connect the emitter of the diode to the diode D. kx Anode and Insulated Gate Bipolar Transistor T kx The point where the emitters are connected is defined as the switching module S. kx The emitter of the diode D kx Cathode and Insulated Gate Bipolar Transistor T kx The collector of the diode is connected, and the diode D is connected to the collector of the diode. kx Cathode and Insulated Gate Bipolar Transistor T kx The point where the collectors are connected is defined as the switching module S. kx The collectors of the inverter are given by the following: x∈{a,b,c}, k∈{1,2,3,4,5}; phase A arm has two output terminals, namely upper output terminal A1 and lower output terminal A2; phase B arm has two output terminals, namely upper output terminal B1 and lower output terminal B2; phase C arm has two output terminals, namely upper output terminal C1 and lower output terminal C2; the three upper output terminals A1, B1 and C1 together form inverter stage 1; the three lower output terminals A2, B2 and C2 together form inverter stage 2; the three-phase load driven by inverter stage 1 is Z. LA1 Z LB1 Z LC1 The three-phase load driven by inverter stage 2 is Z. LA2 Z LB2 Z LC2 ; Two capacitors are connected to the DC side, and they are called capacitors C. U and capacitor C L Capacitor C U The positive terminal of the capacitor is connected to the positive terminal P of the DC bus, and the capacitor C U The negative terminal and capacitor C L The positive terminal is connected, and the capacitor C L The negative terminal of the capacitor is connected to the negative terminal N of the DC bus, and the capacitor C is connected to the negative terminal N of the DC bus. U The negative terminal and capacitor C L The point where the positive terminals are connected is defined as the DC neutral point 0; the voltage between the positive terminal P and the negative terminal N is U. dc The potential of neutral point O is 0, and the voltage between the positive terminal P and neutral point O is U. dc / 2, the voltage between the neutral point O and the negative terminal N is U dc / 2; Three-phase resistive load Z LA1 Z LB1 Z LC1 One end is connected to the upper output terminals A1, B1, and C1 respectively, and the three-phase resistive-inductive load Z LA1 Z LB1 Z LC1 The other end is connected; three-phase resistive-inductive load Z LA2 Z LB2 Z LC2 One end is connected to the lower output terminals A2, B2, and C2 respectively, and the three-phase resistive-inductive load Z LA2 Z LB2 Z LC2 The other end is connected.

2. The three-phase E-type mixed-level dual-output integrated converter according to claim 1, characterized in that, Switch module S 1a The collector is connected to the positive terminal P of the DC bus, and the switching module S 1a emitter and switch module S 2a The collectors are connected, and the switching module S 2a emitter and switch module S 4a The collectors are connected, and the switching module S 4a emitter and switch module S 5a The collectors are connected, and the switching module S 5a The emitter is connected to the negative terminal N of the DC bus; the switch module S is connected. 1a emitter and switch module S 2a The point where the collectors of the circuit are connected is defined as the AC output terminal A1; the switching module S... 4a emitter and switch module S 5a The point where the collectors are connected is defined as the AC output terminal A2; Switch module S 3a The collector of the switch module S is connected to the DC neutral point 0. 3a emitter and switch module S 2a The emitters are connected.

3. The three-phase E-type mixed-level dual-output integrated converter according to claim 1, characterized in that, Switch module S 1b The collector is connected to the positive terminal P of the DC bus, and the switching module S 1b emitter and switch module S 2b The collectors are connected, and the switching module S 2b emitter and switch module S 4b The collectors are connected, and the switching module S 4b emitter and switch module S 5b The collectors are connected, and the switching module S 5b The emitter is connected to the negative terminal N of the DC bus; the switch module S is connected. 1b emitter and switch module S 2b The point where the collectors of the circuit are connected is defined as the AC output terminal B1; the switching module S... 4b emitter and switch module S 5b The point where the collectors are connected is defined as the AC output terminal B2; Switch module S 3b The collector of the switch module S is connected to the DC neutral point 0. 3b emitter and switch module S 2b The emitters are connected.

4. The three-phase E-type mixed-level dual-output integrated converter according to claim 1, characterized in that, Switch module S 1c The collector is connected to the positive terminal P of the DC bus, and the switching module S 1c emitter and switch module S 2c The collectors are connected, and the switching module S 2c emitter and switch module S 4c The collectors are connected, and the switching module S 4c emitter and switch module S 5c The collectors are connected, and the switching module S 5c The emitter is connected to the negative terminal N of the DC bus; the switch module S is connected. 1c emitter and switch module S 2c The point where the collectors of the circuit are connected is defined as the AC output terminal C1; the switching module S... 4c emitter and switch module S 5c The point where the collectors are connected is defined as the AC output terminal C2; Switch module S 3c The collector of the switch module S is connected to the DC neutral point 0. 3c emitter and switch module S 2c The emitters are connected.

5. A carrier PWM modulation method based on the three-phase E-type hybrid-level dual-output integrated converter according to claim 1, characterized in that, Includes the following steps: Step 1: In the three-phase E-type mixed-level dual-output integrated converter, there is a constraint relationship between the output potential of the upper output terminal and the lower output terminal on each phase arm of the same phase bridge, and they are the same. For the A-phase bridge arm, the output potential V at the upper output terminal A1 is... A1 ≥ Output potential V at lower output terminal A2 A2 And the output potential V of A1 A1 For U dc / 2, Lower output A2 output potential V A2 Cannot be U dc / 2; The three-phase E-type mixed-level dual-output integrated converter is configured with the same number of switching modules and reasonable switching states for each of the A, B, and C phase bridge arms. Each phase has 5 switching modules and 5 reasonable switching states. For the A phase bridge arm: The states of the B-phase bridge arm switches and the C-phase bridge arm switches are similar to those of the A-phase bridge arm switches. Step 2: Employ carrier PWM modulation with added DC offset and zero-sequence component, using two triangular carriers u c1 and u c2 It adopts an anti-phase stacking method, that is, two triangular carriers u c1 u c2 Their phases differ by 180°, but their frequencies are the same, and u c1 The variation range is 0 to 1, u c2 The range of variation is -1 to 0; Define two sets of sinusoidal modulation waves u x1 and u x2 Where x∈{A, B, C}, the first group of sinusoidal modulation waves u x1 The expression is: The second group of sinusoidal modulation waves u x2 The expression is: Where m1 and m2 are the modulation intensities of the first and second modulated waves, respectively, and the values ​​of m1 and m2 both range from 0 to 1.15; ω1 and ω2 are the angular frequencies of the first and second modulated waves, respectively. These are the initial phase angles of the first and second modulated waves, respectively. The value range is from -π / 2 to π / 2; the periods of the two sets of modulation waves are set as T1 and T2 respectively, that is, T1=2π / ω1 and T2=2π / ω2; Define u max1 u min1 and u mid1 These represent the maximum, minimum, and median values ​​of the first group of modulated waves, u. max2 u min2 and u mid2 These represent the maximum, minimum, and median values ​​of the second group of modulated waves, and the maximum, minimum, and median values ​​of the first group of modulated waves, respectively. max1 u min1 and u mid1 The expressions are as follows: The maximum, minimum, and median values ​​of the second group of modulated waves, u max2 u min2 and u mid2 The expressions are as follows: Define u 01 and u 02 The zero-sequence components of the superposition of the first and second sinusoidal modulated waves, respectively, u 01 and u 02 The expressions are as follows: Using two sets of modulation waves mx1 and u mx2 Two sets of three-level AC outputs are controlled respectively, where x∈{A, B, C}, and the first set of modulation wave u mx1 The expression is: The second group of modulation waves u mx2 The expression is: Among them, U offset1 and U offset2 These are the DC offsets of the upper output modulated wave and the lower output modulated wave, respectively. offset1 The value range is from 0 to 1-m1 / 1.15, U offset2 The value range is from 0 to 1-m² / 1.15; Modulated wave u mx1 u mx2 Separately with triangular carrier u c1 u c2 By comparing the magnitudes, the potentials v of the upper and lower output terminals can be determined. x1 v x2 Where x∈{A, B, C}; Step 3: Define the line voltage amplitudes between phase A and phase B of the two sets of AC outputs as U. AB1 U AB2 AC output line voltage amplitude U AB1 U AB2 The relationship between the modulation intensities m1 and m2 of the two sets of sinusoidal modulated waves is as follows: Step 4: Generate the logical operations for the drive signals of each switch module; a drive signal value of 1 indicates that the switch module is turned on; a drive signal value of 0 indicates that the switch module is turned off. The first group of modulation waves u mx1 With carrier u c1 Compare the results, and generate signal e1: The first group of modulation waves u mx1 With carrier u c2 Compare the results, and generate signal e2: The second group of modulation waves u mx2 With carrier u c1 Compare the results, and generate signal e3: The second group of modulation waves u mx2 With carrier u c2 Compare the results, and generate signal e4: Signal e5 is generated from signals e1 and e2: in, This indicates a logical NOT operation on u, and the symbol "&" indicates a logical AND operation. Signal e6 is generated from signals e3 and e4: Signal e7 is generated from signal e5: Signal e8 is generated from signal e6: Based on the signals e1 to e8 and the five reasonable switching states of the three-phase E-type mixed-level dual-output integrated converter, the five switching modules S of each phase bridge arm are analyzed. 1x ~S 5x drive signal s 1x ~s 5x , where x∈{a, b, c}.

6. The carrier PWM modulation method for a three-phase E-type hybrid-level dual-output integrated converter according to claim 5, characterized in that, The five reasonable switching states in step one are as follows: Operating state 1: Switch module S 1a Switch module S 3a Switch module S 4a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 For U dc / 2, Lower output A2 output potential V A2 =0; Operating state 2: Switch module S 1a Switch module S 4a Switch module S 5a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 For U dc / 2, Lower output A2 output potential V A2 For -U dc / 2; Operating state 3: Switch module S 2a Switch module S 3a Switch module S 4a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 When the value is 0, the output potential V of A2 is 0. A2 =0; Operating status 4: Switch module S 2a Switch module S 3a Switch module S 5a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 When the value is 0, the output potential V of A2 is 0. A2 For -U dc / 2; Operating Status 5: Switch Module S 2a Switch module S 4a Switch module S 5a When the circuit is turned on, the upper output terminal A1 outputs a potential V. A1 For -U dc / 2, Lower output A2 output potential V A2 For -U dc / 2.

7. The carrier PWM modulation method for a three-phase E-type hybrid-level dual-output integrated converter according to claim 5, characterized in that, In step two, the modulation wave u mx1 u mx2 Separately with triangular carrier u c1 u c2 The comparison method is as follows: If u mx1 >u c1 v x1 For U dc / 2; if u mx1 ≤u c2 v x1 For -U dc / 2; if u c2 ≤u mx1 ≤u c1 v x1 =0; If u mx2 >u c2 v x2 If u is 0; mx2 ≤u c2 v x2 For -U dc / 2.

8. The carrier PWM modulation method for a three-phase E-type hybrid-level dual-output integrated converter according to claim 5, characterized in that, In step four, each phase arm has 5 switching modules S 1x ~S 5x drive signal s 1x ~s 5x The analysis method is as follows: The voltage at the upper output terminal v x1 For U dc / 2, lower output terminal potential v x2 The voltage at the upper output terminal is 0; x1 For U dc / 2, lower output terminal potential v x2 For -U dc / 2, switch module S 1x On, switch module S 1x drive signal s 1x The expression is: s 1x =e1 The voltage at the upper output terminal v x1 The lower output terminal potential v is 0. x2 The voltage at the upper output terminal is 0; x1 The lower output terminal potential v is 0. x2 For -U dc / 2; Upper output terminal potential v x1 For -U dc / 2, lower output terminal potential v x2 For -U dc / 2, switch module S 2x On, switch module S 2x drive signal s 2x The expression is: The symbol "∨" represents the logical OR operation. The voltage at the upper output terminal v x1 For U dc / 2, lower output terminal potential v x2 The voltage at the upper output terminal is 0; x1 The lower output terminal potential v is 0. x2 The voltage at the upper output terminal is 0; x1 The lower output terminal potential v is 0. x2 For -U dc / 2, switch module S 3x On, switch module S 3x drive signal s 3x The expression is: The voltage at the upper output terminal v x1 For U dc / 2, lower output terminal potential v x2 The voltage at the upper output terminal is 0; x1 For U dc / 2, lower output terminal potential v x2 For -U dc / 2; Upper output terminal potential v x1 The lower output terminal potential v is 0. x2 The voltage at the upper output terminal is 0; x1 For -U dc / 2, lower output terminal potential v x2 For -U dc / 2, switch module S 4x On, switch module S 4x drive signal s 4x The expression is: s 4x =e4&e7 The voltage at the upper output terminal v x1 For U dc / 2, lower output terminal potential v x2 For -U dc / 2; Upper output terminal potential v x1 The lower output terminal potential v is 0. x2 For -U dc / 2; Upper output terminal potential v x1 For -U dc / 2, lower output terminal potential v x2 For -U dc / 2, switch module S 5x On, switch module S 5x drive signal s 5x The expression is:

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