A training verification system for a chip

Abstract

The application relates to the technical field of electronic design, in particular to a training verification system for a chip, which comprises a database, a processor and a memory storing a computer program, and the computer program is executed by the processor to realize the following steps: according to a reference delay range, randomly generating simulation delay information configures a delay unit, using a training model to obtain register parameters according to the simulation delay information, and using a register model to write into a register, initializing an interface unit without training, performing read-write testing on the initialized interface unit and the memory, and obtaining read-write testing results. It can be known that the training of the physical layer is not performed in the initialization process, so that a large amount of verification simulation time is saved, register parameters are calculated according to the simulation delay by using the training model, and the physical layer register is configured, so that the training function of the physical layer can be indirectly verified.

Description

Technical Field

[0001] This invention relates to the field of electronic design technology, and in particular to a training and verification system for chips. Background Technology

[0002] In the existing memory topology, the different layout and routing of different memory cells in the hardware can lead to inconsistent deviations between the clock signals and data for different memory cells. Therefore, it is necessary to adjust the output signal delay through the delay line of the physical layer (PHY) transmitter to ensure that the physical layer output signal meets the timing requirements of the JEDEC standard. Correspondingly, it is also necessary to adjust the delay line of the physical layer receiver to ensure that the physical layer can successfully sample the output signal of the memory cell. The process of adjusting the delay line is the physical layer training process.

[0003] In chip front-end verification scenarios, it is necessary to verify the training function of the physical layer. The usual verification method is to insert a delay into the memory cell interface in a verification environment based on UVM to simulate the delay introduced by the placement and routing, and then train the physical layer to verify that the physical layer can work stably after training.

[0004] However, training and validating the physical layer in the pre-simulation stage usually consumes a significant amount of simulation time, and the training time increases dramatically with the size of the validation gate. To address this issue, existing technologies typically include a switch in the validation environment to control whether the training process is skipped in the pre-simulation stage. Obviously, this method cannot validate the training functionality of the physical layer while ensuring a short simulation time, and validating the training functionality of the physical layer results in a long simulation time. Therefore, how to validate the training functionality of the physical layer while ensuring a short simulation time has become an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0006] A training and verification system for a chip includes: an interface unit, a memory unit, a delay unit, a verification platform, a processor, and a memory storing a computer program. The interface unit is connected to the memory unit via a bus, the delay unit is deployed on the bus, and the verification platform is connected to the interface unit. The verification platform includes a training model, a register model, and a database. The database includes a reference delay range [a, b] corresponding to the memory unit. The interface unit includes a physical layer, and the physical layer includes registers. When the computer program is executed by the processor, the following steps are implemented:

[0007] S101, Based on the reference delay range [a, b], randomly generate simulated delay information c within the range [a, b].

[0008] S102, configure the delay unit using c.

[0009] S103, send c to the training model to obtain the register parameter d output by the training model.

[0010] S104, using the register model, write d into the register.

[0011] S105, initialize the interface unit to obtain the initialized interface unit, wherein the initialization does not include training the physical layer.

[0012] S106, perform read / write tests on the initialized interface unit and the memory to obtain read / write test results.

[0013] S107, when the read / write test result shows that the read and write data are consistent, the training and verification of the physical layer are confirmed to be successful.

[0014] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the training and verification system for chips provided by the present invention achieves considerable technological progress and practicality, and has broad industrial application value. It has at least the following advantages:

[0015] This invention provides a training and verification system for chips. The system includes: an interface unit, a memory unit, a delay unit, a verification platform, a processor, and a memory storing a computer program. The interface unit is connected to the memory unit via a bus, the delay unit is deployed on the bus, and the verification platform is connected to the interface unit. The verification platform includes a training model, a register model, and a database. The database includes a reference delay range [a, b] corresponding to the memory unit. The interface unit includes a physical layer, and the physical layer includes registers. When the computer program is executed by the processor, the following steps are implemented: Based on the reference delay range [a, b], simulated delay information c is randomly generated within the range [a, b]. The delay unit is configured using c. c is sent to the training model to obtain the register parameter d output by the training model. The register model is used to write d into the register. The interface unit is initialized to obtain an initialized interface unit. The initialization does not include training of the physical layer. Read and write tests are performed on the initialized interface unit and the memory to obtain read and write test results. When the read and write test results show that the read and write data are consistent, the training and verification of the physical layer are confirmed to be successful.

[0016] It can be seen that the physical layer is not trained during the initialization process, thus saving a lot of verification simulation time. Instead, the training model is used to calculate the register parameters based on the simulation delay, and then the physical layer registers are configured. This allows for indirect verification of the physical layer training function. Furthermore, it has generalization ability on different types of memory units, thus verifying the physical layer training function while ensuring a short simulation time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the execution of a computer program by a processor in a chip training and verification system, as provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This embodiment provides a training and verification system for a chip. The system includes: an interface unit, a memory unit, a delay unit, a verification platform, a processor, and a memory storing a computer program. The interface unit is connected to the memory unit via a bus. The delay unit is deployed on the bus. The verification platform is connected to the interface unit and includes a training model, a register model, and a database. The database includes a reference delay range [a, b] corresponding to the memory unit. The interface unit includes a physical layer, and the physical layer includes registers. See [link to documentation]. Figure 1 This is a flowchart illustrating the execution of a computer program by a processor in a chip training and verification system, as provided in an embodiment of the present invention. When the computer program is executed by the processor, the following steps are implemented:

[0021] S101, Based on the reference delay range [a, b], randomly generate simulated delay information c within the range [a, b];

[0022] S102, configure the delay unit using c;

[0023] S103, send c to the training model to obtain the register parameter d output by the training model;

[0024] S104, using the aforementioned register model, write d into the register;

[0025] S105, initialize the interface unit to obtain the initialized interface unit, wherein the initialization does not include training the physical layer;

[0026] S106, Perform read / write tests on the initialized interface unit and the memory to obtain read / write test results;

[0027] S107, when the read / write test result shows that the read and write data are consistent, the training and verification of the physical layer are confirmed to be successful.

[0028] The interface unit can refer to DDR IP, which can include DDR PHY and memory controller. DDR PHY is also known as the physical layer. The physical layer can be used to convert the data sent from the memory controller into signals that conform to the DDR protocol and send them to the memory unit. At the same time, the physical layer can also be used to convert the data sent from the memory unit into signals that conform to the DFI protocol and send them to the memory controller. The memory unit can refer to DRAM, which can be of types such as DDR, GDDR, HBM, and LPDDR.

[0029] Delay units are used to insert delays into the signals between the physical layer and memory cells to simulate the delays introduced by the placement and routing of memory cells. Since the signals between the physical layer and memory cells are in a delay-free state in the verification scenario, delay units are added between the physical layer and memory cells in order to simulate the signal transmission in the real environment.

[0030] The verification platform can refer to the UVM verification platform. The training model in the verification platform can be used to simulate the training process of the physical layer. That is, based on the simulated delay information c, the corresponding register parameter d of the simulated delay information c is obtained. The register model can refer to the UVM Ral Model. The register model can be used to configure the output of the training model into the registers of the physical layer.

[0031] Specifically, the reference delay range can be preset according to the attributes of the memory unit, which is prior information. In this embodiment, it is assumed that any delay in the reference delay range is within the training and adjustment capability range of the physical layer.

[0032] The simulated delay information c can be obtained by generating random numbers within the range [a, b].

[0033] The initialization and read / write tests described above are common operations in chip verification scenarios. Their implementation methods will not be explained in detail here. However, it should be noted that the initialization process does not include training of the physical layer. That is, in a normal testing scenario, physical layer training is skipped.

[0034] Optionally, the interface unit may further include a memory controller.

[0035] The memory controller is used to manage and plan data transfer between the processor and memory units.

[0036] Optionally, the training model includes a computation function used to calculate d based on c.

[0037] The computation function can be expressed as f, then d = f(c).

[0038] Optionally, the calculation function corresponds one-to-one with the type of the physical layer.

[0039] Depending on the physical layer, the training results for the same latency will differ. Therefore, the training model contains multiple computation functions, each corresponding to a different physical layer type. In this embodiment, the computation function corresponding to the i-th physical layer is represented as f. i Let i be an integer in the range [1, I], and I be the total number of physical layer types. Then d = f i (c)

[0040] Optionally, writing d into the register using the register model includes:

[0041] The backdoor function of the register model is called to write d into the register.

[0042] The register model includes a backdoor function, which implements backdoor write functionality (backload register).

[0043] Optionally, step S102 further includes the following steps:

[0044] S1021, Detect the bidirectional signal of the memory unit to obtain change information;

[0045] S1022, Determine the driving end of the bidirectional signal based on the change information;

[0046] S1023, when the driving end is the physical layer, according to c, a delay is added in the direction from the physical layer to the memory unit;

[0047] S1024, when the driving end is the memory unit, according to c, a delay is added in the direction from the memory unit to the physical layer.

[0048] The interface of the memory unit is a bidirectional port. Therefore, by detecting the interface of the memory unit, the change information of the bidirectional (inout) signal can be obtained, and thus the driver end can be determined.

[0049] Optionally, sending c to the training model includes:

[0050] c is passed to the trained model via UVM's config_db.

[0051] In this embodiment, config_db can be used for communication and parameter passing between different components in UVM. In this embodiment, config_db can be used to pass the simulated delay information c corresponding to the delay unit to the training model in the verification platform.

[0052] Optionally, when the computer program is executed by the processor, the following steps are also performed:

[0053] S108, when the read / write test result is inconsistent with the read / write data, the training and verification of the physical layer is confirmed to have failed.

[0054] When the training and verification of the physical layer fails, the implementer can analyze the reasons for the failure based on the simulation results.

[0055] This embodiment does not perform physical layer training during initialization, thus saving a significant amount of verification simulation time. Instead, it uses a training model to calculate register parameters based on simulation delays and then configures the physical layer registers, thereby indirectly verifying the physical layer training function. Furthermore, it has generalizability across different types of memory units, thus verifying the physical layer training function while ensuring a short simulation time.

[0056] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A training and verification system for chips, characterized in that, The system includes: an interface unit, a memory unit, a delay unit, a verification platform, a processor, and a memory storing a computer program. The interface unit is connected to the memory unit via a bus. The delay unit is deployed on the bus. The verification platform is connected to the interface unit and includes a training model, a register model, and a database. The database includes a reference delay range [a, b] corresponding to the memory unit. The interface unit includes a physical layer, and the physical layer includes registers. When the computer program is executed by the processor, the following steps are implemented: S101, Based on the reference delay range [a, b], randomly generate simulated delay information c within the range [a, b]; S102, configure the delay unit using c; S103, send c to the training model to obtain the register parameter d output by the training model; S104, using the register model, write d into the register, wherein writing d into the register using the register model includes: Call the backdoor function of the register model to write d into the register; S105, initialize the interface unit to obtain the initialized interface unit, wherein the initialization does not include training the physical layer; S106, Perform read / write tests on the initialized interface unit and the memory to obtain read / write test results; S107, when the read / write test result shows that the read and write data are consistent, the training and verification of the physical layer are confirmed to be successful.

2. The training and verification system for chips according to claim 1, characterized in that, The interface unit also includes a memory controller.

3. The training and verification system for chips according to claim 1, characterized in that, The training model includes a computation function that calculates d based on c.

4. The training and verification system for chips according to claim 3, characterized in that, The calculation function corresponds one-to-one with the type of the physical layer.

5. The training and verification system for chips according to claim 1, characterized in that, Step S102 also includes the following steps: S1021, Detect the bidirectional signal of the memory unit to obtain change information; S1022, Determine the driving end of the bidirectional signal based on the change information; S1023, when the driving end is the physical layer, according to c, a delay is added in the direction from the physical layer to the memory unit; S1024, when the driving end is the memory unit, according to c, a delay is added in the direction from the memory unit to the physical layer.

6. The training and verification system for chips according to claim 1, characterized in that, Sending c to the training model includes: c is passed to the trained model via UVM's config_db.

7. The training and verification system for chips according to claim 1, characterized in that, When the computer program is executed by the processor, the following steps are also performed: S108, when the read / write test result is that the read / write data is inconsistent, the training and verification of the physical layer is confirmed to have failed.

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