A method and apparatus for OPUC demultiplexing

Abstract

The application relates to the field of optical communication, in particular to a method and device for OPUC demultiplexing. Mainly comprising: configuring at least two RAMs with consistent data depth for each optical channel payload unit service of cascaded transmission to form a RAM matrix; when data is written, writing each time slot data into a specified depth of a specified RAM according to a writing rule in the time slot order of the OPUC service; when data is read, reading out the data at the specified depth in the RAM matrix according to a reading rule matched with the writing rule in the time slot order and splicing and integrating the data, and taking the spliced and integrated data as the output of the low-order channel service. The application can greatly reduce the logical resource amount required for data conversion during OTUCn super-high-speed transmission demultiplexing, and simultaneously reduce the conversion processing delay.

Description

Technical Field

[0001] This invention relates to the field of optical communication, and in particular to a method and apparatus for demultiplexing OPC. Background Technology

[0002] Data interleaving and deinterleaving / demultiplexing in optical transport networks (OTNs) is a key technology for optical-to-electrical signal service conversion and is widely used in the field of optical-electrical communication. Among them, the OmniTouch Unified Communication n (OTUCn) service defined in the G.709 protocol, with its high-speed and cascaded bonding characteristics, can support ultra-high-speed signal transmission. Therefore, in the design and implementation of OTN bearer chips, the high-speed data multiplexing / demultiplexing conversion of its optical channel payload unit (OPUCn) inevitably requires more physical logic resources, and the large amount of data conversion processing also causes greater transmission delays.

[0003] To address this characteristic, previous methods for handling OPCcn demultiplexing operations involved storing multiple copies of high-order time slot data, then simultaneously extracting the required time slot data from multiple storage devices and concatenating the data to ensure synchronous output of low-order services. Alternatively, a pipelined multi-stage data adjustment and transformation process was employed, adjusting the position and arrangement of time slot data step by step according to the distribution of time slots occupied by low-order services, ultimately achieving sequential output of low-order services.

[0004] Of the two processing schemes above, the former has the advantage of enabling rapid data conversion, but it leads to a significant waste of logical storage resources. A large portion of the time-slot data written to Random Access Memory (RAM) is not read and used. Moreover, as the number of cascaded OTUCn increases, the wasted logical resources increase exponentially, resulting in very high costs. The second scheme, on the other hand, uses a pipelined, step-by-step, batch-based data processing approach to gradually achieve business conversion, avoiding the resource waste problem of the first scheme. However, this method has a much more complex logical design, lower fault tolerance, and the multi-stage pipelined processing also introduces greater latency.

[0005] Therefore, how to overcome the shortcomings of existing technologies and resolve the contradiction between storage resource consumption and processing complexity is a problem to be solved in this technical field. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the prior art, the present invention solves the problem of the contradiction between storage resource consumption and processing complexity in the prior art.

[0007] The embodiments of the present invention adopt the following technical solutions:

[0008] In a first aspect, the present invention provides a method for demultiplexing OPUC, specifically comprising: configuring at least two RAMs with the same data depth for each optical channel payload unit service in cascaded transmission to form a RAM matrix; when data is written, writing the data of each time slot to a specified depth in a specified RAM according to the time slot order of the OPUC service and the writing rules; when data is read out, reading out the data of a specified depth in the RAM matrix according to the time slot order and splicing and integrating it according to the reading rules that match the writing rules, and using the spliced ​​and integrated data as the output of the low-order channel service.

[0009] Preferably, each Optical Channel Payload Unit (OPUC) service in the cascaded transmission is configured with at least two RAMs with the same data depth. Specifically, each RAM is divided into two storage arrays on an average basis according to the address depth to complete the ping-pong rotation process. The data bit width of the RAM is one time slot data bit width, and the storage address depth of the RAM is twice the total number of OPUC service time slots.

[0010] Preferably, the method further includes: after each storage array is filled with time slot data, initiating a data readout operation for that storage array to perform low-level service data readout for that storage array.

[0011] Preferably, the step of writing the data of each time slot to a specified depth in the specified RAM according to the writing rules specifically includes: obtaining the corresponding depth of the current time slot in the specified RAM according to the correspondence between time slot and data depth; and writing the data of the current time slot to the specified RAM at the corresponding depth of the time slot according to the matrix read / write algorithm of OPUC and the multiplexing strategy of OPUCn.

[0012] Preferably, the step of writing the data of the current time slot into a specified RAM at the depth corresponding to the time slot specifically includes: when the data envelopment is enabled, determining the order in which the data of the current time slot is stored in the RAM array based on the low-order channel information to which the time slot belongs, and obtaining the RAM number and depth address where the data is stored based on the order.

[0013] Preferably, the step of reading and integrating data at a specified depth in the RAM matrix according to the time slot order based on the read rule that matches the write rule specifically includes: obtaining the data address to be read based on the time slot occupied by the low-order channel and the write depth of the data in each RAM; reading the data in the specified RAM address sequentially according to the time slot polling order and the read rule corresponding to the time slot, and integrating the read data.

[0014] Preferably, obtaining the data address to be read based on the time slot occupied by the low-order channel and the write depth of the data in each RAM specifically includes: determining the low-order channel number and time slot corresponding to the data to be read through time slot polling configuration; and determining the address of the data to be read in each RAM in the RAM matrix this time based on the obtained time slot and readout rules.

[0015] Preferably, the step of sequentially reading data from a specified RAM address according to the time slot polling order and the corresponding reading rules of the time slot, and then concatenating and integrating the read data, specifically includes: reading data from a specified address depth from each RAM at each clock cycle; after the data in the RAM is read, concatenating and integrating the read data according to the RAM's sequential numbering.

[0016] Preferably, after reading and splicing the data at a specified depth in the RAM matrix in time slot order, the method further includes: performing a barrel shift on the data content according to the data arrangement order during splicing, so as to adjust the corresponding time slot order of the read data.

[0017] On the other hand, the present invention provides an OPC demultiplexing apparatus, specifically comprising at least one processor and a memory, wherein the at least one processor and the memory are connected via a data bus, the memory stores instructions executable by at least one processor, and the instructions, after being executed by the processor, are used to complete the OPC demultiplexing method in the first aspect, wherein the memory includes at least two RAMs with the same data depth for use as RAM in the OPC demultiplexing method in the first aspect.

[0018] Compared with existing technologies, the beneficial effects of the embodiments of the present invention are as follows: Multiple RAMs are configured for each OPCUC service, data from each time slot of the OPCUC service is written into the corresponding depth of the RAM, and the data is read out and integrated according to the corresponding reading rules. The method provided in the embodiments of the present invention avoids multiple data copies and eliminates the need for multi-stage pipeline processing by using multiple RAMs with different storage depths. This method is clear, reliable, and highly implementable, and can greatly reduce the amount of logic resources required for demultiplexing data conversion during OPCUCn ultra-high-speed transmission, while also reducing conversion processing latency. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0020] Figure 1 A flowchart of an OPUC demultiplexing method provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram illustrating the demultiplexing strategy of the method provided in the embodiments of the present invention;

[0022] Figure 3 This refers to the RAM matrix demultiplexing transformation process in the method provided by the embodiments of the present invention;

[0023] Figure 4 This is a schematic diagram of high-order OPUC slot data writing to the array in the method provided in the embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram illustrating the rule-writing algorithm modeling in the method provided in this embodiment of the invention;

[0025] Figure 6 A flowchart of another OPUC demultiplexing method provided in an embodiment of the present invention;

[0026] Figure 7 This is a schematic diagram illustrating the low-level business data reading process in the method provided by this embodiment of the invention.

[0027] Figure 8 A flowchart of another OPUC demultiplexing method provided in an embodiment of the present invention;

[0028] Figure 9 A flowchart of another OPUC demultiplexing method provided in an embodiment of the present invention;

[0029] Figure 10 This is a schematic diagram illustrating the storage of data written in the method provided in this embodiment of the invention;

[0030] Figure 11 This is a schematic diagram showing the storage location of the input time slot data in the method provided by the embodiments of the present invention;

[0031] Figure 12 A flowchart of another OPUC demultiplexing method provided in an embodiment of the present invention;

[0032] Figure 13 This is a schematic diagram of data reading and barrel shifting in the method provided in the embodiments of the present invention;

[0033] Figure 14 This is a schematic diagram of an OPUC demultiplexing device provided in an embodiment of the present invention;

[0034] The reference numerals in the attached figures are as follows:

[0035] 11: Processor; 12: Memory. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0037] This invention is an architecture of a specific functional system. Therefore, the specific embodiments mainly describe the functional logic relationship of each structural module, and do not limit the specific software and hardware implementation methods.

[0038] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0039] Example 1:

[0040] In optical transport lanes (OTLs), optical transport networks (OTNs), and optical channel data units (ODUs), the communication data carried needs to undergo interleaving and deinterleaving / demultiplexing processing between high-order and low-order services. This embodiment provides a simple and efficient demultiplexing method. For example... Figure 1 As shown, the specific steps of the OPUCN demultiplexing method provided in this embodiment of the invention are as follows:

[0041] Step 101: Each Optical Channel Payload Unit (OPUC) service in the cascaded transmission is configured with at least two RAMs of the same data depth to form a RAM matrix.

[0042] In this embodiment, each cascaded OPC service is configured with m RAMs of uniform depth. The storage address depth of each RAM is k times the number of OPC slots. A group of RAMs used by each OPC service is called a RAM array, which is used to store the time slot data of one OPC. Based on the number n of cascaded OPCs, n RAM arrays are combined to form a RAM matrix. In specific implementations, the specific hardware configuration of each RAM matrix can be selected according to the read / write strategy, or a corresponding read / write strategy can be formulated based on the hardware attributes of the RAM matrix, as long as the data read in and written out correspond.

[0043] The strategy diagram of this embodiment is as follows: Figure 2As shown, the specific implementation process of this strategy is accomplished using a RAM matrix. To enable read and write operations for multiple OPC (Optical Programming Union) services, each RAM can be divided into k storage arrays based on the address depth, according to the number of cascaded OPCs. Cyclic read and write operations within the storage arrays further improve read and write efficiency. On the other hand, for ease of read and write control, the data bit width in the RAM needs to be equal to or greater than the bit width corresponding to one time slot. In practical implementation, the number of storage arrays and data bit width in the RAM can be determined according to actual needs. Preferably, each RAM is divided into two storage arrays based on the address depth to achieve ping-pong rotation processing. The data bit width of the RAM is one time slot data bit width, and the RAM's storage address depth is twice the total number of OPC service time slots. Specifically, a RAM with a storage depth of 2 * the total number of OPC time slots is selected, and its storage capacity is divided into two storage arrays. The logic hardware internally divides the RAM array into upper and lower storage spaces according to the depth address to achieve synchronous ping-pong rotation read and write processing. To facilitate memory read / write control, each of the evenly divided storage arrays can be defined as a PAGE page to enable cyclic ping-pong read / write control.

[0044] Step 102: When writing data, according to the time slot order of the OPC service, write the data of each time slot to the specified depth of the specified RAM according to the writing rules.

[0045] Based on the OPUC frame data transmission characteristics, and following step 102, the time slot data input to each OPUC will enter its respective RAM array in a round-robin order from TS0 to TS19. Before writing the time slot data, the RAM write rules for the current time slot are sequentially obtained. Then, according to the configuration settings of the write rules, the time slot data is written to the specific addresses of the corresponding RAMs in the m RAMs of the RAM array, rather than simply writing them sequentially. This is used to cooperate with the RAM matrix read rules in the subsequent step 103 to effectively convert high-order time slot data into low-order service data. Since a set of RAM arrays has 20*m addresses for time slot storage, the total number of RAM time slot data write rules for each OPUC is 20*m.

[0046] Step 103: When data is read out, according to the read out rules that match the write rules, the data at the specified depth in the RAM matrix is ​​read out in time slot order and spliced ​​together. The spliced ​​and integrated data is used as the output of low-order channel services.

[0047] Unlike the control method for writing high-order time slot data, the processing of reading low-order service data requires covering the entire RAM matrix. This processing is based on the cascading and binding transmission function of OPCcn, where the high-order time slots occupied by low-order services can be flexibly distributed across 20*n time slots of n OPCs. However, due to the limitations of RAM address data reading characteristics, each RAM can only read data from one address per clock cycle. To achieve high-speed synchronous data conversion, the reading rules construct the concept of RAM matrix "columns." Each clock cycle outputs m time slots of data belonging to a low-order service, equivalent to extracting one address data from each of the m RAM block "columns" per clock cycle to form the corresponding low-order service data output.

[0048] After each storage array is filled with time slot data, the data read operation for that storage array is initiated, and the low-order service data is read from that storage array. As can be seen above, all low-order service information data is generated by reading from the RAM matrix storage space. Therefore, to flexibly schedule and orderly output the complete low-order channel service data, based on step 103, this embodiment introduces the OPUCN cascaded time slot polling rule. This rule sets the order of low-order service output in the RAM storage space and the corresponding order of RAM matrix data reading rules. Thus, the envelope pattern of the low-order service output can be adjusted and controlled through this rule, and the uniformity of the output envelope can be optimized when necessary.

[0049] Unlike the RAM array data writing rules, the RAM matrix data reading rules and cascaded time slot polling rules are both 20*n. This ensures that a set of time slot polling is completed in 20*n clock cycles. Based on the rule information of the cascaded time slot polling, the corresponding matrix data reading rules are obtained, and m time slot data are output in each cycle. At the end of one cycle, all 20*n*m time slot data in the RAM matrix storage space are read and bound to the low-order service number, realizing the serialized data output of all low-order services.

[0050] Due to the finite boundaries of the RAM matrix, the method of extracting address data and binding low-level services based on the RAM matrix "columns" according to the above-described RAM matrix write and read configurations will result in a reversal of the splicing order of time slots within the data when reading low-level service data. Therefore, after reading low-level service data, it is necessary to perform data shifting and adjustment on its content. This is achieved by adding data shifting logic rules after the read rules to complete the shifting and adjustment of the read data, thereby restoring the correct order of the low-level service data.

[0051] In practice, once the input data is sequentially written into RAM and a page is full, the data read operation begins. Adaptive read rules are formulated based on the time slots occupied by lower-order channels and the data write positions in the RAM matrix. Following the time slot polling order and the corresponding RAM read rules for each time slot, the time slot data belonging to each lower-order service is read out. Unlike writing to RAM, the read operation integrates the RAM of multiple OUCs together for sequential read operations to satisfy the OUCn binding mode.

[0052] Furthermore, due to the design rules of the read / write rules, the order of lower-order business data slots may shift during data reading. Therefore, it is necessary to combine the barrel shift rule with the data content to perform a barrel shift based on the data arrangement order during concatenation. This, combined with the write and read rules of the RAM matrix, will restore the shifted data in this situation. Specifically, based on the acquired slots, the corresponding barrel shift rule is selected, and the read data is barrel shifted according to the barrel shift value in the rule to adjust the corresponding slot order of the read data.

[0053] After steps 101-103 provided in this embodiment, the RAM matrix can be used to quickly demultiplex OPUC data through the corresponding write and read rules.

[0054] In actual implementation, specific read and write rules can be formulated according to actual needs. This embodiment provides some available read and write rules. You can refer to the following read and write rules to read and write data, or adjust them according to the actual scenario, or combine them with other required data processing methods. You can also complete the hardware logic design in the demultiplexing device based on the methods and read and write rules provided in this embodiment.

[0055] To make the technical solution and advantages of the strategy in this embodiment clearer, based on the specific implementation process of engineering applications, the implementation process of data input, output and other configuration processing is analyzed accordingly. The strategy and specific implementation process in this embodiment are described in detail below with reference to the accompanying drawings.

[0056] Figure 3 The process of RAM matrix demultiplexing transformation is demonstrated.

[0057] 1. RAM array writing

[0058] The write operations of the n RAM arrays in the matrix are performed independently. Each OPUC is allocated m RAMs, and filling one matrix storage space involves operating on m*20 time slot data, covering 20 address depths of each RAM. When packet envelopment is enabled, the order in which the current time slot data is stored in the RAM array is determined based on the low-order channel information to which the time slot belongs. The RAM number and depth address where the data is stored are then obtained based on the order. RAM address depth 0 is used to store TS0 data, address depth 1 stores TS1 data, and so on, with address depth 19 storing TS19 data. As the OPUC frame data transmission characteristics indicate, its time slot data is input sequentially. The final address in which RAM is written to each time slot needs to be specified by the RAM array write rules.

[0059] A schematic diagram of high-order OPUC slot data writing to the array is attached. Figure 4 As shown.

[0060] The generation of RAM array write rules requires reference to the low-order channel information to which each time slot belongs. The number of time slots occupied by the low-order channels determines the write position of each time slot. According to the G.709 protocol, the order of occupied time slots determines that the order of time slot data after demultiplexing must also be consistent. This means that data in the same time slot may not be able to be read in one scan, but needs to be interleaved with other time slots belonging to low-order services and output in multiple scans. To conform to the characteristics of RAM data reading, the write rules for each time slot can be finalized through algorithmic modeling.

[0061] The modeling rules are set as follows:

[0062] (1) x time slots belong to a certain low-level service;

[0063] (2) Fill the data from column 0 to m in a loop;

[0064] (3) The same value cannot appear in the first row. If a conflict occurs, the value will be shifted to the next row by (+1).

[0065] Figure 5 A schematic diagram of the writing rule algorithm model is shown;

[0066] The write rules for x time slots belonging to the same low-level service can be modeled by this algorithm. When the data of each time slot arrives at the RAM matrix from front to back, it will be written into the corresponding RAM according to the specified position shown in Figure 6, thus realizing the write rule setting of the RAM array.

[0067] 2. Cascaded time-slot polling

[0068] Once the high-order time slot data fills a set of storage space in the RAM array, the cascaded time slot polling operation begins. By specifying the low-order service number through the polling rules and issuing the corresponding RAM read rule order in sequence, the RAM matrix read rule applicable to that low-order service can be obtained.

[0069] 3. RAM matrix data reading

[0070] This matrix readout rule applies to the entire RAM matrix, dividing the RAM matrix into m columns. Each read opportunity outputs data from a time slot address from each RAM column.

[0071] like Figure 6 As shown, the following procedure can be used to read data from the RAM matrix.

[0072] Step 201: Obtain the address of the data to be read based on the time slot occupied by the low-order channel and the write depth of the data in each RAM.

[0073] By taking advantage of the time slot write pattern of the RAM array and referring to the algorithm modeling above, with the top left corner as the base point, and adopting the pattern of first up and down, then left and right, m ​​consecutive modeling grids are extracted from the model each time. The value in the grid is the column number of the RAM matrix, and the row number corresponding to the grid is the address depth of the time slot data. In this way, x read opportunities will output all the data belonging to this low-level service.

[0074] Step 202: Read the data from the specified RAM address sequentially according to the time slot polling order and the read rule corresponding to the time slot, and integrate the read data.

[0075] By following the above pattern, all time slot data belonging to the lower-level service can be read out step by step. Similarly, under the arrangement of polling scheduling, combined with the specific reading rules of each lower-level service, the data of all lower-level services will also be output in sequence.

[0076] 4. Data shifting

[0077] Due to the limited boundaries of the RAM matrix, in the low-order business data read according to the above rules, there is a conflict between time slot data boundaries, and the data before and after the data exhibits a cylindrical shift phenomenon, which corresponds to item (3) in the modeling algorithm rules, the numerical offset of the modeling table, indicating that a boundary conflict has occurred. This shift phenomenon is also reflected in the matrix data reading rules. Each time, m consecutive modeling grids are extracted from the model. If the values ​​in the grids are consecutive 0, 1, ..., m-2, m-1, then the data order is normal. If the values ​​in the grids are not in the above consecutive order, it indicates that the data order is abnormal. For example, 1, ..., m-2, m-1, 0, or 2, 3, ..., m-1, 0, 1, it indicates that the data sorting has a shift of 1 time slot or 2 time slots.

[0078] If data sorting results in an abnormal shift, a cylindrical data shifting process needs to be performed after acquiring the lower-level business data to restore the data.

[0079] A diagram illustrating the reading of low-level business data is attached. Figure 7 As shown.

[0080] By following the above four steps, the demultiplexing conversion from high-order time slots to low-order services can be achieved. Combined with the write and read processing of the RAM matrix, it is not limited to the above-mentioned modeling rule processing method, but can also generate many other processing strategies.

[0081] like Figure 8 As shown, the process of obtaining the address of the data to be read in step 201 can be completed in the following way.

[0082] Step 301: Determine the low-order channel number and time slot corresponding to the data to be read through time slot polling configuration.

[0083] After a write operation completes a storage page, a low-level service read operation for that RAM storage page is initiated. First, the low-level channel number and the corresponding time slot to be read are determined through the time slot polling configuration (stst_reorder_cfg).

[0084] Step 302: Based on the acquired time slots and readout rules, determine the address of the data to be read from each RAM in the RAM matrix this time.

[0085] After obtaining the low-order channel number and the corresponding time slot, select the corresponding reading rule (stst_rd_cfg) configuration according to the obtained time slot, and determine the address of the four time slot data to be read in the RAM3 to RAM0 matrix.

[0086] After steps 301-302 provided in this embodiment, the data address to be read in this round of reading can be obtained.

[0087] like Figure 9 As shown, the process of sequentially reading the data from the corresponding data addresses and integrating the data in step 202 can be completed in the following way.

[0088] Step 401: At each clock cycle, read data at a specified address depth from each RAM.

[0089] In a specific scenario, each OPC service has 128 bits of data per time slot. When reading data, one time slot data is read from each of the four RAM labels in each clock cycle, and four 128-bit blocks are read at a time.

[0090] Step 402: After the data in the RAM matrix is ​​read, the read data is concatenated in sequence according to the RAM's sequential numbering.

[0091] After reading the data, it is necessary to integrate the data. In the method provided in this embodiment, the read data can be directly concatenated bit by bit. The 128 bits read from RAM No. 3 are placed in the most significant bit, and the 128 bits read from RAM No. 0 are placed in the least significant bit.

[0092] After steps 401-402 provided in this embodiment, after 80 cycles, all the low-order channel data corresponding to a total of 80 time slots can be read out. In order to ensure that the data splicing order is not disordered when reading out the channel data, it is necessary to use RAM storage implemented by stst_wr_cfg to store the results, and the reading task is completed by stst_reorder_cfg, stst_rd_cfg, and barrel_sel_cfg.

[0093] In summary, the RAM matrix conversion strategy for OUC demultiplexing proposed in this embodiment revolves around a RAM storage matrix, combined with logical rules for time slot data writing, time slot polling, low-order service reading, and data shifting, to complete the demultiplexing of low-order services from the high-order OUCn. When implemented, this strategy fully utilizes physical storage resources, ensures coordinated logical processing rules, and maintains rigorous and orderly data transmission, maximizing resource savings. Furthermore, the use of ping-pong rotation and synchronous read / write methods enables more efficient and faster data conversion.

[0094] The OPC demultiplexing method provided in this embodiment employs synchronous read / write operations across multiple RAMs, reducing transmission time loss and maximizing the utilization of RAM resources during data writing and reading, thus avoiding waste of logic resources. Compared with previous technologies and methods, the method provided in this embodiment has the following advantages:

[0095] 1. Using only a single-level RAM matrix structure reduces processing latency and meets the low-latency requirements of 5G.

[0096] 2. This method reduces the design and implementation difficulty of the Register Transfer Level (RTL) in the hardware logic. The precise control configuration is calculated by software, the hardware structure is simple, easier to control, and the probability of error is reduced.

[0097] 3. Saves hardware logic resources, eliminating the waste of RAM resources;

[0098] 4. It has strong scalability and can be widely used in demultiplexing applications such as FlexE.

[0099] Example 2:

[0100] Based on the OPC demultiplexing method provided in Embodiment 1, this embodiment provides an example in a specific implementation scenario to describe the implementation process of the method provided in Embodiment 1 in a specific scenario. This example does not limit the method in Embodiment 1. In actual implementation, the following method can be referred to, or it can be adjusted according to the actual scenario requirements without conflict, or combined with other methods.

[0101] In a specific scenario, four OPUC services are in a bound mode. A lower-order channel 2 occupies TS1 of OPUC#0 and TS2 of OPUC#3. In this scenario, the write data corresponding to lower-order channel 2 is stored at address 1 of the four RAM locations corresponding to OPUC#0 and address 2 of the four RAM locations corresponding to OPUC#3, as shown below. Figure 10 As shown.

[0102] Based on the RAM matrix read / write rules of OUC4 in Example 1, and echoing the multiplexing strategy of OUCn, after writing data according to the write rules in step 101, the storage location of the input time slot data corresponding to the low-order channel 2 should be as follows: Figure 11 As shown.

[0103] When extracting low-level channel data, the data should be read in the following byte order:

[0104] 1st_TS1(0#OPUC)—1st_TS2(3#OPUC)—2st_TS1(0#OPUC)—2st_TS2(3#OPUC);

[0105] 3st_TS1(0#OPUC)—3st_TS2(3#OPUC)—4st_TS1(0#OPUC)—4st_TS2(3#OPUC).

[0106] like Figure 12 As shown, the steps for performing the read operation according to the reading rules in step 102 are as follows.

[0107] Step 501: Read the stst_reorder_cfg configuration to obtain the time slot information corresponding to the lower-order channel 2.

[0108] In this scenario, the stst_reorder_cfg configuration information read is as follows:

[0109] {7'd1,1'b1,7'd2} (2 channels, time slot sequence 1);

[0110] {7'd11,1'b1,7'd2} (2 channels, time slot sequence 11).

[0111] Step 502: After obtaining the time slot information, read stst_rd_cfg and barrel_sel_cfg to configure the RAM according to the time slot sequence number, and obtain the RAM read configuration strategy and barrel shift value.

[0112] In this scenario, the stst_rd_cfg configuration read is as follows:

[0113] Address 1: {(1'b1,2'd0,5'd1),(1'b1,2'd3,5'd2),(1'b1,2'd0,5'd1),(1'b1,2'd3,5'd2)};

[0114] Address 11: {(1'b1,2'd3,5'd2),(1'b1,2'd0,5'd1),(1'b1,2'd3,5'd2),(1'b1,2'd0,5'd1)}.

[0115] The read barrel_sel_cfg configuration is as follows:

[0116] Address 1: {2'd0};

[0117] Address 11: {2'd1}.

[0118] Step 503: Read and barrel shift the data according to the read configuration strategy and the barrel shift value.

[0119] The data read in these two steps are as follows Figure 13 The different background colors within the corresponding cells are used to distinguish the data, and the read data is arranged as follows:

[0120] 1st_TS1(0#OPUC)—1st_TS2(3#OPUC)—2st_TS1(0#OPUC)—2st_TS2(3#OPUC);

[0121] 4st_TS2(3#OPUC)—3st_TS1(0#OPUC)—3st_TS2(3#OPUC)—4st_TS1(0#OPUC).

[0122] The data after barrel displacement is as follows:

[0123] 1st_TS1(0#OPUC)—1st_TS2(3#OPUC)—2st_TS1(0#OPUC)—2st_TS2(3#OPUC);

[0124] 3st_TS1(0#OPUC)—3st_TS2(3#OPUC)—4st_TS1(0#OPUC)—4st_TS2(3#OPUC).

[0125] After steps 501-503, the data reading and integration can be completed, and the demultiplexed data needed for low-level business operations can be obtained.

[0126] As can be seen from the examples in this embodiment, the data obtained after writing and reading data according to the method provided in Embodiment 1 is consistent with the data expected to be obtained when extracting low-order channel data, indicating that the method provided in Embodiment 1 can complete OPC demultiplexing. Furthermore, the data processing process in this embodiment shows that the method provided in Embodiment 1 only requires a single-level RAM structure, and its logic is simple and easy to control.

[0127] Example 3:

[0128] Based on the OPUC demultiplexing methods provided in Embodiments 1 and 2 above, the present invention also provides an apparatus for implementing the above methods, such as... Figure 14 The diagram shown is a schematic representation of the device architecture according to an embodiment of the present invention. The OPCUC demultiplexing device of this embodiment includes one or more processors 11 and a memory 12. Figure 14 Take a processor 11 as an example.

[0129] Processor 11 and memory 12 can be connected via a bus or other means. Figure 14 Taking the example of a connection between China and Israel via a bus.

[0130] The memory 12 serves as a non-volatile computer-readable storage medium for the OPCUC demultiplexing method. It can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the OPCUC demultiplexing methods in Embodiments 1 and 2, which require demultiplexing OPCUC time slot data, as well as write and read rules. The processor 11 executes various functional applications and data processing of the OPCUC demultiplexing device by running the non-volatile software programs, instructions, and modules stored in the memory 12, thereby implementing the OPCUC demultiplexing methods of Embodiments 1 and 2.

[0131] The memory 12 includes at least two RAMs with the same data depth for use as RAM in the OPCUC demultiplexing methods provided in Embodiments 1 and 2. It may also include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 12 may optionally include memory remotely located relative to the processor 11, which can be connected to the processor 11 via a network for storing preset write and read rules to facilitate remote modification or upgrade of the write and read rules. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0132] The program instructions / modules are stored in memory 12. When executed by one or more processors 11, they perform the OPC demultiplexing method described in Embodiments 1 and 2 above, for example, performing the above-described... Figure 1 , Figures 3-5 The steps shown.

[0133] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), RAM, disk or optical disk, etc.

[0134] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for demultiplexing OPUC, characterized in that, Specifically, it includes: Configure at least two RAMs with the same data depth for each cascaded optical channel payload unit (OPUC) service to form a RAM matrix; When data is written, according to the time slot order of the OPC service, each time slot data is written to a specified depth in the specified RAM according to the writing rules; including: obtaining the corresponding depth of the current time slot in the specified RAM according to the correspondence between time slot and data depth; according to the matrix read / write algorithm of OPC and the multiplexing strategy of OPCCN, when the data envelopment is enabled, determining the order in which the current time slot data is stored in the RAM array according to the low-order channel information to which the time slot belongs, and obtaining the RAM number and depth address where the data is stored according to the order; When data is read out, according to the read out rules that match the write rules, the data at a specified depth in the RAM matrix is ​​read out in time slot order and spliced ​​together. The spliced ​​and integrated data is then used as the output of low-order channel services.

2. The OPUC demultiplexing method according to claim 1, characterized in that, The provision of at least two RAMs with consistent data depth for each optical channel payload unit (OPUC) service in cascaded transmission specifically includes: Each RAM is divided into two memory arrays based on the address depth to enable ping-pong switching. The data width of the RAM is one time slot data bit width, and the memory address depth of the RAM is twice the total number of OPUC service time slots.

3. The OPUC demultiplexing method according to claim 2, characterized in that, The method further includes: After each storage array is filled with timeslot data, the data read operation for that storage array is initiated to read low-level business data from that storage array.

4. The OPUC demultiplexing method according to claim 1, characterized in that, The step of reading and concatenating data at a specified depth in the RAM matrix according to time slot order based on read rules that match the write rules specifically includes: Based on the time slots occupied by the low-order channels and the write depth of the data in each RAM, obtain the address of the data to be read; According to the time slot polling order and the read rules corresponding to the time slots, the data in the specified RAM address is read out in sequence, and the read data is integrated.

5. The OPUC demultiplexing method according to claim 4, characterized in that, The step of obtaining the data address to be read based on the time slot occupied by the low-order channel and the write depth of the data in each RAM specifically includes: The low-order channel number and time slot corresponding to the data to be read are determined by the time slot polling configuration; Based on the acquired time slots and readout rules, determine the address of the data to be read from each RAM in the RAM matrix this time.

6. The OPUC demultiplexing method according to claim 5, characterized in that, The process of sequentially reading data from a specified RAM address according to the time slot polling order and the corresponding read rules for each time slot, and then integrating the read data, specifically includes: At each clock cycle, data at a specified address depth is read from each RAM. After the data in RAM is read, the read data is concatenated and integrated in sequence according to the RAM's sequential numbering.

7. The method for demultiplexing OPUC according to any one of claims 1-6, characterized in that, After reading and concatenating the data at a specified depth in the RAM matrix according to the time slot order, the process also includes: Based on the data arrangement order during splicing, the data content is barrel-shifted to adjust the corresponding time slot order of the read data.

8. An OPC demultiplexing device, characterized in that: It includes at least one processor and a memory, wherein the at least one processor and the memory are connected via a data bus; The memory stores instructions executable by the at least one processor, which, when executed by the processor, are used to perform the OPCUC demultiplexing method according to any one of claims 1-7; The memory includes at least two RAMs with the same data depth for use as RAM in the OPUC demultiplexing method according to any one of claims 1-7.

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