Full-bridge synchronous current sampling device

Abstract

The application discloses a full-bridge synchronous current sampling device, which comprises a full-bridge circuit, an input capacitor unit, a mutual inductor unit, a resistance unit, a driving chip and a synchronous sampling unit. The full-bridge circuit comprises first, second, third and fourth transistors and a first current mutual inductor. The first and second transistors are connected in series, and the third and fourth transistors are connected in series. The first end of the first current mutual inductor is arranged between the first and second transistors, and the second end of the first current mutual inductor is arranged between the third and fourth transistors. The input capacitor comprises a first capacitor and a second capacitor, and is arranged in parallel between a power input end Vin and a power input end PGND. The mutual inductor unit comprises second and third current mutual inductors. The second current mutual inductor is connected with the second transistor, and the third current mutual inductor is connected with the fourth transistor. The resistance unit comprises first, second and third resistors. The third resistor is connected with the second and third current mutual inductors. The driving chip is connected with the full-bridge circuit and the synchronous sampling unit.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a full-bridge synchronous current sampling device. Background Technology

[0002] In traditional full-bridge topology current sampling, the current transformer is usually placed on the Vin network, which is a high-side sampling method. In this method, only one current transformer can be used, which will result in a large current carrying capacity of the transformer under high power conditions, making it difficult to select the right transformer. Furthermore, the secondary winding of the transformer needs a diode for reverse protection, and the diode voltage drop varies greatly under three temperatures, causing the current limiting point to shift. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a full-bridge synchronous current sampling device that can solve the problems in the prior art.

[0004] The technical solution of this invention: A full-bridge synchronous current sampling device, wherein the device includes a full-bridge circuit, an input capacitor unit, a current transformer unit, a resistor unit, a driver chip, and a synchronous sampling unit. The full-bridge circuit includes a first transistor VA, a second transistor VB, a third transistor VC, a fourth transistor VD, and a first current transformer T1A. The first transistor VA and the second transistor VB are connected in series, and the third transistor VC and the fourth transistor VD are connected in series. One end of the first current transformer T1A is disposed between the first transistor VA and the second transistor VB, and the other end is disposed between the third transistor VC and the fourth transistor VD. The input capacitor includes a first capacitor C1 and a second capacitor C2, which are connected in parallel at the power supply input. Between the input terminal Vin and the power input terminal PGND, the current transformer unit includes a second current transformer T2 and a third current transformer T3. The second current transformer T2 is connected to the second transistor VB, and the third current transformer T3 is connected to the fourth transistor VD. The resistor unit includes a first resistor R1, a second resistor R2, and a third resistor R3. The third resistor R3 is connected to the second current transformer T2 and the third current transformer T3. The driving chip is connected to the full-bridge circuit. The synchronous sampling unit is connected to the driving chip. The synchronous sampling unit includes a first synchronous sampling transistor VE1 and a second synchronous sampling transistor VE2. The first resistor R1 is connected in parallel with the first synchronous sampling transistor VE1, and the second resistor R2 is connected in parallel with the second synchronous sampling transistor VE2.

[0005] Preferably, when the first transistor VA and the fourth transistor VD are turned on while the second transistor VB and the third transistor VC are turned off, the power current flows through the primary side of the third current transformer T3, forming an induced current flowing from the upper end VcsdA to the lower end Vcs on the secondary side of the third current transformer T3. The drive signal Vgd of the fourth transistor VD forms a drive signal OUTA through the drive chip to drive the first synchronous sampling transistor VE1 to turn on, forming an induced current flowing from the lower end AGND of the first synchronous sampling transistor VE1 to the upper end VcsdA and the lower end Vcs of the secondary side of the third current transformer T3, and forming a sampling voltage Vcs on the third resistor R3.

[0006] Preferably, when the second transistor VB and the third transistor VC are turned on while the first transistor VA and the fourth transistor VD are turned off, the power current flows through the primary side of the second current transformer T2, and an induced current is formed on the secondary side of the second current transformer T2, flowing from the upper end VcsdB to the lower end Vcs. The drive signal Vgb of the second transistor VB is used by the drive chip to form a drive signal OUTB to drive the second synchronous sampling transistor VE2 to turn on, forming an induced current flowing from the lower end AGND of the second synchronous sampling transistor VE2 to the upper end VcsdB and the lower end Vcs of the secondary side of the second current transformer T2, and forming a sampling voltage Vcs on the third resistor R3.

[0007] Preferably, the first synchronous sampling transistor VE1 and the second synchronous sampling transistor VE2 are metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0008] Preferably, the first transistor VA, the second transistor VB, the third transistor VC, and the fourth transistor VD are metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0009] The above technical solution allows for low-side current sampling using a synchronous sampling method. The number of current transformers is two, and the current stress of each current transformer is half of the original, allowing for the use of smaller transformers. At the same time, there is no need for diode reverse protection, there is no voltage drop, and the current limiting point is more accurate. Attached Figure Description

[0010] The accompanying drawings, which form part of this specification, are provided to further illustrate embodiments of the invention and, together with the textual description, explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0011] Figure 1 A schematic diagram of the power circuit of a full-bridge synchronous current sampling device provided in an embodiment of the present invention;

[0012] Figure 2 This is a schematic diagram of the sampling control circuit of a full-bridge synchronous current sampling device provided in an embodiment of the present invention. Detailed Implementation

[0013] Specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following description, specific details are set forth for purposes of explanation and not limitation, in order to aid in a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced in other embodiments departing from these specific details.

[0014] It should be noted that, in order to avoid obscuring the invention with unnecessary details, only the device structure and / or processing steps closely related to the solution according to the invention are shown in the accompanying drawings, while other details that are not closely related to the invention are omitted.

[0015] like Figure 1 and 2As shown, this embodiment of the invention provides a full-bridge synchronous current sampling device, which includes a full-bridge circuit, an input capacitor unit, a current transformer unit, a resistor unit, a driver chip, and a synchronous sampling unit. The full-bridge circuit includes a first transistor VA, a second transistor VB, a third transistor VC, a fourth transistor VD, and a first current transformer T1A. The first transistor VA and the second transistor VB are connected in series, and the third transistor VC and the fourth transistor VD are connected in series. One end of the first current transformer T1A is disposed between the first transistor VA and the second transistor VB, and the other end is disposed between the third transistor VC and the fourth transistor VD. The input capacitor includes a first capacitor C1 and a second capacitor C2, which are connected in parallel at the power input terminal. Between Vin and the power input terminal (input ground) PGND, the current transformer unit includes a second current transformer T2 and a third current transformer T3. The second current transformer T2 is connected to the second transistor VB, and the third current transformer T3 is connected to the fourth transistor VD. The resistor unit includes a first resistor R1, a second resistor R2, and a third resistor R3. The third resistor R3 is connected to the second current transformer T2 and the third current transformer T3. The driving chip is connected to the full-bridge circuit. The synchronous sampling unit is connected to the driving chip. The synchronous sampling unit includes a first synchronous sampling transistor VE1 and a second synchronous sampling transistor VE2. The first resistor R1 is connected in parallel with the first synchronous sampling transistor VE1, and the second resistor R2 is connected in parallel with the second synchronous sampling transistor VE2.

[0016] The driving signals for the first transistor VA, the second transistor VB, the third transistor VC, and the fourth transistor VD are Vga, Vgb, Vgc, and Vgd, respectively.

[0017] The above technical solution allows for low-side current sampling using a synchronous sampling method. The number of current transformers is two, and the current stress of each current transformer is half of the original, allowing for the use of smaller transformers. At the same time, there is no need for diode reverse protection, there is no voltage drop, and the current limiting point is more accurate.

[0018] in, Figure 1 The power circuit of the full-bridge synchronous current sampling device is shown. The power circuit includes a full-bridge circuit, an input capacitor unit, a current transformer unit, and a third resistor. Figure 2 The sampling control circuit of the full-bridge synchronous current sampling device is shown. The sampling control circuit includes a driver chip (MOSTETA driver chip), a synchronous sampling unit, a first resistor, and a second resistor.

[0019] exist Figure 1 and 2In the diagram, VSSA, VSSB, VSSC, and VSSD represent the control ground of the first transistor VA, the control ground of the second transistor VB, the control ground of the third transistor VC, and the control ground of the fourth transistor VD, respectively; Vddp1 represents the 5V supply voltage of the N1 driver chip, and VCC represents the 12V supply voltage of the N1 driver chip.

[0020] According to one embodiment of the present invention, when the first transistor VA and the fourth transistor VD are turned on while the second transistor VB and the third transistor VC are turned off, a power current flows through the primary side of the third current transformer T3, and an induced current is formed on the secondary side of the third current transformer T3, flowing from the upper end (secondary ground) VcsdA to the lower end Vcs. The drive signal Vgd of the fourth transistor VD is used by the drive chip to form a drive signal OUTA to drive the first synchronous sampling transistor VE1 to turn on, forming an induced current flowing from the lower end AGND of the first synchronous sampling transistor VE1 to the upper end VcsdA and the lower end Vcs of the secondary side of the third current transformer T3, and forming a sampling voltage Vcs on the third resistor R3.

[0021] In this path, the third resistor R3 is the maximum resistance, so the sampling voltage Vcs is a lossless sampling voltage. Furthermore, when the second transistor VB and the third transistor VC are off, the drive signal Vgb of the second transistor VB is low, therefore the drive signal OUTB is low, the second synchronous sampling transistor VE2 is off, and the sampling voltage Vcs will not pass through VcsdB.

[0022] According to one embodiment of the present invention, when the second transistor VB and the third transistor VC are turned on while the first transistor VA and the fourth transistor VD are turned off, the power current flows through the primary side of the second current transformer T2, and an induced current is formed on the secondary side of the second current transformer T2, flowing from the upper end (secondary ground) VcsdB to the lower end Vcs. The drive signal Vgb of the second transistor VB is used by the drive chip to form a drive signal OUTB to drive the second synchronous sampling transistor VE2 to turn on, forming an induced current flowing from the lower end AGND of the second synchronous sampling transistor VE2 to the upper end VcsdB and the lower end Vcs of the secondary side of the second current transformer T2, and forming a sampling voltage Vcs on the third resistor R3.

[0023] In this path, the third resistor R3 is the maximum resistance, so the sampling voltage Vcs is a lossless sampling voltage. Furthermore, when the first transistor VA and the fourth transistor VD are off, the drive signal Vgd of the fourth transistor VD is low, therefore the drive signal OUTA is low, the first synchronous sampling transistor VE1 is off, and the sampling voltage Vcs will not pass through VcsdA.

[0024] According to one embodiment of the present invention, the first synchronous sampling transistor VE1 and the second synchronous sampling transistor VE2 are metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0025] According to one embodiment of the present invention, the first transistor VA, the second transistor VB, the third transistor VC and the fourth transistor VD are metal-oxide-semiconductor field-effect transistors (MOSFETs) (primary power MOSFETs).

[0026] At the end of a complete switching cycle, the sampling voltage Vcs (low-side sampling mode) obtained by the full-bridge synchronous current sampling device described in this invention is the same as the voltage under the high-side sampling mode, and the primary current of the current transformer drops to 1 / 2. The secondary side uses a MOSFET instead of the anti-reverse diode, which does not cause a voltage drop.

[0027] As can be seen from the above embodiments, the current stress of each current transformer in the full-bridge synchronous current sampling device described in the above embodiments of the present invention is half of the original, allowing the use of smaller current transformers; furthermore, the current sampling voltage does not require diode reverse protection, there is no voltage drop, and the current limiting point is more accurate. The present invention is applicable to all full-bridge topologies, including hard-switching symmetrical full-bridge and soft-switching asymmetrical full-bridge circuits.

[0028] The features described and / or illustrated above with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, and / or in combination with or in lieu of features in other embodiments.

[0029] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, components, or combinations thereof.

[0030] The apparatus and methods described above can be implemented in hardware or in combination with software. This invention relates to computer-readable programs that, when executed by a logic component, enable that logic component to implement the apparatus or constituent parts described above, or to implement the various methods or steps described above. This invention also relates to storage media for storing the above programs, such as hard disks, magnetic disks, optical disks, DVDs, flash memory, etc.

[0031] Many features and advantages of these embodiments are apparent from this detailed description, and therefore the appended claims are intended to cover all such features and advantages of these embodiments that fall within their true spirit and scope. Furthermore, since many modifications and alterations will readily occur to those skilled in the art, the embodiments of the invention are not intended to be limited to the precise structures and operations illustrated and described, but rather to encompass all suitable modifications and equivalents falling within their scope.

[0032] The parts of this invention not described in detail are techniques known to those skilled in the art.

Claims

1. A full-bridge synchronous current sampling device, characterized in that, The device includes a full-bridge circuit, an input capacitor unit, a current transformer unit, a resistor unit, a driver chip, and a synchronous sampling unit. The full-bridge circuit includes a first transistor VA, a second transistor VB, a third transistor VC, a fourth transistor VD, and a first current transformer T1A. The first transistor VA and the second transistor VB are connected in series, and the third transistor VC and the fourth transistor VD are connected in series. One end of the first current transformer T1A is located between the first transistor VA and the second transistor VB, and the other end is located between the third transistor VC and the fourth transistor VD. The input capacitor includes a first capacitor C1 and a second capacitor C2, which are connected in parallel between the power input terminal Vin and the power input terminal PG. Between ND, the current transformer unit includes a second current transformer T2 and a third current transformer T3. The second current transformer T2 is connected to the second transistor VB, and the third current transformer T3 is connected to the fourth transistor VD. The resistor unit includes a first resistor R1, a second resistor R2, and a third resistor R3. The third resistor R3 is connected to the second current transformer T2 and the third current transformer T3. The driving chip is connected to the full-bridge circuit. The synchronous sampling unit is connected to the driving chip. The synchronous sampling unit includes a first synchronous sampling transistor VE1 and a second synchronous sampling transistor VE2. The first resistor R1 is connected in parallel with the first synchronous sampling transistor VE1, and the second resistor R2 is connected in parallel with the second synchronous sampling transistor VE2.

2. The apparatus according to claim 1, characterized in that, When the first transistor VA and the fourth transistor VD are turned on while the second transistor VB and the third transistor VC are turned off, the power current flows through the primary side of the third current transformer T3, and an induced current is formed on the secondary side of the third current transformer T3, flowing from the upper end VcsdA to the lower end Vcs. The drive signal Vgd of the fourth transistor VD is used by the drive chip to form a drive signal OUTA to drive the first synchronous sampling transistor VE1 to turn on, forming an induced current flowing from the lower end AGND of the first synchronous sampling transistor VE1 to the upper end VcsdA and the lower end Vcs of the secondary side of the third current transformer T3, and forming a sampling voltage Vcs on the third resistor R3.

3. The apparatus according to claim 2, characterized in that, When the second transistor VB and the third transistor VC are turned on while the first transistor VA and the fourth transistor VD are turned off, the power current flows through the primary side of the second current transformer T2, and an induced current is formed on the secondary side of the second current transformer T2, flowing from the upper end VcsdB to the lower end Vcs. The drive signal Vgb of the second transistor VB is used by the drive chip to form a drive signal OUTB to drive the second synchronous sampling transistor VE2 to turn on, forming an induced current flowing from the lower end AGND of the second synchronous sampling transistor VE2 to the upper end VcsdB and the lower end Vcs of the secondary side of the second current transformer T2, and forming a sampling voltage Vcs on the third resistor R3.

4. The apparatus according to claim 1, characterized in that, The first synchronous sampling transistor VE1 and the second synchronous sampling transistor VE2 are metal-oxide-semiconductor field-effect transistors (MOSFETs).

5. The apparatus according to claim 1, characterized in that, The first transistor VA, the second transistor VB, the third transistor VC, and the fourth transistor VD are metal-oxide-semiconductor field-effect transistors (MOSFETs).

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