A high integration 64-channel infrared video processor

Abstract

A kind of high integration 64 channel infrared video processor, including infrared signal processing component and focal plane component, and the size of main body is only 220mm*150mm*105mm, and weight is only 5kg.The present application solves the problems of high orbit super large area array infrared detector, such as many channels, fast readout rate, high real-time image processing on orbit, large data processing capacity, etc., with the progress of simplifying system complexity and improving system integration;At the same time, it solves the problems of traditional large area array infrared detector, such as many output analog channels, large amount of image data real-time processing pressure, leading to traditional infrared video processor, such as many, large volume, heavy weight, poor data transmission capacity, insufficient single video real-time data processing capacity, etc., with the progress of simultaneously collecting detector channel number reaching 64, detector readout rate reaching more than 10MHz, video circuit noise being better than 0.5mV, more than 10 data transmission channels and single transmission rate being up to more than 10Gbps, maximum real-time data throughput being 64Gbit and processing rate being higher than 1Gbps, high integration, miniaturization and light weight.

Description

Technical Field

[0001] This invention relates to a highly integrated 64-channel infrared video processor, belonging to the field of electronic engineering technology. Background Technology

[0002] With the continuous development of my country's aerospace industry, in order to strengthen information technology construction and provide stable, timely, and reliable basic geographic information for national economic development, the proportion of infrared observation satellites is gradually increasing, and the demand for ultra-wide field-of-view infrared observation is becoming increasingly high. To obtain high-orbit detection capabilities with a wider field of view and larger coverage, spaceborne ultra-wide field-of-view infrared cameras have entered a period of comprehensive development. A spaceborne infrared camera mainly consists of three parts: an infrared detector, an infrared video processor, and a cooling system. The most direct part of infrared imaging is the infrared video processor. The infrared video processor is divided into an infrared signal processing component and a focal plane component. The infrared video processor mainly realizes the acquisition of 64 analog signals from the infrared detector and the real-time processing of massive image data. It arranges and outputs the data to the data transmission and data processor according to the image format requirements, while providing the power, bias, and timing control signals required by the detector. Through remote control and telemetry with an external management controller, it achieves the goal of real-time response to ground commands and integrated high-orbit marine observation.

[0003] In the early stages of spaceborne infrared camera development, infrared video processors typically consisted of power supply components, interface components, signal processing components, and focal plane components. Focal plane components were generally built using simple analog circuits. These analog circuits were complex to design, had poor noise levels, and a single infrared video processor could only receive a limited number of analog channels from the detectors. Typically, one analog channel corresponded to one AD acquisition unit, and the various operational amplifiers at the AD front end further contributed to the large size of the focal plane component alone. Moreover, the diverse types of power supplies and bias voltages required by the detectors, along with the numerous power supply paths required by the infrared video processor itself, resulted in a large and complex power supply component. The signal processing component, considering on-orbit reliability, required antifuse FPGAs for uploading and refreshing control, and the use of high-grade components also limited its size and capacity for processing large amounts of image data. As the size of infrared detector arrays has increased significantly, and the number of detector output channels and readout rates have multiplied, the noise level, processing speed, and integration of single infrared video processors need further improvement. Traditional infrared video processors struggle to meet the requirements of high processing power, high integration, miniaturization, and light weight in aerospace applications. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a highly integrated 64-channel infrared video processor that achieves high integration, miniaturization, light weight, and strong computing power.

[0005] The technical solution provided by this invention is as follows:

[0006] A highly integrated 64-channel infrared video processor includes: an infrared signal processing component and a focal plane component;

[0007] The infrared signal processing component is used to receive remote control commands, external synchronization control signals, betting refresh control signals, parameter packets, instruction packets, blind element coordinates, correction coefficients, and betting programs sent by the external management controller, and simultaneously feeds back telemetry data to the external management controller.

[0008] The infrared video processor's operating mode is adjusted according to remote control commands. The presence or absence of an external synchronization control signal determines whether the infrared video processor performs autonomous or program-controlled imaging. The uploading refresh control signal controls the uploading refresh module registers in the infrared signal processing component, and the parameter and instruction packets are parsed to obtain the latest operating parameters and commands for controlling the infrared video processor. The new blind pixel coordinates obtained from uploading replace the old coordinate file in the MRAM module of the infrared signal processing component. The new correction coefficients obtained from uploading are stored in the FLASH module of the infrared signal processing component; these new correction coefficients are used for real-time non-uniformity correction. The new uploading program is loaded when the infrared video processor is powered off and restarted.

[0009] The infrared signal processing component amplifies and converts the 64 analog signals received from the focal plane component into high-speed signals, which are then fed into the FPGA minimum system within the infrared signal processing component. This enables the high-speed transmission of image data to external data transmission and processing units. Simultaneously, it generates control signals for AD acquisition and numerical control signals for the focal plane component, enabling adjustable bias voltage, infrared detector control, and data reading and writing.

[0010] The infrared signal processing component also has the function of feeding back telemetry data such as infrared video processor bus status, reset count, correct / incorrect instruction packet count, detector gain / integration time chip number / integration time adjustment mode / integration time, imaging mode and programmable imaging non-response count, working mode and algorithm switch, correction coefficient write-erase status, parameter / instruction upload error packet sequence number, upload refresh telemetry data to the management controller.

[0011] The focal plane assembly completes the digital and analog power conversion required by itself through the onboard secondary power supply, and provides the analog and digital power required by the detector. The fixed bias voltage required by the infrared detector is generated by the fixed bias voltage module in the focal plane assembly. The numerical control signal generated by the infrared signal processing component generates the adjustable bias voltage required by the infrared detector through the adjustable bias voltage module, and at the same time, the numerical control signal generated by the infrared signal processing component is transmitted to the infrared detector.

[0012] The focal plane assembly receives 64 analog signals output by the detector, which are then transmitted to the infrared signal processing assembly after impedance transformation by the first-stage operational amplifier. At the same time, the temperature measurement signal from the detector is transmitted out.

[0013] Furthermore, the infrared signal processing component includes: a CAN bus interface, an anti-static module, a second-stage operational amplifier module, a reference power supply module, an AD acquisition module, a data transmission module, an FPGA minimum system, a first power supply and analog channel interface, an MRAM module, a buffer module, a power filtering module, an onboard secondary power supply, a DDR3 module, a FLASH module, and an uploading refresh module.

[0014] The infrared signal processing component receives the controlled low-voltage secondary power input from the external secondary power supply, filters it through the power filtering module, and the filtered controlled low-voltage secondary power is used by the onboard secondary power supply to generate all the digital power required by the infrared signal processing component.

[0015] The FPGA minimum system receives remote control commands from an external management controller via a CAN bus interface. The remote control command information is parsed and includes settings for detector gain, detector integration time, imaging mode, operating mode, algorithm switch, image data output switch, calibration coefficient write / erase settings, and bias voltage. The detector gain, detector integration time, and bias voltage settings are sent to the focal plane assembly via the first power supply and analog channel interfaces. Simultaneously, 64 analog signals from the focal plane assembly are received from the first power supply and analog channel interfaces and fed into the second-stage operational amplifier module. Meanwhile, the reference power supply module generates the reference voltage required by the second-stage operational amplifier module. The second-stage operational amplifier module converts the single-ended analog signal into a differential signal, which then enters the AD acquisition module. The AD acquisition module performs analog-to-digital processing and converts the analog signal into a high-speed digital signal, which then enters the FPGA minimum system.

[0016] The FPGA minimum system first calls the blind pixel coordinate file in the MRAM module to complete the blind pixel replacement when it receives the image data. After the blind pixel replacement, the image data is written to the DDR3 module in real time to complete the non-uniformity correction processing. The correction coefficient is entered into the calibration mode when the working mode is set to calibration mode. It is calculated in real time in the DDR3 module. The corrected image data is processed by the DDR3 module and read out according to a certain mode set in the working mode, either single integral time exposure or large dynamic multi-level integral time fusion exposure. After the image data output switch is set to on, the image data is transmitted to the data transmission and data processor in real time by the data transmission module.

[0017] The FPGA minimum system receives external synchronization control signals from an external management controller via the CAN bus interface, and determines whether the infrared signal processing component enters autonomous imaging or programmable imaging in conjunction with the imaging mode setting control commands.

[0018] The FPGA minimum system receives parameter packets and instruction packets from an external management controller via the CAN bus interface. The infrared signal processing component is configured according to the new parameters and executes the new instruction set.

[0019] The FPGA minimum system receives the blind pixel coordinates provided by the external management controller through the CAN bus interface, writes the new coordinates into the MRAM module, and reads the new blind pixel table to replace the image blind pixels when imaging again.

[0020] The FPGA minimum system receives the correction coefficients provided by the external management controller through the CAN bus interface, and writes the new correction coefficients into the FLASH module first by erasing the FLASH module according to the calibration coefficients and the erase setting command.

[0021] The uploading and refresh module receives uploading and refresh control signals from the external management controller via a serial port, completes the configuration of the uploading and refresh module registers, and then feeds back the latest telemetry status of the uploading and refresh module to the external management controller via the CAN bus interface. The uploading and refresh module receives uploading programs from the external management controller via a serial port and writes them into the FLASH memory in the uploading and refresh module. When the FPGA minimum system is powered off and reconfigured, the new uploading program is called, or the new uploading program is called during refresh and reload.

[0022] The anti-static module receives the configuration program from the JTAG process test interface and writes it into the FPGA minimum system; the buffer module receives the numerical control signals from the FPGA minimum system to control the MRAM module, FLASH module, and AD acquisition module, and at the same time transmits the numerical control signals to the focal plane assembly and infrared detector through the first power supply and analog channel interface.

[0023] Furthermore, the focal plane assembly includes: a second power supply and analog channel interface, a first-stage operational amplifier module, an adjustable bias module, a fixed bias module, a power supply module, an onboard secondary power supply, a power supply filtering module, and a temperature measurement signal;

[0024] The focal plane assembly receives controlled low-voltage secondary power from the secondary power input. After being filtered by the power filtering module, the filtered controlled low-voltage secondary power is used by the onboard secondary power supply to generate the digital and analog power required by the focal plane assembly. At the same time, the digital and analog power required by the detector output from the onboard secondary power supply is sent to the external infrared detector through the power supply module. The analog power required by the infrared signal processing component output from the onboard secondary power supply is sent to the infrared signal processing component through the second power supply and analog channel interface. The analog power output from the onboard secondary power supply is sent to the fixed bias module to generate the fixed bias required by the external detector.

[0025] The second power supply and analog channel interface receive the numerical control signals generated by the infrared signal processing component and transmit them to the external infrared detector and adjustable bias module. This controls the integration time, gain, and master clock of the infrared detector, while simultaneously controlling the adjustable bias module to generate the bias voltage required by the infrared detector. The first-stage operational amplifier module receives 64 analog signals output from the external detector, performs impedance transformation, and then sends them to the infrared signal processing component through the second power supply and analog channel interface.

[0026] Furthermore, the uploading refresh module includes: an interface chip, a refresh chip, a crystal oscillator, and a FLASH;

[0027] The interface chip uses 422 level, UART interface protocol and data rate for transmission, and twisted pair cable for transmission. After receiving the uploading and refresh control signal from the external management controller, the refresh chip parses the instruction and configures its internal register state. The external crystal oscillator provides the main clock required by the refresh chip for operation. The refresh chip feeds back the telemetry status to the FPGA minimum system, and then sends it to the external management controller through the CAN bus interface. The uploading and refresh module also receives the uploading program from the external management controller and stores the uploading program in the FLASH memory of the uploading and refresh module. The uploading and refresh module has two FLASH memory chips, one for storing the default configuration program and the other for both backup of the default configuration program and storage of the uploading program. Based on the configuration instructions received from the CAN bus interface, the module selects either the default program or the uploading program for configuring the FPGA minimum system.

[0028] Furthermore, the onboard secondary power supply includes: a DC / DC converter and a low-dropout regulator;

[0029] The onboard secondary power supply uses a DC / DC converter to directly convert the filtered, controlled low-voltage secondary power transmitted from the external secondary power supply into a high-current digital power supply required by the infrared signal processing components. Then, it passes through a low-dropout regulator to generate the remaining secondary power supply required by the onboard power supply.

[0030] Furthermore, the reference power supply module includes: a reference voltage chip and an operational amplifier;

[0031] The reference power supply module enhances the driving capability of the reference power generated by the reference voltage chip through operational amplifiers, meeting the reference voltage and driving capability required by the second-stage operational amplifier module, and is used for adjusting the amplitude and changing the dynamic range of analog signals.

[0032] Furthermore, the FPGA minimum system includes: an FPGA chip, a reset circuit, and a reference crystal oscillator;

[0033] The core of the FPGA minimum system is an FPGA chip with radiation resistance, a reset circuit provides a reset signal to the FPGA, and a reference crystal provides a reference clock to the FPGA.

[0034] Furthermore, the fixed bias module includes: a reference voltage chip, an operational amplifier, and a transistor;

[0035] The fixed bias module converts the reference power generated by the reference voltage chip into the fixed bias voltage required by the detector. It enhances the load-carrying capacity of the bias voltage through operational amplifiers and enhances the drive current capacity of the bias voltage through transistors, thus meeting the fixed bias voltage and drive capacity required by the infrared detector.

[0036] Furthermore, the infrared video processor has two operating modes: imaging mode and calibration mode.

[0037] In imaging mode, the infrared video processor checks the external synchronization control signal each time the camera is powered on for imaging. If no external synchronization control signal is detected, the infrared video processor generates an autonomous imaging synchronization control signal to enable the camera to autonomously image and output the image. When the "imaging mode" command is received, the infrared video processor outputs image data.

[0038] The imaging mode workflow is as follows: the external management controller is powered on first and sends an external synchronization control signal to the infrared video processor. Then the infrared video processor is powered on. After the power-on initialization is completed, if it receives an external synchronization control signal within a certain period of time, it enters the programmable imaging mode; if it does not receive an external synchronization control signal, it generates a frame synchronization signal itself and enters the autonomous imaging mode.

[0039] Start collecting image data from the large-area infrared detector, format and arrange the image data according to the image format, output image data when the working mode setting instruction is received to imaging mode, and perform multi-level integration time adjustment and multi-frame image fusion output when the upper parameter setting instruction is received.

[0040] If a "Set Integration Time" command is received, the single-command integration time adjustment is completed, and a single integration time image is output.

[0041] Furthermore, the calibration mode is divided into "normal temperature calibration mode" and "high temperature calibration mode";

[0042] When the "normal temperature calibration mode" command is received, the camera's heat exchanger is turned off, and low-temperature calibration is performed using multiple integration times. The infrared video processor collects low-temperature calibration data. Afterward, the camera's heat exchanger is turned on to heat up, and then turned off again once the temperature is reached.

[0043] When the camera receives the "high temperature calibration mode" command, it performs high temperature calibration with multiple integration times, the infrared video processor collects high temperature data, and then enters the ground imaging mode; the infrared video processor completes the calculation of the non-uniformity correction coefficient.

[0044] Furthermore, in calibration mode, the camera only performs single-integration-time exposure. The calibration mode workflow is as follows: the external management controller is powered on first and sends an external synchronization control signal to the infrared video processor. Then, the infrared video processor is powered on. After power-on initialization, if it receives an external synchronization control signal within a certain time, it enters the programmable imaging mode. If it does not receive an external synchronization control signal, it generates its own frame synchronization signal and enters the autonomous imaging mode. It begins to acquire image data from the large-area infrared detector, formats and arranges the image data according to the image format, and outputs image data when it receives the working mode setting instruction to imaging mode. At this time, the hot spot is turned off, and the "blind pixel replacement algorithm setting instruction" is received. After the blind element replacement is enabled, the short integration time setting is completed. Upon receiving the "Working Mode Setting Instruction - Short Integration Low Temperature Calibration Mode", the short integration low temperature calibration image data is output. Then, the long integration time setting is completed, and upon receiving the "Working Mode Setting Instruction - Long Integration Low Temperature Calibration Mode", the long integration low temperature calibration image data is output. Then, the hot spot is enabled, the hot spot temperature is increased, and after reaching the set temperature, the hot spot is disabled. After completing the short integration time setting, the "Working Mode Setting Instruction - Short Integration High Temperature Calibration Mode" is received, and the short integration high temperature calibration image data is output. Then, the long integration time setting is completed, and upon receiving the "Working Mode Setting Instruction - Long Integration High Temperature Calibration Mode", the long integration high temperature calibration image data is output. Then, the hot spot is enabled, and upon receiving the "Non-uniform Correction Algorithm Setting Instruction - Non-uniform Correction Enabled", the non-uniform correction image data is output.

[0045] The advantages of this invention compared to the prior art are:

[0046] (1) This invention adopts domestically produced FPGA + large-capacity DDR3 data storage and processing technology, which overcomes the problem of high pressure and tight resources in real-time processing of massive image data in orbit of traditional large-area infrared images. By rationally allocating storage resources, caching and pipeline processing of massive data, the real-time data throughput can reach up to 64Gbit and the processing rate is higher than 1Gbps. This achieves the technical level of real-time on-orbit non-uniformity correction and image fusion processing of massive image data.

[0047] (2) This invention adopts a highly integrated circuit hardware modular design technology, which solves the problems of large number of infrared video processors, large size and heavy weight caused by the large number of output channels of traditional large-area array detectors. The body size of a single infrared video processor is only 220mm*150mm*105mm and the weight is only 5kg, which has the advancement of high integration, miniaturization and light weight.

[0048] (3) This invention adopts a highly integrated circuit hardware modular design technology to overcome the difficulties of high-orbit ultra-large array infrared detectors, such as a large number of channels, fast readout rate, high real-time performance of on-orbit image processing, large data processing volume, high noise, and poor data transmission capability. It achieves the effect of simultaneously acquiring 64 detector channels, detector readout rate of more than 10MHz, video circuit noise better than 0.5mV, more than 10 data transmission channels, and a single channel transmission rate of more than 10Gbps. At the same time, the processing capability of this highly integrated miniaturized infrared video processor reaches the leading level in China, providing technical support for China's first ultra-large field-of-view large array integrated marine observation satellite. Attached Figure Description

[0049] Figure 1 This is a block diagram illustrating the design principle of the highly integrated 64-channel infrared video processor of this invention. Detailed Implementation

[0050] like Figure 1 As shown, the highly integrated 64-channel infrared video processor proposed in this invention includes two main parts: an infrared signal processing component and a focal plane component.

[0051] The infrared signal processing components include: CAN bus interface, anti-static module, second-stage operational amplifier module, reference power supply module, AD acquisition module, data transmission module, FPGA minimum system, first power supply and analog channel interface, MRAM module, buffer module, power filtering module, onboard secondary power supply, DDR3 module, FLASH module, and uploading refresh module.

[0052] The focal plane assembly includes a second power supply and analog channel interface, a first-stage operational amplifier module, an adjustable bias module, a fixed bias module, a power supply module, an onboard secondary power supply, and a power supply filtering module.

[0053] The infrared signal processing component is used to receive remote control commands, external synchronization control signals, uploading refresh control signals, parameter packets, instruction packets, blind element coordinates, correction coefficients, uploading programs, etc. sent by the external management controller via the CAN bus interface, and simultaneously feeds back telemetry data to the external management controller.

[0054] The infrared video processor's operating mode is adjusted according to remote control commands. The presence or absence of an external synchronization control signal determines whether the infrared video processor performs autonomous or program-controlled imaging. The uploading refresh control signal controls the uploading refresh module registers in the infrared signal processing component, and the parameter and instruction packets are parsed to obtain the latest operating parameters and commands for controlling the infrared video processor. The new blind pixel coordinates obtained from uploading replace the old coordinate file in the MRAM module of the infrared signal processing component. The new correction coefficients obtained from uploading are stored in the FLASH module of the infrared signal processing component; these new correction coefficients are used for real-time non-uniformity correction. The new uploading program is loaded when the infrared video processor is powered off and restarted.

[0055] The infrared signal processing component amplifies and converts the 64 analog signals received from the focal plane component into high-speed signals, which are then fed into the FPGA minimum system within the infrared signal processing component. This enables the high-speed transmission of image data to external data transmission and processing units. Simultaneously, it generates control signals for AD acquisition and numerical control signals for the focal plane component, enabling adjustable bias voltage, infrared detector control, and data reading and writing.

[0056] The focal plane assembly completes the digital and analog power conversion required by itself through the onboard secondary power supply, and provides the analog and digital power required by the detector. The fixed bias voltage required by the infrared detector is generated by the fixed bias voltage module in the focal plane assembly. The numerical control signal generated by the infrared signal processing component generates the adjustable bias voltage required by the infrared detector through the adjustable bias voltage module, and at the same time, the numerical control signal generated by the infrared signal processing component is transmitted to the infrared detector.

[0057] The focal plane assembly receives 64 analog signals output by the detector, which are then transmitted to the infrared signal processing assembly after impedance transformation by the first-stage operational amplifier. At the same time, the temperature measurement signal from the detector is transmitted out.

[0058] The infrared video processor mainly operates in two modes: "imaging" mode and "calibration" mode.

[0059] In "Imaging" mode, the video processor checks for external synchronization control signals each time the camera powers on. If no external synchronization control signal is detected, the video processor generates an autonomous imaging synchronization control signal to enable autonomous imaging output. Upon receiving an "Imaging Mode" command, the video processor outputs image data. The imaging mode workflow is as follows: the external management controller powers on first and sends an external synchronization control signal to the infrared video processor. Then, the infrared video processor powers on. After initialization, if an external synchronization control signal is received within a certain time, it enters the programmable imaging mode (if no external synchronization control signal is received, it generates its own frame synchronization signal and enters autonomous imaging mode). It then begins acquiring image data from the large-area infrared detector, formats and arranges the image data according to the image format, and outputs image data when a working mode setting command for imaging mode is received. When a parameter setting command (multi-level integration time cyclic adjustment) is received, multi-level integration time adjustment and multi-frame image fusion output are performed. If a single command ("Integration Time Setting" command) is received, single-command integration time adjustment is completed, and a single-integration time image is output. In summary, in imaging mode, the camera can perform single integration time exposure or multi-stage integration time exposure.

[0060] In calibration mode, there are two modes: "normal temperature calibration mode" and "high temperature calibration mode." When the "normal temperature calibration mode" command is received, the camera's heatsink is turned off, and multi-stage integration time low-temperature calibration is performed, with video data acquisition for low-temperature calibration. Afterward, the camera's heatsink is turned on to raise the temperature, and then turned off again once the desired temperature is reached. When the "high temperature calibration mode" command is received, the camera performs multi-stage integration time high-temperature calibration, with video data acquisition for high-temperature calibration, and then enters ground-level imaging mode. The video processor calculates the non-uniformity correction coefficients. In calibration mode, the camera only performs single-integration-time exposures. The calibration mode workflow is as follows: The external management controller is powered on first and sends an external synchronization control signal to the infrared video processor. Then, the infrared video processor is powered on. After power-on initialization, if it receives an external synchronization control signal within a certain time, it enters the programmable imaging mode (if it does not receive an external synchronization control signal, it generates its own frame synchronization signal and enters the autonomous imaging mode). It begins to acquire image data from the large-area infrared detector and formats and arranges the image data according to the image format. When it receives the working mode setting instruction to imaging mode, it outputs image data. At this time, the hot spot is turned off, and it receives the "blind pixel replacement algorithm setting instruction - blind pixel replacement on" (sent only when the image needs non-uniform correction). It completes the short integration time setting, receives the "working mode setting instruction - short integration low temperature calibration mode", outputs short integration low temperature calibration image data, and then completes the long integration time setting. It receives the "working mode setting instruction - long integration low temperature calibration mode" and outputs long integration low temperature calibration image data. Then the hot spot is turned on, the hot spot heats up, and after reaching the set temperature, the hot spot is turned off. The short integration time setting is completed, and the "Working Mode Setting Instruction - Short Integration High Temperature Calibration Mode" is received. Short integration high temperature calibration image data is output. Then the long integration time setting is completed, and the "Working Mode Setting Instruction - Long Integration High Temperature Calibration Mode" is received. Long integration high temperature calibration image data is output. Then the hot spot is turned on, and the "Non-uniform Correction Algorithm Setting Instruction - Non-uniform Correction On" is received. Non-uniform correction image data is output.

[0061] The infrared signal processing component controls the registers of the up-refresh module according to the up-refresh control signal, and parses the parameter package and instruction package to obtain the latest operating parameters and instructions for controlling the infrared video processor. The parameter package includes up-refresh parameter package with multi-level integration time cyclic adjustment, up-refresh parameter package with multi-level integration time cyclic exposure image fusion, correction coefficient parameter package, and blind cell coordinate parameter package. The instruction package includes detector gain setting instruction, integration time setting instruction, algorithm switching instruction, calibration coefficient write / erase instruction, and adjustable bias voltage instruction.

[0062] The infrared signal processing component replaces the old coordinate file in the MRAM module with the new blind element coordinates obtained above, and stores the new correction coefficients obtained above in the FLASH module. When the new correction coefficients are needed, they are loaded into the DDR3 module for real-time non-uniformity correction.

[0063] The infrared signal processing component stores the new uploading program obtained from the uploading process in the spare FLASH of the uploading refresh module. When needed, the infrared video processor is powered off and restarted to load the new uploading program.

[0064] The infrared signal processing component receives 64 analog signals through the first power supply and analog channel interface, which are then fed into the second-stage operational amplifier module. The second-stage operational amplifier module is provided with a reference voltage by the reference power supply module. After processing by the second-stage operational amplifier module, the 64 analog signals are converted into high-speed signals by the AD acquisition module and then enter the FPGA minimum system. The massive image data is then transmitted at high speed to the data transmission and data processor through the data transmission module. At the same time, the buffer module generates control signals for the AD acquisition module, the adjustable bias module, and the detector, as well as data read and write operations.

[0065] The infrared signal processing component also has the function of feeding back telemetry data such as infrared video processor bus status, reset count, correct / incorrect instruction packet count, detector gain / integration time chip number / integration time adjustment mode / integration time, imaging mode and programmable imaging non-response count, working mode and algorithm switch, correction coefficient write-erase status, parameter / instruction upload error packet sequence number, upload refresh telemetry data to the management controller.

[0066] The infrared signal processing component generates its own required secondary power supply through the onboard secondary power supply, based on the controlled low-voltage secondary power supply generated by the external secondary power supply.

[0067] The following is a detailed introduction to each module.

[0068] 1. The infrared signal processing component receives controlled low-voltage secondary power from the secondary power input. After filtering by the power filter module, the filtered controlled low-voltage secondary power is used by the onboard secondary power supply to generate all the digital power required by the infrared signal processing component. The onboard secondary power supply uses a DC / DC converter to directly convert the filtered controlled low-voltage secondary power from the external secondary power supply into the high-current digital power required by the infrared signal processing component. Then, it is used by a low-dropout regulator to generate the remaining secondary power required by the onboard power supply. Since the DC / DC module required for traditional secondary power conversion is large and requires a separate secondary power conversion circuit, the power supply module of the infrared signal processing component in this invention is integrated on the infrared signal processing component, eliminating the need for a separate secondary power conversion circuit. Moreover, the selected DC / DC converter is small in size and has a high number of channels, thereby improving the integration of the product and reducing its size and weight.

[0069] 2. The core of the FPGA minimum system of the infrared signal processing component is the FPGA chip. A domestically produced FPGA chip with anti-radiation performance is selected. The reset circuit provides a reset signal to the FPGA. The reference crystal oscillator is selected with excellent frequency stability to provide a reference clock for the FPGA. This design achieves the goal of fully domestic design of the infrared signal processing component, improving the reliability and independent controllability of the product.

[0070] 3. The FPGA minimum system receives remote control commands from an external management controller via the CAN bus interface. It parses these commands to set remote control parameters such as detector gain, detector integration time, imaging mode, operating mode, algorithm switch, image data output switch, calibration coefficient write / erase settings, and bias voltage. Simultaneously, it feeds back telemetry data to the management controller, including infrared video processor bus status, reset count, correct / incorrect command packet count, detector gain / integration time chip number / integration time adjustment mode / integration time, imaging mode and programmable imaging non-response count, operating mode and algorithm switch, calibration coefficient write / erase status, parameter / command error packet sequence number, and telemetry refresh data. The CAN bus interface employs a highly integrated interface chip + soft-core control design, improving the product's high integration and miniaturization level.

[0071] 4. The detector gain setting, detector integration time setting, and bias setting are sent to the focal plane assembly via the first power supply and analog channel interface. The detector gain setting and detector integration time setting are used to set the gain and integration time of the external infrared detector, while the bias setting is used to set the adjustable bias module of the focal plane assembly, enabling the provision of adjustable bias voltage to the external infrared detector. Simultaneously, 64 analog signals are received from the second power supply and analog channel interface of the focal plane assembly via the first power supply and analog channel interface. The multiple analog power supplies required by the infrared signal processing component are also supplied from the second power supply and analog channel interface of the focal plane assembly. This design achieves the transmission of multiple power supplies and analog signals through a single board interface, shortening the analog signal transmission path and ensuring signal quality, while avoiding the problem of increased product size caused by the use of external interfaces.

[0072] 5. The infrared signal processing component receives 64 analog signals from the second power supply and analog channel interface of the focal plane component and inputs them into the second-stage operational amplifier module. Simultaneously, the reference power supply module generates the reference voltage required by the second-stage operational amplifier module. The reference power supply module of the infrared signal processing component enhances the driving capability of the reference power generated by the reference voltage chip through the operational amplifier, meeting the reference voltage and driving capability requirements of the second-stage operational amplifier module. This is used to adjust the amplitude and dynamic range of the analog signals to meet the range requirements of the AD acquisition. One reference voltage can meet the voltage reference requirements of four operational amplifiers. The enhanced driving capability through the operational amplifier achieves a level of product miniaturization and significantly improved reliability. The second-stage operational amplifier module converts the 64 single-ended analog signals into differential signals and adjusts the center level and dynamic range of the analog signals to meet the needs of the AD acquisition module. The second-stage operational amplifier module adopts a highly integrated hardware circuit design, reducing the printed circuit board size and thus meeting the miniaturization requirements.

[0073] 6. The second-stage operational amplifier module converts the single-ended analog signal into a differential signal, which then enters the AD acquisition module. After internal analog-to-digital processing, the AD acquisition module converts the analog signal into a high-speed digital signal (image data) which enters the FPGA minimum system. Similarly, the AD acquisition module employs a highly integrated hardware circuit design, reducing the printed circuit board size and thus meeting the miniaturization requirements.

[0074] 7. The FPGA minimum system first calls the blind pixel coordinate file in the MRAM module to complete blind pixel replacement (algorithm switch set to on) after receiving the image data. After blind pixel replacement, the image data is written to the DDR3 module in real time to complete non-uniformity correction processing (algorithm switch set to on). The correction coefficient is calculated in real time in the DDR3 module when the working mode is set to calibration mode. The corrected image data is processed by the DDR3 module according to a certain mode set in the working mode, either single integral time exposure or large dynamic range multi-level integral time fusion exposure, and then read out. After the image data output switch is set to on, the data transmission module transmits the massive image data to the data transmission and data processor in real time. By adopting the data storage and processing technology of domestic FPGA + large-capacity DDR3, the problem of high pressure and limited resources in real-time processing of massive image data in orbit for traditional large-area infrared images is overcome. By rationally allocating storage resources and caching and pipelined processing of massive data, the system achieves a maximum real-time data throughput of 64Gbit and a processing rate of over 1Gbps, reaching the technical level of real-time on-orbit non-uniformity correction and image fusion processing of massive image data. At the same time, it achieved more than 10 data transmission channels and a single channel transmission rate of up to 10Gbps, realizing the progress of high integration, miniaturization and light weight.

[0075] 8. The FPGA minimum system receives external synchronization control signals from the external management controller via the CAN bus interface. Combined with imaging mode setting control commands, it determines whether the infrared signal processing component enters autonomous imaging or programmable imaging. The FPGA minimum system also receives parameter and command packets from the external management controller via the CAN bus interface. The infrared signal processing component is configured according to the new parameters and executes the new command set. Furthermore, the FPGA minimum system receives blind pixel coordinates from the external management controller via the CAN bus interface, writes the new coordinates into the MRAM module, and reads the new blind pixel table to replace image blind pixels during subsequent imaging. Finally, the FPGA minimum system receives correction coefficients from the external management controller via the CAN bus interface, writes erasure setting commands based on the calibration coefficients, first erases the FLASH module, and then writes the new correction coefficients into the FLASH module.

[0076] 9. The uploading and refresh module receives uploading and refresh control signals from the external management controller via a serial port, completes the configuration of the uploading and refresh module registers, and then feeds back the latest telemetry status of the uploading and refresh module to the external management controller via the CAN bus interface. The uploading and refresh module receives the uploading program provided by the external management controller via a serial port and writes it into the FLASH memory in the uploading and refresh module. When the FPGA minimum system is powered off and reconfigured, the new uploading program is called, or when refreshing and reloading. The interface chip in the uploading and refresh module is a domestically produced component, using 422 level, UART interface protocol and transmission rate, and twisted pair cable for transmission. After receiving the uploading and refresh control signal sent by the external management controller, the refresh chip parses the instruction and configures its internal register status. The external crystal oscillator provides the main clock required by the refresh chip for operation. The refresh chip feeds back the telemetry status to the FPGA minimum system, and then sends it to the external management controller via the CAN bus interface. The uploading and refresh module also receives uploading programs from the external management controller and stores them in the FLASH memory. The module has two FLASH chips: one stores the default configuration program, and the other can serve as a backup for the default configuration program or store the uploading program. Based on the configuration commands received from the CAN bus interface, it selects either the default program or the uploading program for configuring the FPGA minimum system. Transmission is achieved through a 422 differential current loop, ensuring reliable signal transmission and improving resistance to external interference. Control of the refresh chip ensures real-time refreshing and reloading of the FPGA minimum system in the event of a single-event event in orbit, improving on-orbit reliability and flexibility. Simultaneously, the FLASH backup ensures the diversity of configuration programs and enhances on-orbit configuration program backup capabilities.

[0077] 10. The anti-static module receives the configuration program from the JTAG process test interface and writes it into the FPGA minimum system, preventing accidental electrostatic damage to the FPGA and improving product reliability.

[0078] 11. The buffer module receives numerical control signals from the FPGA minimum system to control the MRAM module, FLASH module, AD acquisition module and other components in the infrared signal processing component. At the same time, it transmits numerical control signals to the adjustable bias module and infrared detector of the focal plane component through the first power supply and analog channel interface, thereby improving the product integration.

[0079] 12. The focal plane assembly receives controlled low-voltage secondary power from the secondary power supply input. This power is filtered by the power filter module. The filtered low-voltage secondary power then passes through the onboard secondary power supply to generate the digital and analog power required by the focal plane assembly. Simultaneously, the digital and analog power required by the detector output from the onboard secondary power supply is sent to the external infrared detector via the power supply module. The analog power required by the infrared signal processing component output from the onboard secondary power supply is sent to the infrared signal processing component via the second power supply and analog channel interface. The analog power output from the onboard secondary power supply is sent to the fixed bias module to generate the fixed bias voltage required by the external detector. The onboard secondary power supply uses DC power. The DC / DC converter directly converts the filtered, controlled low-voltage secondary power from the external secondary power supply into a high-current power supply required by the infrared signal processing component. Then, a low-dropout regulator generates the low-noise secondary power supply required on the board. Since traditional secondary power conversion requires a large-volume, noisy DC / DC module and a separate secondary power conversion circuit, the power supply module for the infrared signal processing component in this invention is integrated onto the infrared signal processing component, eliminating the need for a separate secondary power conversion circuit. Moreover, the selected low-dropout regulator has low noise, thereby improving the product's integration, reducing its size and weight, and minimizing the impact of power supply noise on the product.

[0080] 13. The digital control signal generated by the infrared signal processing component is received through the second power supply and analog channel interface and transmitted to the external infrared detector and adjustable bias module. This controls the detector's integration time, gain, and master clock, while simultaneously controlling the adjustable bias module to generate the bias voltage required by the detector. This improves the flexibility of the on-orbit detector bias setting and increases the margin for on-orbit detector performance optimization. The fixed bias module of the focal plane assembly converts the reference power generated by the reference voltage chip into the fixed bias voltage required by the detector. The operational amplifier enhances the load-carrying capacity of the bias voltage, and the transistor enhances the driving current capacity of the bias voltage, meeting the fixed bias voltage and driving capacity required by the infrared detector. This achieves a technical level of effective improvement in product miniaturization and reliability.

[0081] 14. The first-stage operational amplifier module receives 64 analog signals output from an external detector. After impedance transformation, the signals are sent to the infrared signal processing component through the second power supply and analog channel interface. Compared with the traditional focal plane assembly design that integrates all analog circuits, this invention significantly reduces the proportion of analog circuits in the focal plane circuit, greatly reduces the size of the analog circuits, and improves the integration of the product. Moreover, the design that the analog signal is transmitted to the signal processing circuit after passing through the first-stage operational amplifier does not affect the quality of the analog signal. Furthermore, the distance between the signal processing component and the focal plane assembly is very short, avoiding the loss and attenuation of the analog signal.

[0082] The infrared video processor of this invention features a video circuit noise level better than 0.5mV, a body size of only 220mm*150mm*105mm, and a weight of only 5kg, achieving the requirements of high integration, miniaturization, and light weight. Simultaneously, this invention solves the problems of high-orbit ultra-large area infrared detectors, such as numerous channels, fast readout rates, high real-time on-orbit image processing, and large data processing volumes, resulting in simplified system complexity and improved system integration. Furthermore, it addresses the issues of traditional large-area infrared detectors having numerous output analog channels and high real-time processing pressure of massive image data, leading to a large number of traditional infrared video processors, large size, heavy weight, poor data transmission capabilities, and insufficient real-time video data processing capacity per unit. This invention achieves simultaneous acquisition of up to 64 detector channels, detector readout rates exceeding 10MHz, more than 10 data transmission channels with a maximum single-channel transmission rate of over 10Gbps, a maximum real-time data throughput of 64Gbit, and a processing rate exceeding 1Gbps.

[0083] This invention has the following advantages:

[0084] (1) By adopting the data storage and processing technology of domestic FPGA + large-capacity DDR3, the problem of high pressure and tight resources in real-time processing of massive image data in orbit of traditional large-area infrared images has been overcome. By rationally allocating storage resources, caching and pipeline processing of massive data has been carried out, achieving a real-time data throughput of up to 64Gbit and a processing rate of more than 1Gbps. This has achieved the technical level of real-time on-orbit non-uniformity correction and image fusion processing of massive image data.

[0085] (2) By adopting a highly integrated circuit hardware modular design technology, the challenges of high-orbit ultra-large area infrared detectors, such as a large number of channels, fast readout rate, high real-time performance of on-orbit image processing, and large data processing volume, have been overcome. This solves the problems of large number of infrared video processors, large size, heavy weight, and poor data transmission capability caused by the large number of output channels of traditional large area detectors. It achieves the effect of simultaneously acquiring 64 detector channels, detector readout rate of over 10MHz, video circuit noise better than 0.5mV, and more than 10 data transmission channels with a single channel transmission rate of up to 10Gbps. At the same time, it achieves progress in high integration, miniaturization, and light weight. The body size of a single infrared video processor is only 220mm*150mm*105mm, and the weight is only 5kg.

[0086] This highly integrated miniaturized infrared video processor boasts leading processing capabilities in China, providing technical support for the country's first ultra-large field-of-view, large-area array staring search and tracking integrated satellite.

Claims

1. A high integration 64 channel infrared video processor, characterized in that The application relates to an infrared signal processing assembly and a focal plane assembly. The infrared signal processing assembly is used for receiving remote control instructions, external synchronization control signals, refresh control signals, parameter packages, instruction packages, blind element coordinates, correction coefficients and uploading programs sent by an external management controller, and simultaneously feeding back telemetry data to the external management controller. The working mode of the infrared video processor is adjusted according to the remote control instructions, and whether the infrared video processor is self-imaging or program-controlled imaging is determined according to the presence or absence of the external synchronization control signals; the register control of the refresh module in the infrared signal processing assembly is completed according to the refresh control signals, and the latest working parameters and working instructions of the infrared video processor are obtained by analyzing the parameter packages and the instruction packages; the old coordinate files in the MRAM module in the infrared signal processing assembly are replaced by the new blind element coordinates obtained by uploading; the new correction coefficients obtained by uploading are stored in the FLASH module of the infrared signal processing assembly, and the new correction coefficients are used for real-time non-uniformity correction; the new uploading program is used for loading when the infrared video processor is restarted after power-off; The infrared signal processing assembly converts the 64-path analog signals received from the focal plane assembly into high-speed signals after amplification and AD conversion, and then the high-speed signals enter the FPGA minimum system in the infrared signal processing assembly, so that the image data is transmitted to the external data transmission and data processor at high speed; meanwhile, the control signals for controlling AD acquisition are generated, and the digital control signals for the focal plane assembly are generated, so that the adjustable bias voltage, the control of the infrared detector and the data read-write are realized; The focal plane assembly completes the conversion of digital and analog power supply required by itself through the on-board secondary power supply, and simultaneously provides the analog and digital power supply required by the detector; the fixed bias voltage required by the infrared detector is generated through the fixed bias voltage module in the focal plane assembly; the adjustable bias voltage required by the infrared detector is generated through the adjustable bias voltage module after the digital control signals generated by the infrared signal processing assembly are processed; meanwhile, the digital control signals generated by the infrared signal processing assembly are transmitted to the infrared detector. The focal plane assembly receives the 64-path analog signals output by the detector, and then the 64-path analog signals are transmitted to the infrared signal processing assembly after impedance conversion by the first operational amplifier, and meanwhile, the temperature measurement signals of the detector are transmitted. The infrared signal processing assembly comprises a CAN bus interface, an anti-static module, a second operational amplifier module, a reference power supply module, an AD acquisition module, a data transmission module, a FPGA minimum system, a first power supply and analog channel interface, an MRAM module, a buffer module, a power supply filtering module, an on-board secondary power supply, a DDR3 module, a FLASH module and an uploading refresh module.

2. The high integration 64-channel infrared video processor according to claim 1, characterized in that: The infrared signal processing assembly receives the controlled low-voltage secondary power input from the external secondary power supply, filters the controlled low-voltage secondary power through the power supply filtering module, and generates all the digital power required by the infrared signal processing assembly through the on-board secondary power supply. ​ The FPGA minimum system receives remote control instructions from an external management controller through a CAN bus interface, and analyzes remote control instruction information including detector gain setting, detector integration time setting, imaging mode setting, working mode setting, algorithm switch setting, image data output switch setting, scaling coefficient write-erase setting, and bias setting. The detector gain setting, detector integration time setting, and bias setting are sent to a focal plane assembly through a first power supply and analog channel interface, and 64 analog signals from the focal plane assembly are received from the first power supply and analog channel interface into a second stage operational amplifier module. A reference voltage required by the second stage operational amplifier module is generated by a reference power supply module. Single-ended analog signals are converted into differential signals by the second stage operational amplifier module, and then the differential signals are input into an AD acquisition module. After analog-digital processing by the AD acquisition module, the analog signals are converted into high-speed digital signals and input into the FPGA minimum system. The FPGA minimum system calls a blind pixel coordinate file in an MRAM module to complete blind pixel replacement, and writes image data into a DDR3 module in real time after the blind pixel replacement. Non-uniformity correction processing is completed, and correction coefficients are calculated in real time in the DDR3 module when the working mode setting is set to a calibration mode. The corrected image data is read out after DDR3 module processing according to a single integration time exposure or a certain mode in large dynamic multi-integration time fusion exposure set by the working mode setting. The image data is transmitted in real time to a data transmission and processor by a data transmission module after the image data output switch setting is set to on. The FPGA minimum system receives an external synchronization control signal from an external management controller through a CAN bus interface, and determines whether an infrared signal processing assembly enters autonomous imaging or program-controlled imaging according to an imaging mode setting control instruction. The FPGA minimum system receives a parameter package and an instruction package from an external management controller through a CAN bus interface, and configures the infrared signal processing assembly according to new parameters and executes a new instruction set. The FPGA minimum system receives blind pixel coordinates from an external management controller through a CAN bus interface, writes new coordinates into an MRAM module, and reads new blind pixel tables for image blind pixel replacement during imaging again. The FPGA minimum system receives correction coefficients from an external management controller through a CAN bus interface, erases a FLASH module according to a scaling coefficient write-erase setting instruction, and then writes new correction coefficients into the FLASH module. The up-load refresh module receives an up-load refresh control signal from an external management controller through a serial port, configures an up-load refresh module register, and then feeds back the latest telemetry state of the up-load refresh module to the external management controller through a CAN bus interface. The up-load refresh module receives an up-load program from the external management controller through the serial port, writes the up-load program into a FLASH in the up-load refresh module, and calls a new up-load program when the FPGA minimum system is configured again after power-off, or when the up-load refresh module is refreshed and reloaded. The anti-static module receives the configuration program from the JTAG process test interface to write the FPGA minimum system; the buffer module receives the digital control signal from the FPGA minimum system to complete the control of the MRAM module, the FLASH module and the AD acquisition module, and simultaneously transmits the digital control signal to the focal plane assembly and the infrared detector through the first power supply and analog channel interface.

3. A high integration 64-channel infrared video processor according to claim 2, characterized in that: The focal plane assembly comprises a second power supply and analog channel interface, a first-stage operational amplifier module, an adjustable bias module, a fixed bias module, a power supply module, an on-board secondary power supply and a power supply filter module. The focal plane assembly receives the controlled low-voltage secondary power input, filters the controlled low-voltage secondary power through the power supply filter module, generates the digital power supply and the analog power supply required by the focal plane assembly from the filtered controlled low-voltage secondary power through the on-board secondary power supply, simultaneously sends the digital power supply and the analog power supply required by the detector output by the on-board secondary power supply to the external infrared detector through the power supply module, sends the analog power supply required by the infrared signal processing assembly output by the on-board secondary power supply to the infrared signal processing assembly through the second power supply and analog channel interface, and sends the analog power supply output by the on-board secondary power supply to the fixed bias module to generate the fixed bias required by the external detector. The second power supply and analog channel interface receive the digital control signal generated by the infrared signal processing assembly and transmit the digital control signal to the external infrared detector and the adjustable bias module to control the integration time, the gain and the main clock of the infrared detector, and simultaneously control the adjustable bias module to generate the bias required by the infrared detector; the first-stage operational amplifier module receives the 64-channel analog signal output by the external detector, converts the impedance of the 64-channel analog signal, and sends the 64-channel analog signal to the infrared signal processing assembly through the second power supply and analog channel interface.

4. The high integration 64-channel infrared video processor according to claim 2, characterized in that: The upper injection refreshing module comprises an interface chip, a refreshing chip, a crystal oscillator and a FLASH. The interface chip adopts the 422 level form, the UART interface protocol and the rate transmission, adopts the twisted pair for transmission, receives the upper injection refreshing control signal sent by the external management controller, and then the refreshing chip analyzes the instruction to configure the internal register state; the external crystal oscillator provides the main clock required by the refreshing chip to work; the refreshing chip feeds back the telemetry state to the FPGA minimum system, and then sends the telemetry state to the external management controller through the CAN bus interface; the upper injection refreshing module also receives the upper injection program sent by the external management controller, stores the upper injection program in the FLASH in the upper injection refreshing module, and has two FLASH in the upper injection refreshing module, one of which stores the default configuration program, and the other of which can be used as the backup of the default configuration program or can store the upper injection program; according to the configuration instruction received through the CAN bus interface, the default program or the upper injection program is selected to configure the FPGA minimum system.

5. A high integration 64-channel infrared video processor according to claim 2, characterized in that: The on-board secondary power supply comprises a DC / DC converter and a low-dropout regulator. The on-board secondary power supply adopts the DC / DC converter to directly convert the controlled low-voltage secondary power transmitted from the external secondary power supply after filtering into the large-current digital power supply required by the infrared signal processing assembly, and then generates the remaining secondary power required by the on-board through the low-dropout regulator.

6. A high integration 64-channel infrared video processor according to claim 2, characterized in that: The reference power supply module comprises a reference voltage chip and an operational amplifier. The reference power module improves the driving capability of the reference power generated by the reference voltage chip through an operational amplifier, meets the reference voltage and driving capability required by the second operational amplifier module, and is used for adjusting the amplitude of the analog signal and changing the dynamic range.

7. A high integration 64-channel infrared video processor according to claim 2, characterized in that: The FPGA minimum system comprises an FPGA chip, a reset circuit and a reference crystal oscillator. The core of the FPGA minimum system is an FPGA chip with anti-radiation indexes, the reset circuit provides a reset signal for the FPGA, and the reference crystal oscillator provides a reference clock for the FPGA.

8. A high integration 64-channel infrared video processor according to claim 3, characterized in that: The fixed bias module comprises a reference voltage chip, an operational amplifier and a triode. The fixed bias module converts the reference power generated by the reference voltage chip into the fixed bias required by the detector, improves the load capacity of the bias through the operational amplifier, improves the driving current capacity of the bias through the triode, and meets the fixed bias and driving capability required by the infrared detector.

9. A high integration 64-channel infrared video processor according to any one of claims 1-8, characterized in that: The working modes of the infrared video processor include imaging mode and calibration mode. In the imaging mode, the infrared video processor judges the external synchronization control signal each time the imaging is started, and generates a self-imaging synchronization control signal to realize the imaging output function of the camera when no external synchronization control signal is detected; when receiving the "imaging mode" instruction, the infrared video processor outputs image data. The working process of the imaging mode is that the external management controller is powered on first, sends an external synchronization control signal to the infrared video processor, and then the infrared video processor is powered on and initialized; if the external synchronization control signal is received within a certain time after the power-on initialization, the programmed imaging mode is entered; if no external synchronization control signal is received, a frame synchronization signal is generated to enter the self-imaging mode. The image data of the large-area infrared detector is collected, and the image data is formatted according to the image format; when receiving the working mode setting instruction as the imaging mode, the image data is output; when receiving the parameter setting instruction, the multi-grade integration time adjustment and multi-frame image fusion output are performed. When receiving the "integration time setting" instruction, the single-instruction integration time adjustment is completed, and the single integration time image is output.

10. The high integration 64-channel infrared video processor according to claim 9, characterized in that: In the calibration mode, it is divided into "normal temperature calibration mode" and "high temperature calibration mode". When receiving the "normal temperature calibration mode" instruction, the camera hot door is closed, the multi-grade integration time low temperature calibration is performed, and the infrared video processor performs low temperature data acquisition; then the camera hot door is opened to heat up, and the hot door is closed again after heating. When receiving the "high temperature calibration mode" instruction, the camera performs multi-grade integration time high temperature calibration, the infrared video processor performs high temperature data acquisition, and then enters the ground imaging mode; the infrared video processor completes the non-uniform correction coefficient calculation.

11. A high integration 64-channel infrared video processor according to claim 10, characterized in that: In the calibration mode, the camera only carries out single integration time exposure, and the calibration mode workflow is that the external management controller is powered on first, sends an external synchronization control signal to the infrared video processor, and then the infrared video processor is powered on. After the power-on initialization is completed, if the external synchronization control signal is received within a certain time, the programmable imaging mode is entered, and if the external synchronization control signal is not received, a frame synchronization signal is generated by itself to enter the autonomous imaging mode. The image data of the large-area infrared detector is collected, the image data is formatted and arranged according to the image format, when the working mode setting instruction is received as the imaging mode, the image data is output, at this time the thermal door is closed, the "blind cell replacement algorithm setting instruction-blind cell replacement on" is received, the short integration time setting is completed, the "working mode setting instruction-short integration low-temperature calibration mode" is received, the short integration low-temperature calibration image data is output, then the long integration time setting is completed, the "working mode setting instruction-long integration low-temperature calibration mode" is received, and the long integration low-temperature calibration image data is output. Then the thermal door is opened, the thermal door is warmed up, the thermal door is closed after warming up, the "working mode setting instruction-short integration high-temperature calibration mode" is received, the short integration high-temperature calibration image data is output, then the long integration time setting is completed, the "working mode setting instruction-long integration high-temperature calibration mode" is received, and the long integration high-temperature calibration image data is output. Then the thermal door is opened, the "non-uniform correction algorithm setting instruction-non-uniform correction on" is received, and the non-uniform correction image data is output.

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