Display panel and electroluminescent display device comprising the same and pixel driving circuit

Abstract

The present disclosure provides a display panel and an electroluminescent display device including the same and a pixel driving circuit. An electroluminescent display device according to an embodiment of the present disclosure includes a plurality of pixels including at least two pixels and a common circuit disposed between the plurality of pixels. One of the plurality of pixels includes a driving transistor including a first node, a second node, and a third node, a capacitor connected to the fourth node and the second node electrically shared by the plurality of pixels, a second transistor connected to the first node and a data line, and a light emitting element electrically connected to the driving transistor. The common circuit includes a high potential voltage supply circuit providing a high potential voltage to the fourth node and a reference voltage supply circuit providing a reference voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0108878, filed on August 30, 2022, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] This disclosure relates to display panels capable of improving image quality, electroluminescent display devices including the same, and pixel driving circuitry. Background Technology

[0004] With the development of information technology, the market for display devices, which serve as a connection medium between users and information, is growing. Consequently, the use of various types of display devices, such as electroluminescent displays, liquid crystal displays, organic light-emitting displays, and quantum dot displays, is increasing.

[0005] Electroluminescent display devices offer advantages such as fast response time, high emission efficiency, and wide viewing angle. An electroluminescent display device includes: a display panel comprising multiple sub-pixels; a pixel driving circuit for supplying signals to drive the display panel; and a power supply for supplying power to the display panel. The pixel driving circuit includes a gate driving circuit that supplies gate signals to the display panel and a data driving circuit that supplies data signals to the display panel.

[0006] For example, an electroluminescent display device can display an image by causing the light-emitting element of a selected sub-pixel to emit light when a gate signal and a data signal are supplied to the sub-pixel. The light-emitting element can be based on organic or inorganic materials.

[0007] Electroluminescent display devices display images based on light generated by light-emitting elements in sub-pixels, offering various advantages. However, to improve image quality, it is necessary to improve the precision of the pixel driving circuit that controls the light emission of the sub-pixels. For example, the precision of the pixel driving circuit can be improved by compensating for the threshold voltage of the driving transistors included in the pixel driving circuit.

[0008] Furthermore, to reduce power consumption, electroluminescent display devices can be driven at low speeds, which may lead to undetectable image quality degradation when driven at high speeds. Therefore, a pixel driving circuit that can prevent image quality degradation is needed. Summary of the Invention

[0009] As mentioned above, with the increasing resolution and power consumption of electroluminescent display devices, driving technologies are being developed to reduce their power consumption. To reduce power consumption, pixels can be driven at a reduced frame rate for specific time periods. For example, for mobile devices, power consumption can be reduced by performing normal driving at a frequency of 60Hz or 120Hz in active mode and low-speed driving at a frequency of 1Hz in standby mode.

[0010] Furthermore, if the transistors included in the pixel driving circuit are implemented as P-type polytransistors, leakage current may occur at the gate node of the driving transistor during low-speed driving. The presence of leakage current makes it difficult for the light-emitting element to maintain the same brightness within a frame and prolongs the data update cycle, which may cause screen flicker.

[0011] Furthermore, as the vertical resolution of the display panel increases due to the larger size and higher resolution of the electroluminescent display device, the sampling time of the threshold voltage of the compensation driving transistor becomes insufficient, making it difficult to perform accurate sub-pixel grayscale representation.

[0012] Furthermore, the large size and high resolution of electroluminescent display devices reduce the width of the high-potential voltage lines supplied to the pixel driving circuits, resulting in increased resistance and significant voltage drop in the high-potential voltage lines.

[0013] Embodiments of this disclosure are intended to provide a display panel that does not flicker when driven at low speeds, and an electroluminescent display device including the same.

[0014] Embodiments of this disclosure are also intended to provide a display panel for accurate grayscale representation and an electroluminescent display device including the same.

[0015] Embodiments of this disclosure are also intended to provide a display panel capable of compensating for voltage drops in high-potential voltage lines, and an electroluminescent display device including the same.

[0016] The purpose of this disclosure is not limited to the foregoing, and other purposes not mentioned below will be apparent to those skilled in the art.

[0017] An electroluminescent display device according to an embodiment of this disclosure includes a plurality of pixels, each comprising at least two pixels, and a common circuit disposed between the plurality of pixels. Each of the plurality of pixels includes: a driving transistor comprising a first node, a second node, and a third node; a capacitor connected to a fourth node and a second node electrically shared by the plurality of pixels; a second transistor connected to the first node and a data line; and a light-emitting element electrically connected to the driving transistor. The common circuit includes a high-potential voltage supply circuit providing a high-potential voltage to the fourth node and a reference voltage supply circuit providing a reference voltage. Therefore, poor image quality of the electroluminescent display device during high-speed and low-speed driving can be prevented.

[0018] A display panel according to another embodiment of this disclosure includes a plurality of pixels and a unit pixel comprising the plurality of pixels. The unit pixel includes: a first data line and a second data line, the first data line and the second data line being included in each of the plurality of pixels; a first high-potential power line disposed between the first data line and the second data line; a first reset voltage line disposed on one side of the first data line or the second data line; and a reference voltage line connected in parallel with the first reset voltage line, disposed on one side of the unit pixel, and electrically connected to the plurality of pixels included in the unit pixel. The reference voltage line is electrically connected to the plurality of pixels included in the unit pixel via a reference voltage supply circuit. Therefore, although the high-potential power line, whose width has been reduced, is disposed in the pixel, the image quality of the display panel can be improved by preventing voltage drop in the high-potential power line by means of the reference voltage supply circuit.

[0019] According to another embodiment of this disclosure, a pixel driving circuit is disposed in each of a plurality of pixels. The pixel driving circuit includes: a driving transistor electrically connected to a light-emitting element and including a first node, a second node, and a third node; a capacitor connected to a fourth node and a second node electrically shared by the plurality of pixels; a second transistor connected to the first node and a data line; and a common circuit disposed among the plurality of pixels. The common circuit includes a high-potential voltage providing circuit for providing a high-potential voltage to the fourth node and a reference voltage providing circuit for providing a reference voltage.

[0020] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0021] According to embodiments of this disclosure, adjacent pixels share a common circuit, and the common circuit is electrically connected to adjacent pixels via a common node. In this case, by employing a common circuit designed to be robust to coupling phenomena, pixels can represent accurate grayscale.

[0022] According to embodiments of this disclosure, high-speed driving and sampling time can be ensured by placing two data lines in a row of pixels and connecting even-numbered pixels and odd-numbered pixels to different data lines.

[0023] According to embodiments of this disclosure, the width of high-potential voltage lines can be reduced by employing a pixel driving circuit that provides driving current without excluding high-potential voltage elements, and the border area can be reduced by placing low-potential voltage lines.

[0024] The above description of the problem to be solved, the means to solve the problem, and the effect is not intended to specify any essential features of the claims, and the scope of the claims is not limited by the contents described in the specification. Attached Figure Description

[0025] The above and other objects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0026] Figure 1 This is a block diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure;

[0027] Figure 2 This is a schematic view of a display panel according to an embodiment of the present disclosure;

[0028] Figure 3 This is a schematic view showing the components disposed in the display area of ​​a display panel according to an embodiment of the present disclosure;

[0029] Figure 4 This is a layout diagram showing the gate signals and voltage lines disposed in the display area of ​​a display panel according to an embodiment of the present disclosure;

[0030] Figure 5 This is a cross-sectional view showing a display panel according to an embodiment of the present disclosure;

[0031] Figure 6 and Figure 7 This is a circuit diagram illustrating a pixel driving circuit according to an embodiment of the present disclosure;

[0032] Figure 8 This is a view showing the waveform of a signal input to a pixel driving circuit according to an embodiment of the present disclosure;

[0033] Figure 9 This is a graph showing the driving current and voltage over time in a sub-pixel according to a comparative example; and

[0034] Figure 10This is a graph showing the driving current and voltage over time in a sub-pixel according to an embodiment. Detailed Implementation

[0035] The advantages and features of this disclosure, as well as the methods for implementing these advantages and features, can be understood through the following description of embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed herein and various modifications can be made thereto. The embodiments disclosed herein are provided merely to inform those skilled in the art of the category of this disclosure. This disclosure is defined only by the appended claims.

[0036] The shapes, dimensions, scales, angles, and quantities disclosed in the accompanying drawings to illustrate embodiments of this disclosure are exemplary and are not intended to limit the disclosure to those shown. Detailed descriptions of known technologies or functions may be skipped when it is determined that the subject matter of this disclosure is unclear. As used herein, when a component “comprises,” “has,” or “includes” another component, that component may include additional components unless the component “only” comprises, has, or includes the other component. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0037] The component is interpreted to include tolerances, even if not explicitly stated otherwise.

[0038] If the description is about the positional relationship between two parts, such as "on top of", "above", "below", "beside", etc., then one or more other parts may be located between the two parts, unless "directly" is used.

[0039] When using terms such as “after,” “immediately following,” and “before,” to describe time relationships, methods of operation, and methods of manufacture, discontinuous relationships may be included unless the terms “immediately” or “directly” are used.

[0040] Features of various embodiments of this disclosure may be combined or coupled in part or in whole with each other, and various technical interlocks and operations are possible, and these embodiments may be practiced independently of each other or in combination with each other.

[0041] The pixel driving circuit formed on the substrate of the electroluminescent display device described herein can be implemented using N-type or P-type transistors. For example, the transistor can be implemented as a transistor with a metal-oxide-semiconductor field-effect transistor (MOSFET) structure. A transistor is a three-electrode device comprising a gate electrode, a source electrode, and a drain electrode. The source and drain electrodes of the transistor can be switched according to the applied voltage, rather than being fixed.

[0042] In the following description, a display panel and an electroluminescent display device including the present disclosure are described with reference to the accompanying drawings.

[0043] Figure 1 This is a block diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure.

[0044] Reference Figure 1 An electroluminescent display device 100 according to an embodiment of the present disclosure may include: a display panel 110 having a plurality of data lines DL and a plurality of gate lines GL disposed thereon, and a plurality of pixels PX connected to the plurality of data lines DL and the plurality of gate lines GL disposed thereon; and a driving circuit that provides driving signals to the display panel 110.

[0045] Multiple pixels PX are shown arranged in a matrix to form a pixel array, but are not limited to this and can be arranged in various other forms.

[0046] The driving circuit may include: a data driving circuit 120 that provides data signals to multiple data lines DL; a gate driving circuit that provides gate signals to multiple gate lines GL; and a controller 130 that controls the data driving circuit 120 and the gate driving circuit.

[0047] The display panel 110 may include a display area DA for displaying an image and a non-display area NDA that is an area outside the display area DA. Multiple pixels PX, data lines DL that provide data signals to the multiple pixels PX, and gate lines GL that provide gate signals may be disposed in the display area DA.

[0048] Multiple data lines DL disposed in the display area DA can extend to the non-display area NDA for electrical connection to the data driving circuit 120. The data lines DL electrically connect multiple pixels PX disposed in the column direction to the data driving circuit 120 and can be configured to extend as a single line. Alternatively, the data lines DL can be connected to the data driving circuit 120 via contact holes and connecting wires.

[0049] Multiple gate lines GL, disposed in the display area DA, can extend to the non-display area NDA for electrical connection to the gate driving circuit. The gate lines GL electrically connect multiple pixels PX positioned in the row direction to the gate driving circuit. Furthermore, lines can be disposed in the non-display area NDA for the gate driving circuit to generate various gate signals or transmit signals to the multiple pixels PX. For example, these lines may include: one or more high-level gate voltage lines supplying a high-level gate voltage to the gate driving circuit; one or more low-level gate voltage lines supplying a low-level gate voltage to the gate driving circuit; multiple clock lines supplying multiple clock signals to the gate driving circuit; and one or more start lines supplying one or more start signals to the gate driving circuit.

[0050] On the display panel 110, multiple data lines DL and multiple gate lines GL are arranged together with a pixel array. As described above, the multiple data lines DL and multiple gate lines GL can be arranged in rows or columns, respectively. For ease of description, it is described that the multiple data lines DL are arranged in columns and the multiple gate lines GL are arranged in rows, but this disclosure is not limited thereto.

[0051] The controller 130 starts scanning the data signal according to the timing in each frame, converts the externally input image data into a data signal format suitable for use in the data drive circuit 120, outputs the converted image data, and controls the data drive circuit 120 at the appropriate time according to the scan.

[0052] The controller 130 receives timing signals, including a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a clock signal, as well as input image data from an external source. The controller 130, receiving the timing signals, generates and outputs control signals for controlling the data drive circuit 120 and the gate drive circuit.

[0053] For example, to control the data drive circuit 120, the controller 130 outputs various data control signals, including, for example, a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of one or more data signal generation circuits constituting the data drive circuit 120. The source sampling clock is a clock signal used to control the sampling timing of data in each data signal generation circuit. The source output enable signal controls the output timing of the data drive circuit 120.

[0054] In addition, the controller 130 outputs gate control signals, including a gate start pulse, a gate shift clock, and a gate output enable signal, to control the gate drive circuit. The gate start pulse controls the start timing of the operation of one or more gate signal generation circuits that constitute the gate drive circuit. The gate shift clock is a clock signal typically input to one or more gate signal generation circuits, which controls the shift timing of the scan signal. The gate output enable signal specifies timing information regarding one or more gate signal generation circuits.

[0055] The controller 130 may be a timing controller used in typical display technologies, or a control device that can perform other control functions as well as the functions of a timing controller.

[0056] The controller 130 can be implemented as a separate component from the data drive circuit 120, or the controller 130 and the data drive circuit 120 can be implemented as an integrated circuit.

[0057] The data driving circuit 120 can be implemented to include one or more data signal generation circuits. These data signal generation circuits may include shift registers, latch circuits, digital-to-analog converters, output buffers, etc. In some cases, the data signal generation circuits may also include analog-to-digital converters.

[0058] The data driving circuit 120 can be connected to the bonding pads of the display panel 110, or directly disposed on the display panel 110 via a tape-on-board (TAB) method, chip-on-glass (COG) method, or chip-on-panel (COP) method, or it can be integrated into the display panel 110. Furthermore, multiple data driving circuits 120 can be implemented as chip-on-film (COF) and mounted on the source circuit film connected to the display panel 110.

[0059] The gate driving circuit sequentially supplies gate signals to multiple gate lines GL to drive multiple pixels PX connected to the multiple gate lines GL. The gate driving circuit may include shift registers, level shifters, etc.

[0060] The gate drive circuit can be connected to the bonding pads of the display panel 110 via a tape-on-board (TAB) method, a chip-on-glass (COG) method, a chip-on-panel (COP) method, or a chip-on-film (COF) method, or it can be integrated into the display area DA or the bezel area BA of the display panel 110.

[0061] When the gate driving circuit is located in the display area DA, it can be positioned in separate spaces between multiple pixels PX. In this case, the scan driving circuit or the emission driving circuit constituting the gate driving circuit can be separated and positioned between the multiple pixels PX.

[0062] When the gate driving circuit is located in the bezel area BA, it can be located in the non-display area NDA on the left and / or right sides of the display panel 110. When the gate driving circuit is located in the bezel areas BA on the left and right sides of the display panel 110, the scan driving circuit and the emission driving circuit can be separated and located on the left and right sides respectively, or symmetrically located on both sides.

[0063] For ease of description, Figure 1 and Figure 2 An example is shown where the gate drive circuitry is directly disposed in the bezel area BA of the display panel 110.

[0064] Multiple gate lines GL disposed on the display panel 110 can be arranged in the row direction, and multiple data lines DL can be arranged in the column direction. Therefore, the data driving circuit 120 can be located on the top side of the display panel 110, and the gate driving circuit can be located on the left and right sides of the display panel 110.

[0065] Under the control of controller 130, the gate drive circuit sequentially supplies gate signals, namely transistor on-state voltage or transistor off-state voltage, to multiple gate lines GL. If a signal is supplied to a specific gate line through the gate drive circuit, the data drive circuit 120 converts the image data received from controller 130 into an analog data signal and supplies it to multiple data lines DL.

[0066] The multiple gate lines GL disposed on the display panel 110 may include multiple scan lines and multiple emitter lines. The multiple scan lines and multiple emitter lines are lines that transmit different types of gate signals to the gate electrodes of different transistors.

[0067] Therefore, the gate drive circuit may include multiple scan drive circuits that output scan signals to multiple scan lines, and multiple transmit drive circuits that output transmit signals to transmit lines.

[0068] According to embodiments of this disclosure, the electroluminescent display device 100 may include a power supply unit. The power supply unit converts or maintains power input to the electroluminescent display device 100 from outside the device into power suitable for driving the driving circuitry included in the device. The power supply unit may be implemented as a single integrated circuit, which is a semiconductor integrated device implemented separately from the gate driving circuitry, data driving circuitry 120, and timing controller 130. When the electroluminescent display device 100 is turned on, the power supply unit ramps up the input voltage and outputs the required voltage to the timing controller 130 or the display panel 110.

[0069] Figure 2 This is a schematic view of a display panel 110 according to an embodiment of the present disclosure.

[0070] Reference Figure 2 Multiple films 121, including lines, are attached to one side of the display panel 110, and a data driving circuit 120 is disposed on each of the multiple films 121. As described above, the data driving circuit 120 is shown to be implemented as a chip-on-film, and depending on the size of the display panel 110 or the number of pixels (PX), a single film 121 or multiple films 121 may be attached to the display panel 110.

[0071] In the display area DA, two data lines DL are provided for each pixel column. A pixel column refers to a pixel PX disposed perpendicular to a side surface of the display panel 110 on which multiple films 121 are disposed. Within a pixel column, an odd-numbered data line DLO and an even-numbered data line DLE are provided. The odd-numbered data line DLO connects to the odd-numbered pixels within the pixel column. The even-numbered data line DLE connects to the even-numbered pixels within the pixel column.

[0072] Odd data lines DLO and DLE are connected to a multiplexer and to data driver circuit 120 via a data link line. The multiplexer includes odd transistor MTO and even transistor MTE. Odd transistor MTO is connected to odd data line DLO, and even transistor MTE is connected to even data line DLE.

[0073] Odd-numbered transistors MTO are controlled via odd-numbered signal lines MLO to provide data signals to odd-numbered pixels, and even-numbered transistors MTE are controlled via even-numbered signal lines MLE to provide data signals to even-numbered pixels.

[0074] As the resolution and size of electroluminescent displays increase, the vertical resolution of the display panel also increases, thereby reducing the sampling time required to compensate for the characteristics of the driving transistors. To address this issue, two data lines can be applied to a single pixel row. In this case, because the two data lines are positioned on a single pixel, the width of the power lines is reduced, which increases the resistance of the power lines.

[0075] Because the resistance of the power lines causes a voltage drop, it is necessary to implement the display panel using a double-fed method, which inputs power voltage from both ends of the power lines to compensate for the voltage drop. However, if the display panel is implemented using a double-fed method, the cost of the circuit system may increase. Therefore, alternative methods are needed.

[0076] The display panel 110 according to the embodiments of this disclosure can be implemented using a single-feed method instead of a double-feed method by applying a pixel driving circuit capable of compensating for voltage drops in the power lines, thereby reducing the manufacturing cost of the display panel 110. (Refer to below) Figure 6 and Figure 7Describe a pixel driving circuit that can compensate for voltage drops in power lines.

[0077] Figure 3 This is a schematic view showing the components disposed in the display area of ​​a display panel according to an embodiment of the present disclosure.

[0078] Figure 3 Two adjacent pixel columns are shown on the display panel 110. When the two adjacent pixel columns are referred to as the first pixel column and the second pixel column, the odd-numbered pixels in the first pixel column can be called the first odd-numbered pixels PX10, the even-numbered pixels in the first pixel column can be called the first even-numbered pixels PX1E, the odd-numbered pixels in the second pixel column can be called the second odd-numbered pixels PX20, and the even-numbered pixels in the second pixel column can be called the second even-numbered pixels PX2E.

[0079] The first odd-numbered data line DL1O and the first even-numbered data line DL1E can be positioned to the left and right of the first pixel column, respectively, and the second odd-numbered data line DL2O and the second even-numbered data line DL2E can also be positioned to the left and right of the second pixel column, respectively. The positions of the odd-numbered and even-numbered data lines can be changed.

[0080] A first odd-numbered data line DL1O is connected to a first odd-numbered pixel PX1O to provide a data signal, and a first even-numbered data line DL1E is connected to a first even-numbered pixel PX1E to provide a data signal. A second odd-numbered data line DL2O is connected to a second odd-numbered pixel PX2O to provide a data signal, and a second even-numbered data line DL2E is connected to a second even-numbered pixel PX2E to provide a data signal.

[0081] A gate line GL is provided in each pixel row. A pixel row refers to the pixels PX arranged in the direction intersecting with the pixel column. The first odd-numbered pixel PX1O and the second odd-numbered pixel PX2O arranged in the first pixel row can be connected to the first gate line GL1; the first even-numbered pixel PX1E and the second even-numbered pixel PX2E arranged in the second pixel row can be connected to the second gate line GL2; the first odd-numbered pixel PX1O and the second odd-numbered pixel PX2O arranged in the third pixel row can be connected to the third gate line GL3; and the first even-numbered pixel PX1E and the second even-numbered pixel PX2E arranged in the fourth pixel row can be connected to the fourth gate line GL4. In this way, two data lines and one gate line are arranged in a pixel region, and the pixel PX in the pixel region is connected to one data line and one gate line.

[0082] By setting two data lines per pixel row in the display panel 110 and connecting odd and even pixels to different data lines, high-speed driving can be performed and two or more vertical time periods or sampling times can be ensured during the sampling and programming phases of the pixel driving circuit to compensate for the threshold voltage of the driving transistor.

[0083] Although Figure 3 Only two pixel columns and four pixel rows are shown, but hundreds to thousands of pixel rows and pixel columns can be set on the display panel 110, and it is not limited to this.

[0084] Figure 4 This is a layout diagram showing the gate signals and voltage lines disposed in the display area of ​​a display panel according to an embodiment of the present disclosure.

[0085] Figure 4 The diagram shows a first pixel PX1, a second pixel PX2, a third pixel PX3, a fourth pixel PX4, a fifth pixel PX5, and a sixth pixel PX6 arranged in a pixel row. A pixel is the smallest unit used to display color and grayscale, and can display red, green, blue, or white. For example, the first pixel PX1 and the fourth pixel PX4 can display red, the second pixel PX2 and the fifth pixel PX5 can display green, and the third pixel PX3 and the sixth pixel PX6 can display blue. Pixels that together display red, green, and blue can be defined as a unit pixel. In this case, the first pixel PX1, the second pixel PX2, and the third pixel PX3 are called the first unit pixel, and the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 are called the second unit pixel.

[0086] In the display panel 110, a common area CA is disposed between adjacent unit pixels (i.e., a first unit pixel and a second unit pixel) and electrically connected to the first unit pixel and the second unit pixel. A gate driving circuit area GA can be disposed on the side surface of the first unit pixel where the common area CA is not disposed, or on the side surface of the second unit pixel where the common area CA is not disposed. As described above, a common area CA and a gate driving circuit area GA can be disposed for every two unit pixels on the display panel 110, but this disclosure is not limited thereto. For example, when the gate driving circuit is disposed in the bezel area BA, a common area CA can be disposed for every unit pixel.

[0087] In the common area CA, control circuitry and a reference voltage line VREFL are installed to compensate for voltage drops in the power lines by providing a reference voltage. Gate drive circuitry, which provides scan and transmit signals to the pixel drive circuitry, is located in the gate drive circuitry area GA.

[0088] The non-display area NDA of the display panel 110 can be reduced by providing a common area CA and a gate drive circuit area GA in the display area DA of the display panel 110 according to an embodiment of the present disclosure.

[0089] Each pixel contains a light-emitting element and a pixel driving circuit that provides driving current to the light-emitting element, and provides a gate signal, a data signal, and a power voltage to the pixel driving circuit. For this purpose, each pixel contains a gate line GL that provides the gate signal, a data line DL that provides the data signal, and a power line that provides the voltage. As described above, each pixel contains two data lines DL.

[0090] The first even-numbered data line DL1E and the first odd-numbered data line DL1O are disposed in the first pixel PX1, which is included in the first unit pixel; the second odd-numbered data line DL2O and the second even-numbered data line DL2E are disposed in the second pixel PX2; and the third even-numbered data line DL3E and the third odd-numbered data line DL3O are disposed in the third pixel PX3. In this case, the first pixel PX1 and the second pixel PX2 can be positioned symmetrically relative to each other. Therefore, the first odd-numbered data line DL1O and the second odd-numbered data line DL2O can be disposed adjacent to each other, and the second even-numbered data line DL2E and the third even-numbered data line DL3E can be disposed adjacent to each other.

[0091] Similarly, the fourth odd-numbered data line DL4O and the fourth even-numbered data line DL4E are located in the fourth pixel PX4, which is included in the second unit pixel; the fifth even-numbered data line DL5E and the fifth odd-numbered data line DL5O are located in the fifth pixel PX5; and the sixth odd-numbered data line DL6O and the sixth even-numbered data line DL6E are located in the sixth pixel PX6. In this case, the fifth pixel PX5 and the sixth pixel PX6 can be positioned symmetrically relative to each other. Therefore, the fourth even-numbered data line DL4E and the fifth even-numbered data line DL5E can be arranged adjacent to each other, and the fifth odd-numbered data line DL5O and the sixth odd-numbered data line DL6O can be placed adjacent to each other.

[0092] The two adjacent units included in the display panel 110, namely the first unit and the second unit, can be arranged symmetrically relative to each other.

[0093] At the same time, for example, when the pixel row with the first pixel PX1 to the sixth pixel PX6 is an even number of pixel rows, the pixels are electrically connected to the even number of data lines.

[0094] The power lines include the reference voltage line VREFL, which provides the reference voltage; the high potential voltage line, which provides the high potential voltage; the reset voltage line, which provides the reset voltage; the initialization voltage line VINIL, which provides the initialization voltage; and the bias voltage line VOBSL.

[0095] The reference voltage line VREFL is positioned in the same direction as the data lines, while the initialization voltage line VINIL and the bias voltage line VOBSL are positioned in the same direction as the gate lines. The high-potential voltage lines and reset voltage lines are arranged in a grid and include all lines positioned in the same direction as the data lines and gate lines.

[0096] The high-potential voltage lines include a first high-potential voltage line VDDL1 disposed in the same direction as the data lines and a second high-potential voltage line VDDL2 disposed in the same direction as the gate lines. The first high-potential voltage line VDDL1 is disposed between the even-numbered and odd-numbered data lines disposed on each pixel. The first high-potential voltage line VDDL1 disposed in the corresponding pixel is connected to a line in the non-display area NDA to receive a high-potential voltage. A second high-potential voltage line VDDL2 is disposed for each pixel row. The first high-potential voltage line VDDL1 and the second high-potential voltage line VDDL2 can be disposed on different layers and electrically connected through contact holes.

[0097] The reset voltage lines include first reset voltage lines VARR1 and VARGB1 arranged in the same direction as the data lines, and second reset voltage lines VARR2 and VARGB2 arranged in the same direction as the gate lines.

[0098] The first reset voltage lines VARR1 and VARGB1 are configured as one per unit pixel, and include a first red reset voltage line VARR1 shared by red pixels and a first green / blue reset voltage line VARGB1 shared by green and blue pixels of two units. The first red reset voltage line VARR1 is located in the first unit pixel, and the first green / blue reset voltage line VARGB1 is located in the second unit pixel. The first red reset voltage line VARR1 is located between the first odd data line DL1O and the second odd data line DL2O, and the first green / blue reset voltage line VARGB1 is located between the fifth odd data line DL5O and the sixth odd data line DL6O, but this disclosure is not limited thereto.

[0099] The second reset voltage lines VARR2 and VARGB2 are set to one per pixel row and include: a second red reset voltage line VARR2 electrically connected to the first red reset voltage line VARR1 and the red pixels included in the pixel row; and a second green / blue reset voltage line VARGB2 electrically connected to the first green / blue reset voltage line VARGB1 and the green and blue pixels included in the pixel row.

[0100] The reset voltage lines are divided into reset voltage lines applied to the red pixels and reset voltage lines applied to the green and blue pixels, and are arranged on the display panel 110. This is why the red light-emitting elements are more prone to degradation than the green and blue light-emitting elements. Therefore, the arrangement of the reset voltage lines is not limited to this, and depending on the characteristics of the light-emitting elements, the green or blue elements can be arranged separately, or they can be arranged in a single line without being divided by pixels.

[0101] In the display panel 110 according to the embodiments of the present disclosure, the voltage uniformity of the entire display panel 110 can be enhanced and voltage drop can be prevented by setting the high-potential voltage lines and reset voltage lines in a grid pattern.

[0102] Figure 5 This is a cross-sectional view showing a display panel according to an embodiment of the present disclosure.

[0103] Figure 5 This is a cross-sectional view showing two switching thin-film transistors 200 and 400 and a capacitor 300. The two thin-film transistors 200 and 400 include a switching thin-film transistor or driving transistor containing polycrystalline semiconductor material and an oxide thin-film transistor containing oxide semiconductor material. In this case, the thin-film transistor containing polycrystalline semiconductor material is referred to as polycrystalline thin-film transistor 200, and the thin-film transistor containing oxide semiconductor material is referred to as oxide thin-film transistor 400.

[0104] Figure 5 The polycrystalline thin-film transistor 200 shown is an emission switch thin-film transistor connected to the light-emitting element 600, and the oxide thin-film transistor 400 is any one of the switch thin-film transistors connected to the capacitor 300.

[0105] A pixel PX includes a light-emitting element 600 and a pixel driving circuit that applies a driving current to the light-emitting element 600. The pixel driving circuit is disposed on a substrate 111, and the light-emitting element 600 is disposed on the pixel driving circuit. An encapsulation layer 130 is disposed on the light-emitting element 600. The encapsulation layer 130 protects the light-emitting element 600.

[0106] A pixel driving circuit can refer to a pixel (PX) array unit that includes driving thin-film transistors, switching thin-film transistors, and capacitors. A light-emitting element 600 can refer to an array unit for emitting light, including an anode electrode, a cathode electrode, and a light-emitting layer disposed between the anode electrode and the cathode electrode.

[0107] In embodiments of this disclosure, the driving thin-film transistor and at least one switching thin-film transistor use oxide semiconductor as the active layer. Compared to thin-film transistors using polycrystalline semiconductor materials as the active layer, thin-film transistors using oxide semiconductor materials as the active layer can have excellent leakage current blocking effect and are relatively inexpensive to manufacture. Therefore, in order to reduce power consumption and manufacturing costs, the pixel driving circuit according to embodiments of this disclosure includes a driving thin-film transistor and at least one switching thin-film transistor using oxide semiconductor materials.

[0108] All thin-film transistors that make up the pixel driving circuit can be implemented using oxide semiconductor materials, while only some switching thin-film transistors can be implemented using oxide semiconductor materials.

[0109] Since thin-film transistors using oxide semiconductor materials are difficult to ensure reliability, while thin-film transistors using polycrystalline semiconductor materials have excellent reliability and high operating speed, embodiments of this disclosure include both switching thin-film transistors using oxide semiconductor materials and switching thin-film transistors using polycrystalline semiconductor materials.

[0110] The substrate 111 can be implemented as a multilayer structure in which organic films and inorganic films are stacked alternately. For example, the substrate 111 can be formed as a multilayer structure in which organic films (e.g., polyimide) and inorganic films (e.g., silicon oxide SiO2) are stacked alternately.

[0111] A lower buffer layer 112 is formed on the substrate 111. The lower buffer layer 112 is used to block moisture that may penetrate from the outside, and can be constructed by stacking multiple layers of silicon oxide (SiO2). X Formation. An auxiliary buffer layer can be further provided on the lower buffer layer 112 to protect the device from moisture penetration.

[0112] A polycrystalline thin-film transistor 200 is formed on a substrate 111. The polycrystalline thin-film transistor 200 may use a polycrystalline semiconductor as the active layer. The polycrystalline thin-film transistor 200 includes a first active layer 201, a first gate electrode 202, a first source electrode 203, and a first drain electrode 204. The first active layer 201 includes a channel through which electrons or holes move.

[0113] The first active layer 201 includes a first channel region and a first source region and a first drain region on two opposite sides of the first channel region.

[0114] The first source region and the first drain region are regions that become conductive by doping the intrinsic polycrystalline semiconductor material with a predetermined concentration of Group 5 or Group 3 impurity ions (e.g., phosphorus (P) or boron (B)). The first channel region maintains the intrinsic state of the polycrystalline semiconductor material and provides a path for the movement of electrons or holes.

[0115] Meanwhile, the polycrystalline thin-film transistor 200 includes a first gate electrode 202 overlapping with the first channel region of the first active layer 201. A first gate insulating layer 113 is disposed between the first gate electrode 202 and the first active layer 201. The first gate insulating layer 113 may be formed by a single inorganic layer or a stack of multiple inorganic layers of silicon oxide (SiO2) film or silicon nitride (SiNx).

[0116] In embodiments of this disclosure, the polycrystalline thin-film transistor 200 has a top-gate structure, wherein the first gate electrode 202 is located above the first active layer 201. Therefore, the first electrode 301 included in the capacitor 300 and the photoblocking layer 410 included in the oxide thin-film transistor 400 can be formed of the same material as the first gate electrode 202. By forming the first gate electrode 202, the first electrode 301, and the photoblocking layer 410 using a single mask process, the number of mask processes can be reduced.

[0117] The first gate electrode 202 is formed of a metallic material. For example, the first gate electrode 202 may be a single-layer or multi-layer structure formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but is not limited thereto.

[0118] A first interlayer insulating layer 114 is formed on the first gate electrode 202. The first interlayer insulating layer 114 can be made of silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0119] The polycrystalline thin-film transistor 200 may further include an upper buffer layer 115, a second gate insulating layer 116, and a second interlayer insulating layer 117 sequentially disposed on the first interlayer insulating layer 114, and include a first source electrode 203 and a first drain electrode 204 formed on the second interlayer insulating layer 117 and respectively connected to the first source region and the first drain region.

[0120] The first source electrode 203 and the first drain electrode 204 can be single-layer or multi-layer structures formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but are not limited thereto.

[0121] The upper buffer layer 115 separates the second active layer 401 of the oxide thin film transistor 400, which is formed of oxide semiconductor material, from the first active layer 201, which is formed of polycrystalline semiconductor material, and provides a basis for forming the second active layer 401.

[0122] The second gate insulating layer 116 covers the second active layer 401 of the oxide thin-film transistor 400. Since the second gate insulating layer 116 is formed on the second active layer 401 formed of an oxide semiconductor material, it is implemented as an inorganic film. For example, the second gate insulating layer 116 can be silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0123] The second gate electrode 402 can be formed of a metallic material. For example, the second gate electrode 402 can be a single-layer or multi-layer structure formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but is not limited thereto.

[0124] Meanwhile, the oxide thin film transistor 400 includes a second active layer 401 formed on the upper buffer layer 115 and made of oxide semiconductor material, a second gate insulating layer 116 covering the second active layer 401, a second gate electrode 402 disposed on the second gate insulating layer 116, a second interlayer insulating layer 117 covering the second gate electrode 402, and a second source electrode 403 and a second drain electrode 404 disposed on the second interlayer insulating layer 117.

[0125] The second active layer 401 is formed of an oxide semiconductor material and includes an intrinsic second channel region that is undoped and a second source region and a second drain region that are doped to make them conductive.

[0126] The oxide thin-film transistor 400 also includes a light-blocking layer 410 located below the upper buffer layer 115 and overlapping the second active layer 401. The light-blocking layer 410 blocks light incident on the active layer 401 to ensure the reliability of the oxide thin-film transistor 400. The light-blocking layer 410 may be formed of the same material as the first gate electrode 202 and may be formed on the upper surface of the first gate insulating layer 113. The light-blocking layer 410 may be electrically connected to the second gate electrode 402 to form a dual-gate system.

[0127] The second source electrode 403 and the second drain electrode 404, together with the first source electrode 203 and the first drain electrode 204, can be formed simultaneously on the second interlayer insulating layer 117 from the same material to reduce the number of mask processes.

[0128] Meanwhile, the capacitor 300 can be realized by placing the second electrode 302 on the first interlayer insulating layer 114 to overlap with the first electrode 301. The second electrode 302 can be a single-layer or multi-layer structure formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0129] The capacitor 300 stores the data voltage applied through the data line DL for a certain period of time, and then provides it to the light-emitting element 600. The capacitor 300 includes two corresponding electrodes and a dielectric disposed between them. A first interlayer insulating layer 114 is located between the first electrode 301 and the second electrode 302.

[0130] The first electrode 301 or the second electrode 302 of the capacitor 300 can be electrically connected to the second source electrode 403 or the second drain electrode 404 of the oxide thin-film transistor 400. However, the connection relationship of the capacitor 300 can be changed according to the pixel driving circuit, and is not limited thereto.

[0131] Simultaneously, a first planarization layer 118 and a second planarization layer 119 are sequentially disposed on the pixel driving circuit to planarize the upper end of the pixel driving circuit. The first planarization layer 118 and the second planarization layer 119 can be organic films, such as polyimide or acrylic resin.

[0132] A light-emitting element 600 is formed on the second planarization layer 119.

[0133] The light-emitting element 600 includes an anode electrode 601, a cathode electrode 603, and a light-emitting layer 602 disposed between the anode electrode 601 and the cathode electrode 603. When implemented as a pixel driving circuit that typically uses a low potential voltage connected to the cathode electrode 603, the anode electrode 601 is configured as a separate electrode for each sub-pixel. In the case of implementing a pixel driving circuit that typically uses a high potential voltage, the cathode electrode 603 can be configured as a separate electrode for each sub-pixel.

[0134] The light-emitting element 600 is electrically connected to the driving element via an intermediate electrode 500 disposed on the first planarization layer 118. Specifically, the anode electrode 601 of the light-emitting element 600 and the first source electrode 203 of the polycrystalline thin-film transistor 200 constituting the pixel driving circuit are connected to each other via the intermediate electrode 500.

[0135] The anode electrode 601 is connected to the intermediate electrode 500, which is exposed through a contact hole penetrating the second planarization layer 119. Furthermore, the intermediate electrode 500 is connected to the first source electrode 203, which is exposed through a contact hole penetrating the first planarization layer 118.

[0136] The intermediate electrode 500 serves as a medium connecting the first source electrode 203 and the anode electrode 601. The intermediate electrode 500 can be formed of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0137] The anode electrode 601 can be formed as a multilayer structure comprising a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film can be formed of a material with a relatively high work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive film can be formed as a single layer or multilayer structure of aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. For example, the anode electrode 601 can be formed by a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are stacked sequentially, or by a structure in which a transparent conductive film and an opaque conductive film are stacked sequentially.

[0138] The light-emitting layer 602 is formed on the anode electrode 601 in the order of hole-related layer, organic light-emitting layer and electron-related layer or in the reverse order.

[0139] The dam layer 120 may be a pixel-defining layer that exposes the anode electrode 601 of each pixel PX. The dam layer 120 may be formed of an opaque material (e.g., black) to prevent light interference between adjacent pixels PX. In this case, the dam layer 120 comprises a light-blocking material formed of at least one of colored pigments, organic black, and carbon. Spacers 700 may be further disposed on the dam layer 120.

[0140] The cathode electrode 603 faces the anode electrode 601 (with the light-emitting layer 602 inserted between the cathode electrode 603 and the anode electrode 601), and the cathode electrode 603 is formed on the top and side surfaces of the light-emitting layer 602. The cathode electrode 603 can be integrally formed over the entire display area DA. When applied to a top-emitting organic light-emitting display device, the cathode electrode 603 can be formed of a transparent conductive layer such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0141] An encapsulation layer 130 for inhibiting moisture penetration can be further disposed on the cathode electrode 603. The encapsulation layer 130 may include a first inorganic encapsulation layer 131, an organic encapsulation layer 132, and a second inorganic encapsulation layer 133 stacked in sequence.

[0142] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 of the encapsulation layer 130 can be formed of inorganic materials such as silicon oxide (SiOx). The organic encapsulation layer 132 of the encapsulation layer 130 can be formed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin.

[0143] Figure 6 and Figure 7 This is a circuit diagram illustrating a pixel driving circuit according to an embodiment of the present disclosure, and Figure 8 Is input to Figure 6 and Figure 7The waveform diagram of the signal of the pixel driving circuit.

[0144] Figure 6 The pixel driving circuitry included in the odd-numbered pixels of a pixel row is shown, and Figure 7 The pixel driving circuitry included in the even-numbered pixels of a pixel row is shown.

[0145] Reference Figure 6 The pixel PX includes a light-emitting element 600 and a pixel driving circuit that controls the amount of current applied to the light-emitting element 600. The pixel driving circuit provides a driving current to the light-emitting element 600, causing the light-emitting element 600 to emit light.

[0146] The anode of the light-emitting element 600 can be connected to the fifth node N5, and the pixel driving circuit can be electrically connected to the light-emitting element 600 at the fifth node N5. In other words, the pixel driving circuit provides driving current to the fifth node N5.

[0147] Reference Figure 6 and Figure 7 In the pixel driving circuit according to an embodiment of the present disclosure, a gate signal including a first scan signal S1, a second scan signal S2, a third scan signal S3, a fourth scan signal S4, and an emission signal EM is provided by a gate driving circuit. Data voltages VDATA_E and VDATA_O are provided by a data driving circuit 120, and a power voltage including a high-potential voltage VDD, a low-potential voltage VSS, an initialization voltage VINI, a bias voltage VOBS, and a reset voltage VAR is provided from a power supply unit. In this case, the second scan signal S2, the third scan signal S3, and the emission signal EM are signals controlling P-type transistors, and the first scan signal S1 and the fourth scan signal S4 are signals controlling N-type transistors.

[0148] The pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a capacitor Cst. In this case, the first transistor T1 is a driving transistor. An example is described in which the first transistor T1, second transistor T2, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, ninth transistor T9, and eleventh transistor T11 in an embodiment of the present disclosure are P-type transistors, and the third transistor T3, fourth transistor T4, and tenth transistor T10 are N-type transistors. The N-type transistor can be implemented as an oxide transistor.

[0149] The electroluminescent display device 100 according to embodiments of this disclosure can employ low-speed driving to reduce power consumption. For example, assuming the frame rate of the electroluminescent display device 100 is 60Hz, when low-speed driving is performed at a frequency lower than 60Hz, the number of image frames for which data voltage is written in low-speed driving is less than the number of image frames for 60Hz driving. In 60Hz driving, 60 image frames are reproduced per second, and data voltage writing operations are performed in all 60 image frames. In contrast, in low-speed driving, data voltage writing operations are performed only on some of the 60 image frames, while the data voltage written in the previous image frame is maintained in the remaining image frames. In other words, power consumption is reduced because the output operation of the data driving circuit 120 and the gate driving circuit is stopped in the remaining image frames where no data voltage is written. Low-speed driving can be used for still images or videos where image changes are infrequent, and the update cycle of the data voltage is longer than that of 60Hz driving. Therefore, the time for which the voltage between the gate electrode and the source electrode of the driving transistor is maintained in the pixel driving circuit is longer during low-speed driving than during 60Hz driving. During low-speed driving, it is necessary to maintain the voltage between the gate electrode and source electrode of the driving transistor for a desired period of time. For this purpose, the switching transistor directly or indirectly connected to the gate electrode of the driving transistor can be implemented as an oxide transistor with good cutoff characteristics. Meanwhile, the electroluminescent display device 100 according to embodiments of this disclosure can selectively employ 60Hz driving and low-speed driving depending on the characteristics of the input image.

[0150] The pixel driving circuit according to the embodiments of this disclosure can operate separately in the first OBS period POA1, the initialization period PNI, the sampling and programming period PSAM, the second OBS period POA2, and the emission period PEM.

[0151] The first scan signal S1 includes pulses used to turn on the third transistor T3 and the tenth transistor T10 during the initialization period PINI and the sampling and programming period PSAM. The first scan signal S1 is a logic high voltage during the initialization period PINI and the sampling and programming period PSAM. The first scan signal S1 turns on the ninth transistor T9 during the first OBS period POA1, the second OBS period POA2, and the emission period PEM. The first scan signal S1 is a logic low voltage during the first OBS period POA1, the second OBS period POA2, and the emission period PEM.

[0152] The second scan signal S2 includes pulses used to turn on the second transistor T2 and the eleventh transistor T11 during the sampling and programming period PSAM. The second scan signal S2 is a gate low voltage during the sampling and programming period PSAM.

[0153] The third scan signal S3 includes pulses used to turn on the seventh transistor T7 and the eighth transistor T8 during the first OBS period POA1 and the second OBS period POA2. The third scan signal S3 is a low gate voltage during the first OBS period POA1 and the second OBS period POA2. The third scan signal S3 is also used to initialize the OBS of the first transistor T1 and the N5 node. In this case, OBS (abbreviation for On-Side Bias Stress) refers to the operation of applying stress to the driving transistor to prevent fluctuations in the threshold voltage of the driving transistor. The hysteresis of the threshold voltage of the driving transistor fluctuating over time can manifest as screen artifacts during low-speed driving. Therefore, the OBS period can mitigate the hysteresis of the driving transistor and enhance the frame response time.

[0154] The fourth scan signal S4 includes a pulse used to turn on the fourth transistor T4 during the initialization period PIN1. The fourth scan signal S4 is a high gate voltage during the initialization period PIN1.

[0155] The transmit signal EM includes pulses used to turn off the fifth transistor T5 and the sixth transistor T6 during the first OBS period POA1, the initialization period PIN1, the sampling and programming period PSAM, and the second OBS period POA2, excluding the emission period PEM. The transmit signal EM is a high gate voltage during the first OBS period POA1, the initialization period PIN1, the sampling and programming period PSAM, and the second OBS period POA2. The pulses of the transmit signal EM overlap with the pulses of the first scan signal S1, the second scan signal S2, the third scan signal S3, the fourth scan signal S4, and the transmit signal EM.

[0156] The following describes the components that constitute the pixel driving circuit during each driving period, the signals input to the components, and the operation of the components.

[0157] The first transistor T1 is a device that provides driving current to the light-emitting element 600, and the gate electrode of the first transistor T1 is connected to the second node N2, the source electrode is connected to the first node N1, and the drain electrode is connected to the third node N3.

[0158] When the fifth transistor T5 and the sixth transistor T6 are turned off by the emission signal EM, the light emission period PEM ends, followed by the first OBS period POA1, which is turned on by the seventh transistor T7 and the eighth transistor T8 by the third scan signal S3.

[0159] The gate electrode of the seventh transistor T7 is connected to the line provided with the third scan signal S3, the source electrode is connected to the line provided with the reset voltage VAR, and the drain electrode is connected to the fifth node N5.

[0160] During the first OBS period POA1, the seventh transistor T7 is turned on to apply a reset voltage VAR to the fifth node N5 to reset the anode of the light-emitting element 600. During the first OBS period POA1, the reset voltage VAR is equal to or lower than the low potential voltage VSS applied to the cathode of the light-emitting element 600, and can be set to be sufficiently lower than the operating voltage of the light-emitting element 600. The reset voltage VAR is a voltage that remains constant and does not change when driving the pixel driving circuit.

[0161] The gate electrode of the eighth transistor T8 is connected to the line provided with the third scan signal S3, the source electrode is connected to the line provided with the bias voltage VOBS, and the drain electrode is connected to the first node N1.

[0162] During the first OBS period POA1, the eighth transistor T8 is turned on to apply a bias voltage VOBS to the first node N1, which in turn turns on the first transistor T1 to apply a certain stress. During the first OBS period POA1, the bias voltage VOBS is equal to or higher than the high potential voltage VDD to turn on the first transistor T1 and keep it in a strong saturation state. In other words, the bias voltage VOBS provided by the turned-on eighth transistor T8 raises the source electrode of the first transistor T1 to the first OBS voltage VOBS1.

[0163] During the first OBS period POA1, the ninth transistor T9 remains on and applies a high-potential voltage VDD to the fourth node N4. Therefore, the ninth transistor T9 can be referred to as the high-potential voltage supply circuit.

[0164] Following the first OBS period POA1 is the initialization period PIN1, during which the third transistor T3 and the tenth transistor T10 are turned on by the first scan signal S1, and the fourth transistor T4 is turned on by the fourth scan signal S4. Between the first OBS period POA1 and the initialization period PIN1, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0165] The gate electrode of the third transistor T3 is connected to the line provided with the first scan signal S1, and the source and drain electrodes of the third transistor T3 are connected to the second node N2 and the third node N3, respectively. During the initialization period PIN1, the third transistor T3 is turned on to electrically connect the second node N2 and the third node N3. In this case, the gate and drain electrodes of the first transistor T1 are conductive to each other.

[0166] The gate electrode of the fourth transistor T4 is connected to the line provided with the fourth scan signal S4, the source electrode is connected to the second node N2, and the drain electrode is connected to the line provided with the initialization voltage VIN1. During the initialization period PIN1, the fourth transistor T4 is turned on to apply the initialization voltage VIN1 to the second node N2, thereby discharging the gate electrode of the first transistor T1. In this case, the initialization voltage VIN1 is a voltage lower than the logic low voltage and low enough to initialize the gate electrode of the first transistor T1 while turning it on.

[0167] The gate electrode of the tenth transistor T10 is connected to the line provided with the first scan signal S1, the source electrode is connected to the line provided with the reference voltage VREF, and the drain electrode is connected to the fourth node N4. During the initialization period PIN1, the tenth transistor T10 is turned on, and the reference voltage VREF is applied to the fourth node N4.

[0168] Following the initialization period PIN1 is the sampling and programming period PSAM, during which the second transistor T2 and the eleventh transistor T11 are turned on by the second scan signal S2. As mentioned above, the sampling and programming period PSAM is equal to or greater than two horizontal periods. Figure 8 The 1H shown represents a horizontal time period.

[0169] The gate electrode of the second transistor T2 is connected to the line provided with the second scan signal S2, the source electrode is connected to the line provided with the data voltage VDATA_O to be supplied to the odd-numbered pixel rows, and the drain electrode is connected to the first node N1. In this case, the data voltage supplied to the odd-numbered pixel rows is referred to as the first data voltage VDATA_O.

[0170] The third transistor T3 remains on during the sampling and programming (PSAM) phase following the initialization phase PIN1, electrically connecting the gate and drain electrodes of the driving transistor T1, thus forming a diode connection. During the PSAM phase, the second transistor T2 is turned on to apply the first data voltage VDATA_O to the source electrode of the driving transistor T1.

[0171] The tenth transistor T10 also remains on during the sampling and programming period PSAM after the initialization period PINI, thereby providing the reference voltage VREF to the fourth node N4.

[0172] The gate electrode of the eleventh transistor T11 is connected to the line supplied with the second scan signal S2, the source electrode is connected to the line supplied with the reference voltage VREF, and the drain electrode is connected to the fourth node N4. During the sampling and programming period PSAM, the eleventh transistor T11 is turned on, keeping the fourth node N4 at the reference voltage VREF without fluctuation. During the sampling and programming period PSAM, a sudden increase in the voltage of the second node N2 may cause coupling phenomena in the capacitor Cr, affecting the fourth node N4. Furthermore, since the tenth transistor T10, which supplies the reference voltage VREF to the fourth node N4, is a thin-film transistor using oxide semiconductor, it has low conductivity and is therefore susceptible to coupling phenomena. Therefore, the eleventh transistor T11, which is a thin-film transistor using polycrystalline semiconductor, is placed between the fourth node N4 and the reference voltage line VREFL to keep the fourth node N4 at the reference voltage VREF during the sampling and programming period PSAM. In this case, the tenth transistor T10 and the eleventh transistor T11 can be referred to as the reference voltage supply circuit.

[0173] During the sampling and programming period (PSAM), current flows between the source and drain electrodes of the first transistor T1. Since the gate and drain electrodes of the first transistor T1 are diode-connected, the voltage at the second node N2 increases due to the current flowing from the source electrode to the drain electrode until the voltage Vgs between the gate and source electrodes of the first transistor T1 becomes the threshold voltage Vth of the first transistor T1.

[0174] During the sampling and programming phase PSAM, the voltage of the second node N2 is charged to a voltage VDATA_O+Vth that corresponds to the sum of the first data voltage VDATA_O and the threshold voltage Vth of the first transistor T1.

[0175] The capacitor Cr includes a first electrode connected to the second node N2 and a second electrode connected to the fourth node N4. In other words, the voltage VDATA_O+Vth at the second node N2 during the sampling and programming period PSAM is stored in the capacitor Cr until the emission period PEM, thereby allowing the first transistor T1 to provide a constant drive current during the emission period PEM.

[0176] Following the sampling and programming period PSAM is the second OBS period POA2, in which the seventh transistor T7 and the eighth transistor T8 are turned on by the third scan signal S3.

[0177] In the second OBS period POA2, similar to the first OBS period POA1, the bias voltage VOBS is applied to the first node N1 through the conducting eighth transistor T8 to turn on the first transistor T1, thereby applying a certain stress to the driving transistor T1. In the second OBS period POA2, the bias voltage VOBS is equal to or higher than the high potential voltage VDD to turn on the first transistor T1 and keep it in a strongly saturated state. In other words, the bias voltage VOBS provided by the conducting eighth transistor T8 raises the source electrode of the first transistor T1 to the second OBS voltage VOBS2. In this case, the value of Vgs becomes VDATA_O + Vth + VDD – VREF – VOBS2, which is less than Vgs of the first transistor T1 in the light-emitting period PEM.

[0178] During the second OBS period POA2, the reset voltage VAR is applied again to the fifth node N5 through the conducting seventh transistor T7, thereby resetting the anode of the light-emitting element 600. During the second OBS period POA2, the reset voltage VAR is equal to or lower than the low potential voltage VSS applied to the cathode of the light-emitting element 600, and can be set to be sufficiently lower than the operating voltage of the light-emitting element 600.

[0179] The second OBS period, POA2, is followed by the emission period, PEM. During the emission period, transistors T5 and T6 are turned on by the emission signal EM.

[0180] The gate electrode of the fifth transistor T5 is connected to the line that is provided with the transmit signal EM, the source electrode is connected to the line that is provided with the high potential voltage VDD, and the drain electrode is connected to the first node N1.

[0181] The gate electrode of the sixth transistor T6 is connected to the line supplied with the emitter signal EM, the source electrode is connected to the third node N3, and the drain electrode is connected to the fifth node N5. The fifth transistor T5 and the sixth transistor T6 can be referred to as emitter transistors.

[0182] During the light-emitting period (PEM), a high-potential voltage VDD is supplied to the source electrode of the first transistor T1 through the fifth transistor T5, and the third node N3 and the fifth node N5 are turned on through the sixth transistor T6. The first transistor T1 is turned on by the voltage stored in its gate node and provides a drive current to the light-emitting element 600. In this case, the drive current is related to (VREF - VDATA_O). 2 Proportional.

[0183] The pixel driving circuit according to the embodiments of this disclosure can compensate the threshold voltage Vth of the first transistor T1 and provide a driving current to the light-emitting element 600 that does not include the high potential voltage VDD, thereby preventing voltage drop in the high potential voltage line VDDL.

[0184] Furthermore, the width of high-potential voltage lines can be reduced by employing a pixel driving circuit that provides driving current while excluding high-potential voltage components, and the bezel area can be reduced by placing low-potential voltage lines. (See reference...) Figure 4 Instead of the first high-potential voltage line VDDL1 located in the third pixel PX3, a low-potential voltage line providing a low-potential voltage VSS can be provided. For example, an additional line of a certain width can be placed in the border area to prevent voltage rise in the low-potential voltage line. Placing the low-potential voltage line inside the pixel significantly reduces the width of the additional line located in the border area.

[0185] Meanwhile, the pixel driving circuit according to the embodiments of this disclosure includes a first common circuit CC1. The first common circuit CC1 includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11 connected to the fourth node N4. The first common circuit CC1 is disposed in a common area CA between two adjacent unit pixels and is shared by the red, green, and blue pixels disposed in the two unit pixels. In other words, the fourth node N4 included in the pixel driving circuit disposed in the red, green, and blue pixels is electrically connected. The fourth node N4, which can be shared by unit pixels, is a node unaffected by data voltage. The circuit that provides voltage to the fourth node N4, which is unaffected by data voltage, is the common circuit. The common circuit applies an electrical voltage to the fourth node N4, rather than a data voltage such as a high potential voltage VDD or a reference voltage Vref.

[0186] For example, if Figure 6 If the pixel driving circuit is set in the red pixel, then the fourth node N4 is connected to the capacitor Cg of the green pixel and the capacitor Cb of the blue pixel, thereby providing the voltage provided by the first common circuit CC1 to the first electrode of the capacitor Cg of the green pixel and the capacitor Cb of the blue pixel.

[0187] The pixel driving circuit according to embodiments of this disclosure includes a first common circuit CC1 shared by at least two pixels, thereby realizing a high-resolution display panel and a display device.

[0188] Reference Figure 7 , Figure 7 The pixel driving circuit is set in conjunction with Figure 6 The pixel driving circuit is located in the even-numbered pixels of the same pixel row. Because... Figure 7 The pixel driving circuit, in addition to the first common circuit CC1 and the data voltage, has the same characteristics as... Figure 6 The same components are used in the pixel driving circuit, so descriptions of the same components will be omitted or simplified.

[0189] Figure 6 Pixel driving circuit and Figure 7 The pixel driving circuits are driven together at the same timing. Figure 6 The second transistor T2 included in the pixel driving circuit provides the first data voltage VDATA_O to the first node N1, which is supplied to the odd-numbered pixel rows. Figure 7 The second transistor T2 included in the pixel driving circuit provides the data voltage VDATA_E, which is supplied to the even-numbered pixel rows, to the first node N1. In this case, the data voltage supplied to the even-numbered pixel rows is referred to as the second data voltage VDATA_E.

[0190] The pixel driving circuit located in even-numbered pixels includes a second common circuit CC2. The second common circuit CC2 includes a ninth transistor T9 and a tenth transistor T10, in addition to the eleventh transistor T11 in the first common circuit CC1.

[0191] Conversely, the first common circuit CC1 and the second common circuit CC2 can be included in even-numbered pixels and odd-numbered pixels, respectively.

[0192] Figure 9 This is a graph showing the driving current and voltage over time in a sub-pixel according to a comparison example. Figure 10 This is a graph showing the driving current and voltage over time in a sub-pixel according to an embodiment.

[0193] Figure 9 It shows when the application Figure 7 The driving current and voltage during pixel driving circuitry.

[0194] Figure 9 (a) is a graph of the driving current waveform in the red pixel over time. The dashed line represents the driving current waveform of the red pixel when the green and blue pixels sharing the fourth node N4 with the red pixel are at 255G (black), while the solid line represents the driving current waveform of the red pixel when the green and blue pixels sharing the fourth node N4 with the red pixel are at 0G (white).

[0195] When 200μs passes, the driving current of the red pixel saturates to a constant current value. The driving current is 68.2nA when the green and blue pixels are at 255G, and 74.8nA when they are at 0G. The difference in driving current value for the red pixel, depending on grayscale, reaches 4.62nA, indicating that the driving current of the red pixel varies according to the grayscale changes of the green and blue pixels shared with the red pixel via the fourth node N4.

[0196] Figure 9(b) is a graph showing the voltage waveform of the gate electrode of the driving transistor and the node shared by the red, green, and blue pixels in the red pixel over time. The gate electrode of the driving transistor is the second node N2, and the node shared by the red, green, and blue pixels is the fourth node N4. Figure 9 In (b), the voltage in the initialization period PNI and the sampling and programming period PSAM can be identified.

[0197] The dashed line of the second node N2 represents the voltage waveform of the gate electrode of the driving transistor included in the red pixel when the green and blue pixels sharing the fourth node N4 with the red pixel are 255G (black), while the solid line of the second node N2 represents the voltage waveform of the fourth node N4 when the green and blue pixels sharing the fourth node N4 with the red pixel are 0G (white).

[0198] from Figure 9 As can be seen in region B of (b), the two curves are separated from each other. Therefore, it can be shown that the voltage of the second node N2, which is included in the red pixel, varies according to the grayscale changes of the green and blue pixels that share the fourth node N4 with the red pixel.

[0199] The dashed line of the fourth node N4 represents the voltage waveform of the fourth node N4 when the green and blue pixels sharing the fourth node N4 with the red pixel are 255G (black), while the solid line of the fourth node N4 represents the voltage waveform of the fourth node N4 when the green and blue pixels sharing the fourth node N4 with the red pixel are 0G (white).

[0200] from Figure 9 As can be seen in region A of (b), similar to region B, the two curves are separated from each other. This indicates that the voltage of the fourth node N4 varies according to the grayscale changes of the green and blue pixels that share the fourth node N4 with the red pixel.

[0201] When a display panel according to an embodiment of this disclosure has a common node shared by pixels (in this case, the fourth node N4), the gate electrode of the driving transistor and the common node may change due to coupling effects during sampling and programming, resulting in grayscale distortion. Therefore, a pixel circuit structure is needed to compensate for this.

[0202] Figure 10 It shows when the application Figure 6 The driving current and voltage during pixel driving circuitry.

[0203] Figure 10(a) is a graph of the driving current waveform in the red pixel over time. The dashed line represents the driving current waveform of the red pixel when the green and blue pixels sharing the fourth node N4 with the red pixel are at 255G (black), while the solid line represents the driving current waveform of the red pixel when the green and blue pixels sharing the fourth node N4 with the red pixel are at 0G (white).

[0204] When 200μs passes, the driving current of the red pixel saturates to a constant value. The driving current is 60.2nA when the green and blue pixels are at 255G, and 61.0nA when they are at 0G. The difference in driving current value for the red pixel, depending on the grayscale, reaches 0.8nA, indicating that the driving current of the red pixel remains almost constant despite grayscale changes shared with the green and blue pixels via the fourth node N4.

[0205] Figure 10 (b) is a graph showing the voltage waveform of the gate electrode of the driving transistor and the node shared by the red, green, and blue pixels in the red pixel over time. The gate electrode of the driving transistor is the second node N2, and the node shared by the red, green, and blue pixels is the fourth node N4. Figure 10 In (b), the voltage in the initialization period PNI and the sampling and programming period PSAM can be identified.

[0206] The dashed line of the second node N2 represents the voltage waveform of the gate electrode of the driving transistor included in the red pixel when the green and blue pixels sharing the fourth node N4 with the red pixel are 255G (black), while the solid line of the second node N2 represents the voltage waveform of the fourth node N4 when the green and blue pixels sharing the fourth node N4 with the red pixel are 0G (white).

[0207] Check Figure 10 Region D in (b) shows that the two curves are difficult to distinguish. Therefore, it can be shown that although the grayscale changes in the green and blue pixels share the fourth node N4 with the red pixel, the voltage of the second node N2 included in the red pixel is constant.

[0208] The dashed line of the fourth node N4 represents the voltage waveform of the fourth node N4 when the green and blue pixels sharing the fourth node N4 with the red pixel are 255G (black), while the solid line of the fourth node N4 represents the voltage waveform of the fourth node N4 when the green and blue pixels sharing the fourth node N4 with the red pixel are 0G (white).

[0209] from Figure 10As can be seen in region C of (b), the two curves are identical to those in region D. This indicates that although the green and blue pixels share the grayscale variations of the fourth node N4 with the red pixels, the voltage of the fourth node N4 remains constant.

[0210] When a display panel according to an embodiment of this disclosure has a common node (in this case, the fourth node N4) shared by pixels and receiving electrical voltage, grayscale can be accurately represented by applying a common circuit designed to be robust to coupling to the pixel drive circuit, thereby keeping the voltage of the gate electrode of the drive transistor or the common node constant during sampling and programming. This can be applied to pixel drive circuits connected to all data lines.

[0211] According to embodiments of the present disclosure, a display panel and an electroluminescent display device including the same can be described as follows.

[0212] An electroluminescent display device according to an embodiment of this disclosure includes a plurality of pixels, each comprising at least two pixels, and a common circuit disposed between the plurality of pixels. Each of the plurality of pixels includes: a driving transistor comprising a first node, a second node, and a third node; a capacitor connected to a fourth node and a second node electrically shared by the plurality of pixels; a second transistor connected to the first node and a data line; and a light-emitting element electrically connected to the driving transistor. The common circuit includes a high-potential voltage providing circuit for providing a high-potential voltage to the fourth node and a reference voltage providing circuit for providing a reference voltage.

[0213] According to another feature of this disclosure, the high-potential voltage supply circuit may include a ninth transistor connected to the fourth node and the high-potential voltage line. The reference voltage supply circuit may include a tenth and an eleventh transistor connected to the fourth node and the reference voltage line. The tenth transistor may include an oxide semiconductor active layer.

[0214] According to another feature of this disclosure, the ninth and tenth transistors can be controlled by a first scan signal, and the eleventh transistor can be controlled by a second scan signal. The first scan signal and the second scan signal can have different pulse signals.

[0215] According to another feature of this disclosure, the electroluminescent display device may further include: a gate driving circuit region spaced apart from a common circuit and disposed between a plurality of pixels.

[0216] According to another feature of this disclosure, multiple gate drive circuit regions can be provided. Drive circuits providing gate signals for controlling transistors included in a pixel can be separately provided in the multiple gate drive circuit regions. The multiple gate drive circuit regions may include areas where no drive circuits are provided.

[0217] According to another feature of this disclosure, two data lines can be set for each pixel in a plurality of pixels. Each pixel in the plurality of pixels can be connected to one of the two data lines.

[0218] According to another feature of this disclosure, multiple pixels can be arranged in the direction in which the data lines are arranged. Even-numbered pixels among the multiple pixels can be connected to one of the two data lines, and odd-numbered pixels among the multiple pixels can be connected to the other of the two data lines.

[0219] Two data lines can be connected to a data link line. The electroluminescent display device may also include a multiplexer disposed between the two data lines and the data link line.

[0220] According to another feature of this disclosure, the electroluminescent display device may further include a third transistor connected to the second node and the third node and controlled by the first scan signal. The third transistor may include an oxide semiconductor active layer.

[0221] According to another feature of this disclosure, the electroluminescent display device may further include a fourth transistor connected to the second node and the initialization voltage line, wherein the fourth transistor includes an oxide semiconductor active layer.

[0222] According to another feature of this disclosure, the driving transistor may include a polycrystalline silicon semiconductor active layer.

[0223] According to another feature of this disclosure, multiple pixels can be divided into unit pixels, including red pixels, green pixels, and blue pixels. A common circuit can be disposed between two adjacent unit pixels and electrically connected to the pixels included in the two unit pixels.

[0224] A display panel according to another embodiment of this disclosure includes a plurality of pixels and a unit pixel comprising the plurality of pixels. The unit pixel includes: a first data line and a second data line, the first data line and the second data line being included in each of the plurality of pixels; a first high-potential power line disposed between the first data line and the second data line; a first reset voltage line disposed on one side of the first data line or the second data line; and a reference voltage line connected in parallel with the first reset voltage line, disposed on one side of the unit pixel, and electrically connected to the plurality of pixels included in the unit pixel. The reference voltage line is electrically connected to the plurality of pixels included in the unit pixel via a reference voltage supply circuit.

[0225] According to another feature of this disclosure, the reference voltage providing circuit may include oxide thin-film transistors and polycrystalline thin-film transistors controlled by different scan signals.

[0226] According to another feature of this disclosure, the display panel may further include a second high-potential power line that intersects with the first high-potential power line and overlaps with the unit pixel.

[0227] According to another feature of this disclosure, the display panel may further include a second reset voltage line, which is configured to intersect the first reset voltage line and overlap with the unit pixel.

[0228] According to another feature of this disclosure, a unit pixel may include red pixels, green pixels, and blue pixels. A first reset voltage line may include lines connected to the red pixels of the unit pixel and lines connected to the green and blue pixels, and a second reset voltage line may include lines connected to the red pixels of the unit pixel and lines connected to the green and blue pixels.

[0229] According to another embodiment of this disclosure, a pixel driving circuit is disposed in each of a plurality of pixels. The pixel driving circuit includes: a driving transistor electrically connected to a light-emitting element and including a first node, a second node, and a third node; a capacitor connected to a fourth node and a second node electrically shared by the plurality of pixels; a second transistor connected to the first node and a data line; and a common circuit disposed among the plurality of pixels. The common circuit includes a high-potential voltage providing circuit for providing a high-potential voltage to the fourth node and a reference voltage providing circuit for providing a reference voltage.

[0230] According to another feature of this disclosure, the high-potential voltage providing circuit may include a ninth transistor connected to the fourth node and the high-potential voltage line, and the reference voltage providing circuit may include a tenth transistor and an eleventh transistor connected to the fourth node and the reference voltage line.

[0231] According to another feature of this disclosure, the pixel driving circuit may further include a third transistor connected to the second node and the third node and controlled by the first scan signal.

[0232] According to another feature of this disclosure, the pixel driving circuit may further include a fourth transistor connected to the second node and the initialization voltage line, wherein the fourth transistor includes an oxide semiconductor active layer.

[0233] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited to these embodiments, and various modifications can be made without departing from the technical spirit of the present disclosure. Therefore, the embodiments set forth herein are provided for illustrative purposes and not to limit the scope of the present disclosure, and it should be understood that the scope of the present disclosure is not limited by the embodiments. Thus, it should be noted that the above embodiments are provided as examples and should not be construed as limiting.

Claims

1. An electroluminescent display device, the electroluminescent display device comprising a plurality of pixels including at least two pixels and a common circuit electrically connected to the plurality of pixels via a common node, wherein, Each of the plurality of pixels includes: Including the driving transistors for the first node, the second node, and the third node; A capacitor connected to the common node and the second node; The second transistor connected to the first node and the data line; and The light-emitting element electrically connected to the driving transistor, The common circuit includes a high-potential voltage supply circuit that provides a high-potential voltage to the common node and a reference voltage supply circuit that provides a reference voltage.

2. The electroluminescent display device according to claim 1, wherein, The high-potential voltage providing circuit includes a ninth transistor connected to the common node and the high-potential voltage line, and the reference voltage providing circuit includes a tenth transistor and an eleventh transistor connected to the common node and the reference voltage line.

3. The electroluminescent display device according to claim 2, wherein, The ninth and tenth transistors are controlled by a first scan signal, and the eleventh transistor is controlled by a second scan signal, wherein the first scan signal and the second scan signal have different pulse signals.

4. The electroluminescent display device according to claim 2, wherein, The tenth transistor includes an oxide semiconductor active layer.

5. The electroluminescent display device according to claim 1, further comprising: A gate drive circuit region spaced apart from the common circuit and disposed between the plurality of pixels.

6. The electroluminescent display device according to claim 5, wherein, The plurality of gate drive circuit regions are provided, wherein drive circuits for controlling the gate signals of the transistors included in each of the plurality of pixels are separately provided in the plurality of gate drive circuit regions.

7. The electroluminescent display device according to claim 6, wherein, The plurality of gate drive circuit regions include regions where no drive circuit is provided.

8. The electroluminescent display device according to claim 1, wherein, Two data lines are provided in each of the plurality of pixels, and each of the plurality of pixels is connected to one of the two data lines.

9. The electroluminescent display device according to claim 8, wherein, The plurality of pixels are arranged in the direction in which the data lines are arranged, wherein even-numbered pixels among the plurality of pixels are connected to one of the two data lines, and odd-numbered pixels among the plurality of pixels are connected to the other of the two data lines.

10. The electroluminescent display device according to claim 9, wherein, The two data lines are connected to the data link line, and the electroluminescent display device further includes a multiplexer disposed between the two data lines and the data link line.

11. The electroluminescent display device according to claim 1, further comprising: A third transistor connected to the second node and the third node and controlled by the first scan signal.

12. The electroluminescent display device according to claim 11, wherein, The third transistor includes an oxide semiconductor active layer.

13. The electroluminescent display device according to claim 1, further comprising: A fourth transistor is connected to the second node and the initialization voltage line, wherein the fourth transistor includes an oxide semiconductor active layer.

14. The electroluminescent display device according to claim 1, wherein, The driving transistor includes a polycrystalline silicon semiconductor active layer.

15. The electroluminescent display device according to claim 1, wherein, The plurality of pixels are divided into unit pixels including red pixels, green pixels and blue pixels, and wherein the common circuit is disposed between two adjacent unit pixels and electrically connected to the pixels included in the two unit pixels.

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