Control method, communication method, controller, node device, readable medium

Abstract

This disclosure provides a control method, comprising: configuring and distributing a time gating list; wherein the time gating list includes at least one deterministic queue and multiple time slices, wherein in each deterministic queue, the gating of the periodic time slices corresponding to the deterministic queue is enabled, the gating of the periodic time slices corresponding to other deterministic queues is disabled, and the gating of the empty time slices is enabled, wherein the periodic time slices of the deterministic queue are the time slices corresponding to the time when the deterministic queue periodically forwards data packets of deterministic service flows, and the empty time slices are the time slices other than the periodic time slices of each deterministic queue. This disclosure also provides a communication method, a controller, a node device, and a computer-readable medium.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of communication, and in particular, to a control method, a communication method, a controller, a node device, and a computer readable medium. BACKGROUND

[0002] In a deterministic network, deterministic queues of different priorities are configured for deterministic traffic flows, different traffic-class deterministic traffic flows correspond to different priorities and enter different deterministic queues, ordinary traffic enters different ordinary queues according to quality of service (QoS), and deterministic traffic flows in the deterministic queues can preempt ordinary traffic in the ordinary queues to achieve priority transmission.

[0003] In order to ensure the end-to-end delay of the deterministic traffic flows, a scheduling mechanism of a time awareness shaper (TAS) is defined, the TAS scheduling mechanism dynamically provides on / off control for an egress queue based on a pre-set periodic gate control list (GCL), each node on a path calculates a gate time, and scheduling of data packets in the deterministic queues is performed through the opening and closing of the gate, so that the deterministic traffic flows are transmitted out at a predetermined opening time.

[0004] However, the scheduling mechanism based on the periodic gate control list cannot guarantee the end-to-end delay, and the jitter of the end-to-end delay is large. SUMMARY

[0005] The present disclosure provides a control method, a communication method, a controller, a node device, and a computer readable medium.

[0006] In a first aspect, the present disclosure provides a control method, comprising:

[0007] configuring and distributing a time gate control list;

[0008] The time gate control list includes at least one deterministic queue and a plurality of time slices, the gate control of each deterministic queue corresponding to the periodic time slice of the deterministic queue is open, the gate control of the periodic time slice corresponding to other deterministic queues is closed, and the gate control of the empty time slice is open, the periodic time slice of the deterministic queue is a time slice corresponding to a time at which the deterministic queue periodically forwards data packets of the deterministic traffic flows, and the empty time slice is a time slice other than the periodic time slice of each deterministic queue.

[0009] In some embodiments, configuring and distributing the time gate control list comprises:

[0010] configuring a real phase time gating list, wherein in each of the deterministic queues of the real phase time gating list, a gate corresponding to a periodic time slice of the deterministic queue is open, a gate corresponding to a periodic time slice of another deterministic queue is closed, and a gate corresponding to the empty time slice is empty;

[0011] configuring a virtual phase time gating list, wherein in each of the deterministic queues of the virtual phase time gating list, a gate corresponding to the empty time slice is open;

[0012] determining the time gating list according to the real phase time gating list and the virtual phase time gating list, and delivering the time gating list.

[0013] In some embodiments, configuring a real phase time gating list comprises:

[0014] calculating a path of a target deterministic traffic flow;

[0015] calculating a time gate of a node device on the path for forwarding a data packet of the target deterministic traffic flow;

[0016] configuring the real phase time gating list according to the time gate.

[0017] In some embodiments, configuring the real phase time gating list according to the time gate comprises:

[0018] setting a gate of a time slice corresponding to the time gate in a deterministic queue corresponding to the target deterministic traffic flow as open;

[0019] setting a gate of a time slice corresponding to the time gate in another deterministic queue as closed.

[0020] In some embodiments, configuring a virtual phase time gating list comprises:

[0021] configuring the virtual phase time gating list according to the time gate.

[0022] In some embodiments, configuring the virtual phase time gating list according to the time gate comprises:

[0023] determining the empty time slice according to the time gate;

[0024] setting a gate of the empty time slice as open.

[0025] In some embodiments, configuring the virtual phase time gating list according to the time gate comprises:

[0026] removing a gate of a time slice corresponding to the time gate in the virtual phase time gating list.

[0027] In some embodiments, the time-gating list is determined and issued according to the real-phase time-gating list and the virtual-phase time-gating list, including:

[0028] The real-phase time-gating list and the virtual-phase time-gating list are merged according to the time slice and the deterministic queue one by one to obtain the time-gating list;

[0029] The time-gating list is issued.

[0030] In some embodiments, the configuration and issuance of the time-gating list further include:

[0031] The flag bit is set in the empty time slice.

[0032] In some embodiments, the control method further includes:

[0033] According to the monitoring information reported by the node device, the data packets of the burst deterministic service flow or the jitter deterministic service flow are counted.

[0034] In a second aspect, the embodiments of the present disclosure provide a communication method, including:

[0035] According to the time-gating list, the data packets of at least one deterministic data flow are forwarded;

[0036] The time-gating list includes at least one deterministic queue and multiple time slices. In each deterministic queue, the gating of the periodic time slice corresponding to the deterministic queue is opened, the gating of the periodic time slice corresponding to other deterministic queues is closed, and the gating of the empty time slice is opened. The periodic time slice of the deterministic queue is the time slice corresponding to the time when the deterministic queue periodically forwards the data packets of the deterministic service flow. The empty time slice is the time slice other than the periodic time slice of each deterministic queue.

[0037] In some embodiments, according to the time-gating list, the data packets of at least one deterministic data flow are forwarded, including:

[0038] According to the flag bit, the data packets of the deterministic service flow transmitted in the empty time slice are monitored;

[0039] The monitoring information is reported to the controller.

[0040] In a third aspect, the embodiments of the present disclosure provide a controller, including:

[0041] One or more processors;

[0042] a memory having stored thereon one or more programs, when executed by the one or more processors, cause the one or more processors to implement the control method according to the first aspect of the embodiments of the present disclosure.

[0043] In a fourth aspect, the embodiments of the present disclosure provide a node device, comprising:

[0044] one or more processors;

[0045] a memory having stored thereon one or more programs, when executed by the one or more processors, cause the one or more processors to implement the communication method according to the second aspect of the embodiments of the present disclosure.

[0046] In a fifth aspect, the embodiments of the present disclosure provide a computer readable medium having stored thereon a computer program, which, when executed by a processor, implements the control method according to the first aspect of the embodiments of the present disclosure and / or the communication method according to the second aspect of the embodiments of the present disclosure.

[0047] In the control method provided by the embodiments of the present disclosure, in the time gating list, the gating of the time slice in which the data packets of the periodic deterministic service flow are forwarded in each deterministic queue is set to be open, and the gating of the time slice in which the data packets of the deterministic service flow are not forwarded in each deterministic queue is set to be open, so that the data packets of the burst flow or the data packets missing the periodic time slice due to jitter can be forwarded in the empty time slice without waiting for the next gating period of the periodic time slice gating to be open, thereby ensuring the delay of the deterministic service flow; meanwhile, the normal forwarding of the periodic data packets of the next gating period of the periodic time slice is not affected, thereby avoiding delay jitter. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 is a schematic diagram of a periodic time gating list;

[0049] Figure 2 is a comparison schematic diagram of a burst flow and a periodic deterministic service flow;

[0050] Figure 3 is a flowchart of a control method in the embodiments of the present disclosure;

[0051] Figure 4 is a schematic diagram of a time gating list in the embodiments of the present disclosure;

[0052] Figure 5 is a flowchart of part of steps in another control method in the embodiments of the present disclosure;

[0053] Figure 6 is a schematic diagram of a real time gating list in the embodiments of the present disclosure;

[0054] Figure 7 is a schematic diagram of a virtual phase time-gated list in an embodiment of the present disclosure;

[0055] Figure 8 is a flowchart of part of steps in another control method in an embodiment of the present disclosure;

[0056] Figure 9 is a flowchart of a communication method in an embodiment of the present disclosure;

[0057] Figure 10 is a component block diagram of a controller in an embodiment of the present disclosure;

[0058] Figure 11 is a component block diagram of a node device in an embodiment of the present disclosure;

[0059] Figure 12 is a component block diagram of a computer readable medium in an embodiment of the present disclosure;

[0060] Figure 13 is a schematic diagram of another real phase time-gated list in an embodiment of the present disclosure;

[0061] Figure 14 is a schematic diagram of another virtual phase time-gated list in an embodiment of the present disclosure;

[0062] Figure 15 is a schematic diagram of another time-gated list in an embodiment of the present disclosure;

[0063] Figure 16 is a schematic diagram of another real phase time-gated list in an embodiment of the present disclosure;

[0064] Figure 17 is a schematic diagram of another virtual phase time-gated list in an embodiment of the present disclosure;

[0065] Figure 18 is a schematic diagram of another time-gated list in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the control method, the communication method, the controller, the node device, and the computer readable medium provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

[0067] In the following, the example embodiments will be described more fully with reference to the accompanying drawings, in which however the example embodiments can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, the purpose of the embodiments is to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art.

[0068] In the case of no conflict, each embodiment of the disclosure and each feature in the embodiments can be combined with each other.

[0069] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0070] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0071] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0072] Periodic time-gated list, and the data packets can reach the receiving point within a certain end-to-end delay. As shown in Figure 1 , the periodic time-gated list has 8 queues in total, corresponding to traffic-classes from 7 to 0 respectively, wherein the queues of traffic-classes 3, 2 and 1 are used as deterministic queues; the periodic time-gated list includes T00 to T09, a total of 10 time slices, and 10 time slices are taken as a gating period to cycle. Among them, the deterministic queue of traffic-class 3 corresponds to the deterministic traffic flow opening the gate at time slices T01 and T02, as shown in Figure 1 , the gate corresponding to time slices T01 and T02 of the deterministic queue of traffic-class 3 in the periodic time-gated list is set to O; the deterministic queue of traffic-class 2 corresponds to the deterministic traffic flow opening the gate at time slices T03 and T04, as shown in Figure 1 , the gate corresponding to time slices T03 and T04 of the deterministic queue of traffic-class 2 in the periodic time-gated list is set to O; the deterministic queue of traffic-class 1 corresponds to the deterministic traffic flow opening the gate at time slices T08 and T09, as shown in Figure 1As shown in the periodic time-gating list, the gate corresponding to time slots T08 and T09 for the deterministic queue with traffic-class 1 is set to O (Open); the gates corresponding to time slots T00, T05, T06, T07 for the deterministic queues with traffic-classes 3, 2, 1 are set to C (Close), and Figure 1 As shown in the periodic time-gating list, the gates corresponding to time slots T00, T05, T06, T07 for the deterministic queues with traffic-classes 3, 2, 1 are set to C (Close). The queues with traffic-classes 7, 6, 5, 4, 0 are not enabled or used as normal queues, and the corresponding gates are set to O.

[0073] However, the deterministic traffic flow can generate a burst flow, such as a burst control signal. The burst flow can generate multiple burst data packets in a short time, and the burst data packet is shorter than the periodic data packet of the deterministic traffic flow. The comparison between the burst flow and the periodic deterministic traffic flow is as follows Figure 2 As shown in the periodic time-gating list, the gates corresponding to time slots T00, T05, T06, T07 for the deterministic queues with traffic-classes 3, 2, 1 are set to C (Close). The queues with traffic-classes 7, 6, 5, 4, 0 are not enabled or used as normal queues, and the corresponding gates are set to O.

[0074] As shown in the periodic time-gating list, the gates corresponding to time slots T00, T05, T06, T07 for the deterministic queues with traffic-classes 3, 2, 1 are set to C (Close). The queues with traffic-classes 7, 6, 5, 4, 0 are not enabled or used as normal queues, and the corresponding gates are set to O. Figure 1 As shown in the periodic time-gating list, the gates corresponding to time slots T00, T05, T06, T07 for the deterministic queues with traffic-classes 3, 2, 1 are set to C (Close). The queues with traffic-classes 7, 6, 5, 4, 0 are not enabled or used as normal queues, and the corresponding gates are set to O.

[0075] Therefore, in a first aspect, with reference to Figure 3 The embodiment of the present disclosure provides a control method, comprising:

[0076] S1, configuring and distributing a time-gating list; wherein the time-gating list comprises at least one deterministic queue and multiple time slots, in each of the deterministic queues, the gate corresponding to the periodic time slot of the deterministic queue is open, the gate corresponding to the periodic time slot of other deterministic queues is closed, and the gate corresponding to the empty time slot is open, the periodic time slot of the deterministic queue is the time slot corresponding to the time when the deterministic queue periodically forwards the data packet of the deterministic traffic flow, and the empty time slot is the time slot other than the periodic time slot of each of the deterministic queues.

[0077] In the embodiments of the present disclosure, the controller configures a time gating list and delivers it to the node device. In the embodiments of the present disclosure, the controller configures a time gating list for each node device respectively and delivers the configured time gating list to the corresponding node device, so that the node device forwards the data packet according to the corresponding time gating list.

[0078] For example, the time gating list configured and delivered by the controller in the embodiments of the present disclosure is described. In the Figure 4 example, O represents on and C represents off. Figure 4

[0079] As shown in the Figure 4 , the time gating list configured and delivered by the controller has 8 queues in total, which correspond to traffic-classes from 7 to 0 respectively, wherein the queues of traffic-classes 3, 2 and 1 are used as deterministic queues; the time gating list includes 10 time slices T00 to T09, and 10 time slices are used as a gating period to cycle. For the deterministic queue of traffic-class 3, time slices T01 and T02 are periodic time slices; for the deterministic queue of traffic-class 2, time slices T03 and T04 are periodic time slices; for the deterministic queue of traffic-class 1, time slices T08 and T09 are periodic time slices; time slices T00, T05, T06 and T07 are empty time slices. In the deterministic queue of traffic-class 3, the gating corresponding to time slices T01 and T02 is on, and the gating corresponding to time slices T03, T04, T08 and T09 is off; in the deterministic queue of traffic-class 2, the gating corresponding to time slices T03 and T04 is on, and the gating corresponding to time slices T01, T02, T08 and T09 is off; in the deterministic queue of traffic-class 1, the gating corresponding to time slices T08 and T09 is on, and the gating corresponding to time slices T01, T02, T03 and T04 is off; in the deterministic queues of traffic-classes 3, 2 and 1, the gating corresponding to time slices T00, T05, T06 and T07 is on.

[0080] In some scenarios, the controller will Figure 4 ​After the time gating list shown in the figure is issued to the node device, when the burst flow of the deterministic traffic flow corresponding to the deterministic queue of traffic-class 3 is generated and the burst data packet arrives at the deterministic queue of traffic-class 3 at the time slice T05, since the gating of the time slice T05 corresponding to the deterministic queue of traffic-class 3 is open, the burst data packet can be forwarded without waiting for the gating of the time slice T01 of the next gating period to be open, avoiding the increase of the delay and thus not affecting the normal forwarding of the periodic data packet of the time slice T01 of the next gating period.

[0081] In some scenarios, the controller will Figure 4 After the time gating list shown in the figure is issued to the node device, when the burst flow of the deterministic traffic flow corresponding to the deterministic queue of traffic-class 3 is generated and the burst data packet arrives at the deterministic queue of traffic-class 3 at the time slice T05, since the gating of the time slice T05 corresponding to the deterministic queue of traffic-class 3 is open, the burst data packet can be forwarded without waiting for the gating of the time slice T01 of the next gating period to be open, avoiding the increase of the delay and thus not affecting the normal forwarding of the periodic data packet of the time slice T01 of the next gating period.

[0082] In the control method provided by the embodiments of the present disclosure, the controller configures and issues a time gating list, sets the gating of the time slice in which the data packet of the periodic deterministic traffic flow is forwarded in each deterministic queue to be open, and sets the gating of the time slice in which the data packet of the deterministic traffic flow is not forwarded in each deterministic queue to be open, so that the data packet of the burst flow or the data packet that misses the periodic time slice due to jitter can be forwarded in the empty time slice without waiting for the gating of the periodic time slice of the next gating period to be open, ensuring the delay of the deterministic traffic flow and not affecting the normal forwarding of the periodic data packet of the periodic time slice of the next gating period, thereby avoiding the delay jitter.

[0083] The embodiments of the present disclosure do not make special limitation on how to configure the time gating list.

[0084] In some embodiments, a two-phase time-gating list is maintained in the controller, including a real-phase time-gating list (R-GCL) and a virtual-phase time-gating list (V-GCL). The real-phase time-gating list is calculated according to the periodic packet-sending deterministic traffic flow, and is used to configure the gating state of the periodic time slice in the deterministic queue; the virtual-phase time-gating list is used to configure the gating state of the empty time slice in the deterministic queue.

[0085] Correspondingly, in some embodiments, referring to Figure 5 , the time-gating list is configured and issued, including:

[0086] S11, configuring the real-phase time-gating list, wherein in each of the deterministic queues of the real-phase time-gating list, the gating corresponding to the periodic time slice of the deterministic queue is open, the gating corresponding to the periodic time slice of other deterministic queues is closed, and the gating corresponding to the empty time slice is empty;

[0087] S12, configuring the virtual-phase time-gating list, wherein in each of the deterministic queues of the virtual-phase time-gating list, the gating corresponding to the empty time slice is open;

[0088] S13, determining the time-gating list according to the real-phase time-gating list and the virtual-phase time-gating list and issuing.

[0089] In Figure 6 , O represents open, and C represents closed. As Figure 6As shown, in the real-time gating list, for a deterministic queue with traffic-class 3, time slices T01 and TO2 are periodic time slices; for a deterministic queue with traffic-class 2, time slices T03 and TO4 are periodic time slices; for a deterministic queue with traffic-class 1, time slices T08 and TO9 are periodic time slices; and time slices T00, T05, T06, and T07 are empty time slices. In the deterministic queue with traffic-class 3, the gating for time slices T01 and T02 is on, and the gating for time slices T03, T04, T08, and T09 is off. In the deterministic queue with traffic-class 2, the gating for time slices T03 and T04 is on, and the gating for time slices T01, T02, T08, and T09 is off. In the deterministic queue with traffic-class 1, the gating for time slices T08 and T09 is on, and the gating for time slices T01, T02, T03, and T04 is off. Time slices T00, T05, T06, and T07 are empty. In the deterministic queues with traffic-class 3, 2, and 1, the gating for time slices T00, T05, T06, and T07 is empty (NA).

[0090] exist Figure 7 In this context, O represents on and C represents off. For example... Figure 7 As shown, in the virtual phase time gating list, time slices T00, T05, T06, and T07 are empty time slices. In the deterministic queues with traffic-classes 3, 2, and 1, the gating for time slices T00, T05, T06, and T07 is enabled.

[0091] Will Figure 6 The real-time gating list shown and Figure 7 By merging the virtual phase time gating lists shown, we can obtain the following: Figure 4 The time gating list is shown.

[0092] This disclosure does not impose any special limitations on how to configure the real-time gating list.

[0093] In some embodiments, configuring a real-time gating list includes: calculating the path of a target deterministic service flow; calculating the time gate for node devices on the path to forward data packets of the target deterministic service flow; and configuring the real-time gating list according to the time gate.

[0094] In the embodiments of the present disclosure, the controller can configure and issue a time gating list for each node device on the path of a periodic packet-sending deterministic service flow according to an existing deterministic service flow, and the controller can also configure and issue a time gating list for each node device on the path of a newly initiated deterministic service flow according to the newly initiated deterministic service flow. The present disclosure does not specially limit this.

[0095] In some embodiments, the controller configures and issues a time gating list for each node device on the path of a deterministic service flow according to an existing periodic packet-sending deterministic service flow, and the target deterministic service flow refers to the existing periodic packet-sending deterministic service flow. It should be noted that the calculated path of the target deterministic service flow is the path of each existing deterministic service flow, and the calculated time gate is the time gate at which the node device on the path of each existing deterministic service flow forwards the data packet of each existing deterministic service flow. For example, there are multiple deterministic service flows, and according to the priority of each deterministic service flow, one deterministic queue of the time gating list corresponds to one or more deterministic service flows, the controller calculates the path of each deterministic service flow, determines the node device on each path, and then calculates the time gate at which the node device on each path forwards the data packet of each deterministic service flow, thereby determining the periodic time slice of each deterministic queue in the time gating list of the node device, and further determining the empty time slice. When configuring the real time gating list, the gate of the periodic time slice corresponding to the current deterministic queue in each deterministic queue of the time gating list of the node device is set to be opened, the gate of the periodic time slice corresponding to other deterministic queues is set to be closed, and the gate of the empty time slice is set to be empty.

[0096] In some embodiments, the controller configures and issues a time gating list for each node device on the path of a deterministic service flow according to a newly initiated deterministic service flow, and the target deterministic service flow refers to the newly initiated deterministic service flow. It should be noted that the calculated path of the target deterministic service flow is the path of the newly initiated deterministic service flow, and the calculated time gate is the time gate at which the node device on the path of the newly initiated deterministic service flow forwards the data packet of the newly initiated deterministic service flow.

[0097] In some embodiments, the real time gating list is configured according to the time gate, including: setting the gate of the time slice corresponding to the time gate in the deterministic queue corresponding to the target deterministic service flow to be opened; and setting the gate of the time slice corresponding to the time gate in other deterministic queues to be closed.

[0098] In some embodiments, the virtual time gating list is configured, including: configuring the virtual time gating list according to the time gate.

[0099] In some embodiments, the controller configures and issues a time-gating list for each node device on the path of the existing periodic packet-sending deterministic traffic flow according to the time gate calculated for the existing periodic packet-sending deterministic traffic flow, which is the time gate for the node device on the path of the existing periodic packet-sending deterministic traffic flow to forward the data packet of the existing periodic packet-sending deterministic traffic flow. The empty time slot can be determined according to the calculated time gate. When configuring the virtual-phase time-gating list, the gate corresponding to the empty time slot is set to open; and the real-phase time-gating list and the virtual-phase time-gating list are combined to obtain the time-gating list of the node device.

[0100] Correspondingly, in some embodiments, the virtual-phase time-gating list is configured according to the time gate, including: determining the empty time slot according to the time gate; and setting the gate corresponding to the empty time slot to open.

[0101] In some embodiments, the controller configures and issues a time-gating list for each node device on the path of the newly initiated deterministic traffic flow according to the time gate calculated for the newly initiated deterministic traffic flow, which is the time gate for the node device on the path of the newly initiated deterministic traffic flow to forward the data packet of the newly initiated deterministic traffic flow. When configuring the virtual-phase time-gating list, only the gate corresponding to the time gate in the virtual-phase time-gating list needs to be removed.

[0102] Correspondingly, the virtual-phase time-gating list is configured according to the time gate, including: removing the gate of the time slot corresponding to the time gate in the virtual-phase time-gating list.

[0103] The present disclosure does not make special limitations on how to determine the time-gating list according to the real-phase time-gating list and the virtual-phase time-gating list.

[0104] In some embodiments, the time-gating list is determined and issued according to the real-phase time-gating list and the virtual-phase time-gating list, including: combining the real-phase time-gating list and the virtual-phase time-gating list according to the one-to-one correspondence between the time slot and the deterministic queue to obtain the time-gating list; and issuing the time-gating list.

[0105] For example, the real-phase time-gating list shown in FIG. 4 and the virtual-phase time-gating list shown in FIG. 5 are combined to obtain the time-gating list shown in FIG. 6. Figure 6 Figure 7 For example, the real-phase time-gating list shown in FIG. 4 and the virtual-phase time-gating list shown in FIG. 5 are combined to obtain the time-gating list shown in FIG. 6. Figure 4 Figure 6 For example, the real-phase time-gating list shown in FIG. 4 and the virtual-phase time-gating list shown in FIG. 5 are combined to obtain the time-gating list shown in FIG. 6. Figure 7

[0106] In some embodiments, as shown in FIG. 7, the time-gating list of the node device is configured and issued according to the real-phase time-gating list and the virtual-phase time-gating list.​​​Figure 4 、 Figure 6 As shown in FIG. 2, the gate of the queue which is not enabled or used as a common queue is set to be opened, and when there is no deterministic flow in transmission, the background flow is transmitted through the common queue.

[0107] In some embodiments, with reference to Figure 8 , the configuring and delivering the time gating list further comprises:

[0108] S14, setting a flag in the empty time slice.

[0109] Setting the flag in the empty time slice enables the node device to monitor the deterministic traffic flow transmitted in the empty time slice. Since the deterministic traffic flow transmitted in the empty time slice is a burst flow (burst deterministic traffic flow) or a deterministic traffic flow missing the periodic time slice due to jitter (jitter deterministic traffic flow), the monitoring of the burst deterministic traffic flow or the jitter deterministic traffic flow can be realized.

[0110] In some embodiments, when the node device monitors the deterministic traffic flow transmitted in the empty time slice, the node device reports the detection information to the controller.

[0111] In some embodiments, with reference to Figure 8 , the control method further comprises:

[0112] S15, according to the monitoring information reported by the node device, counting the data packets of the burst deterministic traffic flow or the jitter deterministic traffic flow.

[0113] In a second aspect, the embodiments of the present disclosure provide a communication method, with reference to Figure 9 , comprising:

[0114] S2, forwarding the data packets of at least one deterministic data flow according to a time gating list; wherein the time gating list comprises at least one deterministic queue and multiple time slices, the gate of the corresponding periodic time slice of the deterministic queue in each deterministic queue is opened, the gate of the periodic time slice of other deterministic queues is closed, and the gate of the empty time slice is opened, the periodic time slice of the deterministic queue is the time slice corresponding to the time when the deterministic queue periodically forwards the data packets of the deterministic traffic flow, and the empty time slice is the time slice other than the periodic time slice of each deterministic queue.

[0115] In the communication method provided by the embodiments of the present disclosure, the node device can forward the data packets of the deterministic data flow according to the time gating list, wherein the gating of the time slice in which the data packets of the deterministic service flow are periodically forwarded in each deterministic queue in the time gating list is open, and the gating of the time slice in which the data packets of the deterministic service flow are not forwarded in each deterministic queue is open, so that the data packets of the burst flow or the data packets missing the periodic time slice due to jitter can be forwarded in the empty time slice without waiting for the next periodic time slice gating to be open, thereby ensuring the time delay of the deterministic service flow and not affecting the normal forwarding of the periodic data packets in the next periodic time slice, thereby avoiding jitter.

[0116] In some embodiments, the empty time slice of the time gating list is also provided with a flag bit, and the node device can monitor the deterministic service flow transmitted in the empty time slice according to the flag bit. Since the deterministic service flow transmitted in the empty time slice is a burst flow (burst deterministic service flow) or a deterministic service flow missing the periodic time slice due to jitter (jitter deterministic service flow), the monitoring of the burst deterministic service flow or the jitter deterministic service flow can be realized.

[0117] Correspondingly, in some embodiments, forwarding the data packets of the at least one deterministic data flow according to the time gating list comprises: monitoring the data packets of the deterministic service flow transmitted in the empty time slice according to the flag bit; and reporting the monitoring information to the controller.

[0118] In a third aspect, referring to Figure 10 The embodiments of the present disclosure provide a controller, which comprises:

[0119] one or more processors 101;

[0120] a memory 102, on which one or more programs are stored, when the one or more programs are executed by the one or more processors, the one or more processors implement the control method of the first aspect of the embodiments of the present disclosure;

[0121] one or more I / O interfaces 103 connected between the processor and the memory, configured to realize the information interaction between the processor and the memory.

[0122] The processor 101 is a device with data processing capability, including but not limited to a central processing unit (CPU) and the like; the memory 102 is a device with data storage capability, including but not limited to a random access memory (RAM, more specifically, SDRAM, DDR, and the like), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), and a flash memory (FLASH); the I / O interface 103 is connected between the processor 101 and the memory 102, and can realize information interaction between the processor 101 and the memory 102, including but not limited to a data bus (Bus) and the like.

[0123] In some embodiments, the processor 101, the memory 102, and the I / O interface 103 are connected to each other through the bus 104, and further connected to other components of the computing device.

[0124] In the fourth aspect, referring to Figure 11 The node device provided by the embodiments of the present disclosure includes:

[0125] one or more processors 201;

[0126] a memory 202, on which one or more programs are stored, when the one or more programs are executed by the one or more processors, the one or more processors implement the communication method in the second aspect of the embodiments of the present disclosure;

[0127] one or more I / O interfaces 203 connected between the processor and the memory, configured to realize information interaction between the processor and the memory.

[0128] The processor 201 is a device with data processing capability, including but not limited to a central processing unit (CPU) and the like; the memory 202 is a device with data storage capability, including but not limited to a random access memory (RAM, more specifically, SDRAM, DDR, and the like), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), and a flash memory (FLASH); the I / O interface (read-write interface) 203 is connected between the processor 201 and the memory 202, and can realize information interaction between the processor 201 and the memory 202, including but not limited to a data bus (Bus) and the like.

[0129] In some embodiments, the processor 201, the memory 202, and the I / O interface 203 are connected to each other through the bus 204, and further connected to other components of the computing device.

[0130] In the fifth aspect, referring to Figure 12The computer readable medium stores a computer program, and the program is executed by a processor to implement the control method in the first aspect of the embodiments of the present disclosure and / or the communication method in the second aspect of the embodiments of the present disclosure.

[0131] In order for those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present disclosure, the technical solutions provided by the embodiments of the present disclosure are described in detail below through specific embodiments:

[0132] Embodiment one

[0133] In this embodiment, when there is a new deterministic service flow demand, the time-gated list is configured and delivered, including:

[0134] The controller calculates the path according to the new deterministic service flow, and calculates the time gate of each hop node on the path;

[0135] The calculated time gate of each hop node is updated to the real phase time gate list in the existing two-phase time gate list in the controller, and the time slice that needs to be newly opened is set to be opened;

[0136] The virtual phase time gate list in the two-phase time gate list of each hop node in the controller is updated, the time slice corresponding to the deterministic queue in the real phase time gate list is set to be opened, and the others are not set;

[0137] The two-phase time gate list is merged and delivered to the port corresponding to each hop node. If the flag bit is set in the time slice of the virtual phase time gate list, it is delivered to the port of each hop node.

[0138] Embodiment two

[0139] In this embodiment, the time slice corresponding to the virtual phase time gate of the two-phase time gate list is not set with a flag bit.

[0140] The existing real phase time gate list in the controller on the specified port of the specified node is as follows: Figure 13As shown, each time slice is represented by a start time, each time slice has a length of 500ns, O represents opening, C represents closing, and NA represents empty. The queues of traffic-class 3 and 2 are used as deterministic queues. The opening time of the deterministic queue of traffic-class 3 is 500ns to 1500ns, that is, the periodic time slices in the deterministic queue of traffic-class 3 are 500ns and 1000ns, and the gating of the periodic time slices 500ns and 1000ns in the deterministic queue of traffic-class 3 is set to O; the opening time of the deterministic queue of traffic-class 2 is 1500ns to 2500ns, that is, the periodic time slices in the deterministic queue of traffic-class 2 are 1500ns and 2000ns, and the gating of the periodic time slices 1500ns and 2000ns in the deterministic queue of traffic-class 2 is set to O; the gating of the time slices 1500ns and 2000ns in the deterministic queue of traffic-class 3 is set to C, and the gating of the time slices 500ns and 1000ns in the deterministic queue of traffic-class 2 is set to C. The time slices other than the time slices 500ns, 1000ns, 1500ns and 2000ns in the deterministic queues of traffic-class 3 and 2 are empty time slices, and the gating is set to NA.

[0141] The real time gating list as shown in Figure 14 As shown, the gating of the time slices other than the time slices 500ns, 1000ns, 1500ns and 2000ns in the deterministic queues of traffic-class 3 and 2 is all set to O.

[0142] The real time gating list as shown in Figure 13 is merged with the virtual time gating list as shown in Figure 14 , and the actual time gating list obtained after the merging is as shown in Figure 15 .

[0143] When a new deterministic traffic flow of traffic-class 3 needs to be deployed, the path of the new deterministic traffic flow is calculated, wherein the path of the new deterministic traffic flow passes through the specified node and is forwarded from port 1, the time gate is 3500ns to 4000ns, and the real time gating list as shown in Figure 13 is updated to obtain the real time gating list as shown in Figure 16The real phase time gating list shown in FIG. 10 is merged with the virtual phase time gating list shown in FIG. 9 to obtain the time gating list shown in FIG. 11. Figure 14 The virtual phase time gating list shown in FIG. 10 is obtained as shown in FIG. 11. Figure 17 The virtual phase time gating list shown in FIG. 10 is obtained as shown in FIG. 11. Figure 16 The real phase time gating list shown in FIG. 10 is merged with the virtual phase time gating list shown in FIG. 9 to obtain the time gating list shown in FIG. 11. Figure 17 The real phase time gating list shown in FIG. 10 is merged with the virtual phase time gating list shown in FIG. 9 to obtain the time gating list shown in FIG. 11. Figure 18 The real phase time gating list shown in FIG. 10 is merged with the virtual phase time gating list shown in FIG. 9 to obtain the time gating list shown in FIG. 11. Figure 18 The time gating list shown in FIG. 11 is issued to the specified port of the specified node, so that the specified port of the specified node forwards data packets according to the time gating list shown in FIG. 11. Figure 18 The time gating list shown in FIG. 11 is issued to the specified port of the specified node, so that the specified port of the specified node forwards data packets according to the time gating list shown in FIG. 11.

[0144] In this embodiment, it is assumed that the deterministic traffic flow corresponding to the traffic-class 2 deterministic traffic flow originally transmits at 2300ns, and due to the jitter of the upstream node, the time of arrival at the specified port of the specified node is 2600ns, while the gating of the time gating list shown in FIG. 11 at 2600ns is open, and the data packet can be forwarded. Figure 18 The time gating list shown in FIG. 11 is issued to the specified port of the specified node, so that the specified port of the specified node forwards data packets according to the time gating list shown in FIG. 11.

[0145] By contrast, according to the standard periodic gating list forwarding, the gating at 2600ns is closed, and needs to be forwarded at the next open time slice, while the next open time slice in the periodic gating list is arranged for the existing deterministic traffic flow, and thus will affect the transmission of the existing deterministic traffic flow.

[0146] Embodiment Three

[0147] In this embodiment, the time slice corresponding to the virtual phase time gating list of the two-phase gating list is provided with a flag bit.

[0148] In this embodiment, the existing time gating list is as shown in FIG. 10, and the updated time gating list is as shown in FIG. 11. Figure 15 In this embodiment, the existing time gating list is as shown in FIG. 10, and the updated time gating list is as shown in FIG. 11. Figure 18The time slice corresponding to the virtual phase time gating list is set with a flag, and the data packet forwarded in the empty time slice needs to be monitored. When the updated time gating list is issued to the specified port of the specified node, the flag of the empty time slice is also issued, and the monitoring is started in the time of 0-500ns, 2500ns-3500ns and 4000ns-5000ns corresponding to the virtual phase time gating list. Assuming that the burst stream corresponding to the traffic-class 2 deterministic queue is transmitted, the burst stream data packet arrives at the specified port of the specified node at the time of 3500ns, and the gating at the time of 3500ns is arranged for the deterministic service stream corresponding to the deterministic queue of the traffic-class 3, the deterministic queue of the traffic-class 2 is closed at the time of 3500ns, and as shown in the time gating list, the gating at the time of 4000ns is open, so the burst stream can be transmitted at the time of 4000ns. The deterministic service stream corresponding to the traffic-class 2 deterministic queue is monitored in the time of 4000ns, and is reported to the controller. The reported value can be used to count the data packet of the burst stream or the data packet missed due to jitter. Figure 18

[0149] ​Those of ordinary skill in the art will realize and understand that all or some of the steps in the methods disclosed above and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, it is common knowledge to those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

[0150] Example embodiments have been disclosed herein and, although the use of specific terms is expressly used herein, they are intended in a generic sense only and are not intended to limit the scope of the present disclosure. In some instances, it will be apparent to those skilled in the art that features, characteristics or / and elements described in connection with a particular embodiment can be used in conjunction with other embodiments unless otherwise explicitly stated. As such, those skilled in the art will appreciate that various changes can be made in form and detail without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A control method, comprising: configuring and delivering a time gating list; wherein the time gating list comprises at least one deterministic queue and a plurality of time slices, in each of the deterministic queues, the gating of the periodic time slice corresponding to the deterministic queue is open, the gating of the periodic time slice corresponding to other deterministic queues is closed, and the gating of the empty time slice is open, the periodic time slice of the deterministic queue is a time slice corresponding to a time when the deterministic queue periodically forwards data packets of a deterministic service flow, and the empty time slice is a time slice other than the periodic time slice of each of the deterministic queues; wherein configuring and delivering the time gating list comprises: configuring a real-time gating list, wherein in each of the deterministic queues of the real-time gating list, the gating of the periodic time slice corresponding to the deterministic queue is open, the gating of the periodic time slice corresponding to other deterministic queues is closed, and the gating of the empty time slice is empty; configuring a virtual-time gating list, wherein in each of the deterministic queues of the virtual-time gating list, the gating of the empty time slice is open; determining the time gating list according to the real-time gating list and the virtual-time gating list and delivering the time gating list.

2. The control method according to claim 1, wherein configuring a real-time gating list comprises: calculating a path of a target deterministic service flow; calculating a time gate of a node device on the path for forwarding data packets of the target deterministic service flow; configuring the real-time gating list according to the time gate.

3. The control method according to claim 2, wherein configuring the real-time gating list according to the time gate comprises: setting the gating of the time slice corresponding to the time gate in the deterministic queue corresponding to the target deterministic service flow to open; setting the gating of the time slice corresponding to the time gate in other deterministic queues to close.

4. The control method according to claim 2, wherein configuring a virtual-time gating list comprises: configuring the virtual-time gating list according to the time gate.

5. The control method according to claim 4, wherein configuring the virtual-time gating list according to the time gate comprises: determining the empty time slice according to the time gate; setting the gating of the empty time slice to open.

6. The control method according to claim 4, wherein configuring the virtual-time gating list according to the time gate comprises: removing the gating of the time slice corresponding to the time gate in the virtual-time gating list.

7. The control method according to claim 1, wherein determining the time gating list according to the real-time gating list and the virtual-time gating list and delivering the time gating list comprises: merging the real-time gating list and the virtual-time gating list according to the time slice and the deterministic queue one by one to obtain the time gating list; delivering the time gating list.

8. The control method according to any one of claims 1 to 7, wherein configuring and delivering the time gating list further comprises: setting a flag bit in the empty time slice.

9. The control method according to claim 8, wherein The control method further comprises: statistically processing data packets of a burst deterministic service flow or a jitter deterministic service flow according to monitoring information reported by a node device. 10.A communication method, comprising: forwarding data packets of at least one deterministic data flow according to a time gating list; wherein the time gating list is configured and delivered according to the control method of any one of claims 1 to 9.

11. The communication method according to claim 10, wherein, Forwarding data packets of at least one deterministic data flow according to a time-gated list, comprising: Monitoring data packets of the deterministic data flow transmitted in the empty time slice according to the flag bit; Reporting the monitoring information to a controller. 12.A controller, comprising: one or more processors; a memory having stored therein one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement the control method according to any one of claims 1 to 9. 13.A node device, comprising: one or more processors; a memory having stored therein one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement the communication method according to claim 10 or 11. 14.A computer readable medium having stored thereon a computer program, which, when executed by a processor, implements at least one of the following methods: the control method according to any one of claims 1 to 9; the communication method according to claim 10 or 11.

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