A method for preparing an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor

Abstract

The present invention discloses a method for preparing an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor. The method comprises the following steps: depositing a first layer of interconnected metal film such as aluminum on an insulating substrate such as glass, depositing a layer of photoresist on the first layer of interconnected metal film such as aluminum, etching away the photoresist covering a central metal region of the first layer of interconnected metal film such as aluminum according to a pre-designed photolithography pattern, retaining the photoresist on the right side, growing a high-dielectric-constant dielectric film, and generating a first layer of high-dielectric-constant dielectric capacitor; growing a second layer of high-dielectric-constant dielectric capacitor on the left side of the first layer of high-dielectric-constant dielectric; repeating the above interdigital operation until a layer of interconnected metal film such as aluminum is grown at the top; and etching away the central photoresist of the topmost layer of high-dielectric-constant dielectric capacitor and the corresponding interconnected metal film such as aluminum above it using a lift-off process, forming interconnection leads on the left and right sides, and generating an isolation chip.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitor isolation chips, and more particularly to a method for preparing an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor. Background Art

[0002] With advances in modern energy and information technologies, the era of automotive electrification has arrived. New energy and IoT technologies are rapidly evolving, placing high demands on IC systems. Isolation technology is now required to have high processing speeds, miniaturization, and high reliability to meet application requirements. Isolation technologies primarily include optocoupler isolation, inductive isolation, and capacitive isolation. In applications requiring fast response speeds, small size, and resistance to strong electromagnetic interference, capacitive isolation is generally considered a better choice, offering advantages across all three metrics. Traditional capacitive isolation technology suffers from high signal frequencies, and the dielectric of traditional capacitive isolation chips has four sides facing the air, significantly impacted by external electromagnetic interference.

[0003] The main drawback of existing capacitive isolation chips is their high complexity. Traditional capacitive isolation chips typically have a complex circuit structure. Because the signal frequency in the transmission circuit cannot be too low, otherwise it cannot be transmitted to the receiving circuit, multiple circuit modules, such as oscillator circuits and signal modulation circuits, must work together. Typical operating frequencies reach 500 MHz or above, within the radio frequency band. This makes circuit design difficult and manufacturing costs high. Furthermore, the higher the frequency, the more significant the impact of parasitic parameters, increasing the probability of tape-out failures, which indirectly increases design and manufacturing costs. High power consumption: Traditional capacitive isolation chips require modulation of high-frequency carrier signals on the transmitter side and demodulation and other signal processing on the receiver side. For CMOS circuits, power consumption primarily consists of static and dynamic power, with the latter accounting for the majority. Dynamic power consumption is proportional to frequency, resulting in high power consumption for traditional isolation chips, which is particularly disadvantageous in low-power mobile and portable devices. Noise and distortion: Due to the complex circuit structure and high carrier frequency, traditional isolation chips struggle to meet high-precision signal-to-noise ratio and distortion requirements. Jitter: Clock jitter in traditional isolation chips inevitably introduces communication errors, especially in high-precision, high-reliability data acquisition applications, where jitter can cause signal distortion and errors. Nonlinearity: Traditional isolation chips often exhibit nonlinear issues, such as differential nonlinearity, which can affect their accuracy and performance. Noise: Traditional isolation chips use higher-frequency carriers, making the transmitting circuit, channel, and receiving circuits more sensitive to noise, reducing circuit reliability and signal fidelity. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the present invention provides a method for preparing an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor.

[0005] According to one aspect of the present invention, a method for preparing an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor is provided, comprising:

[0006] Depositing a first layer of interconnected metal film such as aluminum on an insulating substrate such as glass, and depositing a layer of photoresist on the first layer of interconnected metal film such as aluminum, and etching away the photoresist covering the middle metal region of the first layer of interconnected metal film such as aluminum according to a pre-designed photolithography pattern, leaving the photoresist on the right side;

[0007] Growing a high-dielectric-constant dielectric film on a first layer of interconnected metal film such as aluminum to generate a first layer of high-dielectric-constant dielectric capacitor;

[0008] A second layer of interconnected metal film such as aluminum is grown on the first layer of high-k dielectric, and a layer of photoresist is deposited on the second layer of interconnected metal film such as aluminum. The photoresist covering the middle metal region of the second layer of interconnected metal film such as aluminum is etched away according to the designed photolithography pattern, leaving the photoresist on the left side.

[0009] Growing a high-k dielectric film on the second layer of interconnecting metal film such as aluminum to generate a second layer of high-k dielectric capacitor, wherein the left edge of the second layer of high-k dielectric is at a first predetermined distance to the left of the left edge of the first layer of high-k dielectric, and the right edge of the second layer of high-k dielectric is at a second predetermined distance to the right of the right edge of the first layer of high-k dielectric;

[0010] Generate a third layer of high-dielectric-constant capacitors according to the method for generating the first layer of high-dielectric-constant capacitors, and generate a fourth layer of high-dielectric-constant capacitors according to the method for generating the second layer of high-dielectric-constant capacitors. Repeat the above operations and after generating the last layer of high-dielectric-constant dielectric film, use a photolithography lift-off process to dissolve all photoresists.

[0011] A layer of photoresist is deposited on the surface of the topmost high-k dielectric film, and the photoresist in the middle area is retained according to the photolithography pattern. The photoresist on the left and right sides is etched away, and then a layer of interconnect metal film such as aluminum is grown;

[0012] Using the lift-off process, the middle photoresist of the top-layer high-k dielectric capacitor and the corresponding aluminum and other interconnect metal films above it are etched away, forming interconnect leads on the left and right sides to generate an isolation chip.

[0013] Optionally, a layer of photoresist is deposited on the interconnected metal film such as aluminum, including: using a wrestling machine to deposit the photoresist on the interconnected metal film such as aluminum.

[0014] Optionally, the photolithography pattern is rectangular or circular.

[0015] Optionally, growing a high-dielectric-constant dielectric film on an interconnected metal film such as aluminum includes: growing a high-dielectric-constant dielectric film on an interconnected metal film such as aluminum using a sputtering technique or an electron beam.

[0016] Optionally, the high-k dielectric film is HfO 2 or Ti oxide or Y oxide or La oxide or Ta oxide or Al oxide.

[0017] According to another aspect of the present invention, there is provided an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor prepared by the above-mentioned method for preparing an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor, comprising: interdigital electrodes and a multilayer dielectric.

[0018] According to another aspect of the present invention, there is provided a device for preparing an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor, comprising:

[0019] The first deposition module is used to deposit a first layer of interconnected metal film such as aluminum on an insulating substrate such as glass, and deposit a layer of photoresist on the first layer of interconnected metal film such as aluminum. According to a pre-designed photolithography pattern, the photoresist covering the central metal region of the first layer of interconnected metal film such as aluminum is etched away, leaving the photoresist on the right side.

[0020] The first generation module is used to grow a high-dielectric-constant dielectric film on a first layer of interconnected metal film such as aluminum to generate a first layer of high-dielectric-constant dielectric capacitor;

[0021] The second deposition module is used to grow a second layer of interconnected metal film such as aluminum on the first layer of high dielectric constant dielectric, deposit a layer of photoresist on the second layer of interconnected metal film such as aluminum, and etch away the photoresist covering the middle metal region of the second layer of interconnected metal film such as aluminum according to the designed photolithography pattern, leaving the photoresist on the left side;

[0022] a second generating module, configured to grow a high-k dielectric film on a second layer of interconnecting metal film such as aluminum to generate a second layer of high-k dielectric capacitor, wherein a left edge of the second layer of high-k dielectric is at a first predetermined distance to the left of a left edge of the first layer of high-k dielectric, and a right edge of the second layer of high-k dielectric is at a second predetermined distance to the right of a right edge of the first layer of high-k dielectric;

[0023] a third generation module, configured to generate a third layer of high-dielectric-constant capacitors according to the generation method of the first layer of high-dielectric-constant capacitors, and to generate a fourth layer of high-dielectric-constant capacitors according to the generation method of the second layer of high-dielectric-constant capacitors, repeat the above operations, and after generating the last layer of high-dielectric-constant dielectric film, use a photolithography lift-off process to dissolve all photoresists;

[0024] The third deposition module is used to deposit a layer of photoresist on the surface of the top high-k dielectric film. According to the photolithography pattern, the photoresist in the middle area is retained, the photoresist on the left and right sides is etched away, and then a layer of interconnect metal film such as aluminum is grown.

[0025] The fourth generation module is used to use the lift-off process to etch away the middle photoresist of the top-layer high-k dielectric capacitor and the corresponding aluminum and other interconnect metal films above it, forming interconnect leads on the left and right sides to generate an isolation chip.

[0026] Therefore, the present invention provides a capacitor isolation technology and its preparation process with fast response, strong anti-interference ability, low frequency operation, high integration and low power consumption, so as to meet the needs of high-speed data acquisition, signal processing and control in high-voltage and high-current environments. This technology realizes signal transmission through frequency modulation, and realizes transmission through high-dielectric-constant dielectric interdigital capacitor isolators to reach the receiving end. Since high-dielectric-constant dielectric interdigital capacitor isolators allow lower frequency transmission than traditional modulation waves, this architecture can greatly simplify the transmitter and receiver circuits, reduce the cost of chip design and production, and reduce power consumption. Since high-dielectric-constant dielectric interdigital capacitor isolators are more compact than traditional capacitor isolators, with smaller volume and area, combined with simplified transmitter and receiver circuits, the anti-electromagnetic interference ability of the isolation chip can be effectively enhanced, so it has greater advantages in terms of reliability. The total chip area of ​​this architecture is smaller than that of traditional isolation chips, and therefore has more advantages in application fields. The preparation process of the high-dielectric-constant dielectric interdigital capacitor of this architecture is fully compatible with the preparation process of integrated circuits, and can be photolithographically processed using lift-off technology, which can significantly reduce the photolithography cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] A more complete understanding of exemplary embodiments of the present invention may be obtained by referring to the following drawings:

[0028] Figure 1 This is a flow chart of a method for preparing an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor according to the first aspect of the embodiment of the present application;

[0029] FIG2 is a schematic diagram of a process for preparing an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor according to the first aspect of an embodiment of the present application;

[0030] Figure 3 It is a structural schematic diagram of an isolation chip preparation device based on high dielectric constant dielectric interdigital capacitors provided in the third aspect of the embodiment of the present application. DETAILED DESCRIPTION

[0031] Below, the exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments of the present invention, and it should be understood that the present invention is not limited to the exemplary embodiments described herein.

[0032] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0033] Those skilled in the art will understand that the terms "first" and "second" in the embodiments of the present invention are only used to distinguish different steps, devices or modules, and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0034] It should also be understood that, in the embodiments of the present invention, “a plurality of” may refer to two or more than two, and “at least one” may refer to one, two or more than two.

[0035] It should also be understood that any component, data or structure mentioned in the embodiments of the present invention can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0036] In addition, the term "and / or" in this invention merely describes an association relationship between related objects, indicating that three possible relationships exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Furthermore, the character " / " in this invention generally indicates that the related objects are in an "or" relationship.

[0037] It should also be understood that the description of the various embodiments of the present invention focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced with each other. For the sake of brevity, they will not be described one by one.

[0038] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0039] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0040] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0041] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0042] Figure 1 This is a flow chart of a method for preparing an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor according to the first aspect of the present invention. This embodiment can be applied to electronic devices, such as Figure 1 As shown, the method 100 for preparing an isolation chip based on a high-k dielectric interdigital capacitor includes the following steps:

[0043] Step 101: depositing a first layer of interconnected metal film such as aluminum on an insulating substrate such as glass, and depositing a layer of photoresist on the first layer of interconnected metal film such as aluminum. Then, etching away the photoresist covering the central metal region of the first layer of interconnected metal film such as aluminum according to a pre-designed photolithography pattern, leaving the photoresist on the right side.

[0044] Step 102, growing a high-k dielectric film on the first layer of interconnecting metal film such as aluminum to form a first layer of high-k dielectric capacitor;

[0045] Step 103: growing a second layer of interconnecting metal film such as aluminum on the first layer of high-k dielectric, and depositing a layer of photoresist on the second layer of interconnecting metal film such as aluminum. Then, according to the designed photolithography pattern, etching away the photoresist covering the central metal region of the second layer of interconnecting metal film such as aluminum, leaving the photoresist on the left side.

[0046] Step 104: growing a high-k dielectric film on the second layer of interconnecting metal film such as aluminum to form a second layer of high-k dielectric capacitor, wherein the left edge of the second layer of high-k dielectric is at a first predetermined distance to the left of the left edge of the first layer of high-k dielectric, and the right edge of the second layer of high-k dielectric is at a second predetermined distance to the right of the right edge of the first layer of high-k dielectric.

[0047] Step 105: Generate a third layer of high-k dielectric capacitors according to the method for generating the first layer of high-k dielectric capacitors, and generate a fourth layer of high-k dielectric capacitors according to the method for generating the second layer of high-k dielectric capacitors. Repeat the above steps and after generating the last layer of high-k dielectric film, use a photolithography lift-off process to dissolve all photoresists.

[0048] Step 106: depositing a layer of photoresist on the topmost high-k dielectric film, retaining the photoresist in the middle region according to the photolithography pattern, etching away the photoresist on the left and right sides, and then growing a layer of interconnecting metal film such as aluminum;

[0049] Step 107 , using a lift-off process, etches away the middle photoresist of the top-most high-k dielectric capacitor and the corresponding aluminum or other interconnection metal film above it, forming interconnection leads on the left and right sides to generate an isolation chip.

[0050] Optionally, a layer of photoresist is deposited on the interconnected metal film such as aluminum, including: using a wrestling machine to deposit the photoresist on the interconnected metal film such as aluminum.

[0051] Optionally, the photolithography pattern is rectangular or circular.

[0052] Optionally, growing a high-dielectric-constant dielectric film on an interconnected metal film such as aluminum includes: growing a high-dielectric-constant dielectric film on an interconnected metal film such as aluminum using a sputtering technique or an electron beam.

[0053] Optionally, the high-k dielectric film is HfO 2 or Ti oxide or Y oxide or La oxide or Ta oxide or Al oxide.

[0054] Specifically, the structure of the high-k dielectric interdigital capacitor compatible with the integrated circuit manufacturing process of the present application includes the structure of the electrodes and the spatial configuration of the dielectric.

[0055] The preparation process of high dielectric constant dielectric interdigital capacitors is shown in reference Figure 2a to Figure 2f . Among them, all the design and manufacturing processes of high dielectric constant dielectric finger capacitors are fully compatible with existing integrated circuit design and production processes. By increasing the number of finger electrodes and dielectric layers, the chip area occupied by the capacitor can be made smaller while ensuring that the capacitance meets the requirements. For the same capacitance, the volume occupied by high dielectric constant dielectric finger capacitors is much smaller than that of traditional silicon dioxide or polyimide isolation capacitors. Although the production cost of high dielectric constant dielectric finger isolation capacitors is higher than that of silicon dioxide or polyimide isolation capacitors, the use of high dielectric constant dielectric finger capacitors can significantly reduce the design and production costs of signal transmission circuits and receiving circuits due to the reduction in carrier frequency, so the total cost is more advantageous. In addition, the lower frequency carrier circuit reduces parasitic effects and electromagnetic interference problems caused by the circuit itself and external factors.

[0056] refer to Figure 2a to Figure 2f The present invention is characterized in that it is fully compatible with the design and manufacturing process of integrated circuits.

[0057] Figure 2aDeposit interconnect metals such as aluminum (green) on an insulating substrate such as glass; use a spin coating machine to deposit a layer of photoresist (photoresist) on the interconnect metal film; design a photolithography pattern (taking a rectangle as an example, but not limited to a rectangle) to expose metal on the right edge to prepare for subsequent metal connections), expose and etch, and the photoresist covering the middle metal area that acts as a capacitor plate is etched away, while the photoresist on the right side remains; use sputtering (RF or DC mode) or electron beam (generally, the sputtering growth rate is lower than the electron beam, but the former has better density. If high voltage isolation level is to be achieved, the electron beam growth method can be preferred) to grow a high dielectric constant dielectric film such as HfO2 (not limited to HfO2, it can also be oxides of Ti, Y, La, Ta, Al, etc.). This is the first layer of high dielectric constant dielectric.

[0058] Figure 2b A layer of interconnect metal such as aluminum (red) is grown on the first layer of high-k dielectric; a layer of photoresist (photoresist) is deposited on the interconnect metal film using a spin coating machine; a photolithography pattern is designed (taking a rectangle as an example, but not limited to a rectangle) to expose metal on the left edge in preparation for subsequent metal connections, exposed and etched, the photoresist covering the middle metal area that acts as a capacitor plate is etched away, and the photoresist on the left is retained; a high-k dielectric film such as HfO2 (not limited to HfO2, it can also be oxides of Ti, Y, La, Ta, Al, etc.) is grown using sputtering (RF or DC mode) or electron beam (generally, the sputtering growth rate is lower than that of the electron beam, but the former has better density. If high-voltage isolation levels are to be achieved, the electron beam growth method is preferred). This is the second layer of the high-k dielectric.

[0059] Figure 2c A layer of interconnect metal such as aluminum (green) is grown on the second layer of high-k dielectric; a layer of photoresist (photoresist) is deposited on the interconnect metal film using a spin coating machine; a photolithography pattern is designed (taking a rectangle as an example, but not limited to a rectangle) to expose metal on the right edge in preparation for subsequent metal connections, exposed and etched, the photoresist covering the middle metal area that acts as a capacitor plate is etched away, and the photoresist on the right is retained; a high-k dielectric film such as HfO2 (not limited to HfO2, it can also be oxides of Ti, Y, La, Ta, Al, etc.) is grown using sputtering (RF or DC mode) or electron beam (generally, the sputtering growth rate is lower than that of the electron beam, but the former has better density. If isolation of high voltage levels is to be achieved, the electron beam growth method can be preferred). This is the third layer of the high-k dielectric.

[0060] Figure 2dA layer of interconnect metal such as aluminum (red) is grown on the third layer of high-dielectric-constant dielectric; a layer of photoresist (photoresist) is deposited on the interconnect metal film using a spin coating machine; a photolithography pattern is designed (taking a rectangle as an example, but not limited to a rectangle) to expose metal on the left edge in preparation for subsequent metal connections, exposed and etched, the photoresist covering the middle metal area that acts as a capacitor plate is etched away, and the photoresist on the left is retained; a high-dielectric-constant dielectric film such as HfO2 (not limited to HfO2, it can also be oxides of Ti, Y, La, Ta, Al, etc.) is grown using sputtering (RF or DC mode) or electron beam (generally, the sputtering growth rate is lower than that of the electron beam, but the former has better density. If isolation of high voltage levels is to be achieved, the electron beam growth method can be preferred). This is the fourth layer of high-dielectric-constant dielectric.

[0061] Figure 2e A layer of interconnect metal such as aluminum (green) is grown on the fourth layer of high dielectric constant dielectric; a layer of photoresist (photoresist) is deposited on the interconnect metal film using a spin coating machine; a photolithography pattern is designed (taking a rectangle as an example, but not limited to a rectangle) to expose metal on the right edge in preparation for subsequent metal connections, exposed and etched, the photoresist covering the middle metal area that acts as a capacitor plate is etched away, and the photoresist on the right side is retained; a high dielectric constant dielectric film such as HfO2 (not limited to HfO2, it can also be oxides of Ti, Y, La, Ta, Al, etc.) is grown using sputtering (RF or DC mode) or electron beam (generally, the sputtering growth rate is lower than that of the electron beam, but the former has better density. If isolation of high voltage levels is to be achieved, the electron beam growth method can be preferred). This is the fifth layer of high dielectric constant dielectric.

[0062] Figure 2f This method can be used repeatedly to sequentially grow any number of layers of interconnected metal films and high-dielectric-constant dielectric films. After growing the last layer of dielectric film, a lift-off process using photolithography is used to dissolve away all the photoresist from the previous steps, exposing the metal surfaces on the left and right sides. A layer of photoresist is deposited on the topmost dielectric surface using a spin coating machine. After exposure and etching, the photoresist in the middle area is retained, while the photoresist on the left and right sides is etched away. Another layer of interconnected metal film is grown. Using a lift-off process, the middle photoresist and the corresponding metal film above it are etched away. All corresponding plates of the capacitor are interconnected, forming interconnection leads that can be connected to external transceiver circuits, which can be achieved by wire bonding.

[0063] Figure 2fThe alternative is: after growing the last layer of dielectric film, use the photolithography lift-off process to dissolve all the photoresist in the previous steps to expose the metal surfaces on the left and right sides; use an electron beam (or sputtering, or thermal evaporation) to grow a layer of interconnected metal film (aluminum or other conductive metal), at this time the interconnected metal film covers the entire wafer surface; use a spin coating machine to deposit a layer of photoresist, expose and etch, so that the metal on the left and right sides is retained, and the metal in the middle area is etched away, so that there is no metal connection between the two electrodes of the high dielectric constant interdigital capacitor.

[0064] Figure 2f Another alternative is: after growing the last layer of dielectric film, apply photoresist, perform photolithography, and retain the photoresist in the central area (after the photoresist in this area is removed, the metal electrodes on the left and right sides are separated to avoid electrical short circuit); use electron beam (or sputtering, or thermal evaporation) to grow a layer of interconnect metal film (aluminum or other conductive metal), at this time the interconnect metal film covers the entire wafer surface; use the photolithography lift-off process to dissolve all the photoresist in the previous steps, and complete the metal connections on the left and right sides respectively.

[0065] The above is the design and manufacturing process of a five-layer high dielectric constant dielectric interdigital capacitor. This method can be repeatedly used and can be successively extended to the design and manufacturing of any multi-layer high dielectric constant dielectric interdigital isolation capacitor.

[0066] The high-k dielectric can be HfO2, TiO2, La2O3, Y2O5, or a mixture thereof. The interconnect metal can be Al or a metal with good conductivity such as Cu or Au.

[0067] Therefore, the present application aims to provide a capacitor isolation technology and its preparation process with fast response, strong anti-interference ability, low frequency operation, high integration and low power consumption, so as to meet the needs of high-speed data acquisition, signal processing and control in high-voltage and high-current environments. This technology realizes signal transmission through frequency modulation, and realizes transmission through high-dielectric-constant dielectric fork-finger capacitor isolators to reach the receiving end. Since high-dielectric-constant dielectric fork-finger capacitor isolators allow lower frequency transmission than traditional modulated waves, this architecture can greatly simplify the transmitter and receiver circuits, reduce the cost of chip design and production, and reduce power consumption. Since high-dielectric-constant dielectric fork-finger capacitor isolators are more compact than traditional capacitor isolators, with smaller volume and area, combined with simplified transmitter and receiver circuits, the anti-electromagnetic interference ability of the isolation chip can be effectively enhanced, so it has greater advantages in terms of reliability. The total chip area of ​​this architecture is smaller than that of traditional isolation chips, and therefore has more advantages in application fields. The preparation process of the high-dielectric-constant dielectric fork-finger capacitor of this architecture is fully compatible with the preparation process of integrated circuits, and can be photolithographically processed using lift-off technology, which can significantly reduce the cost of photolithography.

[0068] By using high-k dielectric materials instead of silicon dioxide, polyimide, and other materials used in traditional capacitor isolation chips, this new technology achieves greater coupling capacitance and reduces the transmission impedance of communication signals, allowing for the transmission of lower-frequency signals, given the same isolation voltage level and capacitor plate area.

[0069] High-k dielectric materials can be grown through methods such as sputtering (RF or DC mode) or electron beam (e-beam) evaporation. By selecting the appropriate target material, high-k dielectric thin films can be deposited in a vacuum environment. For example, to prepare HfO2 dielectrics, simply place an HfO2 target in the sputtering chamber and deposit the film using RF magnetron sputtering. Alternatively, an HfO2 target can be placed in an electron beam evaporator and deposited using electron beam evaporation to obtain HfO2 films of appropriate thickness.

[0070] The fabrication method for interdigital capacitors based on high-k dielectrics is fully compatible with integrated circuit production processes and can significantly reduce the area and volume of isolation chips, lower chip design and tape-out costs, and reduce chip power consumption.

[0071] The present invention can be used for isolation between high-voltage circuit systems and low-voltage circuit systems and for signal communication; the frequency modulation circuit controls the voltage-controlled oscillator through an input signal, and uses the output signal of the voltage-controlled oscillator as a modulation signal, which is transmitted in a differential form on a high-dielectric-constant interdigital isolation capacitor to reach the receiving end.

[0072] This invention designs and manufactures a capacitor isolation chip based on a high-permittivity dielectric and an interdigital capacitor structure. This addresses the high signal frequency issues inherent in conventional capacitor isolation technology by introducing a high-permittivity dielectric and an interdigital capacitor structure. This solves both the high signal frequency and low withstand voltage issues while significantly reducing the footprint of the isolation chip. Furthermore, whereas four sides of the dielectric in conventional capacitor isolation chips face the air, only two sides of the interdigital capacitor dielectric face the air. This significantly reduces external electromagnetic interference and improves operational reliability.

[0073] Therefore, the present invention aims to provide a capacitor isolation technology and its preparation process with fast response, strong anti-interference ability, low frequency operation, high integration and low power consumption, so as to meet the needs of high-speed data acquisition, signal processing and control in high-voltage and high-current environments. This technology realizes signal transmission through frequency modulation, and realizes transmission through high-dielectric-constant dielectric interdigital capacitor isolators to reach the receiving end. Since high-dielectric-constant dielectric interdigital capacitor isolators allow lower frequency transmission than traditional modulated waves, this architecture can greatly simplify the transmitter and receiver circuits, reduce the cost of chip design and production, and reduce power consumption. Since high-dielectric-constant dielectric interdigital capacitor isolators are more compact than traditional capacitor isolators, with smaller volume and area, combined with simplified transmitter and receiver circuits, they can effectively enhance the anti-electromagnetic interference ability of the isolation chip, and therefore have greater advantages in terms of reliability. The total chip area of ​​this architecture is smaller than that of traditional isolation chips, and therefore has more advantages in application fields. The preparation process of the high-dielectric-constant dielectric interdigital capacitor of this architecture is fully compatible with the preparation process of integrated circuits, and can be photolithographically processed using lift-off technology, which can significantly reduce the photolithography cost.

[0074] In addition, the second aspect of the present application provides an isolation chip based on a high dielectric constant dielectric interdigital capacitor prepared by the method described in the first aspect of the embodiment of the present application, including: interdigital electrodes and a multilayer dielectric.

[0075] also, Figure 3 The third aspect of the present application provides a schematic structural diagram of an isolation chip preparation device based on a high dielectric constant dielectric interdigital capacitor. Figure 3 As shown, the apparatus 300 includes:

[0076] The first deposition module 310 is configured to deposit a first layer of interconnected metal film such as aluminum on an insulating substrate such as glass, deposit a layer of photoresist on the first layer of interconnected metal film such as aluminum, and etch away the photoresist covering the central metal region of the first layer of interconnected metal film such as aluminum according to a pre-designed photolithography pattern, leaving the photoresist on the right side.

[0077] A first generating module 320 is configured to grow a high-k dielectric film on the first layer of interconnected metal film such as aluminum to generate a first layer of high-k dielectric capacitors;

[0078] The second deposition module 330 is configured to grow a second layer of interconnecting metal film such as aluminum on the first layer of high-k dielectric, deposit a layer of photoresist on the second layer of interconnecting metal film such as aluminum, and etch away the photoresist covering the middle metal region of the second layer of interconnecting metal film such as aluminum according to the designed photolithography pattern, leaving the photoresist on the left side;

[0079] A second generating module 340 is configured to grow a high-k dielectric film on the second layer of interconnected metal film such as aluminum to generate a second layer of high-k dielectric capacitor, wherein a left edge of the second layer of high-k dielectric is at a first predetermined distance to the left of the left edge of the first layer of high-k dielectric, and a right edge of the second layer of high-k dielectric is at a second predetermined distance to the right of the right edge of the first layer of high-k dielectric;

[0080] a third generation module 350 configured to generate a third layer of high-k dielectric capacitors according to the method for generating the first layer of high-k dielectric capacitors, and to generate a fourth layer of high-k dielectric capacitors according to the method for generating the second layer of high-k dielectric capacitors, repeating the above operations and, after generating the last layer of high-k dielectric film, dissolving all photoresist using a lift-off process of photolithography;

[0081] The third deposition module 360 ​​is used to deposit a layer of photoresist on the surface of the top high-k dielectric film, retain the photoresist in the middle area according to the photolithography pattern, etch away the photoresist on the left and right sides, and then grow a layer of interconnect metal film such as aluminum;

[0082] The fourth generation module 370 is used to use a lift-off process to etch away the middle photoresist of the top-layer high-k dielectric capacitor and the corresponding aluminum or other interconnection metal film above it, forming interconnection leads on the left and right sides to generate an isolation chip.

[0083] Optionally, the first deposition module 310, the second deposition module 330 and the third deposition module 360 ​​include: a deposition submodule for depositing the photoresist on the interconnected metal film such as aluminum by using a wrestling machine.

[0084] Optionally, the photolithography pattern is rectangular or circular.

[0085] Optionally, the first generation module 320 , the second generation module 340 and the third generation module 350 include: a growth submodule for growing the high dielectric constant dielectric film on the interconnect metal film such as aluminum by using sputtering technology or electron beam.

[0086] Optionally, the high dielectric constant dielectric film is HfO 2 or Ti oxide or Y oxide or La oxide or Ta oxide or Al oxide.

[0087] Specifically, the device has the same effect as the method described in the first aspect of the embodiment of the present application, and will not be described in detail here.

[0088] The basic principles of the present invention have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in the present invention are merely illustrative and non-limiting, and should not be construed as necessarily possessed by each embodiment of the present invention. Furthermore, the specific details disclosed above are provided for illustrative purposes and to facilitate understanding, and are not intended to be limiting. These details do not necessarily limit the present invention to being implemented using these specific details.

[0089] Each embodiment in this specification is described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. References to the same or similar parts between the various embodiments are sufficient. For system embodiments, since they largely correspond to method embodiments, their description is relatively simple. For relevant parts, references to the description of the method embodiments are sufficient.

[0090] The above description has been provided for the purpose of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present invention to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method for preparing an isolation chip based on a high dielectric constant dielectric interdigital capacitor, characterized in that: include: Depositing a first interconnect metal film on an insulating substrate, and depositing a layer of photoresist on top of the first interconnect metal film, and etching away the photoresist covering the middle metal region of the first interconnect metal film according to a pre-designed photolithography pattern, leaving the photoresist on the right side; growing a high-k dielectric film on the first interconnect metal film to form a first layer of high-k dielectric capacitor; Growing a second layer of interconnect metal film on the first layer of high-k dielectric, and depositing a layer of photoresist on the second layer of interconnect metal film, and etching away the photoresist covering the middle metal region of the second layer of interconnect metal film according to the designed photolithography pattern, leaving the photoresist on the left side; Growing a high-k dielectric film on the second interconnect metal film to generate a second high-k dielectric capacitor, wherein a left edge of the second high-k dielectric is at a first predetermined distance to the left of the left edge of the first high-k dielectric, and a right edge of the second high-k dielectric is at a second predetermined distance to the right of the right edge of the first high-k dielectric; Generating a third layer of high-dielectric-constant capacitors according to the method for generating the first layer of high-dielectric-constant capacitors, and generating a fourth layer of high-dielectric-constant capacitors according to the method for generating the second layer of high-dielectric-constant capacitors, repeating the above operations and after generating the last layer of high-dielectric-constant dielectric film, using a photolithography lift-off process to dissolve all photoresists; Depositing a layer of photoresist on the surface of the topmost high-k dielectric film, retaining the photoresist in the middle region according to the photolithography pattern, etching away the photoresist on the left and right sides, and then growing a layer of interconnect metal film; Using the lift-off process, the middle photoresist of the top-layer high-k dielectric capacitor and the corresponding interconnect metal film above it are etched away, forming interconnect leads on the left and right sides to generate an isolation chip.

2. The method according to claim 1, characterized in that Depositing a layer of photoresist on the interconnect metal film includes: depositing the photoresist on the interconnect metal film using a wrestling machine.

3. The method according to claim 1, characterized in that The photolithography pattern is rectangular or circular.

4. The method according to claim 1, wherein Growing a high dielectric constant dielectric film on the interconnect metal film comprises: growing the high dielectric constant dielectric film on the interconnect metal film by adopting sputtering technology or electron beam.

5. The method according to claim 1, wherein The high dielectric constant dielectric film is HfO2, Ti oxide, Y oxide, La oxide, Ta oxide, or Al oxide.

6. An isolation chip based on a high-dielectric-constant dielectric interdigital capacitor prepared by the method according to any one of claims 1 to 5, characterized in that: include: Interdigitated electrodes and multilayer dielectrics.

7. A device for preparing an isolation chip based on a high-dielectric-constant dielectric interdigital capacitor, characterized in that: include: A first deposition module is configured to deposit a first interconnect metal film layer on an insulating substrate, deposit a layer of photoresist on the first interconnect metal film layer, and etch away the photoresist covering the central metal region of the first interconnect metal film layer according to a pre-designed photolithography pattern, leaving the photoresist on the right side; A first generating module is configured to grow a high-k dielectric film on the first interconnect metal film layer to generate a first layer of high-k dielectric capacitors; a second deposition module, configured to grow a second interconnect metal film on the first high-k dielectric layer, deposit a layer of photoresist on the second interconnect metal film, and etch away the photoresist covering the middle metal region of the second interconnect metal film according to the designed photolithography pattern, leaving the photoresist on the left side; a second generating module, configured to grow a high-k dielectric film on the second interconnect metal film layer to generate a second-layer high-k dielectric capacitor, wherein a left edge of the second-layer high-k dielectric is at a first predetermined distance to the left of the left edge of the first-layer high-k dielectric, and a right edge of the second-layer high-k dielectric is at a second predetermined distance to the right of the right edge of the first-layer high-k dielectric; a third generation module, configured to generate a third layer of high-dielectric-constant capacitors according to the method for generating the first layer of high-dielectric-constant capacitors, and to generate a fourth layer of high-dielectric-constant capacitors according to the method for generating the second layer of high-dielectric-constant capacitors, repeat the above operations, and after generating the last layer of high-dielectric-constant dielectric film, use a photolithography lift-off process to dissolve all photoresists; The third deposition module is used to deposit a layer of photoresist on the surface of the top high-k dielectric film, retain the photoresist in the middle area according to the photolithography pattern, etch away the photoresist on the left and right sides, and then grow a layer of interconnect metal film; The fourth generation module is used to use the lift-off process to etch away the middle photoresist of the top-layer high-k dielectric capacitor and the corresponding interconnect metal film above it, forming interconnect leads on the left and right sides to generate an isolation chip.

8. The device according to claim 7, characterized in that The first deposition module, the second deposition module and the third deposition module include: a deposition submodule for depositing the photoresist on the interconnect metal film using a deposition machine.

9. The device according to claim 7, characterized in that The photolithography pattern is rectangular or circular.

10. The device according to claim 7, characterized in that The first generation module, the second generation module and the third generation module include: a growth submodule for growing the high dielectric constant dielectric film on the interconnect metal film by using sputtering technology or electron beam.

11. The device according to claim 7, characterized in that The high dielectric constant dielectric film is HfO2, Ti oxide, Y oxide, La oxide, Ta oxide or Al oxide.

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