Chip Performance and Power Consumption Analysis Method, Device and Related Equipment

Abstract

An embodiment of the present application provides a method, device and related equipment for analyzing chip performance and power consumption. The method for analyzing chip performance and power consumption includes: obtaining a first set of influence parameters of each type of transistor on the performance and power consumption of the standard cell by simulating the standard cell model; obtaining a second set of influence parameters of each type of transistor on the chip performance and power consumption according to the first set of influence parameters and the standard cell usage ratio; obtaining a third set of influence parameters of different product device target values on the chip performance and power consumption according to the second set of influence parameters and the usage ratio of different types of transistors, and judging the influence of the product device target values on the chip performance and power consumption. This reduces the resource consumption during the chip performance analysis before obtaining the chip sample and reduces the test data during the chip performance analysis, thereby reducing the resource investment in the chip performance analysis in the initial stage of chip production and manufacturing while ensuring timeliness.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and particularly to a method, device and related equipment for analyzing chip performance and power consumption. Background Art

[0002] When analyzing chip performance in the initial stage of chip production and manufacturing in the prior art, a large amount of post-silicon data is required to support the judgment, and more resources need to be invested in the initial stage of chip production and manufacturing. However, the timeliness of a large amount of test data is very poor; and currently, the perfection and coverage rate of the pre-silicon test programs are not high enough. Therefore, how to reduce the resource investment in chip performance analysis in the initial stage of chip production and manufacturing while ensuring timeliness has become an urgent problem for those skilled in the art. Summary of the Invention

[0003] In view of this, the embodiments of the present application provide a method, device and related equipment for analyzing chip performance, so as to reduce the resource investment in chip performance analysis in the initial stage of chip production and manufacturing while ensuring timeliness.

[0004] To achieve the above object, the embodiments of the present invention provide the following technical solutions:

[0005] The embodiments of the present application provide a method for analyzing chip performance, including:

[0006] Constructing a standard cell model for simulating the standard cells of the chip to be analyzed;

[0007] By simulating the standard cell model and simulating the adjustment of the target values of product devices, a first set of influence parameters of the impact of each type of transistor on the performance and power consumption of the standard cell under different target values of product devices is obtained; according to the first set of influence parameters and the standard cell usage ratio, a second set of influence parameters of the impact of each type of transistor on the performance and power consumption of the chip under different target values of product devices is obtained;

[0008] According to the second set of influence parameters and the usage ratio of different types of transistors, a third set of influence parameters of the impact of different target values of product devices on the performance and power consumption of the chip is obtained; the third set of influence parameters is used to judge the impact of the target values of product devices on the performance and power consumption of the chip.

[0009] Optionally, the first set of influence parameters includes: the standard performance parameter value of the performance of the standard cell and the standard power consumption parameter value of the power consumption of the standard cell under the standard threshold voltage; and, the general performance parameter value of the performance of the standard cell and the general power consumption parameter value of the power consumption of the standard cell during the change of the threshold voltage. Optionally, the performance of the standard cell includes: the frequency of the standard cell; the power consumption of the standard cell includes: the static power consumption of the standard cell and the dynamic power consumption of the standard cell.

[0010] Optionally, the step of obtaining a first set of influence parameters of each type of transistor on the performance and power consumption of the standard cell under different target values of the product device by simulating the standard cell model and simulating the adjustment of the target value of the product device includes:

[0011] By detecting the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard threshold voltage, the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard target value of the product device are simulated.

[0012] Adjust the threshold voltage of the transistors in the standard cell model, detect the general performance parameter value and the general power consumption parameter value of the standard cell under different magnitudes of threshold voltage change, and obtain the first set of influence parameters.

[0013] Optionally, the usage ratio of the standard cell includes: the usage ratio of the standard cell in the chip or the usage ratio of the standard cell in the critical path of the chip.

[0014] Optionally, the usage ratio of different types of transistors includes: the usage ratio of different types of transistors to all the transistors in the chip, or the usage ratio of different types of transistors to the critical path of the chip.

[0015] Optionally, the third set of influence parameters includes: a dynamic power consumption influence parameter set;

[0016] The dynamic power consumption influence parameter set includes: the standard dynamic power consumption value of the chip under the standard threshold voltage, and the general dynamic power consumption parameter set of the dynamic power consumption of the chip during the change of the threshold voltage;

[0017] The step of obtaining a third set of influence parameters of different types of transistors on the performance of the chip according to the second set of influence parameters and the usage ratio of different types of transistors includes:

[0018] Obtain the dynamic power consumption influence parameter set according to the second set of influence parameters, the usage ratio of different types of transistors, and the static-dynamic power consumption ratio.

[0019] Optionally, the usage ratio of different types of transistors further includes: a chip power consumption ratio set.

[0020] Optionally, the third set of influence parameters includes: a static power consumption influence parameter set;

[0021] The static power consumption influence parameter set includes: the standard static power consumption value of the chip under the standard threshold voltage, and the general static power consumption parameter set of the static power consumption of the chip during the change of the threshold voltage;

[0022] The step of obtaining a third impact parameter group of the impact of different types of transistors on the chip performance according to the second impact parameter group and the usage ratio of different types of transistors includes:

[0023] Obtain a static power consumption impact parameter group according to the second impact parameter group and the usage ratio of different types of transistors.

[0024] Optionally, the third impact parameter group includes: a frequency impact parameter group;

[0025] The frequency impact parameter group includes: the frequency standard value of the chip under the standard threshold voltage, and a general frequency parameter group of the change of the frequency of the chip relative to the frequency standard value during the change of the threshold voltage;

[0026] The step of obtaining a third impact parameter group of the impact of different types of transistors on the chip performance according to the second impact parameter group and the usage ratio of different types of transistors includes:

[0027] Obtain a frequency impact parameter group according to the second impact parameter group and the usage ratio of different types of transistors in the critical path of the chip.

[0028] Optionally, it further includes using the third impact parameter group to draw a two-dimensional contour map to show the impact of different types of transistors on the chip performance.

[0029] An embodiment of the present application further provides a chip performance analysis device, including:

[0030] A model construction module for constructing a standard cell model for simulating the standard cells of the chip to be analyzed;

[0031] A first parameter group acquisition module for obtaining a first impact parameter group of the impact of each type of transistor on the performance and power consumption of the standard cell under different product device target values by simulating the standard cell model and simulating the adjustment of the product device target value;

[0032] A second parameter group acquisition module for obtaining a second impact parameter group of the impact of each type of transistor on the chip performance and power consumption under different product device target values according to the first impact parameter group and the standard cell usage ratio;

[0033] A third parameter group acquisition module for obtaining a third impact parameter group of the impact of different product device target values on the chip performance and power consumption according to the second impact parameter group and the usage ratio of different types of transistors; the third impact parameter group is used to judge the impact of the product device target value on the chip performance and power consumption.

[0034] Optionally, the first set of influence parameters includes: the standard performance parameter value of the standard cell performance and the standard power consumption parameter value of the standard cell power consumption under the standard threshold voltage; and, the general performance parameter value of the standard cell performance and the general power consumption parameter value of the standard cell power consumption during the threshold voltage change.

[0035] Optionally, the obtaining of the first parameter set includes:

[0036] A standard parameter value obtaining module, configured to simulate the standard performance parameter value and the standard power consumption parameter value of the standard cell under the target value of the standard product device by detecting the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard threshold voltage.

[0037] A variable parameter value obtaining module, adjusts the threshold voltage of the transistors in the standard cell model, detects the general performance parameter value and the general power consumption parameter value of the standard cell under different magnitudes of threshold voltage change, and obtains the first set of influence parameters.

[0038] Optionally, the usage ratio of different types of transistors includes: the usage ratio of different types of transistors in all the transistors of the chip or the usage ratio of different types of transistors in the critical path of the chip.

[0039] Optionally, the third set of influence parameters includes: a dynamic power consumption influence parameter set;

[0040] The dynamic power consumption influence parameter set includes: the standard value of the dynamic power consumption of the chip under the standard threshold voltage, and the general dynamic power consumption parameter set of the dynamic power consumption of the chip during the threshold voltage change;

[0041] The third parameter set obtaining module includes a dynamic power consumption obtaining module, configured to obtain the dynamic power consumption influence parameter set according to the second set of influence parameters, the usage ratio of different types of transistors, and the static-dynamic power consumption ratio.

[0042] Optionally, the third set of influence parameters includes: a static power consumption influence parameter set;

[0043] The static power consumption influence parameter set includes: the standard value of the static power consumption of the chip under the standard threshold voltage, and the general static power consumption parameter set of the static power consumption of the chip during the threshold voltage change;

[0044] The third parameter set obtaining module includes a static power consumption obtaining module, configured to obtain the static power consumption influence parameter set according to the second set of influence parameters and the usage ratio of different types of transistors.

[0045] Optionally, the third set of influence parameters includes: a frequency influence parameter set;

[0046] The frequency influence parameter group includes: the frequency standard value of the chip under the standard threshold voltage, and the general frequency parameter group of the frequency of the chip during the change of the threshold voltage;

[0047] The third parameter group obtaining module includes a frequency obtaining module, which obtains the frequency influence parameter group according to the second influence parameter group and the usage ratio of different types of transistors in the critical path of the chip.

[0048] Optionally, it further includes a drawing module for drawing a two-dimensional contour map using the third influence parameter group.

[0049] The embodiment of the present application also provides a storage medium, which stores a design program of a chip, and when the design program is executed, it implements the chip performance analysis method as described above.

[0050] The embodiment of the present application also provides a computer device, including the chip performance analysis device as described above.

[0051] The chip performance analysis method provided by the embodiment of the present application first constructs a standard cell model for simulating the standard cells of the chip to be analyzed, and simulates the standard cell model to obtain the first influence parameter group of the influence of transistors on the performance of the standard cells. In order to obtain the influence of transistors on the chip performance, the second influence parameter group is obtained according to the first influence parameter group and the standard cell usage ratio. Finally, in order to obtain the influence of different types of transistors on the chip performance, the third influence parameter group is obtained according to the second influence parameter group and the usage ratio of different types of transistors, so as to judge the influence of different types of transistors on the chip performance.

[0052] It can be seen that by only simulating the standard cells with small resource consumption during simulation, then obtaining the influence of transistors on the chip performance and power consumption, and then obtaining the influence of different types of transistors on the chip performance and power consumption. That is, avoiding simulating the complete chip with large resource consumption, simulating the standard cells with small resource consumption, and calculating the influence of different product device target values on the chip performance and power consumption through the usage ratios among transistors, standard cells and chips, so as to reduce the resource consumption during the chip performance and power consumption analysis before obtaining the chip sample, and reduce the test data during the chip performance analysis, thereby reducing the resource investment in the chip performance analysis at the initial stage of chip production and manufacturing while ensuring timeliness. Description of the Drawings

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0054] Figure 1 It is a schematic diagram of the distribution of the target values of the product devices of a chip;

[0055] Figure 2 It is a schematic flowchart of the chip performance analysis method provided by the embodiment of the present application;

[0056] Figure 3 It is another schematic flowchart of the chip performance analysis method provided by the embodiment of the present application;

[0057] Figure 4a and Figure 4b It is a schematic diagram of the two-dimensional contour map drawn by the chip performance analysis method provided by the embodiment of the present application;

[0058] Figure 5 It is a schematic diagram of the ratio acquisition of the chip performance analysis method provided by the embodiment of the present application;

[0059] Figure 6a and Figure 6b and Figure 6c It is a schematic diagram of another group of two-dimensional contour maps drawn by the chip performance analysis method provided by the embodiment of the present application;

[0060] Figure 7a and Figure 7b and Figure 7c and Figure 7d It is a schematic diagram of the coordinate map drawn by the data of the chip performance analysis method provided by the embodiment of the present application;

[0061] Figure 8 It is a schematic diagram of the power consumption analysis of a chip;

[0062] Figure 9 It is a schematic structural diagram of the chip performance analysis device provided by the embodiment of the present application;

[0063] Figure 10 It is another schematic structural diagram of the chip performance analysis device provided by the embodiment of the present application. Detailed implementation manners

[0064] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0065] The product device target is an important indicator for the chip design party to communicate with the foundry for production. In actual production, the drive current values of the chip transistors will show a normal distribution around the product device target. Further, the drive current of the chip transistor is related to the threshold voltage used by the transistor. The higher the threshold voltage of the transistor, the smaller the drive current of the transistor, and the lower the threshold voltage of the transistor, the larger the drive current of the transistor. It should be noted that the product in the product device target refers to the chip, and the device refers to the transistor. As Figure 1 shown, Figure 1 Figure Figure 1 shows a schematic diagram of chip anchor points and their distribution. The abscissa in the figure is the drive current values of different NMOS (Negative channel-Metal-Oxide-Semiconductor) transistors, and the ordinate is the drive current values of different PMOS (Positive channel-Metal-Oxide-Semiconductor) transistors. The coordinates corresponding to each cross point in the figure are the drive current values of the transistors used in a different chip. The center point of the area where the cross points are most concentrated in the figure, that is, the TT point, the drive current values of the NMOS and PMOS corresponding to it are the product device target values of the chip, and SF, FF, SS, and FS are the four process corners of the chip. The process corner is the range of the transistor drive current value. In addition, the drive current value of the transistor also affects the performance and power consumption of the transistor. Therefore, the product device target value affects the performance and power consumption of the transistor, where the performance of the transistor includes the frequency of the transistor. Further, the chip is composed of transistors. Therefore, the performance and power consumption of the transistor also affect the performance and power consumption of the chip, and the product device target value also affects the performance and power consumption of the chip.

[0066] Since the product device target value affects the overall transistor usage design in the chip, the determination of the product device target value is particularly important for actual production. A method for determining the product device target value uses device-level, that is, transistor-level WAT (Wafer Acceptance Test) parameters as the standard. WAT is a test for a dedicated test pattern, which is used to obtain electrical parameters characterizing device performance. However, it is difficult to intuitively estimate the overall performance of a complete chip based on device-level WAT parameters.

[0067] In addition, during the actual production and manufacturing process, due to changes in market demand, different requirements for chip performance and power consumption often arise, thus necessitating adjustments to the target values of product devices. Taking the power consumption of a chip as an example, if the chip is a high-performance computing chip, it is generally applied under high temperature and pressure, and as the process node evolves, the proportion of static power consumption becomes increasingly high, and the power consumption requirement also increases accordingly. Therefore, it is even more necessary to determine the target values of product devices according to requirements to meet strict performance and power consumption requirements.

[0068] The main factors considered in a method for adjusting the target values of product devices include the impact of the target values of product devices on chip yield, as well as the impact on chip performance and power consumption. Among them, the impact of the target values of product devices on chip yield can be relatively intuitively determined through EDA (Electronic Design Automation) tools; while the correlation between the impact of the target values of product devices on chip performance and power consumption and WAT parameters is relatively weak. Therefore, in a method for adjusting the target values of product devices, the target values of product devices are often adjusted by the experience of developers or the correlation between the developers' intuition about the devices and test data to meet product requirements.

[0069] Since there are many subjective judgment processes of personal factors in the above method for adjusting the target values of product devices, the objectivity and professionalism of this adjustment method are relatively poor. Therefore, there is another method for adjusting the target values of product devices. After actually producing samples of the chip, the samples of the chip are tested, and the target values of product devices are adjusted according to the data obtained from the test.

[0070] According to the aforementioned method for adjusting the target values of product devices, after producing samples of the chip, the samples are tested. Since the adjustment of the target values of product devices requires a large amount of test data to support the judgment, a relatively large amount of resources need to be invested in the initial stage of chip production and manufacturing. In addition, in the initial stage of chip production and manufacturing, the perfection and coverage of the test program for the samples of the chip may not be high enough, and it is necessary to wait for the program to be perfected, resulting in relatively poor timeliness of the test.

[0071] Based on this, the embodiments of the present application consider simulating the chip model in the design and introducing the basic concept of process evaluation PPA (power, performance, area; power consumption, performance, area) into the adjustment process of the target values of product devices, so as to quantitatively reflect the impact of the adjustment of the target values of product devices on the overall performance and power consumption of the chip, and adjust the target values of product devices according to quantitative data, thereby reducing the resource investment in the adjustment process of the target values of product devices in the initial stage of chip production and manufacturing on the premise of ensuring timeliness.

[0072] Based on the above idea, the embodiments of the present application provide a method for analyzing chip performance and power consumption. As an optional implementation,Figure 2 The flowchart of the chip performance and power consumption analysis method provided by the embodiments of the present application is shown. As Figure 2 shown, the chip performance and power consumption analysis method provided by the embodiments of the present application includes:

[0073] Step S1: Construct a standard cell model for simulating the standard cells of the chip to be analyzed.

[0074] It should be noted that if directly performing circuit-level simulation on the complete chip to obtain the accurate performance and power consumption of the complete chip, this method is difficult to implement due to the overly complex circuit of the complete chip and the too large simulation scale. And a complete chip is composed of multiple standard cells. In an optional implementation, the standard cells include NOT gates, OR-AND gates, NAND gates, and NOR gates. The performance and power consumption of each of the above standard cells are fixed parameters, and the accurate performance and power consumption of the standard cells can be obtained by performing circuit-level simulation on the standard cells, and the performance and power consumption of the complete chip can be calculated based on the performance and power consumption of the standard cells. Then, by performing data processing on the performance and power consumption of the complete chip, the influence parameters of different types of transistors on the performance and power consumption of the chip after adjusting the product device target value can be obtained.

[0075] In this way, simulating the standard cells can reduce the amount of data that needs to be obtained during testing, thereby improving the timeliness of chip performance analysis and power consumption analysis.

[0076] Step S2: By simulating the standard cell model and simulating the adjustment of the product device target value, obtain the first set of influence parameters of each type of transistor on the performance and power consumption of the standard cell under different product device target values. It should be noted that the standard cell is composed of devices, that is, different transistors, and the characteristics of the transistor are affected by its threshold voltage. By adjusting the threshold voltage of the transistor in the standard cell model, the performance parameter value of the standard cell and the power consumption parameter value of the standard cell after simulating the adjustment of the product device target value can be obtained. Therefore, in an optional real-time manner, the step of simulating the standard cell model to obtain the first set of influence parameters of the transistor on the performance and power consumption of the standard cell, as Figure 3 shown, includes:

[0077] Step S21: By detecting the standard performance parameter values and standard power consumption parameter values of the standard cell under the standard threshold voltage, simulate the standard performance parameter values and standard power consumption parameter values of the standard cell under the target value of the standard product device. Step S22: Adjust the threshold voltage of the transistors in the standard cell model, detect the general performance parameter values and general power consumption parameter values of the standard cell under different amplitudes of threshold voltage changes, and obtain a first set of influence parameters. It should be noted that there are various different transistors in a standard cell. Therefore, during the process of adjusting the threshold voltage of the transistors in the standard cell model, it is necessary to adjust the threshold voltage of each type of transistor separately, and further obtain the performance and power consumption of the standard cell under different combinations of threshold voltages of various transistors, so as to obtain a first set of influence parameters reflecting the performance and power consumption of the standard cell in different states.

[0078] Specifically, in an alternative implementation, the methods for implementing the above Step S21 and Step S22 are traversal simulations. For example, the traversal simulation is to perform combined simulations on the NMOS transistors under 10 different threshold voltage conditions and the PMOS transistors under 10 threshold voltage conditions respectively, and obtain the simulation results under 100 condition combinations of the two types of transistors. Thus, the changes in the performance and power consumption of the standard cell under different target values of the product device can be simulated after adjusting the target value of the product device.

[0079] Furthermore, from the above Step S21 and Step S22, it can be seen that in an alternative implementation, the first set of influence parameters includes: the standard performance parameter values of the standard cell performance and the standard power consumption parameter values of the standard cell power consumption under the standard threshold voltage; and the general performance parameter values of the standard cell performance and the general power consumption parameter values of the standard cell power consumption during the threshold voltage change.

[0080] Furthermore, in order to introduce the PPA concept into the adjustment of the target value of the product device, since the area of the chip is determined, it is necessary to obtain parameters that can characterize the performance and power consumption of the chip. Among them, the performance of the chip can be determined by the frequency of the transistors or the standard cell. Therefore, in an alternative implementation, the standard cell performance includes: the standard cell frequency; and the standard cell power consumption includes: the standard cell static power consumption and the standard cell dynamic power consumption.

[0081] Please refer to 4a and Figure 4b , Figure 4a is the relationship diagram of the frequency and the threshold voltage change obtained by the chip performance and power consumption detection method provided by this application, as Figure 4aAs shown, the target value of the product device is obtained by adjusting the threshold voltage of the transistors in the standard cell model, detecting the change parameter values of the performance and power consumption of the standard cell relative to the standard parameter values under different amplitudes of threshold voltage changes, and obtaining the first influence parameter group. The point (0, 0) in the figure is the standard parameter value of the standard cell frequency. At this time, the threshold voltage does not change, so the threshold voltage change value is 0. Taking (-20, 40) in the figure as an example, it is the general frequency parameter value of the standard cell when the threshold voltage of the NMOS transistor is reduced by 20 mV relative to the standard threshold voltage and the threshold voltage of the PMOS transistor is increased by 40 mV relative to the standard threshold voltage. Figure 4b The graph showing the relationship between the static power consumption and the threshold voltage change obtained by the chip performance and power consumption detection method provided by this application is as Figure 4b As shown, the target value of the product device is obtained by adjusting the threshold voltage of the transistors in the standard cell model, detecting the change parameter values of the performance and power consumption of the standard cell relative to the standard parameter values under different amplitudes of threshold voltage changes, and obtaining the first influence parameter group. The point (0, 0) in the figure is the standard parameter value of the standard cell static power consumption. At this time, the threshold voltage does not change, so the threshold voltage change value is 0. Taking (-20, 40) in the figure as an example, it is the general static power consumption parameter value of the standard cell when the threshold voltage of the NMOS transistor is reduced by 20 mV relative to the standard threshold voltage and the threshold voltage of the PMOS transistor is increased by 40 mV relative to the standard threshold voltage.

[0082] Please continue to refer to Figure 2 , and it further includes step S3: obtaining a second influence parameter group of the influence of each type of transistor on the chip performance and power consumption under different product device target values according to the first influence parameter group and the standard cell usage ratio. Further, in an optional implementation manner, the standard cell usage ratio includes: the usage ratio of the standard cell in the chip or the usage ratio in the critical path of the chip. It should be noted that after the chip is powered on, all the standard cells in the chip are in an operating state and there is power consumption. Therefore, the power consumption of the chip can be calculated from the usage ratio of the standard cell in the chip and the power consumption of each standard cell. In a chip, the frequency of the chip is related to the frequency of the critical path for implementing different functions of the chip. Therefore, the frequency of the chip can be calculated from the usage ratio of the standard cell in the critical path of the chip and the frequency of the standard cell.

[0083] Further, the usage ratio of the standard cells is obtained by counting all types of standard cells used in the chip to obtain the quantity of each type of standard cell, and then dividing by the total quantity of the standard cells. Therefore, the sum of the quantities of all types of standard cells is equal to the total quantity of the standard cells, and the sum of the usage ratios of all different types of standard cells to all transistors in the chip is 100%. For example, for a chip including 20 NOT gates, 50 OR-AND gates, 45 NAND gates, and 25 NOR gates as described above, a total of 140 gates, it can be calculated that the proportion of NOT gates is 14.3%, the proportion of OR-AND gates is 35.7%, the proportion of NAND gates is 32.1%, and the proportion of NOR gates is 17.9%, with a total proportion of 100%. Further, since the first influence parameter group includes the standard performance parameter values of the standard cells and the standard power consumption parameter values of the standard cells under the standard threshold voltage; and the general performance parameter values of the standard cells and the general power consumption parameter values of the standard cells during the change of the threshold voltage. And the performance of the standard cells includes the standard cell frequency; the power consumption of the standard cells includes: the standard static power consumption of the standard cells and the standard dynamic power consumption of the standard cells. Therefore, in an alternative implementation, the second influence parameter group includes the standard chip performance parameter values of the chip and the standard chip power consumption parameter values of the chip under the standard threshold voltage; and the general chip performance parameter values of the chip and the general chip power consumption parameter values of the chip during the change of the threshold voltage; the chip performance includes the chip frequency of the chip; the chip power consumption includes: the chip static power consumption and the chip dynamic power consumption.

[0084] It should be noted that by performing weighted multiplication on the first influence parameter values of different types of standard cells at each threshold voltage change value according to the standard cell usage ratio, a second influence parameter group reflecting the influence of the transistors on the chip performance and power consumption can be obtained. For example, under the standard threshold voltage, the first influence parameter of the first standard cell * 45% + the first influence parameter value of the second standard cell * 30% + the first influence parameter value of the third standard cell * 15% + the first influence parameter value of the fourth standard cell * 10% = the second influence parameter group under the standard threshold voltage.

[0085] Step S4: Obtain a third influence parameter group reflecting the influence of different product device target values on the chip performance and power consumption according to the second influence parameter group and the usage ratios of different types of transistors. The third influence parameter group is used to judge the influence of the product device target values on the chip performance and power consumption.

[0086] It should be noted that by multiplying the second influence parameter values at each threshold voltage change value by weights according to the usage ratios of different types of transistors, a third influence parameter group of the impact of the transistors on the chip performance and power consumption can be obtained. For example, at the standard threshold voltage, the second influence parameter of the first transistor * 45% + the second influence parameter value of the second transistor * 30% + the second influence parameter value of the third transistor * 15% + the second influence parameter value of the fourth transistor * 10% = the third influence parameter group at the standard threshold voltage.

[0087] Furthermore, as Figure 5 shown, Figure 5 within the range of the central solid line rectangle is the impact of the transistors on the performance and power consumption of the standard cell obtained by adjusting the threshold voltage of the transistors, that is, the impact of the transistors in the chip on the NOT gate, NAND gate, AND-OR gate, and NOR gate. Then, as shown by the 5 dashed line rectangles in Figure 5 , by combining the impact of the transistors on the performance and power consumption of the standard cell, the usage ratio of the standard cell, the usage ratio of different types of transistors in all the transistors of the chip, and the usage ratio of different types of transistors in the critical path of the chip, a secondary weighted multiplication can be performed to determine the impact of different product device target values on the chip performance and power consumption. Among them, determining the impact of the transistors on the chip performance and power consumption through the impact of the transistors on the performance and power consumption of the standard cell and the usage ratio of the standard cell is the first-level weighted algorithm. Determining the static power consumption influence parameter group and the dynamic power consumption influence parameter group through the impact of the transistors on the chip performance and power consumption and the usage ratio of different types of transistors in all the transistors of the chip, and determining the frequency influence parameter group through the impact of the transistors on the chip performance and power consumption and the usage ratio of different types of transistors in the critical path of the chip is the second-level weighted multiplication. It should be noted that the usage ratio of the standard cell in the chip, the usage ratio of the standard cell in the critical path of the chip, the usage ratio of different types of transistors in all the transistors of the chip, and the usage ratio of different types of transistors in the critical path of the chip are parameters that can be determined when the chip is designed to obtain a complete chip circuit. It should be noted that there are different requirements for the speeds of the NMOS transistors and PMOS transistors at different positions in the chip. In order to make the operating speeds of the NMOS transistors and PMOS transistors different at the same threshold voltage, multiple different NMOS transistors and multiple different PMOS transistors are provided in the chip. The second influence parameter group is the impact of the transistors on the chip performance and power consumption when all the transistors are regarded as a whole. In order to further reflect the impact of different types of transistors on the chip when the product device target value is adjusted, the second influence parameter group needs to be combined with the usage ratios of different types of transistors, so as to obtain the third influence parameter group to obtain the impact of each type of transistor on the chip performance and power consumption at different threshold voltages.

[0088] Furthermore, since the frequency of the chip is related to the frequency of the critical paths for implementing different functions of the chip, the frequency of the chip can be obtained by calculating the usage ratio of the standard cells within the critical paths of the chip and the frequency of the standard cells. In an alternative implementation, the usage ratios of the different performance transistors include: the usage ratio of different types of transistors to all the transistors of the chip, or the usage ratio of different types of transistors to the critical paths of the chip.

[0089] Furthermore, the method for obtaining the usage ratio of the standard cells within the chip and the usage ratio within the critical paths of the chip is as Figure 5 shown. The usage ratio of different types of transistors to all the transistors of the chip is the ratio obtained by counting all types of transistors used within the chip, obtaining the quantity of each type of transistor, and dividing by the total quantity of transistors. Therefore, the sum of the quantities of all types of transistors is equal to the total quantity of transistors, and the sum of the usage ratios of all different types of transistors to all the transistors of the chip is 100%. Taking the example shown in Figure 5 , the transistor types within the chip include 168,206,099 nrvt_ckt (standard threshold voltage NMOS) transistors, 305,385,094 nlvt_ckt (low threshold voltage NMOS) transistors, 176,619,982 nhvt_ckt (high threshold voltage NMOS) transistors, 191,776,668 prvt_ckt (standard threshold voltage NMOS) transistors, 305,845,324 plvt_ckt (low threshold voltage NMOS) transistors, and 251,695,945 phvt_ckt (standard threshold voltage NMOS) transistors. The total number of all transistors is 1,399,529,112. Thus, by dividing the quantity of different types of transistors by the total quantity of all transistors, the proportion of rvt_ckt (constant voltage device circuit) transistors is 25.7%, the proportion of hvt_ckt (high voltage device circuit) transistors is 30.6%, and the proportion of lvt_ckt (low voltage device circuit) transistors is 43.7%, with a total proportion of 100%. Further, the usage ratio of different types of transistors to the critical paths of the chip and the usage ratio of the standard cells are obtained by the same method. As Figure 5 shown, the usage ratio of different types of transistors to the critical paths of the chip is the usage ratio of rvt_ckt, hvt_ckt, and lvt_ckt transistors.

[0090] It should be noted that in the analysis of the chip performance and power consumption, the commonly used analysis metrics are the static power consumption of the chip, the dynamic power consumption of the chip, and the frequency of the chip. Therefore, the third set of influencing parameters includes the parameter values related to the above three analysis metrics.

[0091] Further, in an alternative implementation, the third influence parameter group includes: a dynamic power consumption influence parameter group; the dynamic power consumption influence parameter group includes: the standard value of the dynamic power consumption of the chip under the standard threshold voltage, and a general dynamic power consumption parameter group of the dynamic power consumption of the chip during the change of the threshold voltage. As Figure 3 shown, the step S4 includes step S41: obtaining a dynamic power consumption influence parameter group according to the second influence parameter group and the usage ratios of different types of transistors.

[0092] It should be noted that, in an alternative implementation, the usage ratios of different types of transistors further include: a chip power consumption ratio group. Specifically, in an alternative implementation, the chip power consumption ratio group includes: the ratio of the dynamic power consumption to the static power consumption of the chip and the ratio of the internal power consumption of the chip components to the effective power consumption of the chip. For example, the ratio of dynamic power consumption to static power consumption is 3:1, and the ratio of the internal power consumption (Internal Power) of the chip components to the effective power consumption (net Power) of the chip is 3:2.

[0093] It should be noted that by performing weighted multiplication on the second influence parameter values under each threshold voltage change value according to the usage ratios of different types of transistors, a third influence parameter group of the influence of transistors on the performance and power consumption of the chip can be obtained. For example, under the standard threshold voltage, (the static power consumption influence parameter of the first transistor * 45% + the static power consumption influence parameter value of the second transistor * 30% + the static power consumption influence parameter value of the third transistor * 15% + the static power consumption influence parameter value of the fourth transistor * 10%) * 3 / 2 * 3 = the dynamic power consumption influence parameter group under the standard threshold voltage. The obtained result is as Figure 6a shown.

[0094] Further, in an alternative implementation, the third influence parameter group includes: a static power consumption influence parameter group; the static power consumption influence parameter group includes: the standard value of the static power consumption of the chip under the standard threshold voltage, and a general static power consumption parameter group of the static power consumption of the chip during the change of the threshold voltage. As Figure 3 shown, the step S4 includes step S42: obtaining a static power consumption influence parameter group according to the second influence parameter group and the usage ratios of different types of transistors. It should be noted that by performing weighted multiplication on the second influence parameter values under each threshold voltage change value according to the usage ratios of different types of transistors, a third influence parameter group of the influence of transistors on the performance and power consumption of the chip can be obtained. For example, under the standard threshold voltage, the static power consumption influence parameter of the first transistor * 45% + the static power consumption influence parameter value of the second transistor * 30% + the static power consumption influence parameter value of the third transistor * 15% + the static power consumption influence parameter value of the fourth transistor * 10% = the static power consumption influence parameter group under the standard threshold voltage. The obtained result is as Figure 6bas shown

[0095] Further, in an alternative implementation, the third influence parameter group includes: a frequency influence parameter group; the frequency influence parameter group includes: the frequency standard value of the chip under the standard threshold voltage, and a general frequency parameter group of the frequency of the chip during the change of the threshold voltage. As Figure 3 shown, step S4 includes step S43: obtaining a frequency influence parameter group according to the second influence parameter group and the usage ratio of different types of transistors in the critical path of the chip.

[0096] It should be noted that by multiplying the second influence parameter values at each threshold voltage change value according to the usage ratio of different types of transistors, a third influence parameter group of the influence of the transistors on the chip performance and power consumption can be obtained. For example, under the standard threshold voltage, the frequency influence parameter of the first transistor * 45% + the frequency influence parameter value of the second transistor * 30% + the frequency influence parameter value of the third transistor * 15% + the frequency influence parameter value of the fourth transistor * 10% = the frequency influence parameter group under the standard threshold voltage. The obtained result is as Figure 6c shown

[0097] In this way, the chip performance and power consumption analysis method provided by the embodiments of the present application, by only simulating the standard cells with small resource consumption during simulation, then obtaining the influence of the transistors on the chip performance and power consumption, and then obtaining the influence of different types of transistors on the chip performance and power consumption. That is, avoiding simulating the complete chip with large resource consumption, but simulating the standard cells with small resource consumption, and calculating the influence of different product device target values on the chip performance and power consumption through the usage ratios among the transistors, standard cells and the chip, so as to reduce the resource consumption during the chip performance analysis before obtaining the chip sample, and reduce the test data during the chip performance and power consumption analysis, thereby reducing the resource investment in the chip performance analysis in the initial stage of chip production and manufacturing while ensuring timeliness.

[0098] Further, as Figure 3 shown, in an alternative implementation, the chip performance and power consumption analysis method provided by the present application further includes step S5: using the third influence parameter group to draw a two-dimensional contour map to show the influence of different types of transistors on the chip performance and power consumption. Since the calculated third influence parameter group is a set of data, it is impossible to directly judge the influence of different types of transistors on the chip performance and power consumption through the parameter values therein, and it is necessary to judge through the change relationship between the parameter values. Drawing a two-dimensional contour map using the third influence parameter group can improve the readability of the third influence parameter group and facilitate the use of the third influence parameter group for judgment.

[0099] In an alternative implementation, the above parameter values can be directly obtained through an EDA tool. In an alternative implementation, the ratio of the dynamic power consumption to the static power consumption of the chip and the ratio of the net power consumption to the device power consumption of the chip are obtained by simulating other chips using an EDA tool. It should be noted that for chips with similar designs, the ratio of the dynamic power consumption to the static power consumption and the ratio of the net power consumption to the device power consumption are also similar. Therefore, the simulation results of other chips can be used for calculation.

[0100] Specifically, the two-dimensional contour map obtained by the chip performance and power consumption analysis method provided by the embodiments of the present application includes Figure 6a the relationship diagram of the dynamic power consumption versus the change of the transistor threshold voltage as shown in Figure 6b the relationship diagram of the static power consumption versus the change of the transistor threshold voltage as shown in Figure 6c and the relationship diagram of the frequency versus the change of the transistor threshold voltage as shown in Figure 5 Among them, the parameter value at the coordinate (0, 0) in each figure is the parameter value under the standard threshold voltage; Figure 5 the parameter value under the standard threshold voltage in the dynamic power consumption figure is 3.00 at the (0, 0) point; the parameter value under the standard threshold voltage in the static power consumption figure is 1.00 at the (0, 0) point; the parameter value under the standard threshold voltage in the frequency figure is 1.00 at the (0, 0) point. Through the data in the three figures at the same coordinates, the influence of different types of transistors on the chip performance and power consumption under different product device target values can be judged, and then the product device target values can be determined based on this. Taking the point (-0.04, -0.02) in each of the figures 4 as an example, the value at the point (-0.04, -0.02) in the dynamic power consumption figure is 3.27, the value at the point (-0.04, -0.02) in the static power consumption figure is 2.01, and the value at the point (-0.04, -0.02) in the frequency figure is 1.06. The difference between the point (-0.04, -0.02) and the point (0, 0) in the dynamic power consumption figure is 0.27, the difference between the point (-0.04, -0.02) and the point (0, 0) in the static power consumption figure is 1.01, and the difference between the point (-0.04, -0.02) and the point (0, 0) in the frequency figure is 0.06. The above differences are the influences of the change of the transistor threshold voltage on the dynamic power consumption, static power consumption and frequency of the chip respectively. When determining the product device target value, for example, if the values at the point (-0.04, -0.02) in each figure are more in line with our expectations, then we choose to determine the performance and power consumption of the transistor under the condition that the transistor threshold voltage change value is (-0.04, -0.02) as the product device target value.

[0101] Specifically, to prove the accuracy of the chip performance and power consumption analysis method provided by the embodiments of the present application, take Figure 4a and Figure 4bTaking the static power consumption vs. threshold voltage change relationship diagram and the frequency vs. threshold voltage change relationship diagram shown as an example, first, according to the parameters in the diagram, draw the frequency vs. threshold voltage change value relationship diagram and the static power consumption vs. threshold voltage change value relationship diagram of different types of transistors as shown in Figure 7a , Figure 7b , Figure 7c and Figure 7d . Among them, Figure 7a is the frequency vs. threshold voltage change value relationship diagram of different types of NMOS transistors, Figure 7c is the static power consumption vs. threshold voltage change value relationship diagram of different types of NMOS transistors, Figure 7b is the frequency vs. threshold voltage change value relationship diagram of different types of PMOS transistors, Figure 7d is the static power consumption vs. threshold voltage change value relationship diagram of different types of PMOS transistors. Taking Figure 7c and Figure 7d in the two static power consumption vs. threshold voltage change value relationship diagrams as an example, when the threshold voltage change value is -0.04, it can be known that when the speed of the PMOS transistor is faster, the static power consumption of the device is higher, while the speed of the NMOS transistor has little effect on the static power consumption. Furthermore, it can be judged that when the speed of the PMOS transistor is faster and the speed of the NMOS transistor is slower, the static power consumption value of the chip is significantly larger. Further, Figure 8 is the data result obtained by testing the samples of the chips with the same design. The leakage data of the SF process corner is inside the circle. It can be seen that the static power consumption of the SF process corner is significantly larger than that of other test points. That is, when the speed of the PMOS transistor is faster and the speed of the NMOS transistor is slower, the static power consumption value of the chip is significantly larger, which is in line with the analysis expectation of Figure 7. Therefore, the results of Figure 7 and Figure 8 are consistent, indicating that the chip performance and power consumption analysis method provided by this application can accurately obtain the influence of different product device target values on the chip performance and power consumption.

[0102] The embodiment of this application also provides a chip performance analysis device, as shown in Figure 9 . Figure 9 is the structural schematic diagram of the chip performance analysis device provided by the embodiment of this application, including:

[0103] A model construction module 100, configured to construct a standard cell model for simulating the standard cells of the chip to be analyzed;

[0104] A first parameter group acquisition module 200, configured to obtain a first influence parameter group of the performance and power consumption of each type of transistor on the standard cell under different product device target values by simulating the standard cell model and simulating the adjustment of the product device target value;

[0105] The second parameter group obtaining module 300 is configured to obtain a second influence parameter group of the influence of each type of transistor on the chip performance and power consumption under different product device target values according to the first influence parameter group and the standard cell usage ratio;

[0106] The third parameter group obtaining module 400 is configured to obtain a third influence parameter group of the influence on the chip performance and power consumption under different product device target values according to the second influence parameter group and the usage ratios of different types of transistors.

[0107] Further, in an optional implementation, the first influence parameter group includes: the standard performance parameter value of the standard cell performance and the standard power consumption parameter value of the standard cell power consumption under the standard threshold voltage; and the general performance parameter value of the standard cell performance and the general power consumption parameter value of the standard cell power consumption during the threshold voltage change.

[0108] Further, as Figure 10 shown, in an optional implementation, the first parameter group obtaining module 200 includes: a standard parameter value obtaining module 210, configured to simulate the general performance parameter value and the general power consumption parameter value of the standard cell under the standard product device target value by detecting the general performance parameter value and the general power consumption parameter value of the standard cell under the standard threshold voltage; a variable parameter value obtaining module, configured to adjust the voltage of the transistors in the standard cell model, detect the general performance parameter value and the general power consumption parameter value of the standard cell under different amplitudes of threshold voltage change, and obtain the first influence parameter group.

[0109] Further, in an optional implementation, the usage ratios of different types of transistors include: the usage ratio of different types of transistors in all the transistors of the chip or the usage ratio of different types of transistors in the critical path of the chip.

[0110] Further, as Figure 10 shown, in an optional implementation, the third influence parameter group includes: a dynamic power consumption influence parameter group; the dynamic power consumption influence parameter group includes: the dynamic power consumption standard value of the chip under the standard threshold voltage, and the general dynamic power consumption parameter group of the chip's dynamic power consumption during the threshold voltage change. The third parameter group obtaining module 400 includes a dynamic power consumption obtaining module 410, configured to obtain the dynamic power consumption influence parameter group according to the second influence parameter group, the usage ratios of different types of transistors, and the static-dynamic power consumption ratio.

[0111] Further, as Figure 10As shown, in an alternative implementation, the third impact parameter group includes: a static power consumption impact parameter group; the static power consumption impact parameter group includes: the standard value of the static power consumption of the chip under the standard threshold voltage, and a general static power consumption parameter group of the static power consumption of the chip during the change of the threshold voltage. The third parameter group acquisition module 400 includes a static power consumption acquisition module 420, which is configured to obtain the static power consumption impact parameter group according to the second impact parameter group and the usage ratio of different types of transistors.

[0112] Further, as Figure 10 shown, in an alternative implementation, the third impact parameter group includes: a frequency impact parameter group; the frequency impact parameter group includes: the standard value of the frequency of the chip under the standard threshold voltage, and a general frequency parameter group of the frequency of the chip during the change of the threshold voltage. The third parameter group acquisition module 400 includes a frequency acquisition module 430, which is configured to obtain the frequency impact parameter group according to the second impact parameter group and the usage ratio of different types of transistors in the critical path of the chip.

[0113] Further, as Figure 10 shown, in an alternative implementation, the chip performance analysis device provided by the embodiments of the present application further includes a drawing module 500, which is configured to draw a two-dimensional contour map using the third impact parameter group.

[0114] It can be seen that by only simulating the standard cells with relatively small resource consumption during simulation, then obtaining the impact of transistors on the chip performance and power consumption, and then obtaining the impact of different types of transistors on the chip performance and power consumption. That is, avoiding simulating the complete chip with relatively large resource consumption, but simulating the standard cells with relatively small resource consumption, and calculating the impact of different product device target values on the chip performance and power consumption through the usage ratios among transistors, standard cells and the chip, so as to reduce the resource consumption during the chip performance and power consumption analysis before obtaining the chip sample, and reduce the test data during the chip performance analysis, thereby reducing the resource investment in the chip performance analysis at the initial stage of chip production and manufacturing while ensuring timeliness.

[0115] The embodiments of the present application further provide a storage medium, which stores a design program of a chip, and when the design program is executed, it implements the chip performance analysis method as described above.

[0116] The embodiments of the present application further provide a computer device, which includes the chip performance analysis device as described above.

[0117] Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method for analyzing chip performance and power consumption, characterized in that, Including: Constructing a standard cell model for simulating the standard cells of the chip to be analyzed; Through simulating the standard cell model and simulating the adjustment of the target values of product devices, obtaining a first set of influence parameters of various types of transistors on the performance and power consumption of the standard cell under different target values of product devices; the target value of the product device is the target value of the chip transistor; the classification basis of various types of transistors is: the threshold voltage of the transistor; the performance of the standard cell is: the frequency of the standard cell; According to the first set of influence parameters and the usage ratio of the standard cell, obtaining a second set of influence parameters of various types of transistors on the performance and power consumption of the chip under different target values of product devices; the performance of the chip is: the frequency of the chip; According to the second set of influence parameters and the usage ratios of different types of transistors, obtaining a third set of influence parameters of different target values of product devices on the performance and power consumption of the chip; the third set of influence parameters is used to judge the influence of the target value of the product device on the performance and power consumption of the chip.

2. The chip performance and power consumption analysis method according to claim 1, characterized in that The first set of influence parameters includes: the standard performance parameter value of the standard cell performance and the standard power consumption parameter value of the standard cell power consumption under the standard threshold voltage; and, the general performance parameter value of the standard cell performance and the general power consumption parameter value of the standard cell power consumption during the change of the threshold voltage.

3. The chip performance and power consumption analysis method according to claim 2, characterized in that The performance of the standard cell includes: the frequency of the standard cell; the power consumption of the standard cell includes: the static power consumption of the standard cell and the dynamic power consumption of the standard cell.

4. The chip performance and power consumption analysis method according to claim 3, characterized in that The step of obtaining a first set of influence parameters of various types of transistors on the performance and power consumption of the standard cell under different target values of product devices by simulating the standard cell model and simulating the adjustment of the target values of product devices includes: By detecting the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard threshold voltage, simulating the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard target value of the product device; Adjusting the threshold voltage of the transistors in the standard cell model, detecting the general performance parameter value and the general power consumption parameter value of the standard cell under different amplitudes of threshold voltage change, and obtaining the first set of influence parameters.

5. The chip performance and power consumption analysis method according to claim 4, wherein, The usage ratio of the standard cell includes: the usage ratio of the standard cell in the chip or the usage ratio of the standard cell in the critical path of the chip.

6. The chip performance and power consumption analysis method according to claim 5, characterized in that The usage ratios of different types of transistors include: the usage ratio of different types of transistors in all the transistors of the chip, or the usage ratio of different types of transistors in the critical path of the chip.

7. The chip performance and power consumption analysis method according to claim 6, wherein The third set of influence parameters includes: a dynamic power consumption influence parameter set; The dynamic power consumption influence parameter set includes: the standard value of the dynamic power consumption of the chip under the standard threshold voltage, and the general dynamic power consumption parameter set of the dynamic power consumption of the chip during the change of the threshold voltage; The step of obtaining a third set of influence parameters of different types of transistors on the performance of the chip according to the second set of influence parameters and the usage ratios of different types of transistors includes: Obtaining a dynamic power consumption influence parameter set according to the second set of influence parameters and the usage ratios of different types of transistors.

8. The method for analyzing chip performance and power consumption according to claim 7, wherein The usage ratios of different types of transistors also include: a chip power consumption ratio set.

9. The method for analyzing chip performance and power consumption according to claim 6, wherein The third influencing parameter group includes: a static power consumption influencing parameter group; The static power consumption influencing parameter group includes: the standard value of the static power consumption of the chip under the standard threshold voltage, and a general static power consumption parameter group of the static power consumption of the chip during the change of the threshold voltage; The step of obtaining the third influencing parameter group of the influence of different types of transistors on the chip performance according to the second influencing parameter group and the usage ratio of different types of transistors includes: Obtaining the static power consumption influencing parameter group according to the second influencing parameter group and the usage ratio of different types of transistors.

10. The method for analyzing chip performance and power consumption according to claim 6, wherein The third influencing parameter group includes: a frequency influencing parameter group; The frequency influencing parameter group includes: the standard frequency value of the chip under the standard threshold voltage, and a general frequency parameter group of the frequency of the chip during the change of the threshold voltage; The step of obtaining the third influencing parameter group of the influence of different types of transistors on the chip performance according to the second influencing parameter group and the usage ratio of different types of transistors includes: Obtaining the frequency influencing parameter group according to the second influencing parameter group and the usage ratio of different types of transistors in the critical path of the chip.

11. The chip performance and power consumption analysis method according to claim 8, characterized in that, The chip power consumption ratio group includes: the ratio of the dynamic power consumption to the static power consumption of the chip, and the ratio of the internal power consumption of the chip to the effective power consumption of the chip.

12. The chip performance and power consumption analysis method according to claim 1, wherein It further includes using the third influencing parameter group to draw a two-dimensional contour map to show the influence of different types of transistors on the chip performance.

13. A chip performance and power consumption analysis device, characterized in that, Includes: A model construction module for constructing a standard cell model for simulating the standard cells of the chip to be analyzed; A first parameter group obtaining module for obtaining a first influencing parameter group of the influence of each type of transistor on the performance and power consumption of the standard cell under different product device target values by simulating the standard cell model and simulating the adjustment of the target values of the product devices; the product device target value is the chip transistor target value; the classification basis of each type of transistor is: the threshold voltage of the transistor; the standard cell performance is: the standard cell frequency; A second parameter group obtaining module for obtaining a second influencing parameter group of the influence of each type of transistor on the chip performance and power consumption under different product device target values according to the first influencing parameter group and the standard cell usage ratio; the chip performance is: the chip frequency; A third parameter group obtaining module for obtaining a third influencing parameter group of the influence of different product device target values on the chip performance and power consumption according to the second influencing parameter group and the usage ratio of different types of transistors; the third influencing parameter group is used to judge the influence of the product device target value on the chip performance and power consumption.

14. The chip performance and power consumption analysis device according to claim 13, characterized in that, The first influencing parameter group includes: the standard performance parameter value of the standard cell performance and the standard power consumption parameter value of the standard cell power consumption under the standard threshold voltage; and, the general performance parameter value of the standard cell performance and the general power consumption parameter value of the standard cell power consumption during the change of the threshold voltage.

15. The chip performance and power consumption analysis device according to claim 13, wherein The first parameter group obtaining module includes: A standard parameter value obtaining module for simulating the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard product device target value by detecting the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard threshold voltage; A variable parameter value acquisition module, which is used to adjust the threshold voltage of transistors in the standard cell model, detect the general performance parameter values and general power consumption parameter values of the standard cell under different magnitudes of threshold voltage changes, and obtain a first influence parameter group.

16. The chip performance and power consumption analysis device according to claim 13, wherein The usage ratios of different types of transistors include: the usage ratio of different types of transistors in all transistors of the chip or the usage ratio of different types of transistors in the critical path of the chip.

17. The chip performance and power consumption analysis device according to claim 16, wherein The third influence parameter group includes: a dynamic power consumption influence parameter group; The dynamic power consumption influence parameter group includes: the standard dynamic power consumption value of the chip under the standard threshold voltage, and the general dynamic power consumption parameter group of the dynamic power consumption of the chip during the threshold voltage change; The third parameter group acquisition module includes a dynamic power consumption acquisition module, which is used to obtain the dynamic power consumption influence parameter group according to the second influence parameter group and the usage ratios of different types of transistors.

18. The chip performance and power consumption analysis device according to claim 16, characterized in that, The third influence parameter group includes: a static power consumption influence parameter group; The static power consumption influence parameter group includes: the standard static power consumption value of the chip under the standard threshold voltage, and the general static power consumption parameter group of the static power consumption of the chip during the threshold voltage change; The third parameter group acquisition module includes a static power consumption acquisition module, which is used to obtain the static power consumption influence parameter group according to the second influence parameter group and the usage ratios of different types of transistors.

19. The chip performance and power consumption analysis device according to claim 16, characterized in that, The third influence parameter group includes: a frequency influence parameter group; The frequency influence parameter group includes: the standard frequency value of the chip under the standard threshold voltage, and the general frequency parameter group of the frequency of the chip during the threshold voltage change; The third parameter group acquisition module includes a frequency acquisition module, which obtains the frequency influence parameter group according to the second influence parameter group and the usage ratio of different types of transistors in the critical path of the chip.

20. The chip performance and power consumption analysis device according to claim 13, wherein It further includes a drawing module, which is used to draw a two-dimensional contour map using the third influence parameter group.

21. A storage medium, characterized in that, The storage medium stores a design program of the chip, and when the design program is executed, it implements the chip performance and power consumption analysis method according to any one of claims 1-12.

22. A computer device, characterized in that, It includes the chip performance and power consumption analysis device according to any one of claims 13-20.

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