Dynamic loop compensation circuit, DC-DC converter
By dynamically adjusting the zero-point resistance and pole circuit of the DC-DC converter, the system instability caused by load changes is solved, and stability and loop bandwidth optimization under different loads are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SG MICRO CORP
- Filing Date
- 2023-12-26
- Publication Date
- 2026-07-24
Smart Images
Figure CN117674594B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of this application relate to the field of electronic circuit technology, specifically to a dynamic loop compensation circuit applied to a DC-DC converter and a DC-DC converter. Background Technology
[0002] In currently widely used DC-DC converters operating under peak current conditions, the output capacitors are ceramic capacitors with relatively low ESR (Equivalent Series Resistance), and the internal error amplifiers typically employ a type-II compensation network. When the output load voltage or current changes, the system loop bandwidth of the DC-DC converter varies, while the zeros and poles generated by the internal type-II compensation network remain fixed, causing instability in the system loop of the DC-DC converter under a certain output load. Summary of the Invention
[0003] The embodiments described herein provide a dynamic loop compensation circuit for a DC-DC converter.
[0004] According to a first aspect of this application, a dynamic loop compensation circuit for a DC-DC converter is provided. The DC-DC converter includes an upper transistor, a lower transistor, and an error amplifier. The error amplifier outputs an error voltage based on the output feedback voltage and a reference input voltage of the DC-DC converter. The dynamic loop compensation circuit includes: a voltage sampling sub-circuit connected to a switching node between the upper and lower transistors for sampling the voltage at the switching node; a zero-point capacitor, one end of which is connected to the output terminal of the error amplifier of the DC-DC converter; and a resistance adjustment sub-circuit connected between the other end of the zero-point capacitor and the voltage sampling sub-circuit for sampling the voltage at the output terminal of the error amplifier and adjusting the zero-point resistance between the other end of the zero-point capacitor and ground based on the voltage at the output terminal of the voltage sampling sub-circuit and the voltage at the output terminal of the error amplifier.
[0005] In some embodiments of this application, the dynamic loop compensation circuit further includes: a pole circuit; one end of the pole circuit is connected to the output terminal of the error amplifier, and the other end of the pole circuit is connected to ground.
[0006] In some embodiments of this application, the voltage sampling sub-circuit includes a voltage divider branch and a filter branch; the voltage divider branch includes a first voltage divider resistor and a second voltage divider resistor connected in series between the switching node and ground; the filter branch includes at least one stage of filter sub-circuit connected in parallel with the second voltage divider resistor.
[0007] In some embodiments of this application, the above-mentioned at least one-stage filtering sub-circuit includes: a first-stage filtering sub-circuit connected in parallel with the second voltage divider resistor; the first-stage filtering sub-circuit includes: a first filter resistor and a first filter capacitor connected in series, one end of the first filter resistor being connected to the second voltage divider resistor, and one end of the first filter capacitor being connected to ground.
[0008] In some embodiments of this application, the aforementioned resistor adjustment sub-circuit includes: a total comparator sub-circuit and a partial comparator sub-circuit, a fixed resistor, and a zero-point resistor including: a total adjustment resistor and a partial adjustment resistor; a zero-point capacitor is connected between the output terminal of the error amplifier and one end of the fixed resistor; the total adjustment resistor and the partial adjustment resistor are connected in series between the other end of the fixed resistor and ground; the total comparator sub-circuit is used to compare the output voltage with the calculated voltage, outputs a control signal to the partial comparator sub-circuit based on the comparison result of the output voltage and the calculated voltage, and controls the total adjustment resistor to be connected or not connected between the fixed resistor and ground based on the comparison result of the output voltage and the calculated voltage, and calculates the value equal to the zero-point resistor value multiplied by the reference input voltage value of the error amplifier multiplied by the transconductance of the error amplifier multiplied by the sampling coefficient divided by the loop bandwidth of the DC-DC converter divided by the capacitance value of the output capacitor of the DC-DC converter divided by twice pi; the partial comparator sub-circuit is used to compare the voltage at the output terminal of the error amplifier with the reference voltage, and controls the partial adjustment resistor to be connected or not connected between the fixed resistor and ground based on the comparison result of the voltage and the reference voltage and the control signal.
[0009] In some embodiments of this application, the above-mentioned total comparator circuit includes: a total comparator, a total NOT gate, and a total field-effect transistor; the input terminal of the total comparator is used to receive the output voltage and calculate the voltage, the output terminal of the total comparator is connected to the input terminals of the sub-comparator circuit and the total NOT gate, the output terminal of the total NOT gate is connected to the gate of the total field-effect transistor, the drain of the total field-effect transistor is connected to one end of the fixed resistor and one end of the total adjustment resistor, and the source of the total field-effect transistor is connected to the other end of the total adjustment resistor.
[0010] In some embodiments of this application, the above-mentioned comparator circuit includes: a comparator, a NOT gate, a selector, and a field-effect transistor; the input terminal of the comparator is used to connect the voltage at the output terminal of the error amplifier and the reference voltage, and the output terminal of the comparator is connected to one input terminal of the selector; the NOT gate is connected between the output terminal of the comparator and the other input terminal of the selector; the control terminal of the selector is used to connect the control signal; the output terminal of the selector is connected to the gate of the field-effect transistor; the drain of the field-effect transistor is connected to the other end of the main adjustment resistor and one end of the individual adjustment resistor, respectively; and the source of the field-effect transistor is connected to the other end of the individual adjustment resistor and ground, respectively.
[0011] In some embodiments of this application, the reference voltage includes a low voltage and a high voltage, wherein the high voltage is greater than the low voltage. The comparator circuit includes a low-voltage branch and a high-voltage branch. The adjustment resistor includes a low-voltage adjustment resistor and a high-voltage adjustment resistor. The low-voltage branch includes a low-voltage comparator, a low-voltage NOT gate, a low-voltage selector, and a low-voltage field-effect transistor. The input terminal of the low-voltage comparator is used to connect the voltage at the output terminal of the error amplifier and the low voltage. The output terminal of the low-voltage comparator is connected to one input terminal of the low-voltage selector and the input terminal of the low-voltage NOT gate, respectively. The output terminal of the low-voltage NOT gate is connected to the other input terminal of the low-voltage selector. The control terminal of the low-voltage selector is used to connect to the control signal. The output terminal of the low-voltage selector is connected to the gate of the low-voltage field-effect transistor, and the drain of the low-voltage field-effect transistor is connected to the total adjustment resistor. The other end of the resistor is connected to one end of the low adjustment resistor. The source of the low field-effect transistor is connected to the other end of the low adjustment resistor and one end of the high adjustment resistor, respectively. The high voltage branch includes: a high comparator, a high NOT gate, a high selector, and a high field-effect transistor. The input of the high comparator is used to connect the voltage at the output of the error amplifier and the high voltage. The output of the high comparator is connected to one input of the high selector and the input of the high NOT gate, respectively. The output of the high NOT gate is connected to the other input of the high selector. The control terminal of the high selector is used to connect the control signal. The output of the high selector is connected to the gate of the high field-effect transistor. The drain of the high field-effect transistor is connected to the other end of the low adjustment resistor and one end of the high adjustment resistor, respectively. The source of the high field-effect transistor is connected to the other end of the high adjustment resistor and ground, respectively.
[0012] According to a second aspect of this application, a DC-DC converter is provided, comprising: a dynamic loop compensation circuit as described in any embodiment of the first aspect; an upper transistor, a lower transistor, and an error amplifier.
[0013] In some embodiments of this application, the converter further includes:
[0014] The system comprises a PWM comparator, logic gates, an inductor, a capacitor, a first resistor, and a second resistor. The non-inverting input of the PWM comparator is connected to the output of the error amplifier. The inverting input of the PWM comparator is used to input the voltage value corresponding to the inductor current and / or the slope compensation value. The output of the PWM comparator is connected to the input of the logic gates. The logic gates are connected to the control terminals of the upper and lower transistors, respectively. The drain of the upper transistor is connected to the power supply, and the source of the lower transistor is connected to ground. The connection between the source of the upper transistor and the drain of the lower transistor serves as a switching node. One end of the inductor is connected to the switching node, and the other end of the inductor is connected to one end of the capacitor and one end of the first resistor. The other end of the capacitor is connected to ground. The other end of the first resistor and one end of the second resistor are both connected to the inverting input of the error amplifier, and the other end of the second resistor is connected to ground.
[0015] The dynamic loop compensation circuit for a DC-DC converter provided in the embodiments of this application includes: a voltage sampling sub-circuit connected to the switching node between the upper and lower transistors of the DC-DC converter, used to sample the voltage at the switching node; a zero-point capacitor, one end of which is connected to the output terminal of the error amplifier of the DC-DC converter; and a resistance adjustment sub-circuit connected between the other end of the zero-point capacitor and the voltage sampling sub-circuit, used to sample the voltage at the output terminal of the error amplifier, and adjust the zero-point resistance between the other end of the zero-point capacitor and ground based on the voltage at the output terminal of the voltage sampling sub-circuit and the voltage at the output terminal of the error amplifier. Thus, by sampling the voltage at the switching node between the upper and lower transistors through the voltage sampling sub-circuit, sampling the voltage at the output terminal of the error amplifier through the resistance adjustment sub-circuit, and adjusting the zero-point resistance between the other end of the zero-point capacitor and ground based on the voltage at the output terminal of the voltage sampling sub-circuit and the voltage at the output terminal of the error amplifier, the zero-point resistance changes with the output voltage and output current, ensuring the dynamic change of the zero and pole points of the DC-DC converter and improving the stability of the DC-DC converter under different output loads. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this application and are not intended to limit this application, wherein:
[0017] Figure 1 This is a schematic diagram of a structure of an embodiment of a dynamic loop compensation circuit applied to a DC-DC converter according to this application;
[0018] Figure 2 This is a schematic diagram of another embodiment of the dynamic loop compensation circuit applied to a DC-DC converter according to this application;
[0019] Figure 3 This is a schematic diagram of the structure of an embodiment of the DC-DC converter according to this application;
[0020] Figure 4 This is a zero-pole distribution diagram in the dynamic loop compensation circuit of this application. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are also within the scope of protection of this application.
[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.
[0023] In traditional technologies, when a DC-DC converter is connected to a Type II compensation network, the bandwidth of the DC-DC converter changes when the DC-DC converter has different loads. The fixed Type II compensation network can only compensate for part of the load of the DC-DC converter, resulting in poor stability of the overall network formed by the DC-DC converter and the Type II compensation network.
[0024] To address the shortcomings of the aforementioned conventional technologies, this application proposes a dynamic loop compensation circuit for DC-DC converters. This dynamic loop compensation circuit improves the stability of the DC-DC converter. The DC-DC converter includes an upper transistor, a lower transistor, and an error amplifier. The error amplifier outputs an error voltage based on the output feedback voltage and the reference input voltage of the DC-DC converter. Figure 1 A schematic diagram of one embodiment of the dynamic loop compensation circuit according to this application is shown. Figure 1 As shown, the dynamic loop compensation circuit includes: a voltage sampling sub-circuit connected to the switching node between the upper and lower transistors of the DC-DC converter, used to sample the voltage at the switching node; a zero-point capacitor, one end of which is connected to the output terminal of the error amplifier of the DC-DC converter; and a resistance adjustment sub-circuit connected between the other end of the zero-point capacitor and the voltage sampling sub-circuit, used to sample the voltage at the output terminal of the error amplifier, and adjust the zero-point resistance between the other end of the zero-point capacitor and ground based on the voltage at the output terminal of the voltage sampling sub-circuit and the voltage at the output terminal of the error amplifier.
[0025] In this embodiment, the DC-DC converter is a conventional DC-DC converter without a type II compensation network. The bandwidth of this DC-DC converter is variable, and therefore, the zeros and poles of the DC-DC converter are unstable.
[0026] In this embodiment, the switching node of the DC-DC converter is the node between the upper and lower transistors of the DC-DC converter.
[0027] In this embodiment, the zero-point resistor is the resistance between the other end of the zero-point capacitor and ground. Specifically, the zero-point resistor can be an adjustable resistor. The resistance value of the zero-point resistor can be adjusted by comparing the output voltage with the calculated voltage (first comparison result) and the voltage at the error amplifier output terminal with the reference voltage (second comparison result). In this embodiment, the dynamic loop compensation device is a network in the same circuit as the DC-DC converter. As the load of the DC-DC converter changes, i.e., the output voltage and output current change, the dynamic loop compensation circuit dynamically adjusts the zero-point resistor based on the changes in the voltage at the output terminal of the voltage sampling sub-circuit and the voltage at the output terminal of the error amplifier. This allows the overall circuit, composed of the dynamic loop compensation circuit and the DC-DC converter, to change with the load, thereby achieving the purpose of dynamically adjusting the zeros and poles of the overall circuit and ensuring the stability of the overall circuit.
[0028] The dynamic loop compensation circuit for a DC-DC converter provided in the embodiments of this application includes: a voltage sampling sub-circuit connected to the switching node between the upper and lower transistors of the DC-DC converter, used to sample the voltage at the switching node; a zero-point capacitor, one end of which is connected to the output terminal of the error amplifier of the DC-DC converter; and a resistance adjustment sub-circuit connected between the other end of the zero-point capacitor and the voltage sampling sub-circuit, used to sample the voltage at the output terminal of the error amplifier, and adjust the zero-point resistance between the other end of the zero-point capacitor and ground based on the voltage at the output terminal of the voltage sampling sub-circuit and the voltage at the output terminal of the error amplifier. Thus, by sampling the voltage at the switching node between the upper and lower transistors through the voltage sampling sub-circuit, sampling the voltage at the output terminal of the error amplifier through the resistance adjustment sub-circuit, and adjusting the zero-point resistance between the other end of the zero-point capacitor and ground based on the voltage at the output terminal of the voltage sampling sub-circuit and the voltage at the output terminal of the error amplifier, the zero-point resistance changes with the output voltage and output current, ensuring the dynamic change of the zero and pole points of the DC-DC converter and improving the stability of the DC-DC converter under different output loads.
[0029] In some embodiments of this application, the dynamic loop compensation circuit further includes a pole circuit.
[0030] In this circuit, one end of the pole circuit is connected to the output of the error amplifier, and the other end is connected to ground. The pole circuit can be directly adopted as follows: Figure 2 The pole capacitor Cp shown can be set based on the pole adjustment requirements of the dynamic loop compensation circuit.
[0031] The dynamic loop compensation circuit provided in this embodiment includes a pole circuit, which can dynamically compensate for the poles of the DC-DC converter and improve the pole stability of the DC-DC converter.
[0032] In some embodiments of this application, the voltage sampling sub-circuit includes: a voltage divider branch and a filter branch; the voltage divider branch includes: a first voltage divider resistor and a second voltage divider resistor connected in series between the switching node and ground; the filter branch includes: at least one stage of filter sub-circuit connected in parallel with the second voltage divider resistor.
[0033] In this embodiment, the at least one filtering sub-circuit can have multiple stages. The more stages of the at least one filtering sub-circuit, the better the filtering effect of the voltage sampling sub-circuit. However, the number of stages of the at least one filtering sub-circuit also needs to take into account the circuit area. Therefore, the number of stages of the at least one filtering sub-circuit is determined by a trade-off between the circuit area and the required filtering effect. The multi-stage filtering sub-circuit can be ordered based on the order of RC filtering. For example, the first-stage filtering sub-circuit includes a first filter resistor and a first filter capacitor connected in series, while the second-stage filtering sub-circuit is a filter circuit connected in parallel with the first filter capacitor.
[0034] In this embodiment, the resistance values of the first voltage divider resistor and the second voltage divider resistor are both resistors, and the resistance values of the first voltage divider resistor and the second voltage divider resistor can be determined based on the voltage withstand capability of the circuit components in the dynamic loop compensation circuit. For example... Figure 2 In this circuit, the first voltage divider resistor can be a resistor as shown in Rt, and the second voltage divider resistor can be a resistor as shown in Rb.
[0035] The voltage sampling sub-circuit provided in this embodiment includes a voltage divider branch and a filter branch. The voltage divider branch can effectively sample the output voltage, and the filter branch can effectively filter the output voltage, thereby improving the reliability of the obtained output voltage.
[0036] In some embodiments of this application, at least one stage of the filtering sub-circuit includes: a first stage filtering sub-circuit connected in parallel with the second voltage divider resistor; the first stage filtering sub-circuit includes: a first filter resistor and a first filter capacitor connected in series, one end of the first filter resistor being connected to the second voltage divider resistor, and one end of the first filter capacitor being connected to ground.
[0037] In this embodiment, one end of the first filter capacitor is connected to ground, and the other end of the first filter capacitor is connected to the other end of the first filter resistor. The first filter resistor is a resistor, and the first filter capacitor is a capacitor. The resistance value of the first filter resistor and the capacitance value of the first filter capacitor can be determined based on the filtering requirements of the first-stage filter sub-path.
[0038] The filter sub-circuit provided in this embodiment includes a first-stage filter sub-circuit connected between the second voltage divider resistor and ground. The first-stage filter sub-circuit includes a first filter resistor and a first filter capacitor connected in series. One end of the first filter resistor is connected to the second voltage divider resistor, one end of the first filter capacitor is connected to ground, and the other end of the first filter capacitor is connected to the first filter resistor. Therefore, when there is only one stage of the filter sub-circuit, a reliable implementation method is provided for the first-stage filter sub-circuit.
[0039] Optionally, such as Figure 2 As shown, at least one filtering sub-circuit includes: a second filtering sub-circuit and a first filtering sub-circuit connected in parallel with the second voltage divider resistor; the first filtering sub-circuit includes: a first filtering resistor R1 and a first filtering capacitor C1 connected in series, one end of the first filtering resistor R1 is connected to one end of the second voltage divider resistor Rb, and one end of the first filtering capacitor is connected to ground.
[0040] The second-stage filter circuit is connected between one end of the first filter capacitor C1 and ground. The second-stage filter circuit includes: a second filter resistor R2 and a second filter capacitor C2. One end of the second filter capacitor C2 is connected to one end of the second filter resistor R2, and the other end of the second filter capacitor C2 is connected to ground. The other end of the second filter resistor R2 is connected to the other end of the first filter capacitor. One end of the second filter resistor is used to output the output voltage Vo_spl.
[0041] In some embodiments of this application, the resistor adjustment sub-circuit includes: a total comparator sub-circuit and a partial comparator sub-circuit, and a fixed resistor; the zero-point resistor includes: a total adjustment resistor and a partial adjustment resistor. The zero-point capacitor is connected between the output terminal of the error amplifier and one end of the fixed resistor.
[0042] The main adjusting resistor and the individual adjusting resistors are connected in series between the other end of the fixed resistor and ground.
[0043] The total comparator circuit is used to compare the output voltage with the calculated voltage. Based on the comparison result, it outputs a control signal to the sub-comparator circuits and controls whether the total adjustment resistor is connected between the fixed resistor and ground based on the comparison result. The calculated voltage is obtained through a fixed loop bandwidth.
[0044] The comparator circuit is used to compare the voltage at the output of the error amplifier with the reference voltage. Based on the comparison result and the control signal, it controls whether the adjustment resistor is connected between the fixed resistor and ground.
[0045] In this embodiment, the zero-point capacitor and the fixed resistor are fixedly connected between the output terminal of the error amplifier and ground. The capacitance value of the zero-point capacitor and the resistance value of the fixed resistor can be set based on the zero-pole offset requirements. Specifically, the zero-point capacitor can be... Figure 2A capacitor with a capacitance value of Cz, and a fixed resistor can be... Figure 2 The resistor with a resistance value of Rz0.
[0046] In this embodiment, the calculated voltage is equal to the zero-point resistance value multiplied by the reference input voltage value of the error amplifier multiplied by the transconductance of the error amplifier multiplied by the sampling coefficient divided by the loop bandwidth of the DC-DC converter divided by the capacitance value of the output capacitor of the DC-DC converter divided by twice pi. Specifically, the calculated voltage Vref_vo is obtained by equation (1). When the bandwidth GBW is fixed, the calculated voltage Vref_vo can be directly obtained by formula (1).
[0047] GBW=Rz*Gm*gm*vref / (2pi*Co*Vref_vo) (1)
[0048] Equation (1) is the formula for approximating the bandwidth GBW, where Rz is the zero-point resistance and Gm is... Figure 2 In the formula, isense is the sampling coefficient, gm is the transconductance of the error amplifier, vref is the reference input voltage of the error amplifier, Co is the capacitance of the output capacitor, and pi is the mathematical symbol for pi.
[0049] The resistor adjustment sub-circuit provided in this embodiment includes: a total comparator sub-circuit, a sub-comparator sub-circuit, a total adjustment resistor, and sub-adjustment resistors. The total comparator sub-circuit controls whether the total adjustment resistor is connected between the fixed resistor and ground, and the sub-comparator sub-circuit controls whether the sub-adjustment resistor is connected between the fixed resistor and ground. This achieves the purpose of dynamically changing the zero and pole of the DC-DC converter based on the output voltage and output current.
[0050] In some embodiments of this application, such as Figure 2 As shown, the above-mentioned total comparator sub-circuit includes: a total comparator Bz, a total NOT gate Fz, and a total field-effect transistor Yz; the input terminal of the total comparator Bz is used to receive the output voltage Vo_spl and calculate the voltage Vref_vo; the output terminal of the total comparator Bz is connected to the input terminal of the sub-comparator circuit and the total NOT gate Bz, respectively; the output terminal of the total NOT gate Bz is connected to the gate of the total field-effect transistor Yz; the drain of the total field-effect transistor Yz is connected to one end of the fixed resistor and the total adjustment resistor (…). Figure 2 One end of a resistor with a resistance of 2Rs is connected, and the source of the total field-effect transistor Yz is connected to the other end of the total adjustment resistor.
[0051] The total comparator circuit provided in the embodiments of this application includes a total comparator, a total NOT gate, and a total field-effect transistor. The total comparator controls the total field-effect transistor to connect or disconnect the total adjustment resistor between the drain and source of the total field-effect transistor, thereby providing a reliable implementation of the total comparator circuit.
[0052] In some embodiments of this application, the comparator circuit includes: a comparator, a NOT gate, a selector, and a field-effect transistor; the input terminal of the comparator is used to connect the voltage at the output terminal of the error amplifier and the reference voltage, and the output terminal of the comparator is connected to one input terminal of the selector; the NOT gate is connected between the output terminal of the comparator and the other input terminal of the selector; the control terminal of the selector is used to connect the control signal; the output terminal of the selector is connected to the gate of the field-effect transistor; the drain of the field-effect transistor is connected to the other end of the main adjustment resistor and one end of the individual adjustment resistor, respectively; and the source of the field-effect transistor is connected to the other end of the individual adjustment resistor and ground, respectively.
[0053] The comparator circuit provided in this embodiment includes a comparator, a NOT gate, a selector, and a field-effect transistor. The selector determines whether to use the comparator, and the comparator controls the field-effect transistor to connect or disconnect the adjustment resistor between the drain and source of the field-effect transistor, thus providing a reliable implementation method for the comparator sub-circuit.
[0054] In some embodiments of this application, such as Figure 2 As shown, the reference voltages include: low voltage VL1 and high voltage VH1, where the high voltage VH1 is greater than the low voltage VL1. The comparator circuit includes: a low-voltage branch and a high-voltage branch. The adjustment resistors include: a low-adjustment resistor and a high-adjustment resistor. The low-adjustment resistor and the high-adjustment resistor can be set based on the zero-pole setting requirements of the dynamic loop compensation circuit, and their resistance values can be equal or unequal. Figure 2 The resistance value of both the low-to-medium and high-to-medium adjustment resistors is Rs. Figure 2 In the circuit, the resistor with a resistance value of Rs that is closer to ground is the high adjustment resistor, and the resistor with a resistance value of Rs that is farther from ground is the low adjustment resistor.
[0055] The low-voltage branch includes: low comparator B l Low NOT gate F l Low selector X l Low field-effect transistor Y l Low comparator B l The input terminal is used to connect the voltage at the output terminal of the error amplifier W and the low voltage VL1, and the low voltage comparator B. l The output terminals are respectively connected to the low selector X l One input terminal, low NOT gate F l The input terminals are connected; the low NOT gate F l The output terminal and the low selector X l The other input is connected to the low selector X. l The control terminal is used to receive control signals, low selector X lThe output terminal of the low field-effect transistor Y l Gate connection, low field-effect transistor Y l The drain of the transistor is connected to the other end of the main adjustment resistor and the other end of the low adjustment resistor, respectively. l The source is connected to the other end of the low adjustment resistor and the other end of the high adjustment resistor, respectively.
[0056] The high-voltage branch includes: high comparator B h High-Nongate F h High selector X h Y-type high field-effect transistor h High comparator B h The input terminal is used to connect the voltage Veao at the output of the error amplifier and the high voltage VH1, and the high comparator B. h The output terminals are respectively connected to the high selector X h One input terminal, high NOT gate F h The input terminals are connected; high NOT gate F h The output terminal of the high selector is connected to another input terminal of the high selector. The control terminal of the high selector is used to receive control signals. High selector X h The output terminal of the high field-effect transistor Y h Gate connection, high field-effect transistor Y h The drain of the high field-effect transistor Y is connected to the other end of the low adjustment resistor and the other end of the high adjustment resistor, respectively. h The source terminals are connected to the other end of the high adjustment resistor and ground, respectively.
[0057] In this embodiment, the high selector X h and low selector X l Both have two input terminals ( Figure 2 In the above, there is a 2-to-1 selector (with terminals a and b). When the output of the total comparator is Vc = 0, the selector output is the output of terminal a; when the output of the total comparator is Vc = 1, the selector output is the output of terminal b.
[0058] In this embodiment, the reference voltage is determined by the stability of the DC-DC converter under different loads. Therefore, the low voltage and high voltage are also determined by the stability of the DC-DC converter under different loads, and the voltage value of the high voltage is greater than the voltage value of the low voltage.
[0059] The comparator circuit provided in this embodiment includes a low-voltage branch and a high-voltage branch. The low-voltage branch includes a low comparator, a low NOT gate, a low selector, and a low field-effect transistor. The high-voltage branch includes a high comparator, a high NOT gate, a high selector, and a high field-effect transistor. The adjustment resistor includes a low adjustment resistor and a high adjustment resistor. The low selector determines whether to use the low comparator and controls the low field-effect transistor, so that the low adjustment resistor between the drain and source of the low field-effect transistor is connected or disconnected. The high selector determines whether to use the high comparator and controls the high field-effect transistor, so that the high adjustment resistor between the drain and source of the high field-effect transistor is connected or disconnected. This provides another reliable implementation method for the comparator sub-circuit.
[0060] Optionally, the reference voltage may further include at least one intermediate voltage between a low voltage value and a high voltage value. The comparator circuit may further include at least one intermediate voltage branch, and the adjustment resistor may further include at least one intermediate voltage adjustment resistor. The intermediate voltage branch in the at least one intermediate voltage branch includes an intermediate voltage comparator, a neutron gate, a selector, and a field-effect transistor (FET). The input terminal of the intermediate voltage comparator is used to connect the voltage at the output terminal of the error amplifier and the intermediate voltage. The output terminal of the intermediate voltage comparator is connected to one input terminal of the selector and the input terminal of the neutron gate, respectively. The output terminal of the neutron gate is connected to the other input terminal of the selector. The control terminal of the selector is used to receive a control signal. The output terminal of the selector is connected to the gate of the FET. The drain of the FET is connected to one end of the intermediate voltage adjustment resistor, and the source of the FET is connected to the other end of the intermediate voltage adjustment resistor. By adding an intermediate voltage and an intermediate voltage adjustment resistor to the reference voltage, the adjustment accuracy of the zero-point resistance of the dynamic compensation network can be improved, thus improving the effect of dynamic loop compensation.
[0061] This application also provides a DC-DC converter. Figure 3 A schematic diagram of the structure of one embodiment of the DC-DC converter according to this application is shown. Figure 3 As shown, the DC-DC converter includes: a dynamic loop compensation circuit, an upper transistor, a lower transistor, and an error amplifier as described in the above embodiment.
[0062] The output of the error amplifier is connected to the dynamic loop compensation circuit.
[0063] The DC-DC converter provided in this embodiment includes a dynamic loop compensation circuit. By adjusting the zero-point resistance of the DC-DC converter under different output loads through the dynamic loop compensation circuit, the stability of the circuit loop in the DC-DC converter under different output loads can be optimized.
[0064] In some embodiments of this application, such as Figure 2As shown, the aforementioned DC-DC converter also includes: a PWM comparator K, a logic gate circuit, an inductor L0, a capacitor Co, a first resistor, and a second resistor;
[0065] The non-inverting input of PWM comparator K is connected to the output of error amplifier W. The inverting input of PWM comparator K is used to input the voltage value corresponding to the current of inductor L0 and / or the slope compensation value. The output of PWM comparator K is connected to the input of logic gate circuit. The logic gate circuit is connected to the control terminals of upper transistor G1 and lower transistor G2 respectively. The drain of upper transistor G1 is connected to the power supply VIN, the source of lower transistor G2 is connected to ground, and the source of upper transistor G1 and the drain of lower transistor G2 are connected as a switching node.
[0066] like Figure 2 As shown, one end of inductor L0 is connected to the switching node, and the other end of inductor L0 is connected to one end of capacitor Co and the first resistor R. v1 One end of the capacitor Co is connected to ground; the other end of the capacitor Co is connected to ground, and the first resistor R... v1 The other end is connected to the second resistor R v2 One end of the resistor is connected to the inverting input of the error amplifier W, and the second resistor R v2 The other end is connected to the ground.
[0067] In this embodiment, one end of capacitor Co or the first resistor R v1 The output voltage at one end is the output voltage of the dynamic loop compensation circuit, which is also the voltage obtained after the power supply VIN undergoes power conversion.
[0068] In this embodiment, the load resistor Ro is connected between the other end of the inductor L0 and ground, and is used to characterize the load of the DC-DC converter.
[0069] In this embodiment, the inductance value of inductor L0, the capacitance value of capacitor Co, the resistance value of load resistor Ro, and the first resistor R are... v1 The resistance value, the second resistor R v2 The resistance value can be determined according to the setting requirements of the dynamic loop compensation circuit.
[0070] In this embodiment, the slope compensation slope is the slope compensation provided for the PWM comparator K, and this slope compensation slope is the value of the slope compensation generated by the slope function. For example... Figure 2 As shown, the voltage value isense of inductor L0 in the load circuit is obtained by sampling the inductor current.
[0071] The switching power supply provided in this embodiment includes: a PWM comparator, a logic gate circuit, an upper transistor, and a lower transistor. The PWM comparator controls the logic gate circuit to output level signals to the upper transistor and the lower transistor respectively, thereby realizing the level conversion of DC to DC power supply.
[0072] In a specific example of this application, combined with Figure 2 and Figure 4 The zero-pole diagram shown below provides a detailed description of the dynamic loop compensation circuit workflow of this application:
[0073] Dynamic loop compensation circuit through Figure 2 The voltage sampling sub-circuit shown samples the output voltage Vo_spl. The output voltage Vo_spl can be used to determine the bandwidth GBW of the dynamic loop compensation circuit. As Vo_spl increases, the bandwidth GBW of the dynamic loop compensation circuit gradually decreases. Simultaneously, the bandwidth of the dynamic loop compensation circuit is affected by the output load. As the load current decreases, the load impedance Ro gradually increases, and the output pole p2 moves towards the origin (…). Figure 4 The movement of the output current (Veao) deteriorates the stability of the dynamic loop compensation circuit. Information about the output load can be obtained by detecting the output of the error amplifier; as the output load current increases, Veao gradually increases. Figure 3 The diagram shows the zeros and poles that contribute to the stability of the dynamic loop compensation circuit. p1 is the output pole of the error amplifier, p2 is the output pole of the dynamic loop compensation circuit, z1 is the compensation zero of the dynamic compensation network, and p3 is the compensation pole of the dynamic compensation network. z1 and p3 are determined by the resistors and capacitors of the dynamic compensation network. p1 is determined by the output resistance Reao of the error amplifier and the zero-point capacitor, and p2 is determined by the load resistance Ro and the load capacitance Co of the load circuit. Because the load capacitance Co and the output resistance Reao of the error amplifier are relatively large, p1 and p2 will be closest to the origin. Figure 4 As shown, this is a zero-pole distribution diagram, with the origin being 0. When p (p1 or p2 or p3) or z1 increases, the poles move to the left away from the origin, and when p or z decreases, the poles move to the right closer to the origin.
[0074] When the output voltage Vo_spl is greater than the calculated voltage Vref_vo, the control signals Vc = 1 and Vex = b for the high selector Xh and low selector Xl. At this time, the bandwidth GBW of the dynamic loop compensation circuit is less than 10z1, and the contribution of p3 to the phase of GBW is less than the contribution of z1 to the phase of GBW. The larger the equivalent zero-point resistance Rz = Rz0 + nRs, the closer z1 is to the origin, and the greater its positive contribution to the phase at GBW, resulting in better stability of the dynamic loop compensation circuit. Therefore, as Veao decreases, the zero-point resistance Rz is dynamically increased. Specifically:
[0075] When Veao < VL1, Vs1 = Vs2 = 0, and since Vc = 1, then Ve0 = Ve1 = Ve2 = 0, and Rz = Rz0 + 4Rs; when VL1 < Veao < VH1, Vs1 = 1, Vs2 = 0, and since Vc = 1, then Ve0 = Ve2 = 0, Ve1 = 1, and Rz = Rz0 + 3Rs; when VH1 < Veao, Vs1 = Vs2 = 1, and since Vc = 1, then Ve0 = 0, Ve1 = Ve2 = 1, and Rz = Rz0 + 2Rs.
[0076] Similarly, when the output voltage Vo_spl is less than the calculated voltage Vref_vo, the control signals Vc = 0 and Vex = a of the high selector Xh and the low selector Xl. At this time, the bandwidth GBW of the dynamic loop compensation circuit is greater than 10z1, and the positive contribution of z1 to the phase of GBW reaches the maximum. The smaller the zero - point resistance Rz = Rz0 ± nRs, the unchanged positive contribution of z1 to the phase of GBW, and the farther p3 is from the origin, the smaller the negative contribution to the phase of GBW, then the better the stability of the dynamic loop compensation circuit. Therefore, as Veao decreases, the zero - point resistance Rz is reduced, specifically as follows:
[0077] When Veao < VL1, Vs1 = Vs2 = 0, and since Vc = 0, then Ve0 = Ve1 = Ve2 = 1, and Rz = Rz0; when VL1 < Veao < VH1, Vs1 = 1, Vs2 = 0, and since Vc = 0, then Ve0 = Ve2 = 1, Ve1 = 0, and Rz = Rz0 + Rs; when VH1 < Veao, Vs1 = Vs2 = 1, and since Vc = 0, then Ve0 = 1, Ve1 = Ve2 = 0, and Rz = Rz0 + 2Rs.
[0078] In summary, through the dynamic loop compensation circuit of the present application, the zero - point resistance of the compensation network can be adjusted under different loads to optimize the stability of the dynamic loop compensation circuit under a wider range of loads.
[0079] Unless the context clearly indicates otherwise, the singular forms of words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the corresponding plural is generally included. Similarly, the terms "comprising" and "including" shall be interpreted as inclusive rather than exclusive. Likewise, the terms "including" and "or" shall be interpreted as inclusive, unless such an interpretation is explicitly prohibited in this specification. Where the term "example" is used in this specification, especially when it is located after a group of terms, "example" is merely exemplary and illustrative and should not be considered exclusive or extensive.
[0080] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.
[0081] Several embodiments of this application have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of this application. The scope of protection of this application is defined by the appended claims.
Claims
1. A dynamic loop compensation circuit applied to a DC-DC converter, the DC-DC converter including an upper transistor, a lower transistor, and an error amplifier, the error amplifier being used to output an error voltage based on the output feedback voltage and a reference input voltage of the DC-DC converter, characterized in that, The dynamic loop compensation circuit includes: A voltage sampling sub-circuit is connected to the switching node between the upper and lower transistors and is used to sample the voltage at the switching node. The zero-point capacitor has one end connected to the output of the error amplifier of the DC-DC converter; A resistor adjustment sub-circuit is connected between the other end of the zero-point capacitor and the voltage sampling sub-circuit. It is used to sample the voltage at the output of the error amplifier and adjust the zero-point resistance between the other end of the zero-point capacitor and ground based on the voltage at the output of the voltage sampling sub-circuit and the voltage at the output of the error amplifier.
2. The circuit according to claim 1, characterized in that, The dynamic loop compensation circuit also includes: a pole circuit; One end of the pole circuit is connected to the output of the error amplifier, and the other end of the pole circuit is connected to ground.
3. The circuit according to claim 1, characterized in that, The voltage sampling sub-circuit includes: a voltage divider branch and a filter branch; The voltage divider branch includes: a first voltage divider resistor and a second voltage divider resistor connected in series between the switch node and ground; The filtering branch includes at least one filtering sub-path connected in parallel with the second voltage divider resistor.
4. The circuit according to claim 3, characterized in that, The at least one-stage filtering sub-path includes: a first-stage filtering sub-path connected in parallel with the second voltage divider resistor; The first-stage filtering sub-circuit includes a first filtering resistor and a first filtering capacitor connected in series. One end of the first filtering resistor is connected to the second voltage divider resistor, and one end of the first filtering capacitor is connected to ground.
5. The circuit according to claim 1, characterized in that, The resistor adjustment sub-circuit includes: a total comparator sub-circuit and a sub-comparator sub-circuit, and a fixed resistor; the zero-point resistor includes: a total adjustment resistor and a sub-adjustment resistor. The zero-point capacitor is connected between the output terminal of the error amplifier and one end of the fixed resistor. The total adjusting resistor and the individual adjusting resistors are connected in series between the other end of the fixed resistor and ground; The total comparator subcircuit is used to compare the voltage at the output of the voltage sampling subcircuit with the calculated voltage. Based on the comparison result of the voltage at the output of the voltage sampling subcircuit and the calculated voltage, it outputs a control signal to the sub-comparator subcircuit and controls whether the total adjustment resistor is connected between the fixed resistor and ground based on the comparison result of the voltage at the output of the voltage sampling subcircuit and the calculated voltage. The calculated voltage is equal to the zero-point resistor value multiplied by the reference input voltage value of the error amplifier multiplied by the transconductance of the error amplifier multiplied by the sampling coefficient divided by the loop bandwidth of the DC-DC converter divided by the capacitance value of the output capacitor of the DC-DC converter divided by 2 times pi. The sub-comparison circuit is used to compare the voltage at the output of the error amplifier with a reference voltage. Based on the comparison result of the voltage and the reference voltage and the control signal, it controls whether the sub-adjustment resistor is connected between the fixed resistor and ground.
6. The circuit according to claim 5, characterized in that, The total comparator sub-circuit includes: a total comparator, a total NOT gate, and a total field-effect transistor; The input terminal of the total comparator is used to receive the voltage from the output terminal of the voltage sampling sub-circuit and the calculated voltage. The output terminal of the total comparator is connected to the input terminal of the sub-comparator and the total NOT gate, respectively. The output terminal of the total NOT gate is connected to the gate of the total field-effect transistor. The drain of the total field-effect transistor is connected to the other end of the fixed resistor and one end of the total adjustment resistor, respectively. The source of the total field-effect transistor is connected to the other end of the total adjustment resistor.
7. The circuit according to claim 5, characterized in that, The comparator sub-circuit includes: a comparator, a NOT gate, a selector, and a field-effect transistor (FET). The input terminal of the comparator is used to connect the voltage at the output terminal of the error amplifier and the reference voltage. The output terminal of the comparator is connected to one input terminal of the selector. The NOT gate is connected between the output terminal of the comparator and the other input terminal of the selector. The control terminal of the selector is used to connect the control signal. The output terminal of the selector is connected to the gate of the FET. The drain of the FET is connected to the other end of the main adjustment resistor and one end of the individual adjustment resistor, respectively. The source of the FET is connected to the other end of the individual adjustment resistor and ground, respectively.
8. The circuit according to claim 5, characterized in that, The reference voltage includes a low voltage and a high voltage, wherein the high voltage value is greater than the low voltage value; the comparator circuit includes a low voltage branch and a high voltage branch; and the adjustment resistor includes a low adjustment resistor and a high adjustment resistor. The low-voltage branch includes: a low-voltage comparator, a low-voltage NOT gate, a low-voltage selector, and a low-voltage field-effect transistor (FET). The input terminal of the low-voltage comparator is used to connect the voltage and low voltage at the output terminal of the error amplifier. The output terminal of the low-voltage comparator is connected to one input terminal of the low-voltage selector and the input terminal of the low-voltage NOT gate. The output terminal of the low-voltage NOT gate is connected to the other input terminal of the low-voltage selector. The control terminal of the low-voltage selector is used to connect to the control signal. The output terminal of the low-voltage selector is connected to the gate of the low-voltage FET. The drain of the low-voltage FET is connected to the other end of the total adjustment resistor and one end of the low adjustment resistor. The source of the low-voltage FET is connected to the other end of the low adjustment resistor and one end of the high adjustment resistor. The high-voltage branch includes: a high-voltage comparator, a high-voltage NOT gate, a high-voltage selector, and a high-voltage field-effect transistor (FET). The input terminal of the high-voltage comparator is used to connect the voltage and high voltage of the output terminal of the error amplifier. The output terminal of the high-voltage comparator is connected to one input terminal of the high-voltage selector and the input terminal of the high-voltage NOT gate. The output terminal of the high-voltage NOT gate is connected to the other input terminal of the high-voltage selector. The control terminal of the high-voltage selector is used to connect the control signal. The output terminal of the high-voltage selector is connected to the gate of the high-voltage FET. The drain of the high-voltage FET is connected to the other end of the low-voltage adjustment resistor and one end of the high-voltage adjustment resistor. The source of the high-voltage FET is connected to the other end of the high-voltage adjustment resistor and ground.
9. A DC-DC converter, characterized in that, The converter includes: The dynamic loop compensation circuit according to any one of claims 1-8.
10. The converter according to claim 9, characterized in that, The converter also includes: PWM comparator, logic gate circuit, inductor, capacitor, first resistor, second resistor; The non-inverting input of the PWM comparator is connected to the output of the error amplifier, and the inverting input of the PWM comparator is used to input the voltage value corresponding to the inductor current and / or the slope compensation value; the output of the PWM comparator is connected to the input of the logic gate circuit, and the logic gate circuit is connected to the control terminal of the upper transistor and the control terminal of the lower transistor respectively. The drain of the upper transistor is connected to the power supply, the source of the lower transistor is connected to ground, and the source of the upper transistor and the drain of the lower transistor are connected as a switching node; One end of the inductor is connected to the switching node, and the other end of the inductor is connected to one end of the capacitor and one end of the first resistor respectively; the other end of the capacitor is connected to ground, and the other end of the first resistor and one end of the second resistor are connected together to the inverting input terminal of the error amplifier, and the other end of the second resistor is connected to ground.