Semiconductor structure and method of forming the same
By modifying the substrate side to form bit lines of uniform thickness, the problem of high resistance in buried bit lines is solved, thus improving the electrical performance of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-08-15
- Publication Date
- 2026-07-03
AI Technical Summary
In existing semiconductor structures such as DRAM, the embedded bit line structure forms rapidly in the horizontal direction, resulting in a thinner structure, which increases resistance and reduces electrical performance.
By modifying the substrate below the active region on the side of the substrate to form a bit line extending along the first direction, a metal silicide treatment and annealing process are used to form a bit line with uniform thickness.
It effectively reduces the resistance of bit lines, improves the electrical performance of semiconductor structures, and enhances the uniformity of bit line thickness distribution.
Smart Images
Figure CN117677179B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] In semiconductor structures such as DRAM, buried bit line structures are often used. However, during the formation of buried bit line structures, the formation rate of the bit line structure in the horizontal direction is greater than that in the vertical direction. This results in a thinner buried bit line structure, which has a larger resistance, thereby reducing the electrical performance of semiconductor structures such as DRAM.
[0004] Therefore, how to reduce the resistance of embedded bit lines to improve the electrical performance of semiconductor structures is a technical problem that urgently needs to be solved. Summary of the Invention
[0005] This disclosure provides semiconductor structures and their formation in some embodiments for reducing the resistance of embedded bit lines, thereby improving the electrical performance of the semiconductor structure.
[0006] According to some embodiments, this disclosure provides a method for forming a semiconductor structure, including the following steps:
[0007] A substrate is formed, and a plurality of active regions are arranged at intervals above the substrate along a first direction, wherein the first direction is parallel to the top surface of the substrate;
[0008] The substrate below the active region is modified from the side of the substrate to form bit lines that extend along the first direction and are electrically connected to a plurality of active regions arranged at intervals along the first direction.
[0009] In some embodiments, the specific steps of forming a substrate and a plurality of active regions located above the substrate and spaced apart along a first direction include:
[0010] Provide initial substrate;
[0011] The initial substrate is etched to form a plurality of first trenches spaced apart along a first direction. The initial substrate remaining between adjacent first trenches serves as the active region, and the initial substrate remaining below the first trenches and the active region serves as the substrate.
[0012] In some embodiments, the specific steps of forming a plurality of first trenches spaced apart along a first direction include:
[0013] The initial substrate is etched to form a plurality of second trenches spaced apart along a second direction. The initial substrate remaining between adjacent second trenches serves as a semiconductor layer. The initial substrate remaining below the second trenches and the semiconductor layer serves as the substrate. The second direction is parallel to the top surface of the substrate, and the first direction intersects the second direction.
[0014] An isolation layer is formed within the second trench;
[0015] The semiconductor layer and the isolation layer are etched to form a plurality of first trenches spaced apart along the first direction, and the semiconductor layer remaining between adjacent first trenches serves as the active region.
[0016] In some embodiments, before modifying the substrate below the active region from the side of the substrate, the following steps are further included:
[0017] A first protective layer is formed covering the sidewalls of the first trench within the semiconductor layer.
[0018] In some embodiments, the specific steps of modifying the substrate below the active region from the side of the substrate include:
[0019] The substrate below the active region is modified along the second direction.
[0020] In some embodiments, the specific steps of modifying the substrate below the active region along the second direction include:
[0021] The substrate below the active region is simultaneously modified from both opposite sides of the substrate along the second direction.
[0022] In some embodiments, the depth of the second trench is greater than the depth of the first trench along a third direction, wherein the third direction is perpendicular to the top surface of the substrate; the specific steps of modifying the substrate below the active region from the side of the substrate include:
[0023] The isolation layer below the first trench is etched along the first trench to form an etching groove located below the first trench within the isolation layer;
[0024] The substrate below the active region is modified along the etching groove.
[0025] In some embodiments, before etching the isolation layer below the first trench along the first trench, the following steps are further included:
[0026] A second protective layer is formed covering the sidewalls of the first trench within the isolation layer.
[0027] In some embodiments, the specific steps of forming an etching trench below the first trench within the isolation layer include:
[0028] Anisotropic etching is performed on the isolation layer below the first trench along the first trench, such that the etching rate of the isolation layer along the first direction is greater than the etching rate along the third direction, thereby forming an etching groove in the isolation layer that extends along the first direction and is continuously connected to a plurality of the first trenches that are spaced apart along the first direction.
[0029] In some embodiments, the specific steps of forming an etching trench below the first trench within the isolation layer include:
[0030] A selective etching process is used to etch the isolation layer below the first trench along the first trench, forming an etched groove in the isolation layer that extends along the first direction and is continuously connected to a plurality of the first trenches that are spaced apart along the first direction.
[0031] In some embodiments, the specific steps of forming an etching trench below the first trench within the isolation layer include:
[0032] A wet etching process is used to etch the isolation layer below the first trench along the first trench, forming an etching groove in the isolation layer that extends along the first direction and is continuously connected to a plurality of the first trenches that are spaced apart along the first direction.
[0033] In some embodiments, the modification process is a metal silicide formation process or a doped ion implantation process.
[0034] In some embodiments, the substrate below the active region is modified along the etching trench:
[0035] Metal material is deposited along the etch groove on the side of the substrate below the active region;
[0036] The substrate is annealed to form the bit line.
[0037] In some embodiments, the metallic material is one or more of Ti, Co, Mo, Ni, or Sn.
[0038] In some embodiments, the specific steps of annealing the substrate below the active region include:
[0039] The substrate is subjected to a first annealing process at a first temperature to form initial bit lines;
[0040] Remove the metallic material that did not participate in the reaction;
[0041] The initial bit line is subjected to a second annealing process at a second temperature, wherein the second temperature is higher than the first temperature.
[0042] In some embodiments, after forming the bit line, the following steps are further included:
[0043] A dielectric layer is formed to fill the first trench in the isolation layer, and the etched grooves retained below the dielectric layer serve as air gaps between adjacent bit lines.
[0044] In some embodiments, after forming the bit line, the following steps are further included:
[0045] A dielectric layer is formed that fills the first trench and the etched groove in the isolation layer.
[0046] According to other embodiments, this disclosure also provides a semiconductor structure, including:
[0047] Substrate;
[0048] Bit lines are located on the substrate and extend along a first direction, wherein the first direction is parallel to the top surface of the substrate;
[0049] Multiple active regions are located above the bit line and are spaced apart along a first direction. The bit line is continuously electrically connected to the multiple active regions spaced apart along the first direction. The thickness of the bit line is uniformly distributed in the first direction.
[0050] In some embodiments, the plurality of bit lines are spaced apart along a second direction, wherein the second direction is parallel to the top surface of the substrate, and the first direction intersects the second direction; the semiconductor structure further includes:
[0051] An isolation layer is located between the bit lines spaced apart along the second direction, and along the third direction, the bottom surface of the isolation layer is below the bottom surface of the bit lines, wherein the third direction is perpendicular to the top surface of the substrate.
[0052] In some embodiments, it also includes:
[0053] An air gap is located within the isolation layer and extends along the first direction, and the air gap is aligned with the bit line.
[0054] In some embodiments, along the third direction, the top surface of the air gap is flush with the top surface of the bit line, and the bottom surface of the air gap is flush with the bottom surface of the bit line;
[0055] Along the first direction, the length of the air gap is equal to the length of the bit line.
[0056] In some embodiments, it also includes:
[0057] A dielectric layer is located within the isolation layer and extends along the first direction, and the dielectric layer is aligned with the bit line.
[0058] In some embodiments, along the third direction, the top surface of the dielectric layer is flush with the top surface of the bit line, and the bottom surface of the dielectric layer is flush with the bottom surface of the bit line;
[0059] Along the first direction, the length of the dielectric layer is equal to the length of the bit line.
[0060] In some embodiments, the bit line is made of a metal silicide or a silicon material including doped ions.
[0061] In some embodiments, the thickness of the bit line is 5 nm to 50 nm.
[0062] The semiconductor structure and its formation method provided in some embodiments of this disclosure form bit lines by modifying the substrate below the active region from the side of the substrate. This results in a uniform thickness distribution of the formed bit lines and allows for the formation of thicker bit lines, thereby effectively reducing the resistance of the bit lines and ensuring uniform thickness distribution along their extension direction, thus improving the electrical performance of the semiconductor structure. Other embodiments of this disclosure simultaneously modify the substrate below the active region from opposite sides along a second direction, which not only improves the formation efficiency of the bit lines but also further enhances the uniformity of the bit line thickness distribution, thereby further improving the electrical performance of the semiconductor structure. Attached Figure Description
[0063] Appendix Figure 1 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure;
[0064] Appendix Figure 2 This is a top view schematic diagram of the semiconductor structure formed by specific embodiments of the present disclosure;
[0065] Appendix Figure 3-Appendix Figure 6 This is a schematic diagram of the main process cross-sections during the formation of the semiconductor structure according to a specific embodiment of this disclosure. Detailed Implementation
[0066] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0067] This specific embodiment provides a method for forming a semiconductor structure, with appendix... Figure 1 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figure 2 This is a top view schematic diagram of the semiconductor structure formed by specific embodiments of the present disclosure, with attached... Figure 3 -Appendix Figure 6 This is a schematic diagram of the main process cross-sections during the formation of the semiconductor structure according to a specific embodiment of this disclosure. Among them, Figures 3-6 yes Figure 2 The diagram shows the main process cross-sections of the four positions (aa, bb, cc, and dd) during the semiconductor structure formation process, clearly illustrating the semiconductor structure formation process. Figures 1-6 As shown, the method for forming the semiconductor structure includes the following steps:
[0068] Step S11: Form a substrate 22 and a plurality of active regions 20 located above the substrate 22 and spaced apart along a first direction D1, wherein the first direction D1 is parallel to the top surface of the substrate 22.
[0069] Step S12: Modify the substrate 22 below the active region 20 from the side of the substrate 22 to form bit lines 21 extending along the first direction D1 and electrically connected to a plurality of active regions 20 arranged at intervals along the first direction D1, such as... Figure 2 and Figure 6 As shown.
[0070] In some embodiments, the specific steps of forming the substrate 22 and the plurality of active regions 20 located above the substrate 22 and spaced apart along the first direction D1 include:
[0071] Provide initial substrate;
[0072] The initial substrate is etched to form a plurality of first trenches 31 spaced apart along the first direction D1. The initial substrate remaining between adjacent first trenches 31 serves as the active region 20, and the initial substrate remaining below the first trenches 31 and the active region 20 serves as the substrate 22.
[0073] The semiconductor structure formed in this specific embodiment can be, but is not limited to, DRAM. The following description uses DRAM as an example. For instance, the initial substrate can be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example. In other embodiments, the initial substrate can also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
[0074] In some embodiments, the specific steps of forming a plurality of first trenches 31 spaced apart along the first direction D1 include:
[0075] The initial substrate is etched to form a plurality of second trenches spaced apart along the second direction D2. The initial substrate remaining between adjacent second trenches serves as a semiconductor layer. The initial substrate remaining below the second trenches and the semiconductor layer serves as the substrate 22. The second direction D2 is parallel to the top surface of the substrate 22, and the first direction D1 intersects the second direction D2.
[0076] An isolation layer 24 is formed within the second trench;
[0077] The semiconductor layer and the isolation layer 24 are etched to form a plurality of first trenches 31 spaced apart along the first direction D1. The semiconductor layer remaining between adjacent first trenches 31 serves as the active region 20. Figure 2 and Figure 3 As shown.
[0078] Specifically, a photolithography process can be used to first etch the initial substrate along the first direction D1 to form multiple second trenches extending along the first direction D1 but not penetrating the initial substrate along a third direction, and the multiple second trenches are spaced apart along the second direction D2. After forming the second trenches, the initial substrate remaining between adjacent second trenches serves as a semiconductor layer, and the initial substrate remaining below the second trenches and the semiconductor layer serves as the substrate 22. The third direction D3 is perpendicular to the top surface of the substrate 22. In this specific embodiment, the top surface of the substrate 22 refers to the surface of the substrate 22 facing the active region 20. The intersection described in this specific embodiment can be a vertical intersection (i.e., orthogonal) or a horizontal intersection. Next, an insulating dielectric material such as an oxide material (e.g., silicon dioxide) can be deposited in the second trenches using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process to form the isolation layer 24 filling the second trenches. Subsequently, a patterned mask layer is formed over the initial substrate. For example, the patterned mask layer is located over the semiconductor layer and the isolation layer 24, and the mask layer 24 has etching windows that expose a portion of the semiconductor layer and a portion of the isolation layer 24. Then, the semiconductor layer and the isolation layer 24 are etched downwards along the etching windows in the mask layer 24 to form a plurality of first trenches 31 spaced apart along the first direction D1. The first trenches 31 extend along the second direction D2, and the semiconductor layer remaining between adjacent first trenches 31 serves as the active region 20. Figure 2 and Figure 3 As shown. Along the third direction D3, the depth of the first trench 31 is less than the depth of the isolation layer 24, that is, the top surface of the first trench 31 is above the top surface of the isolation layer 24. The specific value of the difference in depth between the first trench 31 and the isolation layer 24 along the third direction D3 can be set by those skilled in the art according to actual needs, for example, determined based on the thickness of the bit line 21 to be formed subsequently. In one example, the material of the mask layer 24 is a nitride material (e.g., silicon nitride).
[0079] In some embodiments, before modifying the substrate 22 below the active region 20 from the side of the substrate 22, the following steps are further included:
[0080] A first protective layer 40 is formed covering the sidewalls of the first trench 31 within the semiconductor layer, such as Figure 4 As shown.
[0081] Specifically, a nitride material (e.g., silicon nitride) can be deposited on the entire inner wall of the first trench 31 within the semiconductor layer (including the sidewalls and bottom wall of the first trench 31 within the semiconductor layer) to form the first protective layer 40. Then, the first semiconductor layer 40 on the bottom wall of the first trench 31 within the semiconductor layer is etched back to expose the substrate 22 beneath the first trench 31. The first protective layer 40 covering the sidewalls of the first trench 31 protects the sidewalls of the active region 20, preventing damage to the active region 20 during subsequent bit line formation processes, thereby further ensuring the electrical performance of the semiconductor structure. This specific embodiment uses a nitride material (e.g., silicon nitride) as an example to illustrate the use of the first protective layer 40 as the material. In other embodiments, the material of the first protective layer 40 can also be other insulating dielectric materials, as long as a high etch selectivity ratio is ensured between the first protective layer 40 and the substrate 22. In one example, the etch selectivity ratio between the first protective layer 40 and the substrate 22 is greater than 3.
[0082] In some embodiments, the specific steps of modifying the substrate 22 below the active region 20 from the side of the substrate 22 include:
[0083] The substrate 22 below the active region 20 is modified along the second direction D2.
[0084] Specifically, according to the pre-designed layout, the pre-formed bit line 21 extends along the first direction D1, and the second direction D2 modifies the substrate 22 below the active region 20, which can improve the formation efficiency of the bit line 21 and further improve the thickness uniformity of the bit line 21 along the second direction D2.
[0085] To further improve the formation efficiency of the bit line 21, in some embodiments, the specific steps of modifying the substrate 22 below the active region 20 along the second direction D2 include:
[0086] The substrate 22 below the active region 20 is simultaneously modified from both opposite sides of the substrate 22 along the second direction D2.
[0087] In some embodiments, along a third direction D3, the depth of the second trench is greater than the depth of the first trench 31, wherein the third direction D3 is perpendicular to the top surface of the substrate 22; the specific steps for modifying the substrate 22 below the active region 20 from the side of the substrate 22 include:
[0088] The isolation layer 24 below the first trench 31 is etched along the first trench 31, forming an etching groove 50 located below the first trench 31 within the isolation layer 24. Figure 5 As shown;
[0089] The substrate 22 below the active region 20 is modified along the etching groove 50.
[0090] In some embodiments, before etching the isolation layer 24 below the first trench 31 along the first trench 31, the following steps are further included:
[0091] A second protective layer 41 is formed covering the sidewalls of the first trench 31 within the isolation layer 24, such as Figure 4 As shown.
[0092] Specifically, to further simplify the semiconductor structure formation process, a second protective layer 41 covering the sidewalls of the first trench 31 within the isolation layer 24 can be formed simultaneously with the formation of the first protective layer 40 covering the sidewalls of the first trench 31 within the semiconductor layer. For example, a nitride material (e.g., silicon nitride) can be deposited on the entire inner wall of all the first trenches 31 (including the sidewalls and bottom wall of the first trenches 31). Then, the nitride material located on the bottom wall of the first trench 31 is etched away, leaving the nitride material remaining on the sidewalls of the first trenches 31 within the semiconductor layer as the first protective layer 40, and the nitride material remaining on the sidewalls of the first trenches 31 within the isolation layer 24 as the second protective layer 41. The second protective layer 41 protects the sidewalls of the first trenches 31, preventing damage to the sidewalls of the first trenches 31 during the subsequent etching process of the etched trench 50.
[0093] In some embodiments, the specific steps of forming an etching groove 50 located below the first trench 31 within the isolation layer 24 include:
[0094] Anisotropic etching is performed on the isolation layer 24 below the first trench 31 along the first trench 31, such that the etching rate of the isolation layer 24 along the first direction D1 is greater than the etching rate along the third direction D3, thereby forming an etching groove 50 in the isolation layer 24 that extends along the first direction D1 and is continuously connected to a plurality of the first trenches 31 that are spaced apart along the first direction D1.
[0095] Specifically, by selecting a suitable etchant or adjusting etching parameters (such as etching temperature, etching pressure, plasma concentration, etc.), the etching rate of the isolation layer 24 along the first direction D1 can be greater than the etching rate along the third direction D3. This ensures that the formed etching trench 50 can continuously connect the multiple first trenches 31 spaced apart along the first direction D1 without penetrating the isolation layer 24 along the third direction D3, thus avoiding damage to the substrate 22 beneath the isolation layer 24. Those skilled in the art can control the depth of the etching trench 50 along the third direction according to actual needs, for example, by controlling etching parameters such as etching time and etchant dosage, thereby flexibly adjusting the thickness of the subsequently formed bit line 21 along the third direction D3.
[0096] In other embodiments, the specific steps of forming the etching groove 50 located below the first trench 31 within the isolation layer 24 include:
[0097] A selective etching process is used to etch the isolation layer 24 below the first trench 31 along the first trench 31, forming an etching groove 50 in the isolation layer 24 that extends along the first direction D1 and is continuously connected to a plurality of the first trenches 31 that are spaced apart along the first direction D1.
[0098] Specifically, in order to use a selective etching process to etch the isolation layer 24 below the first trench 31 along the first trench 31, the etching amount of the isolation layer 24 below the first trench 31 along the first direction D1 is greater than the etching amount of the isolation layer 24 along the third direction D3. This ensures that the formed etching trench 50 can continuously connect multiple first trenches 31 spaced apart along the first direction D1, and will not penetrate the isolation layer 24 along the third direction D3, so as to avoid damaging the substrate 22 below the isolation layer 24.
[0099] In other embodiments, the specific steps of forming the etching groove 50 located below the first trench 31 within the isolation layer 24 include:
[0100] A wet etching process is used to etch the isolation layer 24 below the first trench 31 along the first trench 31, forming an etching groove 50 in the isolation layer 24 that extends along the first direction D1 and is continuously connected to a plurality of the first trenches 31 that are spaced apart along the first direction D1.
[0101] Specifically, after forming the second protective layer 41 covering the sidewalls of the first trench 31 within the isolation layer 24, a wet etching process can be used to etch the isolation layer 24 below the first trench 31 along the first trench 31, thereby simplifying the formation process of the etched trench 50. By adjusting the etching parameters during the wet etching process, such as the type of etchant and the etching temperature, the formed etched trench 50 can continuously connect multiple first trenches 31 spaced apart along the first direction D1 without penetrating the isolation layer 24 along the third direction D3, thus avoiding damage to the substrate 22 below the isolation layer 24.
[0102] In one example, the length of the etching trench 50 along the first direction D1 is greater than or equal to the length of the semiconductor layer along the first direction D1, thereby ensuring that the bit line 21 formed by the etching trench 50 can be electrically connected to the plurality of active regions 20 spaced apart along the first direction D1. The width of the etching trench 50 along the second direction D2 can be less than or equal to the width of the isolation layer 24 along the second direction D2, so as to increase the process window of the modification process while avoiding damage to the active regions 20.
[0103] The modification process involves modifying a portion of the substrate 22 below the active region 20, thereby enhancing the conductivity of the modified portion of the substrate 22 to form bit lines 21 electrically connected to the plurality of active regions 20 spaced apart along the first direction D1. In some embodiments, the modification process is a metal silicide treatment or a doped ion implantation treatment.
[0104] In some embodiments, the substrate 22 below the active region 20 is modified along the etching trench 50:
[0105] Metal material is deposited along the etching groove 50 on the side of the substrate 22 below the active region 20;
[0106] The substrate 22 is annealed to form the bit line 21.
[0107] In some embodiments, the metallic material is one or more of Ti, Co, Mo, Ni, or Sn. For example, when the metallic material is Ti, it can be deposited using a chemical vapor deposition process; when the metallic material is Co, it can be deposited using an atomic layer deposition process.
[0108] In some embodiments, the specific steps of annealing the substrate 22 below the active region 20 include:
[0109] The substrate 22 is subjected to a first annealing process at a first temperature to form initial bit lines;
[0110] Remove the metallic material that did not participate in the reaction;
[0111] The initial bit line is subjected to a second annealing process at a second temperature to form the bit line 21, wherein the second temperature is higher than the first temperature.
[0112] The following description uses the modification process as forming a metal silicide and the annealing process as rapid thermal annealing (RTP) as an example. For instance, the etching trench 50 exposes the opposite sidewalls of the substrate 22 below the active region 20 along the second direction D2. After forming the etching trench 50, a chemical vapor deposition process can be used to deposit metal Ti along the etching trench 50 onto the opposite sidewalls of the substrate 22 below the active region 20 along the second direction D2. Alternatively, an atomic layer deposition process can be used to deposit metal Co along the etching trench 50 onto the opposite sidewalls of the substrate 22 below the active region 20 along the second direction D2. Then, the substrate 22 undergoes a first annealing treatment at a lower first temperature, causing the metal material to react with the silicon material in the substrate 22 to form a high-resistivity metal silicide material, which serves as the initial bit line. Next, the unreacted metal material is etched away, and the initial bit line is annealed a second time at a higher second temperature to form the low-resistivity bit line 21. In one example, the first temperature is 500°C-700°C, and the second temperature is 850°C-100°C.
[0113] This specific embodiment is illustrated using a two-stage annealing process involving both low-temperature and high-temperature annealing. In other embodiments, only a single annealing process may be performed to simplify the semiconductor structure formation process.
[0114] In some embodiments, after forming the bit line 21, the following steps are further included:
[0115] A dielectric layer is formed that fills the first trench 31 in the isolation layer 24, and the etched groove 50 retained below the dielectric layer serves as an air gap between adjacent bit lines 21.
[0116] Specifically, the dielectric layer fills only the first trench 31 in the isolation layer 24, and the etched trench serves as the air gap between adjacent bit lines 21, thereby utilizing the low dielectric constant of air to further enhance the electrical isolation effect between adjacent bit lines 21. In one embodiment, the dielectric layer can be made of an oxide material (e.g., silicon dioxide).
[0117] To further simplify the semiconductor structure formation process, in some embodiments, after forming the bit line 21, the following steps are also included:
[0118] A dielectric layer is formed that fills the first trench 31 and the etching trench 50 in the isolation layer 24.
[0119] In one embodiment, after forming the bit line 21, a channel region and source and drain regions distributed along the third direction D3 on opposite sides of the channel region can be defined in the active region 20, and the source regions are electrically connected to the bit line 21. Then, a conductive material such as TiN or tungsten is deposited along the first trench 21 to form a word line 30 covering the channel region. Figure 2 As shown, the word lines 30 extend along the second direction D2 and continuously cover the channel regions of the plurality of active regions 20 spaced apart along the second direction D2, and the plurality of word lines 30 are spaced apart along the first direction D1. Next, a capacitor electrically connected to the drain region can be formed above the drain region.
[0120] This specific embodiment also provides a semiconductor structure, which can be adopted as follows: Figures 1-6 The semiconductor structure shown is formed using the method for forming the semiconductor structure. A schematic diagram of the semiconductor structure provided in this specific embodiment can be found in [reference]. Figure 2 and Figure 6 .like Figures 1-6 As shown, the semiconductor structure includes:
[0121] Substrate 22;
[0122] Bit line 21 is located on the substrate 22 and extends along a first direction D1, wherein the first direction D1 is parallel to the top surface of the substrate 22;
[0123] Multiple active regions 20 are located above the bit line 21, and the multiple active regions 20 are arranged at intervals along the first direction D1. The bit line 21 is continuously electrically connected to the multiple active regions 20 arranged at intervals along the first direction D1. The thickness of the bit line 21 is uniformly distributed in the first direction D1.
[0124] The semiconductor structure formed in this specific embodiment can be, but is not limited to, DRAM. The following description uses DRAM as an example. For instance, the substrate 22 can be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example. In other embodiments, the substrate 22 can also be a gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI semiconductor substrate. The top surface of the substrate 22 refers to the surface of the substrate 22 facing the active region 20.
[0125] In this specific embodiment, the thickness of the bit line 21 refers to the thickness of the bit line 21 along a third direction D3. The third direction D3 is perpendicular to the top surface of the substrate 22. By ensuring a uniform thickness distribution of the bit line 21 along its extension direction, this specific embodiment achieves two advantages: firstly, it enables stable transmission of electrical signals along the bit line 21, thereby ensuring the uniformity of the electrical signals obtained by the multiple active regions electrically connected to the bit line 21; secondly, it reduces the resistance of the bit line 21, thereby improving the electrical performance of the semiconductor structure.
[0126] In some embodiments, the plurality of bit lines 21 are arranged at intervals along a second direction D2, wherein the second direction D2 is parallel to the top surface of the substrate 22, and the first direction D1 intersects the second direction D2; the semiconductor structure further includes:
[0127] An isolation layer 24 is located between the bit lines 21 spaced apart along the second direction D2, and along the third direction D3, the bottom surface of the isolation layer 24 is below the bottom surface of the bit lines 21, wherein the third direction D3 is perpendicular to the top surface of the substrate 22.
[0128] Specifically, a plurality of active regions 20 are arranged in a two-dimensional array above the substrate 22 along the first direction D1 and the second direction D2, forming an active array structure. An isolation layer 24 extends along the first direction D1, and a plurality of isolation layers 24 are spaced apart along the second direction D2. The isolation layer 24 is located between the bit lines 21 spaced apart along the second direction D2 and between two columns of active regions 20 spaced apart along the second direction D2, for electrically isolating adjacent bit lines 21 along the second direction D2 and adjacent active regions 20 along the second direction D2. The isolation layer 24 is set to a greater depth along the third direction D3 to form thicker and more uniformly distributed bit lines 21, i.e., the uniformly distributed bit lines 21 can be formed by modifying the substrate 22 below the active regions 20 from the side of the substrate 22. In one example, the material of the isolation layer 24 is an oxide material (e.g., silicon dioxide).
[0129] In some embodiments, the semiconductor structure further includes:
[0130] An air gap is located within the isolation layer 24 and extends along the first direction D1. The air gap is aligned with the bit line 21.
[0131] In some embodiments, along the third direction D3, the top surface of the air gap is flush with the top surface of the bit line 21, and the bottom surface of the air gap is flush with the bottom surface of the bit line 21.
[0132] Along the first direction D1, the length of the air gap is equal to the length of the bit line 21.
[0133] Specifically, along the second direction D2, the air gaps and bit lines 21 are arranged alternately. The air gaps serve two purposes: firstly, they utilize the low dielectric constant of air to further enhance the electrical isolation between adjacent bit lines 21; secondly, the location of the air gaps also serves to modify the silicon material below the active region 20 from the side, thereby forming the bit lines 21.
[0134] In some embodiments, the semiconductor structure further includes:
[0135] A dielectric layer is located within the isolation layer 24 and extends along the first direction D1, and the dielectric layer is aligned with the bit line 21.
[0136] In some embodiments, along the third direction D3, the top surface of the dielectric layer is flush with the top surface of the bit line 21, and the bottom surface of the dielectric layer is flush with the bottom surface of the bit line 21.
[0137] Along the first direction D1, the length of the dielectric layer is equal to the length of the bit line 21.
[0138] In some embodiments, the bit line 21 is made of a metal silicide or a silicon material including doped ions. In one example, the bit line 21 is made of a titanium silicon compound or a cobalt silicon compound.
[0139] To further reduce the resistance of the bit line 21, in some embodiments, the thickness of the bit line 21 is 5nm to 50nm.
[0140] The semiconductor structure and its formation method provided in some embodiments of this specific embodiment form bit lines by modifying the substrate below the active region from the side of the substrate. This results in a uniform thickness distribution of the formed bit lines and allows for the formation of thicker bit lines, thereby effectively reducing the resistance of the bit lines and ensuring uniform thickness distribution along their extension direction, thus improving the electrical performance of the semiconductor structure. In other embodiments of this specific embodiment, the substrate below the active region is modified simultaneously from opposite sides along a second direction from both sides of the active region. This not only improves the formation efficiency of the bit lines but also further enhances the uniformity of the bit line thickness distribution, thereby further improving the electrical performance of the semiconductor structure.
[0141] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A method for forming a semiconductor structure, characterized in that, Includes the following steps: A substrate is formed, and a plurality of active regions are arranged at intervals above the substrate along a first direction, wherein the first direction is parallel to the top surface of the substrate; The substrate below the active region is modified from the side of the substrate to form bit lines that extend along the first direction and are electrically connected to a plurality of active regions that are spaced apart along the first direction. The specific steps of forming a substrate and a plurality of active regions located above the substrate and spaced apart along a first direction include: Provide initial substrate; The initial substrate is etched to form a plurality of first trenches spaced apart along a first direction. The initial substrate remaining between adjacent first trenches serves as the active region, and the initial substrate remaining below the first trenches and the active region serves as the substrate. The specific steps for forming a plurality of first trenches spaced apart along a first direction include: The initial substrate is etched to form a plurality of second trenches spaced apart along a second direction. The initial substrate remaining between adjacent second trenches serves as a semiconductor layer. The initial substrate remaining below the second trenches and the semiconductor layer serves as the substrate. The second direction is parallel to the top surface of the substrate, and the first direction intersects the second direction. An isolation layer is formed within the second trench; The semiconductor layer and the isolation layer are etched to form a plurality of first trenches spaced apart along the first direction, and the semiconductor layer remaining between adjacent first trenches serves as the active region. The specific steps for modifying the substrate below the active region from the side of the substrate include: The substrate below the active region is modified along the second direction; Along a third direction, the depth of the second trench is greater than the depth of the first trench, wherein the third direction is perpendicular to the top surface of the substrate; the specific steps for modifying the substrate below the active region from the side of the substrate include: The isolation layer below the first trench is etched along the first trench to form an etching groove located below the first trench within the isolation layer; The substrate below the active region is modified along the etching groove.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, Before modifying the substrate below the active region from the side of the substrate, the following steps are also included: A first protective layer is formed covering the sidewalls of the first trench within the semiconductor layer.
3. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for modifying the substrate below the active region along the second direction include: The substrate below the active region is simultaneously modified from both opposite sides of the substrate along the second direction.
4. The method for forming a semiconductor structure according to claim 1, characterized in that, Before etching the isolation layer below the first trench along the first trench, the following steps are also included: A second protective layer is formed covering the sidewalls of the first trench within the isolation layer.
5. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for forming an etching groove located below the first trench within the isolation layer include: Anisotropic etching is performed on the isolation layer below the first trench along the first trench, such that the etching rate of the isolation layer along the first direction is greater than the etching rate along the third direction, thereby forming an etching groove in the isolation layer that extends along the first direction and is continuously connected to a plurality of the first trenches that are spaced apart along the first direction.
6. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for forming an etching groove located below the first trench within the isolation layer include: A selective etching process is used to etch the isolation layer below the first trench along the first trench, forming an etched groove in the isolation layer that extends along the first direction and is continuously connected to a plurality of the first trenches that are spaced apart along the first direction.
7. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for forming an etching groove located below the first trench within the isolation layer include: A wet etching process is used to etch the isolation layer below the first trench along the first trench, forming an etching groove in the isolation layer that extends along the first direction and is continuously connected to a plurality of the first trenches that are spaced apart along the first direction.
8. The method for forming a semiconductor structure according to claim 1, characterized in that, The modification process is either metal silicide formation or dopant ion implantation.
9. The method for forming a semiconductor structure according to claim 8, characterized in that, The substrate below the active region is modified along the etching trench: Metal material is deposited along the etch groove on the side of the substrate below the active region; The substrate is annealed to form the bit line.
10. The method for forming a semiconductor structure according to claim 9, characterized in that, The metallic material is one or more of Ti, Co, Mo, Ni, or Sn.
11. The method for forming a semiconductor structure according to claim 10, characterized in that, The specific steps for annealing the substrate below the active region include: The substrate is subjected to a first annealing process at a first temperature to form initial bit lines; Remove the metallic material that did not participate in the reaction; The initial bit line is subjected to a second annealing process at a second temperature, wherein the second temperature is higher than the first temperature.
12. The method for forming a semiconductor structure according to claim 9, characterized in that, After the bit line is formed, the following steps are also included: A dielectric layer is formed to fill the first trench in the isolation layer, and the etched grooves retained below the dielectric layer serve as air gaps between adjacent bit lines.
13. The method for forming a semiconductor structure according to claim 9, characterized in that, After the bit line is formed, the following steps are also included: A dielectric layer is formed that fills the first trench and the etched groove in the isolation layer.
14. A semiconductor structure, said semiconductor structure being formed using the formation method according to any one of claims 1-13, characterized in that, include: Substrate; Bit lines are located on the substrate and extend along a first direction, wherein the first direction is parallel to the top surface of the substrate; Multiple active regions are located above the bit line and are spaced apart along a first direction. The bit line is continuously electrically connected to the multiple active regions spaced apart along the first direction. The thickness of the bit line is uniformly distributed in the first direction.
15. The semiconductor structure according to claim 14, characterized in that, The plurality of bit lines are arranged at intervals along a second direction, wherein the second direction is parallel to the top surface of the substrate, and the first direction intersects the second direction; the semiconductor structure further includes: An isolation layer is located between the bit lines spaced apart along the second direction, and along the third direction, the bottom surface of the isolation layer is below the bottom surface of the bit lines, wherein the third direction is perpendicular to the top surface of the substrate.
16. The semiconductor structure according to claim 15, characterized in that, Also includes: An air gap is located within the isolation layer and extends along the first direction, and the air gap is aligned with the bit line.
17. The semiconductor structure according to claim 16, characterized in that, Along the third direction, the top surface of the air gap is flush with the top surface of the bit line, and the bottom surface of the air gap is flush with the bottom surface of the bit line; Along the first direction, the length of the air gap is equal to the length of the bit line.
18. The semiconductor structure according to claim 15, characterized in that, Also includes: A dielectric layer is located within the isolation layer and extends along the first direction, and the dielectric layer is aligned with the bit line.
19. The semiconductor structure according to claim 18, characterized in that, Along the third direction, the top surface of the dielectric layer is flush with the top surface of the bit line, and the bottom surface of the dielectric layer is flush with the bottom surface of the bit line; Along the first direction, the length of the dielectric layer is equal to the length of the bit line.
20. The semiconductor structure according to claim 14, characterized in that, The material of the bit line is a metal silicide material or a silicon material including doped ions.
21. The semiconductor structure according to claim 14, characterized in that, The thickness of the bit line is 5nm to 50nm.