Electronic device and method of secure access software

Abstract

The embodiment of the present application provides an electronic device and a method for securely accessing software, the electronic device comprises a processor and a first controller; the processor is used for running current software, and provides a logical address of a memory to be accessed by the current software to the first controller; the first controller is used for converting the logical address into a physical address in the memory, and determining whether the physical address is in a preset physical address range corresponding to a current exception level of the current software; when the physical address is in the preset physical address range, the current software is allowed to access the logical address; wherein the electronic device has a plurality of exception levels, each exception level in the plurality of exception levels reflects a permission level, and each exception level corresponds to a physical address range, the current exception level is one of the plurality of exception levels, and the electronic device and the method for securely accessing software provided by the embodiment of the present application can improve the security of the running software.

Description

Technical Field

[0001] This application relates to the field of computer security, and more particularly to a method for an electronic device and secure access software. Background Technology

[0002] With the rapid development of Internet technology and smart terminals, more and more applications are running on smart terminals. These applications usually involve various fields, such as electronic payment applications, biometric applications, and instant messaging applications. Because these applications are related to the user's own interests, the requirements for the security of the terminal operating environment are getting higher and higher.

[0003] To ensure the security of the terminal operating environment, the industry has proposed setting multiple exception levels (EL) for electronic devices. Software running at a higher exception level can access the physical address range corresponding to lower exception levels. In related technologies, important data such as biometric data (fingerprint data, facial image data) and keys are typically stored in the physical address range corresponding to lower exception levels. When software running at a higher exception level is attacked, hackers can access this important data, leading to data breaches and threatening user interests. Therefore, improving software security remains a problem that needs to be solved. Summary of the Invention

[0004] The electronic device and secure access software method provided in this application can improve the security of the running software. To achieve the above objectives, this application adopts the following technical solution.

[0005] In a first aspect, embodiments of this application provide an electronic device comprising: a processor and a first controller; the processor is configured to run current software and provide the first controller with a logical address of a memory to be accessed by the current software; the first controller converts the logical address into a physical address in the memory and determines whether the physical address is within a preset physical address range corresponding to the current exception level of the current software; when the physical address is within the preset physical address range, the current software is allowed to access the logical address; wherein the electronic device has multiple exception levels, each of the multiple exception levels reflects a privilege level (PL), and each exception level corresponds to a physical address range, and the current exception level is one of the multiple exception levels.

[0006] This application embodiment sets a corresponding physical address range for each anomaly level, restricting each physical address range to be accessed only by software running at the corresponding anomaly level. As a result, some important instructions or data can be stored in the restricted physical address range, which can prevent hackers from accessing the physical address range corresponding to low anomaly levels by running software at high anomaly levels to tamper with or steal important instructions or data, thereby improving the security of software operation.

[0007] In one possible implementation, the first controller is specifically configured to: provide the physical address to the processor when the current software is allowed to access the logical address; the processor is further configured to: continue running the current software to access the physical address.

[0008] In one possible implementation, the electronic device further includes: a storage unit for storing the mapping relationship between the plurality of exception levels and the plurality of physical address ranges; and a first controller specifically configured to determine the preset physical address range corresponding to the current exception level based on the mapping relationship.

[0009] In one possible implementation, the storage unit includes a plurality of registers; the processor is further configured to: load the mapping relationship into the plurality of registers when the electronic device is started; and lock the plurality of registers after the loading is completed.

[0010] Once the registers are locked, the mapping relationships within them cannot be altered during the operation of the electronic device. This prevents hackers from stealing important data by rewriting the register mapping relationships during device operation, further enhancing software security.

[0011] In one possible implementation, the processor is further configured to: detect whether the plurality of physical address ranges in the mapping relationship are correct when performing the loading; and when at least one of the plurality of physical address ranges is detected to be incorrect, perform an operation to terminate the startup of the processor.

[0012] By checking whether the multiple physical address ranges in the above mapping relationship are correct, it is possible to avoid the risk that certain important data is not set in the physical address range, thus avoiding the risk of being rewritten or stolen by hackers.

[0013] In one possible implementation, the storage unit includes the memory; the electronic device further includes a second controller for modifying the mapping relationship in the memory.

[0014] By setting up a second controller to manage the mapping relationship, it is possible to prevent hackers from directly rewriting the mapping relationship by running a processor.

[0015] In one possible implementation, the first controller is further configured to: perform a security protection operation when the physical address is not within the preset physical address range.

[0016] In one possible implementation, the first controller is further configured to: perform a security protection operation when the physical address is within one or more other physical address ranges corresponding to one or more other anomaly levels, wherein the plurality of anomaly levels includes the one or more other anomaly levels; and allow the current software to access the logical address when the physical address is not within the preset physical address range and is not within the one or more other physical address ranges.

[0017] In one possible implementation, the security protection operation includes at least one of the following: resetting the processor, denying the access, instructing the processor to stop running, disabling at least some of the functions of the processor, or preventing the processor from accessing the memory.

[0018] Secondly, embodiments of this application provide a method for secure access software applied to an electronic device. The method includes: converting the logical address of a memory to be accessed by the currently running software into a physical address in the memory; determining whether the physical address is within a preset physical address range corresponding to the current exception level of the current software; and allowing the current software to access the logical address when the physical address is within the preset physical address range. The electronic device has multiple exception levels, each exception level reflecting a permission level, and each exception level corresponding to a physical address range, wherein the current exception level is one of the multiple exception levels.

[0019] Based on the second aspect, in one possible implementation, the mapping relationship between the multiple exception levels and the multiple physical address ranges is stored in a storage unit; determining whether the physical address is within a preset physical address range corresponding to the current exception level of the current software includes: determining the preset physical address range corresponding to the current exception level according to the mapping relationship.

[0020] Based on the second aspect, in one possible implementation, the method further includes: performing a security protection operation when the physical address is not within the preset physical address range.

[0021] Based on the second aspect, in one possible implementation, the method further includes: performing a security protection operation when the physical address is within one or more other physical address ranges corresponding to one or more other anomaly levels, wherein the plurality of anomaly levels includes the one or more other anomaly levels; and allowing the current software to access the logical address when the physical address is not within the preset physical address range and is not within the one or more other physical address ranges.

[0022] Based on the second aspect, in one possible implementation, the security protection operation includes at least one of the following: resetting the processor in the electronic device, denying the access, instructing the processor to stop operating, disabling at least some functions of the processor, or preventing the processor from accessing the memory.

[0023] Thirdly, embodiments of this application provide an apparatus comprising: a conversion module for converting a logical address of a memory to be accessed by currently running software into a physical address in the memory; a determination module for determining whether the physical address is within a preset physical address range corresponding to the current exception level of the current software; and a first access permission module for allowing the current software to access the logical address when the physical address is within the preset physical address range; wherein the electronic device has multiple exception levels, each exception level reflecting a permission level, and each exception level corresponding to a physical address range, and the current exception level is one of the multiple exception levels.

[0024] In one possible implementation, the mapping relationship between the multiple exception levels and multiple physical address ranges is stored in a storage unit; the determining module is specifically used to: determine the preset physical address range corresponding to the current exception level according to the mapping relationship.

[0025] In one possible implementation, the device further includes: a first security protection module, used to perform a security protection operation when the physical address is not within the preset physical address range.

[0026] In one possible implementation, the device further includes: a second security protection module, configured to perform a security protection operation when the physical address is within one or more other physical address ranges corresponding to one or more other anomaly levels, wherein the plurality of anomaly levels includes the one or more other anomaly levels; and a second access permission module, configured to allow the current software to access the logical address when the physical address is not within the preset physical address range and is not within the one or more other physical address ranges.

[0027] In one possible implementation, the security protection operation includes at least one of the following: resetting the processor in the electronic device, denying the access, instructing the processor to stop operating, disabling at least some of the functions of the processor, or preventing the processor from accessing the memory.

[0028] Fourthly, embodiments of this application provide an apparatus comprising a memory and a controller, the memory being used to store a computer program, and the controller being configured to invoke all or part of the computer program stored in the memory to execute the method described in the second aspect above.

[0029] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a controller, is used to implement the method described in the second aspect.

[0030] In a sixth aspect, embodiments of this application provide a computer program product that, when executed by a controller, is used to implement the method described in the second aspect above.

[0031] It should be understood that the second to sixth aspects of this application are consistent with the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, so they will not be described again. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application;

[0034] Figure 2 This is a schematic diagram of the software architecture of an electronic device provided in an embodiment of this application;

[0035] Figure 3 This is a schematic diagram illustrating the mapping relationship between the physical address range and the exception level in the memory provided in an embodiment of this application;

[0036] Figure 4 This is another schematic diagram illustrating the mapping relationship between physical address ranges and exception levels in a memory, provided in an embodiment of this application.

[0037] Figure 5 This is a flowchart of a detection method for a controller provided in an embodiment of this application;

[0038] Figure 6 This is a flowchart of a detection method applied to a controller in a specific scenario provided in the embodiments of this application;

[0039] Figure 7 This is another hardware structure diagram of the electronic device provided in the embodiments of this application;

[0040] Figure 8 This is a flowchart of a method for securely accessing software provided in an embodiment of this application;

[0041] Figure 9 This is a schematic diagram of the device provided in an embodiment of this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] The terms "first," "second," and similar terms used in this article do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one" and similar terms do not indicate a quantity limitation, but rather indicate the existence of at least one. Terms such as "connection" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect, equivalent to connectivity in a broad sense.

[0044] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. For example, multiple exception levels refer to two or more exception levels.

[0045] Please refer to Figure 1 This illustration shows a hardware architecture diagram of an electronic device 100 provided in an embodiment of this application. The electronic device 100 can be located within a terminal. The terminal can be a user equipment (UE), such as a mobile phone, tablet computer, or wearable device (such as a smartwatch) and other types of portable terminal devices. Figure 1This is merely one example of electronic device 100. Alternatively, electronic device 100 can be any type of device, such as a chip or chipset, or a circuit board with a chip or chipset mounted on it, etc., and this embodiment is not limited to this. The chip or chipset, or the circuit board with a chip or chipset mounted on it, can operate under suitable software drivers. Electronic device 100 includes a processor 101 and a controller 102. Optionally, the processor 101 and the controller 102 can be integrated into one or more chips, which can be considered as a chipset. When one or more processors are integrated into the same chip, the chip is also called a system on a chip (SOC), specifically as follows: Figure 1 As shown. The system-on-a-chip (SoC) may also integrate a cache. The processor 101 may include a logic computing unit and registers (including but not limited to data registers and instruction registers) for loading programs and executing instructions. The controller 104 may also exist outside the processor 101; this embodiment does not limit this. The processor 101 may include, for example, a central processing unit (CPU) or a dedicated processor. For example, a dedicated processor includes an artificial intelligence processor, a neural network processor, a digital signal processor, or an image processing processor. The controller 102 may include, but is not limited to, a memory management unit (MMU). As long as the controller 102 can perform virtual address to physical address translation and implement subsequent judgment processes, its implementation form is not limited in this embodiment. The electronic device 100 may also include one or more other components, such as a memory 103. The memory 103 may exemplary include volatile memory, such as dynamic random access memory (DRAM), for storing instructions and data. The memory 103 may be selectively integrated into the aforementioned SoC or located outside the aforementioned SoC. Figure 1 The diagram schematically illustrates a scenario where the memory 103 is located outside the System-on-a-Chip (SOC). The memory 103 can store various operating system programs (e.g., general-purpose operating system programs and trusted operating system programs), application programs, instruction codes, and data required for operation. The processor 101 and controller 102 execute various functional applications and data processing of the electronic device 100 by loading programs and instructions and acquiring data.

[0046] In this embodiment, the software operating architecture of the electronic device 100 can be based on the TrustZone architecture proposed by ARM. Under the TrustZone architecture, the software operating environment of the electronic device 100 can include a rich execution environment (REE) and a trust execution environment (TEE), such as... Figure 2 As shown. The software running in the TEE can be called TEE software, and the software running in the REE can be called REE software. The code of the TEE software is different from and isolated from the code of the REE software. The security of the TEE software is higher than that of the REE software. REE software may include, for example, ordinary application (AP) software, general operating system software, and hypervisor software; TEE software may include, for example, trusted application software, trusted operating system software, secure partition management (SPM) software, and monitor software. The software described in this application embodiment may include instructions and data. The aforementioned general operating system refers to an operating system that provides users with applications and services (such as instant messaging or shopping services). The general operating system mainly implements computing functions, such as, but not limited to, Windows systems, Android systems, Red Hat Linux systems, or HarmonyOS. These operating systems can be used to support general non-secure ordinary applications. These ordinary applications are usually third-party applications (such as video applications, shopping applications). The aforementioned trusted operating system is used to support secure applications, implementing tasks such as security measurement, access control, and security rule decision-making during the runtime of the general operating system, ensuring the correct and reliable operation of the general operating system. This security application may include applications that perform security services such as signature verification, encryption / decryption calculations, and facial recognition. The aforementioned monitoring software is used to support switching between REE and TEE.

[0047] In this embodiment, the software operating architecture of the electronic device 100 is based on the TrustZone architecture, and the electronic device 100 may also include multiple exception levels (ELs). Figure 2The diagram schematically illustrates four anomaly levels, EL0 to EL3. In a specific scenario, the aforementioned ordinary applications and trusted applications can run at anomaly level EL0, general-purpose operating systems and trusted operating systems can run at anomaly level EL1, management programs and security partition management can run at anomaly level EL2, and monitors can run at anomaly level EL3. Anomaly level EL0 is the lowest level, and anomaly level EL3 is the highest level. In this embodiment, each anomaly level corresponds to a physical address range in memory 103. Important data such as keys, facial information, fingerprint data, and signature authentication data are typically stored in the physical address range corresponding to anomaly level EL1, which is used for storing trusted data. Each physical address range corresponding to each anomaly level is restricted to access only by TEE software running at the corresponding anomaly level. Access as described in this embodiment can refer to reading instructions, reading data, or writing data. The following specific examples will explain in detail the mapping relationship between anomaly levels and physical address ranges, as well as the software's access permissions to each physical address range. Figure 3 The diagram schematically illustrates the physical address ranges in memory 103 corresponding to each exception level, thus demonstrating the mapping relationship. For example... Figure 3 As shown, the physical address range 0x0000~0x2000 corresponds to exception level EL0; the physical address range 0x3000~0x5000 corresponds to exception level EL1; the physical address range 0x7000~0x9000 corresponds to exception level EL2; and the physical address range 0x1100~0x1300 corresponds to exception level EL3. Software such as TA running at exception level EL0 can only access the physical address range 0x0000~0x2000 in memory 103, such as... Figure 3 The remaining physical address ranges shown are inaccessible; software running at exception level EL1, such as the TEE operating system, can only access the physical address range 0x3000 to 0x5000 in memory 103. Figure 3 The remaining physical address ranges shown are inaccessible; software running at exception level EL2, such as SPM, can only access the physical address range 0x7000 to 0x9000 in memory 103, such as... Figure 3 The remaining physical address ranges shown are inaccessible; software running at exception level EL3, such as trusted firmware, can only access the physical address range 0x1100 to 0x1300 in memory 103, such as... Figure 3 The remaining physical address ranges shown are inaccessible.

[0048] In traditional technologies, software running at higher anomaly levels typically has higher access permissions, meaning it can access the physical address range corresponding to lower anomaly levels. For example, suppose processor 101 is currently running monitor software. Since the monitor software runs at EL3, it can access the physical address range corresponding to anomaly level EL1. Because important data such as facial feature data and fingerprint data are stored in the physical address range corresponding to anomaly level EL1, hackers can attack the monitor software to steal important data such as facial feature data or fingerprint recognition data, leading to the leakage of important data and reducing the security of software operation. This application embodiment sets a corresponding physical address range for each anomaly level, restricting each physical address range to be accessed only by software running at the corresponding anomaly level. Therefore, some important instructions or data can be stored in the restricted physical address range, preventing hackers from accessing the physical address range corresponding to lower anomaly levels by running software at higher anomaly levels. This prevents important instructions or data from being tampered with or stolen, thus improving the security of software operation.

[0049] It should be noted that the restricted physical address ranges corresponding to each anomaly level can be a partial or complete range. When the physical address range corresponding to each anomaly level includes other physical address ranges besides the restricted ranges, these other physical address ranges may not be subject to restrictions, and software access to these other physical address ranges can be the same as with traditional techniques (e.g., software running at a high anomaly level can access the physical address range corresponding to a low anomaly level). For example, suppose that besides… Figure 3 In addition to the physical address range corresponding to exception level EL1 shown, the physical address range corresponding to exception level EL1 also includes the physical address range 0x2050 to 0x2FFF; since exception level EL3 is higher than exception level EL1, software running at exception level EL3 can access the physical address range 0x2050 to 0x2FFF.

[0050] In this embodiment, restricting access to physical address ranges corresponding to other exception levels by software running at the current exception level is achieved by controller 102 based on the physical address to be accessed by the software currently running on processor 101 and the mapping relationship between each exception level and the physical address range. Typically, before accessing instructions or data in memory 103, the software currently running on processor 101 needs to provide controller 102 with the logical address VA1 in memory 103 that the software needs to access. Controller 102 converts the logical address VA1 into a physical address PA1 and checks whether the physical address PA1 is within the physical address range R1 corresponding to the current exception level of the software. When controller 102 detects that the physical address PA1 is within the physical address range R1, the software is allowed to access the logical address VA1. When controller 102 detects that the physical address PA1 is not within the physical address range R1, controller 102 can directly execute a security protection operation. Alternatively, when controller 102 detects that physical address PA1 is not within the physical address range R1, controller 102 may further detect whether physical address PA1 is within the physical address range corresponding to one or more other exception levels. When controller 102 detects that physical address PA1 is not within the physical address range corresponding to one or more other exception levels, it may allow the current software to access logical address VA1; when controller 102 detects that physical address PA1 is within the physical address range corresponding to one or more other exception levels, it may perform security protection operations. The security protection operations described herein may specifically include, but are not limited to, at least one of the following: resetting processor 101, denying access to logical addresses by the currently running software on processor 101, instructing processor 101 to stop running, disabling at least some functions of processor 101, and preventing processor 101 from accessing memory 103. This improves the security of software operation. It should be noted that, in this embodiment, the controller 102 and the processor 101 can be connected via electronic circuitry. After the electronic device 100 is powered on, and after the exception level of the software running by the processor 101 changes, the processor 101 can provide an indication signal indicating the current exception level to the controller 102 via the aforementioned electronic circuitry. For example, this indication signal can be two bits: "00" indicates exception level EL0, "01" indicates exception level EL1, "10" indicates exception level EL2, and "11" indicates exception level EL3. For instance, assuming the software running by the processor 101 jumps from exception level EL2 to exception level EL3, the exception level of the software running by the processor 101 changes. At this time, the processor 101 can provide the indication signal "11" to the controller 102. Thus, the controller 102 can determine the current exception level of the software running by the processor 101 based on the indication signal provided by the processor 101.

[0051] In this embodiment, the controller 102's permission for the currently running software of the processor 101 to access the logical address VA1 can include two possible implementations. In the first possible implementation, the controller 102 can directly provide the physical address PA1, obtained by converting the logical address VA1, to the processor 101, so that the processor 101 accesses the physical address PA1 from the memory 103 to read instructions, read data, or write data to the physical address PA1. In the second possible implementation, the electronic device 100 may further include a direct memory access (DMA) controller. The controller 102 can provide the physical address PA1 to the DMA controller, so that the DMA controller moves the instructions or data stored at physical address PA1 in the memory 103 to a storage area desired by the processor 101 or other processors 101, or moves data to be stored in the processor 101 or the storage area to physical address PA1.

[0052] In this embodiment, the workflow of processor 101 typically includes multiple stages such as instruction fetching from memory 103, instruction decoding, and instruction execution. During the instruction execution stage, processor 101 needs to read data from memory 103 and write the completed data back to memory 103. Therefore, controller 102 restricts access to physical address ranges corresponding to other exception levels by software running at the current exception level, which can be applied to the instruction fetching and instruction execution stages of processor 101. Since the reading of instructions and the reading and writing of data by the software running in processor 101 are located in different process stages, in one possible implementation of this embodiment, each of the multiple physical address ranges corresponding to each exception level can be further divided into two parts: one part is used to store instructions, and the other part is used to store data. Figure 3 The physical address range of the memory 103 shown can be further divided as follows: Figure 4The diagram illustrates the following: Physical address range 0x0000–0x1000 stores instructions at exception level EL0; physical address range 0x1001–0x2000 stores data at exception level EL0; physical address range 0x3000–0x4000 stores instructions at exception level EL1; physical address range 0x4001–0x5000 stores data at exception level EL1; physical address range 0x7000–0x8000 stores instructions at exception level EL2; physical address range 0x8001–0x9000 stores data at exception level EL2; physical address range 0x1100–0x1200 stores instructions at exception level EL3; and physical address range 0x1201–0x1300 stores data at exception level EL3.

[0053] based on Figure 4 In one possible implementation of the physical address range of the memory 103 shown in this application embodiment, when the processor 101 provides the logical address VA2 to the controller 102, it can also send indication information I1 to the controller 102 at the same time. This indication information I1 is used to indicate whether the content to be accessed by the software currently running by the processor 101 is an instruction or data. Alternatively, the indication information I1 can be provided to the controller 102 in a separate indication information independent of the logical address VA2; this embodiment does not limit this. After receiving the logical address VA2 and indication information I1 from the processor 101, and after converting the logical address VA2 into the physical address PA2, the controller 102 can execute different detection processes depending on the content to be accessed by the currently running software. The following describes... Figure 5 For a more detailed description of the detection process shown, please refer to [link / reference]. Figure 5 , Figure 5 The detection process 500 applied to the controller 102 includes the following procedures.

[0054] Step 501: Based on the logical address VA2 and indication information I1 received from processor 101, the logical address VA2 is translated into physical address PA2. When indication information I1 indicates that the content to be accessed by the software currently running on processor 101 is an instruction, step 502 is executed; when indication information I1 indicates that the content to be accessed by the software currently running on processor 101 is data, step 505 is executed. In specific implementation, processor 101's request to access instructions typically occurs during the instruction fetching stage, while processor 101's request to access data occurs during the instruction execution stage.

[0055] Step 502: Check if physical address PA2 is within the physical address range R2. Here, physical range R2 is the physical address range used to store instructions, corresponding to the exception level of the currently running software. If physical address PA2 is detected to be within physical address range R2, proceed to step 503; if physical address PA2 is detected to be outside physical address range R2, proceed to step 504. Step 503: Allow the currently running software of processor 101 to access logical address VA2. Step 504: Perform security protection operations.

[0056] Step 505: Detect whether physical address PA2 is within the physical address range corresponding to one or more other exception levels. These one or more other exception levels include one or more exception levels other than the current exception level. If physical address PA2 is detected to be within the physical address range corresponding to one or more other exception levels, proceed to step 504; if physical address PA2 is not within the physical address range corresponding to one or more other exception levels, proceed to step 503.

[0057] In other words, for instructions, this solution uses a whitelist protection method. If PA2 falls within the physical address range R2, access is allowed. That is, physical address range R2 is whitelisted, and instructions within this range are accessible to software at the current exception level. Access is not allowed if PA2 does not fall within physical address range R2. For data, this solution uses a blacklist protection method. One or more physical address ranges corresponding to other exception levels are blacklisted. Data within these ranges is inaccessible to software at the current exception level, while data outside these ranges is accessible. Access is allowed if PA2 does not fall into one or more other exception levels; otherwise, access is not allowed if PA2 falls into any of the other exception levels.

[0058] based on Figure 5 The detection process of controller 102 shown below is illustrated using the example of the software currently running on processor 101 being at exception level EL3. Figure 4 The physical address ranges shown, corresponding to exception levels EL3, EL2, and EL1, are obtained through... Figure 6 The specific application scenarios shown provide a more detailed description of the operation of controller 102. Please continue reading. Figure 6 , Figure 6This is a schematic diagram of an application scenario illustrating the operation of controller 102. Controller 102 can obtain in advance an indication signal via electronic circuitry indicating that the software currently running on processor 101 is in exception level EL3. After receiving logical address VA3 and indication information I2 from processor 101, controller 102 executes the following steps.

[0059] Step 601: Convert logical address VA3 into physical address PA3. Based on indication information I2, if indication information I2 indicates that the content to be accessed by the software currently running in processor 101 is an instruction, execute step 602. If indication information I2 indicates that the content to be accessed by the software currently running in processor 101 is data, execute step 603.

[0060] Step 602: Determine whether physical address PA3 is within the physical address range of 0x1100 to 0x1200. If it is determined that physical address PA3 is within the physical address range of 0x1100 to 0x1200, output physical address PA3; if it is determined that physical address PA3 is not within the physical address range of 0x1100 to 0x1200, perform a security protection operation.

[0061] Step 603: Determine if physical address PA3 is within the physical address range of 0x8001 to 0x9000. If physical address PA3 is not within the range, proceed to step 604; if physical address PA3 is within the range, perform a security protection operation. Step 604: Determine if physical address PA3 is within the physical address range of 0x4001 to 0x5000. If physical address PA3 is not within the range, output physical address PA3; if physical address PA3 is within the range, perform a security protection operation.

[0062] Based on the mapping relationship between each exception level and the physical address range described in the above embodiments, the embodiments of this application can store the mapping relationship between each exception level and the physical address range in multiple ways. In a first possible implementation, the mapping relationship between the exception level and the physical address range can be stored in the memory 103. Specifically, the memory 103 can store a page table, which is dedicated to recording the mapping relationship between the exception level and the physical address range. This mapping relationship is recorded in the page table in the form of a mapping table. In this possible implementation, to prevent hackers from modifying the mapping relationship recorded in the page table, the electronic device 100 can also be provided with a controller 104. The controller 104 can be integrated into the same SOC as the processor 101 and other components, or it can be set outside the SOC. The controller 104 is used to modify the mapping relationship recorded in the page table. Specifically, the controller 104 can be a management unit used to manage and maintain the mapping relationship to avoid security risks caused by the processor 101 itself managing the mapping relationship. Even if the running software of the processor 101 is risky, its software will not modify the mapping relationship, and the judgment scheme based on the above process is still safe. The controller 104, used to maintain and manage the mapping relationship, may include a security processor or security processor subsystem, whose security level may be higher than that of the processor 101. For example, the processor 101 may not have access to at least some of the data and instructions maintained by the controller 104.

[0063] In the second possible implementation, the SOC can have multiple registers, which can be selectively located within or outside the processor 101, and can be used to store the mapping relationship between multiple exception levels and multiple physical address ranges. For example... Figure 7 As shown, Figure 7 This schematically illustrates a configuration where the electronic device 100's SOC includes eight registers, IP1 to IP8. The following example illustrates this configuration. Figure 4 The mapping relationship between the physical address ranges and exception levels in memory 103 shown is used as a reference, combined with Figure 7 The registers shown describe how multiple registers store the above mapping relationship. Based on Figure 4 The eight physical address ranges shown can be configured with eight registers IP1 to IP8, each dedicated to storing one of the physical address ranges. In practice, each register can be pre-mapped with an exception level and a data type. Then, when the electronic device boots up, the exception level and the corresponding physical address range for that data type are loaded into the corresponding register. The data type referred to here is such as... Figure 4The instructions or data described herein. For example, register IP1 can be pre-set to store the physical address range of instructions located at exception level EL0, and register IP2 can be pre-set to store the physical address range of data located at exception level EL0. Then, when electronic device 100 starts up, processor 101 can load the physical address range 0x0000 to 0x1000 into register IP1 and the physical address range 0x1001 to 0x2000 into register IP2. The settings of other registers are similar to those of registers IP1 and IP2, and will not be described again. Furthermore, after processor 101 loads the mapping relationship between physical address ranges and exception levels into the registers, it can also lock each register. After the registers are locked, the mapping relationship in the registers cannot be changed during the operation of electronic device 100. This prevents hackers from stealing important data by rewriting the mapping relationship in the registers during the operation of electronic device 100, thereby further improving the security of software operation. When the electronic device 100 is started, the mapping relationship can be loaded from the memory 103 or other memory, such as non-volatile memory, into the register.

[0064] It should be noted that in the above embodiments, when each register is locked, the TEE software at any exception level can read the mapping relationship in each register during the operation of the electronic device 100. The configuration of the registers is described below with specific examples.

[0065] In specific implementation, when the electronic device 100 starts up, firstly, the processor 101 loads the software program located at exception level EL3 into the physical address range corresponding to exception level EL3 in memory 103 by running the startup software. The processor 101 then loads the physical address range for storing instructions corresponding to exception level EL3 into register IP7 by running the software program located at EL3, and then locks register IP7; it also loads the physical address range for storing data corresponding to exception level EL3 into register IP8, and then locks register IP8. Next, the processor 101 loads the software program located at exception level EL2 into the physical address range corresponding to exception level EL2 in memory 103 by running the software program located at exception level EL3, loads the software program located at exception level EL1 into the physical address range corresponding to exception level EL1 in memory 103, loads the software program located at exception level EL0 into the physical address range corresponding to exception level EL0 in memory 103, loads the physical address range for storing data corresponding to exception level EL2 into register IP6, and then locks register IP6. Then, processor 101 switches from running the software program located at EL3 to running the software program located at EL2. By running the software program located at EL2, processor 101 checks whether the physical address range in register IP6 is correct, that is, whether it completely covers the physical address range of the data corresponding to exception level EL2, to prevent certain important data from being overwritten or stolen by hackers if it is not set within that physical address range. If the physical address range in register IP6 is detected to be incorrect, the processor 101 is terminated from booting. If the physical address range in register IP6 is detected to be correct, the physical address range used to store the instructions corresponding to exception level EL2 is loaded into IP5, and then IP5 is locked; the physical address range used to store the data corresponding to exception level EL1 is loaded into IP4, and then IP4 is locked. Again, processor 101 switches from running the software program located at EL2 to running the software program located at EL1. Processor 101 runs a software program located in EL1 to check if the physical address range in register IP4 is correct. If the physical address range in register IP4 is incorrect, it terminates the startup process of processor 101. If the physical address range in register IP4 is correct, it loads the physical address range used to store the instructions corresponding to exception level EL1 into IP3 and then locks IP3. It loads the physical address range used to store the data corresponding to exception level EL0 into IP2 and then locks IP2. Finally, processor 101 switches from running the software program located in EL1 to running the software program located in EL0.Processor 101 runs a software program located at EL0 to check if the physical address range in register IP2 is correct. If the physical address range in register IP2 is incorrect, it executes an operation to terminate the startup of processor 101; if the physical address range in register IP2 is correct, it loads the physical address range used to store the instruction corresponding to exception level EL0 into IP1, and then locks IP1. This completes the configuration of registers IP1 through IP8.

[0066] In this embodiment, the electronic device 100 may further include a communication unit (not shown in the figure). This communication unit includes, but is not limited to, a short-range communication unit or a cellular communication unit. The short-range communication unit interacts with other devices located outside the mobile terminal for internet access by running a short-range wireless communication protocol. This short-range wireless communication protocol may include, but is not limited to, various protocols supported by radio frequency identification (RFID) technology, Bluetooth communication technology protocols, or infrared communication protocols. The cellular communication unit accesses a wireless access network by running a cellular wireless communication protocol to enable the mobile communication unit to interact with servers on the internet that support various applications. This communication unit may be integrated into the same SOC as the processor 101 and controller 102 described in this embodiment, or it may be separately configured. Furthermore, the electronic device 100 may selectively include a bus or input / output ports (I / O). Both the bus and I / O ports may be integrated into the same SOC as the processor 101 and controller 102. It should be understood that in practical applications, the electronic device 100 may include more than... Figure 1 and Figure 7 The number of more or fewer components shown in the embodiments of this application is not limited.

[0067] Based on the same inventive concept, embodiments of this application also provide a method for secure access to software, which is applied to, for example... Figure 1 The electronic device 100 shown. Please continue reading. Figure 8This document illustrates a flowchart 800 of a method for securely accessing software provided in an embodiment of this application. The flowchart 800 of this method can be executed by a controller 102 and includes the following steps: Step 801, converting the logical address of the memory to be accessed by the currently running software into a physical address in the memory; Step 802, determining whether the physical address is within a preset physical address range corresponding to the current exception level of the current software; Step 803, when the physical address is within the preset physical address range, allowing the current software to access the logical address; wherein the electronic device has multiple exception levels, each exception level reflects a permission level, and each exception level corresponds to a physical address range, and the current exception level is one of the multiple exception levels. It is understood that the permission level and exception level in this embodiment can be understood as the same concept or similar concepts applied in different scenarios, reflecting a level restriction of security permissions. This level restriction may have other different names or appellations. If such name changes do not exceed the technical essence of permission levels, such changes should essentially be considered equivalent transformations of the embodiments of this application and do not exceed the scope of this application.

[0068] In one possible implementation, the mapping relationship between the multiple exception levels and multiple physical address ranges is stored in a storage unit; determining whether the physical address is within a preset physical address range corresponding to the current exception level of the current software includes: determining the preset physical address range corresponding to the current exception level based on the mapping relationship.

[0069] In one possible implementation, the method further includes performing a security protection operation when the physical address is not within the preset physical address range.

[0070] In one possible implementation, the method further includes: performing a security protection operation when the physical address is within one or more other physical address ranges corresponding to one or more other anomaly levels, wherein the plurality of anomaly levels includes the one or more other anomaly levels; and allowing the current software to access the logical address when the physical address is not within the preset physical address range and is not within the one or more other physical address ranges.

[0071] In one possible implementation, the security protection operation includes at least one of the following: resetting the processor in the electronic device, denying the access, instructing the processor to stop operating, disabling at least some of the functions of the processor, or preventing the processor from accessing the memory.

[0072] It is understood that, in order to achieve the above-mentioned functions, the controller 102 includes hardware and / or software modules corresponding to the execution of each function. Based on the steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in a manner that drives hardware or computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of this application.

[0073] This embodiment can divide the controller 102 into functional modules according to the above method example. For example, different functional modules can be divided for each function, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0074] When dividing each function into modules according to its corresponding function. Figure 9 This diagram illustrates one possible embodiment of the apparatus 900 described above. Further extensions of the previously mentioned apparatus are possible, for example... Figure 9 The corresponding device 900 can be a software device running on the controller 102, or the device 900 can be a combination of software and hardware, embedded in the controller 102. For example... Figure 9 As shown, the device 900 may include a conversion module 901, a determination module 902, and a first access permission module 903. The conversion module 901 is used to convert the logical address of the memory to be accessed by the currently running software into a physical address in the memory. The determination module 902 is used to determine whether the physical address is within a preset physical address range corresponding to the current exception level of the current software. The first access permission module 903 is used to allow the current software to access the logical address when the physical address is within the preset physical address range. The electronic device has multiple exception levels, each exception level reflecting a permission level, and each exception level corresponding to a physical address range. The current exception level is one of the multiple exception levels.

[0075] In one possible implementation, the mapping relationship between the multiple exception levels and multiple physical address ranges is stored in a storage unit; the determining module 902 is specifically used to: determine the preset physical address range corresponding to the current exception level according to the mapping relationship.

[0076] In one possible implementation, the device 900 further includes a first security protection module (not shown in the figure), used to perform a security protection operation when the physical address is not within the preset physical address range.

[0077] In one possible implementation, the device 900 further includes: a second security protection module (not shown in the figure), configured to perform a security protection operation when the physical address is within one or more other physical address ranges corresponding to one or more other anomaly levels, wherein the plurality of anomaly levels includes the one or more other anomaly levels; and a second access permission module (not shown in the figure), configured to allow the current software to access the logical address when the physical address is not within the preset physical address range and is not within the one or more other physical address ranges.

[0078] In one possible implementation, the security protection operation includes at least one of the following: resetting the processor in the electronic device, denying the access, instructing the processor to stop operating, disabling at least some of the functions of the processor, or preventing the processor from accessing the memory.

[0079] The apparatus 900 provided in this embodiment is used to execute a method for secure access software executed by the controller 102, and can achieve the same effect as the above-described implementation method or apparatus. Specifically, the above... Figure 9 Each module can be implemented using software, hardware, or a combination of both. For example, each module can be implemented in software to drive the controller 102. Alternatively, each module can include a corresponding processor and corresponding driver software, i.e., implemented using a combination of software and hardware.

[0080] Exemplarily, the controller 102 may further include at least one processor and a memory. The at least one processor can invoke all or part of the computer program stored in the memory to control and manage the actions of the controller 102, for example, it can be used to support the controller 102 in executing the steps performed by the various modules described above. The memory can be used to support the controller 102 in executing stored program code and data, and the memory includes, but is not limited to, at least a portion of the storage space, cache, or registers of the memory 103 described above. The at least one processor can implement or execute various exemplary multiple logic modules described in conjunction with the disclosure of this application, which may be a combination of one or more microprocessors implementing computing functions. Furthermore, the at least one processor may also include other programmable logic devices, transistor logic devices, or discrete hardware components, etc.

[0081] This embodiment also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed on a computer, the computer performs the aforementioned method steps to implement the method for securely accessing software described in the above embodiment.

[0082] This embodiment also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the method for securely accessing software described in the above embodiment.

[0083] In this embodiment, the computer-readable storage medium or computer program product is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding method provided above, and will not be repeated here.

[0084] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0085] Furthermore, the functional units in the various embodiments of this application can be integrated into a single product, or each unit can exist physically separately, or two or more units can be integrated into a single product. Corresponding to Figure 9 If the aforementioned modules are implemented as software functional units and sold or used as independent products, they can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An electronic device, characterized in that, Includes a processor and a first controller; The processor is used to run the current software and provide the logical address of the memory to be accessed by the current software to the first controller. The first controller converts the logical address into a physical address in the memory and determines whether the physical address is within a preset physical address range corresponding to the current exception level of the current software. When the physical address is within the preset physical address range, the current software is allowed to access the logical address; wherein, the electronic device has multiple exception levels, each exception level reflects a permission level, and each exception level corresponds to a physical address range, and the current exception level is one of the multiple exception levels.

2. The electronic device according to claim 1, characterized in that, The first controller is specifically configured to: provide the physical address to the processor when the current software is allowed to access the logical address; The processor is also configured to: continue running the current software to access the physical address.

3. The electronic device according to claim 1 or 2, characterized in that, The electronic device further includes: a storage unit for storing the mapping relationship between the plurality of exception levels and the plurality of physical address ranges; The first controller is specifically configured to determine the preset physical address range corresponding to the current anomaly level based on the mapping relationship.

4. The electronic device according to claim 3, characterized in that, The storage unit includes multiple registers; The processor is further configured to: load the mapping relationship into the plurality of registers when the electronic device is started; and lock the plurality of registers after the loading is completed.

5. The electronic device according to claim 4, characterized in that, The processor is also used for: During the loading process, it is checked whether the multiple physical address ranges in the mapping relationship are correct; When at least one of the plurality of physical address ranges is detected to be incorrect, the operation of terminating the startup of the processor is performed.

6. The electronic device according to any one of claims 3-5, characterized in that, The storage unit includes the memory; The electronic device further includes a second controller for modifying the mapping relationship in the memory.

7. The electronic device according to any one of claims 1-6, characterized in that, The first controller is also configured to: perform a security protection operation when the physical address is not within the preset physical address range.

8. The electronic device according to any one of claims 1-6, characterized in that, The first controller is further configured to: perform a security protection operation when the physical address is within one or more other physical address ranges corresponding to one or more other anomaly levels, wherein the plurality of anomaly levels includes the one or more other anomaly levels; When the physical address is not within the preset physical address range and is not within the range of one or more other physical addresses, the current software is allowed to access the logical address.

9. The electronic device according to claim 7 or 8, characterized in that, The security protection operation includes at least one of the following: resetting the processor, denying the access, instructing the processor to stop running, disabling at least some functions of the processor, or preventing the processor from accessing the memory.

10. A method for secure access software applied to an electronic device, characterized in that, include: The logical address of the memory that the current software wants to access is converted into a physical address in the memory. Determine whether the physical address is within a preset physical address range corresponding to the current exception level of the current software; When the physical address is within the preset physical address range, the current software is allowed to access the logical address; The electronic device has multiple anomaly levels, each of which reflects a permission level and corresponds to a physical address range. The current anomaly level is one of the multiple anomaly levels.

11. The method according to claim 10, characterized in that, The mapping relationship between the multiple exception levels and multiple physical address ranges is stored in the storage unit; determining whether the physical address is within the preset physical address range corresponding to the current exception level of the current software includes: Based on the mapping relationship, the preset physical address range corresponding to the current anomaly level is determined.

12. The method according to claim 10 or 11, characterized in that, The method further includes: When the physical address is not within the preset physical address range, a security protection operation is performed.

13. The method according to any one of claims 10-12, characterized in that, The method further includes: When the physical address is within one or more other physical address ranges corresponding to one or more other anomaly levels, a security protection operation is performed, wherein the multiple anomaly levels include the one or more other anomaly levels; When the physical address is not within the preset physical address range and is not within the range of one or more other physical addresses, the current software is allowed to access the logical address.

14. The method according to claim 12 or 13, characterized in that, The security protection operation includes at least one of the following: resetting the processor in the electronic device, denying the access, instructing the processor to stop operating, disabling at least some of the functions of the processor, or preventing the processor from accessing the memory.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by the controller, is used to implement the method as described in any one of claims 10 to 14.

16. A computer program product, characterized in that, When the computer program product is executed by the controller, it is used to implement the method as described in any one of claims 10 to 14.

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