Wafer thinning system and method, electronic device, storage medium

Abstract

This application discloses a wafer thinning system and method, electronic device, and storage medium. The wafer thinning method includes: for the nth wafer in a batch of wafers to be thinned, controlling a grinding module to grind the nth wafer according to a grinding coefficient, and controlling a polishing module to polish the ground wafer once according to a pressure response coefficient, to obtain a thinned wafer. The pressure response coefficient characterizes the relationship between the desired applied pressure and the desired removal rate morphology of each polishing region; updating the pressure response coefficient of each polishing region according to the removal rate morphology corresponding to each pair of adjacent polishing regions in the nth wafer, where n is a positive integer; and continuing to grind and polish the (n+1)th wafer based on the updated pressure response coefficient until the thinning of a batch of wafers is completed. The solution of this application can effectively improve the problem of insufficient polishing accuracy during the thinning process.

Description

Technical Field

[0001] This application relates to the field of wafer fabrication technology, and more particularly to a wafer thinning system and method, electronic device, and storage medium. Background Technology

[0002] Backside thinning of wafers refers to the high-precision grinding of semiconductor materials before packaging to reduce their shape to a suitable form, thereby reducing the packaging height, chip package size, and improving the chip's thermal diffusion efficiency, electrical performance, and mechanical performance.

[0003] In related back-side thinning technologies, wafer polishing can be performed after wafer grinding to further improve the flatness of the wafer surface. Before polishing, the desired removal amount in each region of the wafer is calculated based on the post-grind wafer morphology and the set desired morphology. Then, the polishing pressure is adjusted according to the desired removal amount in each region. Therefore, the accuracy of pressure adjustment control is one of the important parameters affecting the wafer polishing process.

[0004] Current polishing processes utilize zoned pressure control. However, due to differences in the gas mold structure and material characteristics, different zones exhibit varying inter-zone coupling effects. This leads to mutual influence between different zones of the polishing head, thereby affecting the pressure control accuracy of each zone. Summary of the Invention

[0005] In view of this, embodiments of this application provide a wafer thinning scheme to improve pressure control accuracy.

[0006] According to a first aspect of the embodiments of this application, a wafer thinning system is provided, comprising a front-end module, a grinding module, a polishing module, and a controller; the front-end module is used to move wafers in or out; the grinding module is used to grind the wafers; the polishing module is used to polish the ground wafers to achieve wafer thinning; the controller is used to execute the following wafer thinning method: for the nth wafer in a batch of wafers to be thinned, the grinding module is controlled to grind the nth wafer according to the grinding coefficient, and the polishing module is controlled to polish the ground wafer once according to the pressure response coefficient. Polishing yields a thinned wafer, wherein the pressure response coefficient is used to characterize the relationship between the expected applied pressure and the expected removal rate morphology of each polished region; the pressure response coefficient of each polished region is updated according to the removal rate morphology corresponding to each two adjacent polished regions in the nth wafer, wherein the pressure response coefficient is used to characterize the relationship between the expected applied pressure and the expected removal rate morphology of each polished region, and n is a positive integer; based on the updated pressure response coefficient, grinding and polishing are continued on the (n+1)th wafer until a batch of wafers to be thinned is completed.

[0007] According to a second aspect of the embodiments of this application, a wafer thinning method is provided, comprising: for the nth wafer in a batch of wafers to be thinned, controlling a grinding module to grind the nth wafer according to a grinding coefficient, and controlling a polishing module to polish the ground wafer once according to a pressure response coefficient, to obtain a thinned wafer, wherein the pressure response coefficient is used to characterize the relationship between the expected applied pressure and the expected removal rate morphology of each polishing region; updating the pressure response coefficient of each polishing region according to the removal rate morphology corresponding to each two adjacent polishing regions in the nth wafer, wherein the pressure response coefficient is used to characterize the relationship between the expected applied pressure and the expected removal rate morphology of each polishing region, and n is a positive integer; and continuing to grind and polish the (n+1)th wafer based on the updated pressure response coefficient until the thinning of a batch of wafers to be thinned is completed.

[0008] According to a third aspect of the embodiments of this application, a computer storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect.

[0009] According to a fourth aspect of the embodiments of this application, a computer program product is provided, including computer instructions that instruct a computing device to perform an operation corresponding to the method described in the first aspect.

[0010] According to the wafer thinning schemes provided in the embodiments of this application, for the same batch of wafers that need to be thinned, the coupling relationship between the regions under different pressure states is estimated based on the two expected removal rate morphologies of two adjacent polishing regions in the thinned wafer, and the pressure response coefficient is adjusted. Then, the wafer thinning is continued according to the adjusted pressure response coefficient. This can effectively improve the problem of low pressure calculation accuracy caused by the coupling effect between the regions of the polishing head during the thinning process, improve the polishing accuracy, and thus obtain a better wafer polishing morphology. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0012] Figure 1 This is a schematic diagram of a wafer thinning apparatus applicable to the wafer thinning method in the embodiments of this application.

[0013] Figure 2 For a type of application Figure 1An exemplary chemical mechanical polishing apparatus in the wafer thinning equipment shown.

[0014] Figure 3 for Figure 2 A schematic diagram of the support device used in a chemical mechanical polishing (CMP) apparatus is shown.

[0015] Figure 4 For a kind of corresponding Figure 3 A schematic diagram of the wafer.

[0016] Figure 5 This is a flowchart illustrating a wafer thinning method as an exemplary embodiment of this application.

[0017] Figure 6 This is a flowchart illustrating a wafer thinning method as another exemplary embodiment of this application.

[0018] Figure 7 This is a structural block diagram of a wafer thinning system as an exemplary embodiment of this application.

[0019] Figure 8 This is a schematic diagram of the structure of an electronic device that is an exemplary embodiment of this application. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0021] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Where there is no conflict between the embodiments, the following embodiments and features can be combined with each other. The steps in the following method embodiments are for illustrative purposes only and are not intended to limit the invention.

[0022] Backside thinning of wafers refers to the high-precision grinding of semiconductor materials before packaging to reduce their shape to a suitable form, thereby reducing the packaging height, chip package size, and improving the chip's thermal diffusion efficiency, electrical performance, and mechanical performance.

[0023] In related technologies, wafer polishing (e.g., chemical mechanical polishing) can be performed after wafer grinding to further improve the flatness of the wafer surface, reduce the total thickness variation (TTV) of the wafer, and remove the damage layer caused by the grinding process.

[0024] Chemical Mechanical Polishing (CMP) is one of the key technologies in integrated circuit manufacturing. CMP is a polishing method that combines chemical etching with mechanical polishing. Polishing pressure is a crucial parameter affecting material removal rate and uniformity. In practice, excessive polishing pressure can disrupt the uniform distribution of the polishing slurry on the material surface, leading to uneven removal rates. Conversely, insufficient polishing pressure reduces material removal rates and decreases wafer polishing efficiency.

[0025] When performing the above-mentioned wafer polishing process, the wafer is mainly pressed onto the polishing pad by the polishing head, and polishing is carried out by mechanical friction between the wafer and the polishing pad. Furthermore, since the thickness of the wafer has been ground down to close to the preset thickness, the thickness that can be polished may be less than 1nm. Not only can wafer polishing be performed only once, but the precision requirements for polishing are also extremely high, and the error tolerance of the polishing process is extremely low.

[0026] Furthermore, with the continuous increase in wafer size during polishing, zoned pressure control technology has been introduced into chemical mechanical polishing (CMP) processes to ensure the uniformity of material removal from the wafer surface. However, in related technologies, when using 5-zone or 7-zone polishing heads to perform wafer polishing operations, different regions exhibit different inter-regional coupling effects due to variations in their gaseous structures and material characteristics. This leads to mutual influence between different regions of the polishing head. If only the difference between the current wafer morphology (previous value) and the desired morphology (later value) is used as the wafer removal adjustment amount and polishing control is based on this, while ignoring the influence of inter-regional coupling effects, it will be impossible to effectively control the morphology between wafer regions during the wafer polishing process. Therefore, the accuracy of pressure adjustment control in each region of the polishing head becomes one of the most important influencing parameters, directly related to the wafer thinning accuracy. The solution proposed in this application can improve polishing accuracy and control the flatness of the thinned wafer morphology after polishing.

[0027] In view of this, the embodiments of this application provide a wafer thinning solution that can effectively improve the above-mentioned problems.

[0028] For ease of understanding, some technical terms used in this application will be explained below:

[0029] The wafer morphology referred to in the embodiments of this application refers to the variation of the height and undulation of the wafer surface. The desired removal rate morphology of the wafer is determined based on the difference between the current morphology of the wafer (or the previous value of the wafer morphology, the wafer grinding morphology) and the desired morphology (or the subsequent value of the wafer morphology, the target thinning morphology).

[0030] Furthermore, the wafer removal rate morphology refers to the removal rate of the wafer morphology per unit time. Since the removal rates at different locations on the wafer surface are different, the combined removal rates at each location form the wafer removal rate morphology.

[0031] The wafer thinning system of the wafer thinning scheme of this application embodiment will be briefly described below.

[0032] Figure 1 An embodiment of the present invention provides a wafer thinning device, including: a front-end module 1, a polishing module 2, and a grinding module 3.

[0033] Equipment front-end module 1 is used to realize the entry and exit of wafers. Equipment front-end module 1 is set at the front end of the wafer thinning equipment. Equipment front-end module 1 is a transition module that realizes the transfer of wafers from the outside to the inside of the equipment, so as to realize the "dry entry and dry exit" of wafers.

[0034] Grinding module 3 is used to grind the wafer, including rough grinding and fine grinding. Grinding module 3 is located at the end of the wafer thinning equipment.

[0035] Polishing module 2 is used to perform chemical mechanical polishing on the wafer after the grinding is completed. It also has the function of transferring the wafer between these three modules (equipment front-end module 1, grinding module 3, and polishing module 2). Polishing module 2 is located between equipment front-end module 1 and grinding module 3. Figure 1 As shown, polishing module 2 includes chemical mechanical polishing equipment 4.

[0036] Understandable, Figure 1 The thinning device shown is merely an example. In other implementations, the grinding module 3 may include multiple grinding passes, such as 3, 4, or 5 passes. Any such variations that achieve wafer thinning by grinding should fall within the scope of this application.

[0037] Figure 2 An exemplary chemical mechanical polishing (CMP) apparatus 100 applied to the aforementioned wafer thinning equipment is shown. As shown, the CMP apparatus 100 mainly includes a support device 102 for holding a wafer 200, a polishing disk 104 covered with a polishing pad 106, and a supply device 108 for providing polishing slurry. During wafer polishing, the support device 102 can press the wafer 200 onto the polishing pad 106 and drive the wafer 200 to rotate (refer to indicator arrow F1) and move horizontally (refer to indicator arrow F2) relative to the polishing disk 106, while the polishing disk 106 also rotates simultaneously (refer to indicator arrow F3). Under the chemical action of the polishing slurry, the relative movement between the support device 102 and the polishing disk 104 causes the polishing pad 106 to rub against the surface of the wafer 200, thus polishing the wafer 200.

[0038] refer to Figure 3 Below the support device 102 is a flexible membrane 110 for applying pressure to the wafer 200 and a retaining ring 112 for positioning the wafer 200 below the flexible membrane 110. The support device 102 has multiple concentrically arranged pressure chambers, each corresponding to a polishing area of ​​the wafer 200. The support device is typically a 5-zone or 7-zone polishing head.

[0039] For example, in Figure 3 and Figure 4 In the example shown, the carrier device 102 includes pressure chamber 1, pressure chamber 2, and pressure chamber 3 arranged sequentially from the center to the outer edge. The surface of the wafer 200 is divided into polishing area 1 corresponding to pressure chamber 1, polishing area 2 corresponding to pressure chamber 2, and polishing area 3 corresponding to pressure chamber 3. Each pressure chamber of the carrier device 102 can apply different pressures to the corresponding polishing area.

[0040] Based on the above wafer thinning system, this application provides a wafer thinning method for precisely controlling the applied pressure in each pressure chamber of the support device 102 during the thinning process. The following will provide a detailed description through several embodiments.

[0041] Figure 5 The processing flow of a wafer thinning method according to an exemplary embodiment of this application is shown. For example... Figure 5 As shown, the method 500 in this embodiment mainly includes:

[0042] Step S502: For the nth wafer in a batch of wafers to be thinned, the grinding module is controlled to grind the nth wafer according to the grinding coefficient, and the polishing module is controlled to polish the ground wafer once according to the pressure response coefficient to obtain the thinned wafer.

[0043] A batch of wafers to be thinned can be one or more boxes of wafers, with the wafers having basically the same morphology and the same desired morphology for thinning.

[0044] The grinding coefficient is used to characterize the relationship between the grinding force of the grinding wheel and the grinding morphology.

[0045] The pressure response coefficient is used to characterize the relationship between the desired applied pressure and the desired removal rate morphology for each polished region.

[0046] In this embodiment, it should be noted that the number of polishing areas is determined based on the type of polishing head used to perform the polishing operation. For example, when using a 5-zone polishing head to perform wafer polishing, the wafer is divided into 5 polishing areas; when using a 7-zone polishing head, the wafer is divided into 7 polishing areas. The polishing head remains the same, and the number of polishing areas on the wafer being polished remains the same.

[0047] In this embodiment, each polishing area of ​​the wafer includes a circular polishing area and multiple annular polishing areas. The circular polishing area is located at the center of the wafer, and the multiple annular polishing areas are multiple concentric rings distributed radially along the wafer. Any two adjacent polishing areas in each polishing area are connected to each other.

[0048] For example, in Figure 4 In the example shown, wafer 200 includes three polishing regions. Polishing region 1 is a circular polishing region, and polishing regions 2 and 3 are both annular polishing regions. Polishing region 1 is located at the center of wafer 200, and polishing regions 2 and 3 are concentric rings distributed sequentially along the radial direction of wafer 200. Polishing region 1 and polishing region 2 are adjacent to each other, and polishing regions 2 and 3 are adjacent to each other.

[0049] In this embodiment, the pressure response coefficient can characterize the relationship between the desired applied pressure and the desired removal rate morphology of each polished region of wafer 200.

[0050] In some embodiments, the desired removal rate morphology of each polished region of the wafer can be obtained based on the current morphology, desired morphology, and polishing time of each polished region of the wafer. The current morphology is the morphology after wafer grinding, and the desired morphology is the morphology after desired thinning.

[0051] In some embodiments, the current morphology of each polished region of the wafer can be obtained by measurement using a measuring tool. The desired morphology can be determined by preset settings or by calculation. The polishing time can be determined by preset settings or by calculating the difference between the current morphology and the desired morphology.

[0052] In this embodiment, the actual morphology of the wafer refers to the wafer morphology value actually measured after the wafer has completed the polishing process (or after the wafer has completed the thinning process).

[0053] In some embodiments, the pressure response coefficient may be a pressure response coefficient matrix.

[0054] During testing and experimentation, the inventors discovered that the ratio of the pressure adjustment value to the change in the desired removal rate morphology follows a certain pattern and can accurately characterize the coupling between multiple polishing regions. Therefore, in some embodiments, the pressure adjustment value for each polishing region of the wafer can be obtained based on the pressure response coefficient of each polishing region and the change in the desired removal rate morphology, and the wafer can be polished according to the pressure adjustment value of each polishing region. The change in the desired removal rate morphology is the change in the desired removal rate morphology of the nth wafer relative to the actual removal rate morphology of the (n-1)th wafer.

[0055] Specifically, the pressure adjustment value for each polishing region of the wafer can be obtained using the following formula 1, based on the pressure response coefficient of each polishing region and the change value of the desired removal rate morphology.

[0056] ΔP i =ΔRR i / K i (Formula 1)

[0057] Wherein, ΔP i ΔRR represents the pressure adjustment value for the i-th polishing region. i K represents the change in the expected removal rate morphology of the i-th polished region relative to the expected removal rate morphology of the previous wafer. i This represents the pressure response coefficient of the i-th polishing region.

[0058] In this embodiment, the pressure adjustment value refers to the pressure adjustment value of the currently processed wafer relative to the previous processed wafer when processing multiple wafers continuously. The obtained value is the relative pressure control value of the currently processed wafer.

[0059] For example, pressure chambers 1, 2, and 3 in the carrier device 102 can be controlled to apply corresponding pressures to polishing areas 1, 2, and 3 of the wafer, respectively, according to the recommended pressure values ​​for each polishing area of ​​the wafer, so as to perform the wafer polishing operation.

[0060] Step S504: Update the pressure response coefficient of each polishing region according to the removal rate morphology corresponding to each pair of adjacent polishing regions in the nth wafer, where n is a positive integer.

[0061] For example, when the polishing operation of the second wafer has been completed, the pressure response coefficient of each polishing region can be updated according to the removal rate morphology corresponding to each pair of adjacent polishing regions in the second wafer.

[0062] Specifically, a fitting operation can be performed based on the ratio of the change in removal rate morphology of each pair of adjacent polishing regions in the nth wafer to the pressure adjustment value, to obtain the polishing weight, center position, and influence area of ​​each polishing region.

[0063] In this embodiment, the polishing weight characterizes the polishing influence of each polishing region, and the influence region is the width of each polishing region determined based on the wafer radius value.

[0064] In some embodiments, any one of the polishing regions can be defined as the target region, and a polishing region in each polishing region that is adjacent to the outer periphery of the target region can be defined as the reference region of the target region. A fitting operation is performed based on the ratio of the change value of the removal rate morphology of the target region and the reference region to the pressure adjustment value to obtain the polishing weight, center position, and influence area of ​​the target region. Then, based on the polishing weight, center position, and influence area of ​​each polishing region, the pressure response coefficient of each polishing region is obtained.

[0065] For example, when polishing region 1 is defined as the target region, polishing region 2, which is adjacent to the outer periphery of polishing region 1, is the reference region of polishing region 1. A fitting operation can be performed based on the ratio of the change value of the expected removal rate morphology of polishing regions 1 and 2 to the pressure adjustment value to obtain the polishing weight, center position, and influence region of polishing region 1. Similarly, when polishing region 2 is defined as the target region, polishing region 3, which is adjacent to the outer periphery of polishing region 2, is the reference region of polishing region 2. A fitting operation can be performed based on the ratio of the change value of the expected removal rate morphology of polishing regions 2 and 3 to the pressure adjustment value to obtain the polishing weight, center position, and influence region of polishing region 2.

[0066] In some embodiments, a given neighboring region removal rate morphology estimation function can be used to perform least squares fitting based on the expected value of the target region, the ratio of the change value of the removal rate morphology of the reference region to the pressure adjustment value, to obtain the polishing weight, center position, and influence area of ​​the target region.

[0067] In this embodiment, the adjacent region removal rate topography estimation function is expressed as the following formula 2:

[0068]

[0069] In Formula 2 above, x represents the wafer radius, and f (x) a represents the ratio of the change in removal rate morphology of the polished area corresponding to radius x to the pressure adjustment value. i b represents the polishing weight of the i-th target region. i c represents the center position of the i-th target region. iLet x represent the area of ​​influence of the i-th target region. i Let a represent the radius value of the i-th target region. ir b represents the polishing weight of the reference region for the i-th target region. ir c represents the center position of the reference region for the i-th target region. ir The influence area of ​​the reference area for the i-th target region, x ir Let represent the radius of the reference region for the i-th target region; e is a natural constant.

[0070] In some embodiments, the value of x ranges from 0 to 150 millimeters.

[0071] In some embodiments, e = 2.71828.

[0072] In some embodiments, the polishing weight, center position, and affected area of ​​the target area can be substituted into a given formula for calculating the pressure response coefficient matrix to obtain the pressure response coefficient matrix of the target area.

[0073] In this embodiment, the formula for calculating the pressure response coefficient matrix is ​​expressed as Formula 3 below:

[0074]

[0075] In formula 3 above, K i This represents the pressure response coefficient matrix of the i-th target region.

[0076] Step S506: Based on the updated pressure response coefficient, continue grinding and polishing the (n+1)th wafer until a batch of wafers to be thinned is completed.

[0077] In this embodiment, based on the updated pressure response coefficient, the execution step S502 is returned to perform grinding on the (n+1)th wafer, and the ground wafer is polished according to the updated pressure response coefficient to obtain the thinned (n+1)th wafer, until the thinning of this batch of wafers is completed.

[0078] In summary, the wafer thinning method of this embodiment, for the same batch of wafers that need to be thinned, estimates the coupling relationship between the regions of the wafer under different pressure conditions based on the two desired removal rate morphologies of two adjacent polishing regions in the thinned wafer, and adjusts the pressure response coefficient. Then, based on the adjusted pressure response coefficient, the subsequent wafer thinning is continued. This can effectively improve the problem of low accuracy in pressure calculation caused by the coupling effect between the regions of the polishing head during the thinning process, thereby obtaining a better wafer polishing morphology.

[0079] Figure 6The processing flow of a wafer thinning method according to another exemplary embodiment of this application is shown. This embodiment illustrates a specific implementation scheme for further adjusting the grinding coefficient.

[0080] As shown in the figure, the method 600 of this embodiment mainly includes the following steps:

[0081] Step S602: For the nth wafer in a batch of wafers to be thinned, the grinding module is controlled to grind the nth wafer according to the grinding coefficient, and the polishing module is controlled to polish the ground wafer once according to the pressure response coefficient to obtain the thinned wafer.

[0082] The grinding coefficient is used to characterize the relationship between the grinding force of the grinding wheel and the grinding morphology.

[0083] The pressure response coefficient is used to characterize the relationship between the desired applied pressure and the desired removal rate morphology for each polished region.

[0084] The specific implementation scheme of this step can be referred to step S502 in the above embodiment, and will not be repeated here.

[0085] It should be noted that the grinding wheel of the grinding module performs axial infeed grinding on the wafer under the drive of the spindle. After grinding, the morphology of the wafer changes with the radius. Therefore, the grinding coefficient can be used to characterize the relationship between the grinding force and the change in the wafer grinding morphology. The grinding coefficient can be an array that changes with the radius.

[0086] Based on the grinding coefficient and the desired grinding morphology, the grinding force corresponding to different radii can be adjusted, and the grinding module can grind the wafer according to the adjusted grinding force.

[0087] Step S604: Update the pressure response coefficient of each polishing region according to the removal rate morphology corresponding to each pair of adjacent polishing regions in the nth wafer, where n is a positive integer.

[0088] The specific implementation scheme of this step can be referred to step S504 in the above embodiment, and will not be repeated here.

[0089] Step S606: Update the grinding coefficient based on the thinning error of the nth wafer.

[0090] In some embodiments, the thinning error is the difference between the actual morphology of the thinned wafer and the desired morphology.

[0091] In some embodiments, the grinding coefficient can be updated based on the thinning error of the nth wafer and the morphology of the nth wafer after grinding, with the minimum removal rate morphology change value and the shortest thinning time corresponding to the polishing process as constraints.

[0092] The removal rate morphology of the nth wafer can be calculated based on the morphology after grinding and thinning, and the removal rate morphology change value can be obtained accordingly.

[0093] The time required for grinding and polishing processes can be calculated by combining the grinding coefficient and pressure response coefficient with the corresponding grinding and polishing formulas. Then, the wafer transport time during the thinning process can be added to obtain the thinning time. Alternatively, since the wafer transport time is fixed, the time required for grinding and polishing processes can be used as the thinning time.

[0094] The constraints are the minimum removal rate morphology change value and the shortest thinning time corresponding to the polishing process. Specifically, the removal rate morphology change value and the thinning time corresponding to the polishing process can be calculated separately, and then normalized and weighted summed. The minimum weighted sum value is used as the constraint.

[0095] In some embodiments, the controller may be configured with a grinding control model and a polishing control model. The grinding control model includes the grinding coefficient, and the polishing control model includes the pressure response coefficient. The method further includes: performing end-to-end training on the grinding control model and the polishing control model based on the thinning error of the nth wafer and the morphology of the nth wafer after grinding, with the minimum removal rate morphology change value and the shortest thinning time corresponding to the polishing process as constraints, to update the grinding coefficient and the pressure response coefficient.

[0096] Specifically, when thinning the first few wafers (e.g., the first 5 wafers) of a batch, the pressure response coefficient can be adjusted in step S604. Then, when thinning subsequent wafers, the grinding control model and the polishing control model are trained end-to-end to update the grinding coefficient and the pressure response coefficient, and the pressure response coefficient is fine-tuned at this time. Thus, at the beginning of thinning a batch of wafers, the wafer thinning accuracy can be ensured by adjusting the pressure response coefficient. After the pressure response coefficient reaches a certain accuracy, the grinding coefficient and pressure response coefficient are jointly adjusted through end-to-end training. This ensures accuracy while minimizing the change in wafer removal rate morphology, reducing polishing errors caused by variations, further guaranteeing thinning accuracy, and minimizing thinning time to improve thinning efficiency.

[0097] Step S608: Based on the updated grinding coefficient and pressure response coefficient, continue grinding and polishing the (n+1)th wafer until a batch of wafers to be thinned is completed.

[0098] The solution in this embodiment can adjust the grinding process while ensuring accuracy, so that the change in wafer removal rate morphology is minimized, thereby reducing polishing errors caused by the change, further ensuring thinning accuracy, and minimizing the thinning time to improve thinning efficiency.

[0099] The specific implementation and corresponding effects of each module provided in this embodiment can be found in the above embodiments, and will not be repeated here. Figure 7 A schematic diagram of the architecture of a wafer thinning system 700 according to an exemplary embodiment of this application is shown. As shown, the wafer thinning system 700 of this embodiment includes a wafer thinning device 702 and a controller 704.

[0100] Reference Figure 1 The wafer thinning equipment 702 includes: a front-end module for moving wafers in or out; a grinding module for grinding wafers; and a polishing module for polishing the ground wafers to achieve wafer thinning.

[0101] The controller 704 is communicatively connected to the wafer thinning equipment 702. The controller 704 stores control instructions. When the control instructions are executed, the controller 704 performs each step of each wafer thinning method embodiment to control the wafer thinning equipment 702 to thin the wafer.

[0102] In summary, the wafer thinning schemes provided in the embodiments of this application utilize the expected removal rate morphology of two adjacent polishing regions in the wafer and the pressure response coefficient of each polishing region to adjust the pressure control of each polishing region during the polishing process. This can effectively improve the problem of inaccurate pressure calculation caused by the inter-region coupling effect of the wafer, ensure the wafer thinning accuracy, and minimize the thinning time on this basis.

[0103] This application provides a computer storage medium storing computer program code. When the computer program code is run by a processor, the processor executes the wafer thinning method described in various embodiments of this application.

[0104] An exemplary embodiment of this application provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor. The memory stores a computer program executable by the at least one processor, which, when executed by the at least one processor, causes the electronic device to perform a wafer thinning method according to various exemplary embodiments of this application.

[0105] Please refer to Figure 8The present invention describes a structural block diagram of an electronic device 800 that can serve as a server or client of this application, which is an example of a hardware device that can be applied to various aspects of this application. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the application described and / or claimed herein.

[0106] like Figure 8 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0107] Multiple components in electronic device 800 are connected to I / O interface 805, including: input unit 806, output unit 807, storage unit 808, and communication unit 809. Input unit 806 can be any type of device capable of inputting information to electronic device 800. Input unit 806 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of electronic device. Output unit 807 can be any type of device capable of presenting information and may include, but is not limited to, a display, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 808 may include, but is not limited to, disks and optical discs. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth™ devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0108] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above. For example, in some embodiments, the wafer thinning method described above can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. In some embodiments, the computing unit 801 can be configured to perform the wafer thinning method described above by any other suitable means (e.g., by means of firmware).

[0109] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0110] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0111] As used in this application, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, device, and / or apparatus (e.g., disk, optical disk, memory, programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including machine-readable media that receive machine instructions as machine-readable signals. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0112] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0113] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or middleware components (e.g., an application server), or frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0114] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other.

[0115] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0116] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A wafer thinning system, characterized in that, Equipment front-end module, grinding module, polishing module, controller; The front-end module of the equipment is used to move wafers in or out. The grinding module is used to grind wafers; The polishing module is used to polish the ground wafer to achieve wafer thinning; The controller is used to perform the following wafer thinning methods: For the nth wafer in a batch of wafers to be thinned, the grinding module is controlled to grind the nth wafer according to the grinding coefficient, and the polishing module is controlled to polish the ground wafer once according to the pressure response coefficient to obtain the thinned wafer. The grinding coefficient is used to characterize the relationship between the grinding force of the grinding wheel and the grinding morphology, and the pressure response coefficient is used to characterize the relationship between the expected applied pressure and the expected removal rate morphology of each polishing area. Based on the removal rate morphology corresponding to each pair of adjacent polishing regions in the nth wafer, update the pressure response coefficient of each polishing region, where n is a positive integer; Based on the updated pressure response coefficient, the (n+1)th wafer continues to be ground and polished until a batch of wafers to be thinned is completed.

2. The system according to claim 1, characterized in that, If n≥2, then updating the pressure response coefficient of each polishing region based on the removal rate morphology corresponding to each pair of adjacent polishing regions in the nth wafer includes: Based on the ratio of the change in removal rate morphology of each two adjacent polishing regions in the nth wafer to the pressure adjustment value of the (n-1)th wafer, a fitting operation is performed to obtain the polishing weight, center position, and influence area of ​​each polishing region. Update the pressure response coefficient of each polishing area based on its polishing weight, center position, and area of ​​influence. The polishing weight represents the polishing influence of each polishing region, and the influence region is the width of each polishing region determined based on the wafer radius value.

3. The system according to claim 1, characterized in that, The method further includes: updating the grinding coefficient based on the thinning error of the nth wafer, and continuing to grind and polish the (n+1)th wafer based on the updated grinding coefficient and pressure response coefficient until a batch of wafers to be thinned is completed.

4. The system according to claim 3, characterized in that, The step of updating the grinding coefficient based on the thinning error of the nth wafer includes: Based on the thinning error of the nth wafer and the morphology of the nth wafer after grinding, the grinding coefficient is updated with the constraints of minimizing the morphology change value corresponding to the removal rate during the polishing process and minimizing the thinning time.

5. The system according to claim 4, characterized in that, The controller is configured with a grinding control model and a polishing control model. The grinding control model includes the grinding coefficient, and the polishing control model includes the pressure response coefficient. The method further includes: Based on the thinning error of the nth wafer and the morphology of the nth wafer after grinding, the grinding control model and the polishing control model are trained end-to-end to update the grinding coefficient and the pressure response coefficient, with the minimum removal rate morphology change value and the shortest thinning time corresponding to the polishing process as constraints.

6. A wafer thinning method, characterized in that, include: For the nth wafer in a batch of wafers to be thinned, the grinding module is controlled to grind the nth wafer according to the grinding coefficient, and the polishing module is controlled to polish the ground wafer once according to the pressure response coefficient to obtain the thinned wafer. The grinding coefficient is used to characterize the relationship between the grinding force of the grinding wheel and the grinding morphology, and the pressure response coefficient is used to characterize the relationship between the expected applied pressure and the expected removal rate morphology of each polishing area. Based on the removal rate morphology corresponding to each pair of adjacent polishing regions in the nth wafer, update the pressure response coefficient of each polishing region, where n is a positive integer; Based on the updated pressure response coefficient, the (n+1)th wafer continues to be ground and polished until a batch of wafers to be thinned is completed.

7. The method according to claim 6, characterized in that, If n≥2, then updating the pressure response coefficient of each polishing region based on the removal rate morphology corresponding to each pair of adjacent polishing regions in the nth wafer includes: Based on the ratio of the change in removal rate morphology of each two adjacent polishing regions in the nth wafer to the pressure adjustment value of the (n-1)th wafer, a fitting operation is performed to obtain the polishing weight, center position, and influence area of ​​each polishing region. Update the pressure response coefficient of each polishing area based on its polishing weight, center position, and area of ​​influence. The polishing weight represents the polishing influence of each polishing region, and the influence region is the width of each polishing region determined based on the wafer radius value.

8. The method according to claim 6, characterized in that, The method further includes: updating the grinding coefficient based on the thinning error of the nth wafer, and continuing to grind and polish the (n+1)th wafer based on the updated grinding coefficient and pressure response coefficient until a batch of wafers to be thinned is completed.

9. The method according to claim 8, characterized in that, The step of updating the grinding coefficient based on the thinning error of the nth wafer includes: Based on the thinning error of the nth wafer and the morphology of the nth wafer after grinding, the grinding coefficient is updated with the constraints of minimizing the morphology change value corresponding to the removal rate during the polishing process and minimizing the thinning time.

10. The method according to claim 9, characterized in that, The step of updating the grinding coefficient based on the thinning error of the nth wafer and the morphology of the nth wafer after grinding, with the constraints of minimizing the morphology change value corresponding to the removal rate during the polishing process and minimizing the thinning time, includes: Based on the thinning error of the nth wafer and the morphology of the nth wafer after grinding, the grinding control model and the polishing control model are trained end-to-end to update the grinding coefficient and the pressure response coefficient, with the minimum removal rate morphology change value and the shortest thinning time corresponding to the polishing process as constraints.

11. An electronic device, comprising: The processor, the communication interface, the memory, and the bus are connected, and the processor, the communication interface, and the memory communicate with each other via the bus. The memory is used to store at least one executable instruction that causes the processor to perform an operation corresponding to the method as described in any one of claims 6 to 10.

12. A computer-readable storage medium storing computer instructions that, when executed by a processor, cause the processor to perform the method of any one of claims 6 to 10.

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