A low dropout linear regulator based on double adjustment tube and double loop

Abstract

The application provides a low-dropout linear voltage regulator based on double adjustment tubes and double loops, which comprises a main loop and an auxiliary loop; the main loop comprises a first amplification unit, a second amplification unit and a third amplification unit; the first amplification unit is used for performing at least one stage of amplification processing on a feedback signal of an output signal and a reference voltage division signal to obtain a first processing signal; the second amplification unit is used for processing the first processing signal under the action of a first control signal which changes with a load current to obtain a second processing signal; the third amplification unit is connected to the output end of the first amplification unit and is used for processing the first processing signal to obtain a third processing signal; the control end of a main adjustment tube is connected to the output end of the main loop; and the control end of a secondary adjustment tube is connected to the output end of the auxiliary loop; beneficial effects are as follows: the main adjustment tube and the secondary adjustment tube and their control loops respectively cope with the demand of the voltage stabilization output under different load conditions; and a dynamic biasing mechanism is introduced at the same time, so that the circuit can still maintain good large-signal response capability under low static power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a low-dropout linear regulator based on double adjustment tubes and double loops. BACKGROUND

[0002] With the continuous progress of technology, as a new generation of integrated circuit voltage regulator, the low-dropout linear regulator (LDO) has become an indispensable part of the power system. Compared with the traditional three-terminal voltage regulator, the LDO has the characteristics of a very low self-consumption micro system on a chip (SOC), can be used for current main channel control, and integrates hardware circuits such as MOSFETs with extremely low on-resistance, Schottky diodes, sampling resistors, and dividing resistors, and also has functions such as overcurrent protection, overtemperature protection, precision reference source, differential amplifier, and delay.

[0003] With the rapid development of integrated circuits and the trend of the integration of computer, communication, and multimedia technologies, more and more functions are integrated into chips. Mobile communication devices have higher requirements for the large load current, transient response, and low power consumption of the power system, so the large load current, transient response, and low power consumption LDO have become a research hotspot.

[0004] The existing LDO usually provides a load current by a single adjustment tube. Due to the characteristics of the single adjustment tube structure, even in the absence of a load current, the adjustment tube still needs a certain static current to maintain its normal work, which leads to an increase in static power consumption, thereby reducing the energy efficiency of the entire system; at the same time, when the load current suddenly changes, the adjustment tube needs a certain time to adjust the output voltage, thereby causing a delay and instability in the transient response; in addition, when the load current exceeds the capacity of the adjustment tube, the LDO may not work normally or the output voltage may drop, thereby affecting the performance of the entire system. Therefore, the traditional single adjustment tube structure has a difficult-to-balance contradiction among static power consumption, transient response, and load capacity. SUMMARY

[0005] To solve the above technical problems, the present application provides a low-dropout linear regulator based on double adjustment tubes and double loops.

[0006] The technical problems solved by the present application can be implemented by the following technical solutions:

[0007] A low-dropout linear regulator based on double adjustment tubes and double loops, comprising:

[0008] a main loop, the main loop comprising:

[0009] a first amplification unit, configured to perform at least one stage of amplification on a feedback signal of an output signal of the low-dropout linear regulator and a reference voltage division signal to obtain a first processing signal;

[0010] a second amplification unit, connected to an output end of the first amplification unit, configured to perform amplification on the first processing signal under the action of a first control signal to obtain a second processing signal, wherein the first control signal changes with a load current;

[0011] an auxiliary loop, the auxiliary loop comprising: a third amplification unit, connected to the output end of the first amplification unit, configured to perform auxiliary amplification on the first processing signal to obtain a third processing signal;

[0012] an adjustment unit, the adjustment unit comprising:

[0013] a main adjustment tube, a control end of the main adjustment tube being connected to an output end of the main loop, configured to provide the load current under the action of the second processing signal;

[0014] a secondary adjustment tube, a control end of the secondary adjustment tube being connected to an output end of the auxiliary loop, configured to provide the load current under the action of the third processing signal.

[0015] Preferably, the first amplification unit comprises a two-stage amplification subunit, the two-stage amplification subunit comprising:

[0016] a first-stage amplification circuit, configured to perform first-stage amplification on the feedback signal of the output signal and the reference voltage division signal to clamp the output signal to obtain a first-stage amplification signal;

[0017] a second-stage amplification circuit, connected to the first-stage amplification circuit, configured to perform second-stage amplification on the first-stage amplification signal to obtain the first processing signal.

[0018] Preferably, the first-stage amplification circuit adopts a folded operational amplifier circuit, the folded operational amplifier circuit comprising:

[0019] a first NMOS tube and a second NMOS tube, a gate of the first NMOS tube and a gate of the second NMOS tube being connected to a first bias voltage respectively, a drain of the first NMOS tube being connected to a first bias current, a drain of the second NMOS tube being connected to a second bias current and outputting the first-stage amplification signal;

[0020] a third NMOS tube, a gate of the third NMOS tube being connected to the drain of the first NMOS tube, a drain of the third NMOS tube being connected to a source of the first NMOS tube through a first resistor, and a source of the third NMOS tube being grounded.

[0021] a fourth NMOS transistor, a gate of the fourth NMOS transistor being connected to a gate of the third NMOS transistor, a drain of the fourth NMOS transistor being connected to a source of the second NMOS transistor through a second resistor, and a source of the fourth NMOS transistor being grounded;

[0022] a first PMOS transistor and a second PMOS transistor, a gate of the first PMOS transistor being connected to a feedback signal of the output signal, a gate of the second PMOS transistor being connected to the reference voltage signal, sources of the first PMOS transistor and the second PMOS transistor being connected to a third bias current, a drain of the first PMOS transistor being connected to a source of the first NMOS transistor, and a drain of the second PMOS transistor being connected to a source of the second NMOS transistor;

[0023] the folded operational amplifier circuit further comprises a first bias circuit for providing the first bias current, a second bias circuit for providing the second bias current, and a third bias circuit for providing the third bias current, the first bias circuit, the second bias circuit and the third bias circuit respectively comprising:

[0024] a third PMOS transistor and a fourth PMOS transistor, a gate of the third PMOS transistor being connected to a second bias voltage, a source of the third PMOS transistor being connected to the input signal, a drain of the third PMOS transistor being connected to a source of the fourth PMOS transistor, a gate of the fourth PMOS transistor being connected to a third bias voltage, and a drain of the fourth PMOS transistor being connected to a drain of the first NMOS transistor, or a drain of the second NMOS transistor, or a source of the first PMOS transistor, for providing the first bias current, or the second bias current, or the third bias current.

[0025] Preferably, the second-stage amplification circuit comprises:

[0026] a fifth PMOS transistor, a gate of the fifth PMOS transistor being connected to the first-stage amplification signal, a source of the fifth PMOS transistor being connected to a fourth bias current, and a drain of the fifth PMOS transistor being used for outputting the first processing signal;

[0027] a fifth NMOS transistor, a gate and a drain of the fifth NMOS transistor being connected to a drain of the fifth PMOS transistor respectively, and a source of the fifth NMOS transistor being grounded;

[0028] the second-stage amplification circuit further comprises a sixth PMOS transistor, a gate of the sixth PMOS transistor being connected to a fourth bias voltage, a source of the sixth PMOS transistor being connected to the input signal, and a drain of the sixth PMOS transistor being used for providing the fourth bias current.

[0029] Preferably, the second amplification unit comprises:

[0030] a sixth NMOS transistor, a gate of the sixth NMOS transistor being connected to the first processing signal through a third resistor and grounded through a first capacitor, a source of the sixth NMOS transistor being grounded;

[0031] a seventh NMOS transistor, a gate of the seventh NMOS transistor being connected to the first processing signal, a source of the seventh NMOS transistor being grounded;

[0032] an eighth NMOS transistor, a gate of the eighth NMOS transistor being connected to the first control signal, a source of the eighth NMOS transistor being connected to a drain of the sixth NMOS transistor and a drain of the seventh NMOS transistor respectively, a drain of the eighth NMOS transistor being connected to a control end of the main adjusting tube;

[0033] the second amplification unit further comprises a ninth NMOS transistor, a gate of the ninth NMOS transistor being connected to a second control signal opposite to the first control signal, a drain of the ninth NMOS transistor being connected to the input signal, a source of the ninth NMOS transistor being connected to the control end of the main adjusting tube;

[0034] an input end of the main adjusting tube being connected to the input signal, an output end of the main adjusting tube being connected to the output signal.

[0035] Preferably, the third amplification unit comprises:

[0036] a tenth NMOS transistor, a gate of the tenth NMOS transistor being connected to the first processing signal, a source of the tenth NMOS transistor being grounded, a drain of the tenth NMOS transistor being connected to a control end of the secondary adjusting tube;

[0037] an input end of the secondary adjusting tube being connected to the input signal, an output end of the secondary adjusting tube being connected to the output signal.

[0038] Preferably, the third amplification unit further comprises:

[0039] an eleventh NMOS transistor, a gate of the eleventh NMOS transistor being connected to a fifth bias voltage, a source of the eleventh NMOS transistor being connected to the control end of the secondary adjusting tube, a drain of the tenth NMOS transistor being connected to the input signal;

[0040] the fifth bias voltage is provided by a fifth bias circuit, the fifth bias circuit comprising:

[0041] a seventh PMOS transistor, the gate and the drain of the seventh PMOS transistor are connected to the gate of the eleventh NMOS transistor respectively, the drain of the seventh PMOS transistor is connected to the input signal through a fourth resistor and a fifth resistor in an on-off manner.

[0042] Preferably, further comprising:

[0043] a first logic control unit, which is controllably connected between the input terminal of the first amplification unit and the ground terminal under the action of an inverted signal of an enable signal;

[0044] a second logic control unit, which is controllably connected between the input signal and one end of a sixth resistor under the action of the inverted signal of the enable signal, the other end of the sixth resistor being connected to the control terminal of the main adjustment tube;

[0045] a third logic control unit, which is controllably connected between the input signal and one end of a seventh resistor under the action of the inverted signal of the enable signal, the other end of the seventh resistor being connected to the control terminal of the secondary adjustment tube;

[0046] a fourth logic control unit, which is controllably connected between the input signal and the connection point of the fourth resistor and the fifth resistor under the action of the inverted signal of the enable signal;

[0047] a fifth logic control unit, which is controllably connected between the input signal and the control terminal of the main adjustment tube under the action of a first protection control signal;

[0048] a sixth logic control unit, which is controllably connected between the input signal and the control terminal of the secondary adjustment tube under the action of the first protection control signal;

[0049] a seventh logic control unit, which is controllably connected between the input signal and the fifth resistor under the action of the first protection control signal;

[0050] an eighth logic control unit, which is controllably connected between the first processing signal and the ground terminal under the action of an inverted signal of the first protection control signal;

[0051] a ninth logic control unit, which is controllably connected between the zero frequency compensation signal of the first processing signal and the ground terminal under the action of the inverted signal of the first protection control signal.

[0052] Preferably, further comprising:

[0053] a first zero frequency compensation unit, which is connected between the input signal and the input terminal of the second amplification unit;

[0054] A Miller compensation unit is connected between the second output end of the first-stage amplification circuit and the output signal, and is used for Miller compensation of a negative signal of the first processing signal.

[0055] Preferably, the size of the secondary adjustment tube is smaller than the size of the primary adjustment tube.

[0056] The advantages or beneficial effects of the technical scheme of the present application are as follows:

[0057] The present application is composed of a primary adjustment tube, a secondary adjustment tube and their control loops, and the primary adjustment tube and the secondary adjustment tube are respectively responsible for heavy-load and light-load or no-load voltage stabilization output, so that the voltage stabilization output demand under different load conditions can be more effectively met; a dynamic bias mechanism is introduced while improving the voltage stabilization output capacity, so that the circuit can still maintain good large-signal response capability under low static power consumption, and the balance between static power consumption and transient response is considered, and the contradiction between static power consumption, transient response and load capacity in the traditional single adjustment tube structure is overcome. BRIEF DESCRIPTION OF DRAWINGS

[0058] Figure 1 For the preferred embodiment of the present application, a structure block diagram of a low-dropout linear voltage regulator based on double adjustment tubes and double loops is shown in the figure;

[0059] Figure 2 For the preferred embodiment of the present application, a structure block diagram of a low-dropout linear voltage regulator based on double adjustment tubes and double loops is shown in the figure;

[0060] Figure 3 For the preferred embodiment of the present application, a structure block diagram of a low-dropout linear voltage regulator based on double adjustment tubes and double loops is shown in the figure;

[0061] Figure 4 For the preferred embodiment of the present application, a structure block diagram of a low-dropout linear voltage regulator based on double adjustment tubes and double loops is shown in the figure;

[0062] Figure 5 For the preferred embodiment of the present application, a structure block diagram of a low-dropout linear voltage regulator based on double adjustment tubes and double loops is shown in the figure;

[0063] Figure 6 For the preferred embodiment of the present application, an application schematic diagram of a low-dropout linear voltage regulator is shown in the figure. DETAILED DESCRIPTION

[0064] In a power management system, a low-dropout linear voltage regulator (LDO) is used to adjust the voltage of an input signal to a lower voltage of an output signal. Static power consumption, transient response and load capacity are important indicators for evaluating the performance of the LDO.

[0065] Quiescent Current: Quiescent current is the power consumption of an LDO when there is no load. Even without a load, an LDO needs some current to maintain the normal operation of the internal circuit. Lower quiescent current means better energy efficiency of the LDO in light load or standby mode.

[0066] Transient Response: Transient response refers to the adjustment speed and stability of the output voltage of an LDO when the load changes suddenly. In some applications, the load may change suddenly, and the LDO needs to be able to adjust quickly to maintain stable output voltage. A good transient response LDO can adapt faster when the load changes, reducing the fluctuation of the output voltage.

[0067] Load Regulation: Load regulation represents the adaptability of an LDO to load changes. It measures the stability of the LDO output voltage when the load changes. Good load regulation means that the LDO can maintain a relatively stable output voltage under different load conditions.

[0068] These performance indicators are critical for different application scenarios, and the specific requirements depend on the design needs of the power management system.

[0069] With the high requirements of large load current, transient response, and low power consumption of the power system. The traditional single adjustment tube structure has a difficult balance between static power consumption, transient response, and load capacity, and cannot meet the needs of modern power management systems.

[0070] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0071] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0072] The present application will be further described below in combination with the drawings and specific embodiments, but not as a limitation of the present application.

[0073] Referring to Figure 1 , in the preferred embodiments of the present application, based on the above-mentioned problems existing in the prior art, a low-dropout linear regulator based on double adjustment tubes and double loops is provided, comprising:

[0074] A main loop 1, the main loop 1 comprises:

[0075] The first amplification unit 11 is configured to amplify at least one level the feedback signal VFB of the output signal of the low dropout regulator (LDO) and a reference voltage division signal VP55 to obtain a first processing signal Vp1.

[0076] The second amplification unit 12 is connected to the output end of the first amplification unit 11 and configured to amplify the first processing signal Vp1 under the action of a first control signal control1 to obtain a second processing signal, wherein the first control signal control1 varies with the load current.

[0077] The auxiliary loop 2 includes a third amplification unit 21 connected to the output end of the first amplification unit 11 and configured to perform auxiliary amplification on the first processing signal Vp1 to obtain a third processing signal.

[0078] The adjustment unit 3 includes:

[0079] The main adjustment tube 31 has a control end connected to the output end of the main loop 1 and is configured to provide the load current under the action of the second processing signal.

[0080] The secondary adjustment tube 32 has a control end connected to the output end of the auxiliary loop 2 and is configured to provide the load current under the action of the third processing signal.

[0081] Specifically, to solve the problem that the single adjustment tube structure in the prior art is difficult to balance between static power consumption, transient response and load capacity, the main adjustment tube 32 and the secondary adjustment tube 32 and their control loops are constructed in the embodiment, and the main adjustment tube 32 and the secondary adjustment tube 32 are respectively responsible for heavy load and light load or no load voltage regulation output, which can more effectively cope with the voltage regulation output demand under different load conditions; while improving the voltage regulation output capacity, the above-mentioned first control signal control1 introduces a dynamic biasing mechanism and an output end fast discharge circuit, so that the circuit can still obtain good large signal response capability under low static power consumption, can more quickly adapt to load changes, improves the overall stability and reliability, balances the static power consumption and the transient response, and overcomes the contradiction between the static power consumption, the transient response and the load capacity of the traditional single adjustment tube structure.

[0082] As a preferred embodiment, the first amplification unit 11 includes at least one amplification subunit configured to amplify at least one level the feedback signal VFB of the output signal of the LDO and the reference voltage division signal VP55. The number of amplification stages can be set according to actual needs, and the embodiment of the present application takes two amplification stages as an example, but this is not limited.

[0083] As a preferred embodiment, the first amplification unit 11 includes at least one amplification subunit configured to amplify at least one level the feedback signal VFB of the output signal of the LDO and the reference voltage division signal VP55. The number of amplification stages can be set according to actual needs, and the embodiment of the present application takes two amplification stages as an example, but this is not limited. Figure 2As shown, the first amplification unit 11 includes two-stage amplification sub-units, specifically including:

[0084] The first-stage amplification circuit 111 is configured to perform first-stage amplification processing on the feedback signal VFB of the output signal and the reference voltage division signal VP55, so as to clamp the output signal to obtain a first-stage amplification signal.

[0085] The second-stage amplification circuit 112 is connected to the first-stage amplification circuit 111 and is configured to perform second-stage amplification processing on the first-stage amplification signal to obtain a first processing signal Vp1.

[0086] Specifically, in the embodiment, the first-stage amplification circuit 111 uses an amplifier to input the feedback signal VFB of the output signal and the reference voltage division signal VP55 to the non-inverting input terminal and the inverting input terminal of the amplifier respectively, so that the feedback signal VFB of the output signal is amplified to obtain a first-stage amplification signal, the feedback signal VFB of the output signal is clamped to approach the reference voltage division signal VP55, and the accuracy of the output voltage is ensured.

[0087] The second-stage amplification circuit 112 makes the first-stage amplification signal pass through second-stage amplification processing to obtain a first processing signal Vp1, so as to improve the linearity of the loop when the load changes from light to heavy.

[0088] In the above scheme, the first-stage amplification circuit 111 ensures the accuracy of the output voltage, and the second-stage amplification circuit 112 improves the linearity of the loop when the load changes from light to heavy.

[0089] As a preferred implementation, wherein, as shown in Figure 3 The first-stage amplification circuit 111 adopts a folded operational amplifier circuit, and the folded operational amplifier circuit includes:

[0090] A first NMOS tube NM1 and a second NMOS tube NM2, the gate of the first NMOS tube NM1 and the gate of the second NMOS tube NM2 are connected to a first bias voltage Vb1 respectively, the drain of the first NMOS tube NM1 is connected to a first bias current, and the drain of the second NMOS tube NM2 is connected to a second bias current and outputs the first-stage amplification signal;

[0091] A third NMOS tube NM3, the gate of the third NMOS tube NM3 is connected to the drain of the first NMOS tube NM1, the drain of the third NMOS tube NM3 is connected to the source of the first NMOS tube NM1 through a first resistor R1, and the source of the third NMOS tube NM3 is grounded.

[0092] A fourth NMOS transistor NM4, a gate of the fourth NMOS transistor NM4 is connected with a gate of the third NMOS transistor NM3, a drain of the fourth NMOS transistor NM4 is connected with a source of the second NMOS transistor NM2 through a second resistor R2, a source of the fourth NMOS transistor NM4 is grounded;

[0093] A first PMOS transistor PM1 and a second PMOS transistor PM2, a gate of the first PMOS transistor PM1 is connected with a feedback signal VFB of the output signal, a gate of the second PMOS transistor PM2 is connected with a reference voltage signal VP55, sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are connected with a third bias current, a drain of the first PMOS transistor PM1 is connected with a source of the first NMOS transistor NM1, a drain of the second PMOS transistor PM2 is connected with a source of the second NMOS transistor NM2.

[0094] Specifically, in the first stage amplification circuit 111 of the embodiment, the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4, the first PMOS transistor PM1, the second PMOS transistor PM2, the first resistor R1 and the second resistor R2 constitute a folded operational amplifier as the first stage amplification circuit 111 of the main loop 1, and the feedback signal VFB of the output signal is clamped by the first PMOS transistor PM1 and the second PMOS transistor PM2 to approach the reference voltage signal VP55, so as to ensure the precision of the output voltage.

[0095] As a preferred embodiment, wherein, as shown in Figure 3 the folded operational amplifier circuit further comprises: a first bias circuit 41 for providing a first bias current, a second bias circuit 42 for providing a second bias current, and a third bias circuit 43 for providing a third bias current, the first bias circuit 41, the second bias circuit 42 and the third bias circuit 43 respectively comprise:

[0096] A third PMOS transistor and a fourth PMOS transistor, a gate of the third PMOS transistor is connected with a second bias voltage Vb2, a source of the third PMOS transistor is connected with the input signal V IN , a drain of the third PMOS transistor is connected with a source of the fourth PMOS transistor, a gate of the fourth PMOS transistor is connected with a third bias voltage Vb3, a drain of the fourth PMOS transistor is connected with a drain of the first NMOS transistor NM1, or a drain of the second NMOS transistor NM2, or a source of the first PMOS transistor PM1, for providing the first bias current, or the second bias current, or the third bias current.

[0097] Specifically, in this embodiment of the folded operational amplifier circuit, multiple bias circuits are also included to provide different bias currents. Each bias circuit includes two PMOS transistors, which are connected in series to the LDO input signal V. IN In the folded op-amp circuit, a bias current must be provided, and the gates of the two PMOS transistors are respectively connected to the corresponding internal bias voltages of the LDO, namely the second bias voltage Vb2 and the third bias voltage Vb3. The voltage values ​​of the second bias voltage Vb2 and the third bias voltage Vb3 can be the same or different.

[0098] In some implementations, such as Figure 3 As shown, the first bias circuit 41 includes two PMOS transistors, namely a third PMOS transistor PM32 and a fourth PMOS transistor PM42. The gate of the third PMOS transistor PM32 is connected to the second bias voltage Vb2, and the source is connected to the input signal V. IN The drain is connected to the source of the fourth PMOS transistor PM42; the gate of the fourth PMOS transistor PM42 is connected to the third bias voltage Vb3, and the drain is connected to the drain of the first NMOS transistor NM1 to provide the first bias current.

[0099] In some implementations, such as Figure 3 As shown, the second bias circuit 42 includes two PMOS transistors, namely a third PMOS transistor PM33 and a fourth PMOS transistor PM43. The gate of the third PMOS transistor PM33 is connected to the second bias voltage Vb2, and the source is connected to the input signal V. IN The drain is connected to the source of the fourth three-phase PMOS transistor PM43; the gate of the fourth three-phase PMOS transistor PM43 is connected to the third bias voltage Vb3, and the drain is connected to the drain of the second NMOS transistor NM2 to provide the second bias current.

[0100] In some implementations, such as Figure 3 As shown, the third bias circuit 43 includes two PMOS transistors, namely the third PMOS transistor PM31 and the fourth PMOS transistor PM41. The gate of the third PMOS transistor PM33 is connected to the second bias voltage Vb2, and the source is connected to the input signal V. IN The drain is connected to the source of the fourth PMOS transistor PM41; the gate of the fourth PMOS transistor PM41 is connected to the third bias voltage Vb3, and the drain is connected to the source of the first PMOS transistor PM1 to provide the third bias current.

[0101] The above-mentioned folded operational amplifier circuit structure has high stability and reliability, and can provide stable bias current under different operating conditions, thereby achieving more accurate signal amplification and processing.

[0102] In a preferred embodiment, such asFigure 3 The second-stage amplification circuit 112 comprises:

[0103] A fifth PMOS tube PM5, the gate of the fifth PMOS tube PM5 is connected to the first-stage amplified signal, the source of the fifth PMOS tube PM5 is connected to a fourth bias current, and the drain of the fifth PMOS tube PM5 is used to output the first processed signal Vp1.

[0104] A fifth NMOS tube NM5, the gate and the drain of the fifth NMOS tube NM5 are respectively connected to the drain of the fifth PMOS tube PM5, and the source of the fifth NMOS tube NM5 is grounded.

[0105] Specifically, in the embodiment, the fifth PMOS tube PM5 is used as the second-stage amplification of the main loop 1, so that the first-stage amplified signal is processed by the second-stage amplification to obtain the first processed signal Vp1; the fifth NMOS tube NM5 is used as the load of the second-stage amplification of the main loop 1, which ensures the amplitude of the first processed signal Vp1.

[0106] Further, the fifth PMOS tube PM5 can adjust the conduction degree of the PMOS tube according to the size of the input first-stage amplified signal, so as to realize linear adjustment of the output signal. When the load current changes from light load to heavy load, the conduction degree of the PMOS tube will also be adjusted accordingly to maintain the linearity of the output signal, thereby achieving the purpose of improving the linearity of the loop when the load changes from light load to heavy load.

[0107] As a preferred embodiment, wherein, as shown in Figure 3 The second-stage amplification circuit 112 further comprises: a sixth PMOS tube PM6, the gate of the sixth PMOS tube PM6 is connected to a fourth bias voltage Vb4, the source of the sixth PMOS tube PM6 is connected to the input signal V IN , and the drain of the sixth PMOS tube PM6 is used to provide a fourth bias current.

[0108] Specifically, in the embodiment, the sixth PMOS tube PM6 is used as the bias current source of the second-stage amplification of the main loop 1, which is used to provide the fourth bias current for the fifth PMOS tube PM5. Specifically, when the input signal V IN enters the second-stage amplification circuit 112, it will be transmitted to the source of the sixth PMOS tube PM6. Due to the characteristics of the PMOS tube, when the gate voltage of the sixth PMOS tube PM6 is lower than the source voltage, the PMOS tube will be turned on, thereby transmitting the input signal V IN to the fifth PMOS tube PM5 for providing the fourth bias current.

[0109] As a preferred embodiment, wherein, as shown in Figure 4 The second-stage amplification circuit 112 further comprises: a sixth PMOS tube PM6, the gate of the sixth PMOS tube PM6 is connected to a fourth bias voltage Vb4, the source of the sixth PMOS tube PM6 is connected to the input signal V IN , and the drain of the sixth PMOS tube PM6 is used to provide a fourth bias current.

[0110] a sixth NMOS transistor NM6, a gate of the sixth NMOS transistor NM6 is connected to the first processing signal Vp1 through a third resistor and to ground through a first capacitor, and a source of the sixth NMOS transistor NM6 is connected to ground;

[0111] a seventh NMOS transistor NM7, a gate of the seventh NMOS transistor NM7 is connected to the first processing signal Vp1, and a source of the seventh NMOS transistor NM7 is connected to ground;

[0112] an eighth NMOS transistor NM8, a gate of the eighth NMOS transistor NM8 is connected to the first control signal control1, a source of the eighth NMOS transistor NM8 is connected to a drain of the sixth NMOS transistor NM6 and a drain of the seventh NMOS transistor NM7 respectively, and a drain of the eighth NMOS transistor NM8 is connected to the control end of the main adjustment transistor 31.

[0113] Specifically, in the embodiment, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 constitute the third stage amplification of the main loop 1, and the eighth NMOS transistor NM8 has a strong pull-down capability, and when the eighth NMOS transistor NM8 is turned on, the control end voltage of the main adjustment transistor 31 will be pulled down.

[0114] Further, the first control signal control1 changes with the load current, and by introducing a dynamic current bias mechanism, the circuit can still obtain better large signal response capability under low static power consumption, can more quickly adapt to load changes, and improves the transient response performance.

[0115] Further, the above-mentioned first control signal control1 changes with the load current of the LDO output end. Specifically, control1 is in a positive proportional relationship with the load current, that is, as the load current rises, control1 will also rise; as the load current decreases, control1 will also decrease.

[0116] Further, zero frequency compensation is performed through the third resistor and the first capacitor.

[0117] As a preferred embodiment, wherein, as shown in Figure 4 the second amplification unit 12 further comprises: a ninth NMOS transistor NM9, a gate of the ninth NMOS transistor NM9 is connected to a second control signal control2 which is reverse to the first control signal control1, a drain of the ninth NMOS transistor NM9 is connected to the input signal V IN , and a source of the ninth NMOS transistor NM9 is connected to the control end of the main adjustment transistor 31.

[0118] the input end of the main adjustment transistor 31 is connected to the input signal V IN, the output end of the main adjusting tube 31 is connected with the output signal V OUT .

[0119] Specifically, in the embodiment, the ninth NMOS tube NM9 is used as the bias current source of the third stage amplification of the main loop 1, for providing the bias current. The ninth NMOS tube NM9 has strong pull-up ability, and when the ninth NMOS tube NM9 is turned on, the control end voltage of the main adjusting tube 31 will be pulled up under heavy load condition.

[0120] The second control signal control2 changes with the change of the load current of the LDO output end. Specifically, control2 is inversely proportional to the change of the load current, that is, as the load current rises, control1 will decrease; as the load current decreases, control1 will increase.

[0121] As a preferred embodiment, as shown in Figure 5 , the third amplification unit comprises:

[0122] A tenth NMOS tube NM10, the gate of the tenth NMOS tube NM10 is connected with the first processing signal Vp1, the source of the tenth NMOS tube NM10 is grounded, and the drain of the tenth NMOS tube NM10 is connected with the control end of the secondary adjusting tube 32.

[0123] The input end of the secondary adjusting tube 32 is connected with the input signal V IN , and the output end of the secondary adjusting tube 32 is connected with the output signal V OUT .

[0124] Specifically, in the embodiment, the tenth NMOS tube NM10 is used as the third stage amplification of the auxiliary loop 2, and the tenth NMOS tube NM10 is turned on or turned off under the action of the first processing signal Vp1, thereby controlling the secondary adjusting tube 32 to be turned on or turned off. Specifically, under light load condition, when the tenth NMOS tube NM10 is turned on, the control end voltage of the secondary adjusting tube 32 is pulled down, so that the secondary adjusting tube 32 is turned on to provide the load current.

[0125] Further, the first two stage amplifications of the auxiliary loop 2 are shared with the first two stage amplifications of the main loop 1, which can reduce the required device quantity and material cost, reduce the overall manufacturing cost, reduce the size of the whole system, make it more compact and convenient to integrate, thereby simplifying the design and layout of the LDO, and reducing the complexity and difficulty of the design.

[0126] Further, the main adjusting tube 31 is implemented by using a PM 主 , the source of the PM 主 is used as the input end of the main adjusting tube 31, for connecting the input signal V IN , and the drain of the PM 主the drain of the PMOS transistor as the output terminal of the main adjustment, for connecting the output signal V OUT In the heavy load case, the load current is mainly provided by the main adjustment tube 31.

[0127] Further, the secondary adjustment tube 32 adopts PM 次 The source of the PM 次 The drain of the PM IN The drain of the PM 次 The drain of the PM OUT In the light load case, the load current is mainly provided by the secondary adjustment tube 32.

[0128] In some embodiments, in the idle case, the load current is provided by the secondary adjustment tube 32; in the light load case, the load current is provided by the main adjustment tube 31 and the secondary adjustment tube 32 together, in which the secondary adjustment tube 32 plays a major role; in the heavy load case, the load current is provided by the main adjustment tube 31 and the secondary adjustment tube 32 together, in which the main adjustment tube 31 plays a major role.

[0129] As a preferred embodiment, wherein, as shown in Figure 5 Further comprising:

[0130] An eleventh NMOS tube NM11, the gate of the eleventh NMOS tube NM11 is connected to a fifth bias voltage, the source of the eleventh NMOS tube NM11 is connected to the control terminal of the secondary adjustment tube 32, and the drain of the eleventh NMOS tube NM11 is connected to the input signal V IN ;

[0131] The fifth bias voltage is provided by a fifth bias circuit, which comprises:

[0132] A seventh PMOS tube PM7, the gate and the drain of the seventh PMOS tube PM7 are connected to the gate of the eleventh NMOS tube NM11 respectively, and the drain of the seventh PMOS tube PM7 is connected to the input signal through a fourth resistor R4 and a fifth resistor R5 in a controllable manner.

[0133] Specifically, in this embodiment, the seventh PMOS tube PM7, the fourth resistor R4 and the fifth resistor R5 provide a bias voltage for the eleventh NMOS tube NM11 to control the conduction or cutoff of the eleventh NMOS tube NM11. When the eleventh NMOS tube NM11 is turned on, the control terminal voltage of the secondary adjustment tube 32 is pulled up.

[0134] In some embodiments, a twelfth NMOS transistor NM12 is further included, a gate of the twelfth NMOS transistor NM12 is connected to the first processing signal Vp1, a source of the twelfth NMOS transistor NM12 is grounded, a drain of the twelfth NMOS transistor NM12 is connected to the seventh PMOS transistor PM7, the twelfth NMOS transistor NM12 and the fifth NMOS transistor NM5 are current mirrors, and the twelfth NMOS transistor NM12 is used to provide a mirror current for the seventh PMOS transistor.

[0135] As a preferred embodiment, as shown in Figure 3 Further comprising:

[0136] A first logic control unit 71 is controllably connected between the input terminal of the first amplification unit 11 and the ground terminal under the action of an inverted signal of an enable signal.

[0137] Specifically, in the embodiment, the first logic control unit 71 is controlled by the inverted signal of the enable signal, i.e. the logic low level controlled by the LDO internal EN. When the first logic control unit 71 is turned on, the first amplification unit 11 does not work; when the first logic control unit 71 is turned off, the first amplification unit 11 works.

[0138] Further, the first logic control unit 71 includes a thirteenth NMOS transistor NM13, a gate of the thirteenth NMOS transistor NM13 is connected to the inverted signal of the enable signal EN_L, a drain of the thirteenth NMOS transistor NM13 is connected to the drain of the first NMOS transistor NM1, and a source of the thirteenth NMOS transistor NM13 is grounded. When EN_L is high, the thirteenth NMOS transistor NM13 is turned on, and the first amplification unit 11 does not work; when EN_L is low, the thirteenth NMOS transistor NM13 is turned off, and the first amplification unit 11 works.

[0139] As a preferred embodiment, as shown in Figure 4 Further comprising:

[0140] A second logic control unit 72 is controllably connected between the input signal V IN and one end of a sixth resistor R6 under the action of the inverted signal of the enable signal, the other end of the sixth resistor R6 is connected to the control terminal of the main adjustment tube 31.

[0141] Specifically, in the embodiment, the second logic control unit 72 is controlled by the inverted signal of the enable signal, i.e. the logic low level controlled by the LDO internal EN. When the second logic control unit 72 is turned on, the control terminal voltage of the main adjustment tube 31 is pulled up.

[0142] Further, the second logic control unit 72 includes an eighth PMOS transistor PM8, a gate of the eighth PMOS transistor PM8 is connected to the inverted signal of the enable signal EN_L, a source of the eighth PMOS transistor PM8 is connected to the input signal V INThe control end of the main adjusting tube 31 is connected to the drain of the sixth resistance R6. When the EN_L is high, the eighth PMOS PM8 is off, and the voltage of the control end of the main adjusting tube 31 is not affected. When the EN_L is low, the eighth PMOS PM8 is on, and the voltage of the control end of the main adjusting tube 31 is pulled up, so that the load current provided by the main adjusting tube 31 is gradually reduced. After the main adjusting tube 31 is off, no load current is provided.

[0143] Further, due to the existence of the sixth resistance R6, the equivalent impedance of the gate of the main adjusting tube 31 is reduced, so that the current is more easily flowed into the main adjusting tube 31 through the gate.

[0144] As a preferred embodiment, as shown in Figure 5 , further comprising:

[0145] A third logic control unit 73 is controllably connected between the input signal V IN and the connection place of the fourth resistance and the fifth resistance under the action of the inverse signal of the enable signal. One end of a seventh resistance R7 is connected to the control end of the secondary adjusting tube 32, and the other end of the seventh resistance R7 is connected to the ground.

[0146] Specifically, in the embodiment, the third logic control unit 73 is controlled by the inverse signal of the enable signal, i.e. the logic low level of the EN control inside the LDO. When the third logic control unit 73 is on, the voltage of the control end of the main adjusting tube 31 is pulled up.

[0147] Further, the third logic control unit 73 comprises a ninth PMOS PM9, the gate of the ninth PMOS PM9 is connected to the inverse signal of the enable signal EN_L, the source is connected to the input signal V IN , and the drain is connected to the control end of the secondary adjusting tube 32 through the seventh resistance R7. When the EN_L is high, the ninth PMOS PM9 is off, and the voltage of the control end of the secondary adjusting tube 32 is not affected. When the EN_L is low, the ninth PMOS PM9 is on, and the voltage of the control end of the secondary adjusting tube 32 is pulled up, so that the load current provided by the secondary adjusting tube 32 is gradually reduced. After the secondary adjusting tube 32 is off, no load current is provided.

[0148] Further, due to the existence of the seventh resistance R7, the equivalent impedance of the gate of the secondary adjusting tube 32 is reduced, so that the current is more easily flowed into the secondary adjusting tube 32 through the gate.

[0149] As a preferred embodiment, as shown in Figure 5 , further comprising:

[0150] A fourth logic control unit 74 is controllably connected between the input signal V IN and the connection place of the fourth resistance and the fifth resistance under the action of the inverse signal of the enable signal.

[0151] Further, the fourth logic control unit 74 comprises a tenth PMOS transistor PM10, the gate of which is connected to the inverted enable signal EN_L, the source of which is connected to the input signal V IN , and the drain of which is connected between the fourth resistor R4 and the fifth resistor R5. When EN_L is high, the tenth PMOS transistor PM10 is off, and the eleventh NMOS transistor NM11 is off; when EN_L is low, the tenth PMOS transistor PM10 is on, and the eleventh NMOS transistor NM11 is on, thereby pulling down the control end voltage of the secondary adjusting transistor 32.

[0152] Further, the enable signal inside the LDO can be a signal for enabling the LDO chip to work, i.e., when the LDO works, the enable signal is high, at this time, the corresponding EN_L is low; when the LDO does not work, the enable signal is low, at this time, EN_L is high.

[0153] As a preferred embodiment, as shown in Figure 4 , further comprising:

[0154] a fifth logic control unit 75, which is controllably connected between the input signal V IN and the control end of the primary adjusting transistor 31 under the action of a first protection control signal H.

[0155] Specifically, in this embodiment, the first protection control signal, i.e., the internal logic combination of the LDO is high, controls the on-off of the fifth logic control unit 75. When the fifth logic control unit 75 is on, the control end voltage of the primary adjusting transistor 31 is pulled up.

[0156] Further, the fifth logic control unit 75 comprises an eleventh PMOS transistor PM11, the gate of which is connected to the first protection control signal H, the source of which is connected to the input signal V IN , and the drain of which is connected to the control end of the primary adjusting transistor 31. When H is high, the eleventh PMOS transistor PM11 is off, and does not affect the control end voltage of the primary adjusting transistor 31; when H is low, the eleventh PMOS transistor PM11 is on, and pulls up the control end voltage of the primary adjusting transistor 31, so that the load current provided by the primary adjusting transistor 31 gradually decreases.

[0157] As a preferred embodiment, as shown in Figure 5 , further comprising:

[0158] a sixth logic control unit 76, which is controllably connected between the input signal V IN and the control end of the secondary adjusting transistor 32 under the action of the first protection control signal.

[0159] Specifically, in the embodiment, the first protection control signal, i.e. the high level combined by the internal logic of the LDO, is used to control the on-off of the sixth logic control unit 76. When the sixth logic control unit 76 is turned on, the control end voltage of the secondary regulator 32 is pulled high.

[0160] Further, the sixth logic control unit 76 includes a twelfth PMOS PM12, the gate of the twelfth PMOS PM12 is connected to the first protection control signal H, the source is connected to the input signal V IN , and the drain is connected to the control end of the secondary regulator 32. When H is high, the twelfth PMOS PM12 is cut off, and the control end voltage of the secondary regulator 32 is not affected; when H is low, the twelfth PMOS PM12 is turned on, the control end voltage of the secondary regulator 32 is pulled high, and the load current provided by the secondary regulator 32 gradually decreases.

[0161] As a preferred embodiment, as shown in Figure 5 , it further comprises:

[0162] A seventh logic control unit 77 is controllably connected between the input signal V IN and the fifth resistor under the action of the first protection control signal.

[0163] Specifically, in the embodiment, the first protection control signal, i.e. the high level combined by the internal logic of the LDO, is used to control the on-off of the seventh logic control unit 77. When the seventh logic control unit 77 is turned on, the seventh PMOS, the fourth resistor and the fifth resistor provide bias voltage for the eleventh NMOS.

[0164] Further, the seventh logic control unit 77 includes a thirteenth PMOS PM13, the gate of the thirteenth PMOS PM13 is connected to the first protection control signal H, the source is connected to the input signal V IN , and the drain is connected to the fifth resistor. When H is high, the thirteenth PMOS PM13 is cut off, the eleventh NMOS NM11 is cut off, and the control end voltage of the secondary regulator 32 is not affected; when H is low, the thirteenth PMOS PM13 is turned on, the eleventh NMOS NM11 is turned on, the control end voltage of the secondary regulator 32 is pulled high, and the load current provided by the secondary regulator 32 gradually decreases.

[0165] Further, the above-mentioned first protection control signal can be determined according to the existing protection circuit inside the LDO, including but not limited to overvoltage, overcurrent, overtemperature, etc. When including but not limited to overvoltage, overcurrent, overtemperature, the first protection control signal is high, otherwise it is low.

[0166] As a preferred embodiment, as shown in Figure 4 , it further comprises:

[0167] an eighth logic control unit 78, which is controllably connected between the first processing signal Vp1 and the ground under the action of the inverse signal of the first protection control signal.

[0168] Specifically, in this embodiment, the on-off of the eighth logic control unit 78 is controlled by the inverse signal of the first protection control signal, i.e. the low level of the internal logic combination of the LDO. When the eighth logic control unit 78 is turned on, the first processing signal Vp1 is pulled low, so that the third-stage amplification of the main loop 1 does not work.

[0169] Further, the eighth logic control unit 78 comprises a fourteenth PMOS tube PM14, the gate of the fourteenth PMOS tube PM14 is connected to the inverse signal L of the first protection control signal, the source is grounded, and the drain is connected to the first processing signal Vp1. When L is high, the fourteenth PMOS tube PM14 is turned on, the first processing signal Vp1 is pulled low, so that the third-stage amplification of the main loop 1 does not work; when L is low, the fourteenth PMOS tube PM14 is turned off, and the third-stage amplification of the main loop 1 works.

[0170] As a preferred embodiment, as shown in Figure 4 , it further comprises:

[0171] a ninth logic control unit 79, which is controllably connected between the zero frequency compensation signal of the first processing signal Vp1 and the ground under the action of the inverse signal of the first protection control signal.

[0172] Specifically, in this embodiment, the on-off of the ninth logic control unit 79 is controlled by the inverse signal of the first protection control signal, i.e. the low level of the internal logic combination of the LDO. When the ninth logic control unit 79 is turned on, the first processing signal Vp1 is pulled low, so that the third-stage amplification of the main loop 1 does not work.

[0173] Further, the ninth logic control unit 79 comprises a fifteenth PMOS tube PM15, the gate of the fifteenth PMOS tube PM15 is connected to the inverse signal L of the first protection control signal, the source is grounded, and the drain is connected to the sixth NMOS tube NM6. When L is high, the fifteenth PMOS tube PM15 is turned on, the sixth NMOS tube NM6 is turned off, and the drain voltage of the seventh NMOS tube NM7 is pulled low; when L is low, the fifteenth PMOS tube PM15 is turned off.

[0174] As a preferred embodiment, as shown in Figure 3 , it further comprises:

[0175] a first zero frequency compensation unit 5, which is connected between the input signal V IN and the input end of the second amplification unit 12.

[0176] Further, the first zero frequency compensation unit 5 performs zero frequency compensation through an eighth resistor and a second capacitor.

[0177] As a preferred embodiment, wherein, as shown in Figure 3 , further comprising:

[0178] A Miller compensation unit 6 is connected between the second output end of the first stage amplification circuit 111 and the output signal, for performing Miller compensation on the negative signal of the first processing signal Vp1; wherein the negative signal of the first processing signal Vp1 is a signal lower than the first processing signal Vp1 by one drain-source voltage.

[0179] Specifically, in the embodiment, the Miller compensation unit 6 realizes Miller compensation through a third capacitor C3 and a ninth resistor R9 connected in series between the second NMOS tube NM2 and the output signal.

[0180] As a preferred embodiment, wherein the size of the secondary adjustment tube 32 is smaller than the size of the primary adjustment tube 31.

[0181] Specifically, the size of the secondary adjustment tube 32 is smaller than the size of the primary adjustment tube 31, and since the gate stray capacitance of the secondary adjustment tube 32 is smaller than that of the primary adjustment tube 31, the response time of the auxiliary loop 2 is smaller than that of the primary loop 1 when facing load transient response.

[0182] As shown in Figure 6 , it is an application schematic diagram of low dropout linear regulator, LDO includes six ports, namely IN port for receiving input signal V IN , OUT port for outputting the above output signal V OUT , EN port for receiving external enable signal V EN , FB port for receiving feedback signal VFB of output signal, DNC (do not connect) port, GND port for grounding.

[0183] In the above scheme, as shown in Figure 3 , Figure 4 , Figure 5 , Vb1, Vb2, Vb3, Vb4, control (control1, control2) are LDO internal bias voltage, respectively corresponding MOS tube provides gate voltage; VP55 is the reference voltage signal obtained by dividing the reference signal, VFB is the feedback signal of the output signal, V OUT is the output signal, EN_L is the logic low level of EN control, H is the logic combination high level inside LDO, L is the logic combination low level inside LDO.

[0184] The main adjustment tube 31 mainly provides the load current under heavy load, and the secondary adjustment tube 32 assists in providing the load current; under light load, since the gate stray capacitance of the secondary adjustment tube 32 is smaller than that of the main adjustment tube 31, the response time of the auxiliary loop 2 is shorter than that of the main loop 1 when facing the load transient response, the main adjustment tube 31 is cut off, the current is provided by the auxiliary loop 2 in which the secondary adjustment tube 32 is located, the load gradually decreases until no load, at this time, the first control signal control1 is lowered according to the change of the load current, the third stage of the main loop 1, i.e. the branch in which the eighth NMOS tube NM8 is located, is reduced, so as to reduce the power consumption in the standby state.

[0185] The specific working principle of the embodiment of the present application for improving the transient response is as follows:

[0186] When the load current jumps from light load to heavy load, the first control signal control1 is raised according to the change of the load current, the eighth NMOS tube NM8 and the ninth NMOS tube NM9 can quickly respond, the eighth NMOS tube NM8 is turned on, the ninth NMOS tube NM9 is cut off, the gate voltage of the main adjustment tube 31 can be quickly pulled down, and the main adjustment tube 31 can provide the load current in time.

[0187] When the load current jumps from heavy load to light load, the auxiliary loop 2 can be adjusted faster, and the ninth NMOS tube NM9 is turned on according to the change of the load current, so that the gate voltage of the main adjustment tube 31 is quickly pulled up, and the source-drain current of the main adjustment tube 31 is reduced.

[0188] The embodiment of the present application meets the requirements of load capacity, transient response performance and low power consumption.

[0189] The above is only the preferred embodiment of the present application, and does not limit the implementation and protection scope of the present application, and those skilled in the art should be able to realize that any equivalent replacement and obvious change obtained by applying the contents of the present application and the drawings should be included in the protection scope of the present application.

Claims

1. A low-dropout linear regulator based on dual regulating tubes and dual loops, characterized in that, include: A main loop, the main loop comprising: The first amplification unit is used to amplify the feedback signal of the output signal of the low dropout linear regulator and a reference voltage divider signal by at least one stage to obtain a first processed signal. The second amplification unit is connected to the output terminal of the first amplification unit and is used to amplify the first processed signal under the action of a first control signal to obtain a second processed signal; wherein, the first control signal changes with the load current. An auxiliary loop, comprising: a third amplification unit connected to the output of the first amplification unit, used to perform auxiliary amplification processing on the first processed signal to obtain a third processed signal; An adjustment unit, the adjustment unit comprising: A main regulating transistor, the control terminal of which is connected to the output terminal of the main loop, is used to provide the load current under the action of the second processing signal; A primary regulating tube, the control terminal of which is connected to the output terminal of the auxiliary loop, is used to provide the load current under the action of the third processing signal.

2. The low-dropout linear regulator based on dual regulating tubes and dual loops according to claim 1, characterized in that, The first amplification unit includes a two-stage amplification subunit, the two-stage amplification subunit comprising: The first-stage amplifier circuit is used to amplify the feedback signal of the output signal and the reference voltage divider signal in the first stage to clamp the output signal and obtain a first-stage amplified signal. The second-stage amplifier circuit is connected to the first-stage amplifier circuit and is used to perform a second-stage amplification processing on the first-stage amplified signal to obtain the first processed signal.

3. The low-dropout linear regulator based on dual regulating tubes and dual loops according to claim 2, characterized in that, The first-stage amplifier circuit employs a folded operational amplifier circuit, which includes: A first NMOS transistor and a second NMOS transistor are provided. The gates of the first NMOS transistor and the second NMOS transistor are respectively connected to a first bias voltage. The drain of the first NMOS transistor is connected to a first bias current. The drain of the second NMOS transistor is connected to a second bias current and outputs the first stage amplified signal. A third NMOS transistor, the gate of which is connected to the drain of the first NMOS transistor, the drain of which is connected to the source of the first NMOS transistor through a first resistor, and the source of which is grounded. A fourth NMOS transistor, the gate of which is connected to the gate of the third NMOS transistor, the drain of which is connected to the source of the second NMOS transistor through a second resistor, and the source of which is grounded. A first PMOS transistor and a second PMOS transistor are provided. The gate of the first PMOS transistor is connected to the feedback signal of the output signal, and the gate of the second PMOS transistor is connected to the reference voltage divider signal. The sources of the first PMOS transistor and the second PMOS transistor are connected to a third bias current. The drain of the first PMOS transistor is connected to the source of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the source of the second NMOS transistor. The folded operational amplifier circuit further includes: a first bias circuit for providing the first bias current, a second bias circuit for providing the second bias current, and a third bias circuit for providing the third bias current, wherein the first bias circuit, the second bias circuit, and the third bias circuit each include: A third PMOS transistor and a fourth PMOS transistor are provided. The gate of the third PMOS transistor is connected to a second bias voltage, the source of the third PMOS transistor is connected to an input signal, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to a third bias voltage, and the drain of the fourth PMOS transistor is connected to the drain of the first NMOS transistor, or the drain of the second NMOS transistor, or the source of the first PMOS transistor, for providing the first bias current, or the second bias current, or the third bias current.

4. The low-dropout linear regulator based on dual regulating tubes and dual loops according to claim 2, characterized in that, The second-stage amplifier circuit includes: A fifth PMOS transistor, the gate of which is connected to the first stage amplified signal, the source of which is connected to a fourth bias current, and the drain of which is used to output the first processed signal. A fifth NMOS transistor, wherein the gate and drain of the fifth NMOS transistor are respectively connected to the drain of the fifth PMOS transistor, and the source of the fifth NMOS transistor is grounded; The second-stage amplifier circuit further includes: a sixth PMOS transistor, the gate of which is connected to a fourth bias voltage, the source of which is connected to the input signal, and the drain of which is used to provide the fourth bias current.

5. The low-dropout linear regulator based on dual regulating tubes and dual loops according to claim 1, characterized in that, The second amplification unit includes: A sixth NMOS transistor, wherein the gate of the sixth NMOS transistor is connected to the first processed signal through a third resistor and grounded through a first capacitor, and the source of the sixth NMOS transistor is grounded; A seventh NMOS transistor, wherein the gate of the seventh NMOS transistor is connected to the first processed signal, and the source of the seventh NMOS transistor is grounded; An eighth NMOS transistor is provided, wherein the gate of the eighth NMOS transistor is connected to the first control signal, the source of the eighth NMOS transistor is connected to the drain of the sixth NMOS transistor and the drain of the seventh NMOS transistor, and the drain of the eighth NMOS transistor is connected to the control terminal of the main adjustment transistor. The second amplification unit further includes: a ninth NMOS transistor, the gate of which is connected to a second control signal that is opposite to the first control signal, the drain of which is connected to the input signal, and the source of which is connected to the control terminal of the main adjustment transistor; The input terminal of the main regulating transistor is connected to the input signal, and the output terminal of the main regulating transistor is connected to the output signal.

6. The low-dropout linear regulator based on dual regulating tubes and dual loops according to claim 1, characterized in that, The third amplification unit includes: A tenth NMOS transistor, the gate of which is connected to the first processing signal, the source of which is grounded, and the drain of which is connected to the control terminal of the secondary adjustment transistor; The input terminal of the secondary adjustment tube is connected to the input signal, and the output terminal of the secondary adjustment tube is connected to the output signal.

7. The low-dropout linear regulator based on dual regulating tubes and dual loops according to claim 1, characterized in that, Also includes: An eleventh NMOS transistor, the gate of which is connected to a fifth bias voltage, the source of which is connected to the control terminal of the secondary adjustment transistor, and the drain of which is connected to the input signal. The fifth bias voltage is provided by a fifth bias circuit, which includes: A seventh PMOS transistor, the gate and drain of which are respectively connected to the gate of the eleventh NMOS transistor, and the source of which is connected to the input signal in a way that can be switched on and off through a fourth resistor and a fifth resistor.

8. The low-dropout linear regulator based on dual regulating tubes and dual loops according to claim 7, characterized in that, Also includes: A first logic control unit is controllably connected between the input terminal and the ground terminal of the first amplification unit under the action of the inverted signal of an enable signal; A second logic control unit is controllably connected between the input signal and one end of a sixth resistor under the action of the inverted signal of the enable signal, and the other end of the sixth resistor is connected to the control terminal of the main regulating transistor. A third logic control unit is controllably connected between the input signal and one end of a seventh resistor under the action of the inverted signal of the enable signal, and the other end of the seventh resistor is connected to the control terminal of the secondary adjustment transistor. A fourth logic control unit is controllably connected between the input signal and the connection point of the fourth resistor and the fifth resistor under the action of the inverted signal of the enable signal; A fifth logic control unit is controllably connected between the input signal and the control terminal of the main regulating transistor under the action of a first protection control signal; A sixth logic control unit is controllably connected between the input signal and the control terminal of the secondary adjustment tube under the action of the first protection control signal; A seventh logic control unit is controllably connected between the input signal and the fifth resistor under the action of the first protection control signal; An eighth logic control unit is controllably connected between the first processing signal and the ground terminal under the action of the inverted signal of the first protection control signal; A ninth logic control unit is controllably connected between the zero-point frequency compensation signal of the first processing signal and the ground terminal under the action of the inverted signal of the first protection control signal.

9. The low-dropout linear regulator based on dual regulating tubes and dual loops according to claim 2, characterized in that, Also includes: A first zero-point frequency compensation unit is connected between the input signal and the input terminal of the second amplification unit; A Miller compensation unit is connected between the second output terminal of the first stage amplifier circuit and the output signal, and is used to perform Miller compensation on the negative signal of the first processed signal; wherein, the negative signal of the first processed signal is a signal that is lower than the first processed signal by one drain-source voltage.

10. The low-dropout linear regulator based on dual regulating tubes and dual loops according to claim 1, characterized in that, The size of the secondary adjustment tube is smaller than the size of the main adjustment tube.

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