Test structure and method for parasitic capacitance

Abstract

The application provides a test structure and a test method of a parasitic capacitance. The test structure comprises a first test structure, a second test structure and a third test structure. The first test structure, the second test structure and the third test structure each comprise a gate structure on a substrate, a source-drain structure in the substrate and a contact hole structure. The gate structure is electrically connected to a first test pad and forms a first parasitic capacitance with the substrate. The source-drain structure forms a second parasitic capacitance with the gate structure. The contact hole structure is electrically connected to a second test pad and forms a third parasitic capacitance with the gate structure. The first test structure is used for testing the sum of the first parasitic capacitance and the second parasitic capacitance. The second test structure is used for testing the second parasitic capacitance. The third test structure is used for testing the second parasitic capacitance. The test structure and the test method of the technical solution of the application can test a single parasitic capacitance.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing, and in particular to a test structure and test method for parasitic capacitance. Background Technology

[0002] As device dimensions shrink further, especially below the 90nm node, parasitic capacitance effects become significant, particularly the parasitic capacitance between the gate structure and contact vias (C0). GT-CT Parasitic capacitance (C) between the gate structure and the active substrate GT-AA ) and the parasitic capacitance (C) between the gate structure and the source / drain structure. GT-SD This can affect the performance of the device.

[0003] Traditional test structures and methods can measure the sum of the three parasitic capacitances mentioned above, but cannot measure individual parasitic capacitances. Consequently, it is impossible to analyze the impact of individual parasitic capacitances on device performance. Therefore, it is necessary to design new test structures and methods to obtain individual parasitic capacitances. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide a test structure and test method for parasitic capacitance, which can test individual parasitic capacitances.

[0005] To address the aforementioned technical problems, this application provides a test structure for parasitic capacitance, including a first test structure, a second test structure, and a third test structure. Each of the first, second, and third test structures includes a gate structure located on a substrate, a source / drain structure located in the substrate, and a contact hole structure. The gate structure is electrically connected to a first test pad and forms a first parasitic capacitance with the substrate. The source / drain structure forms a second parasitic capacitance with the gate structure. The contact hole structure is electrically connected to a second test pad and forms a third parasitic capacitance with the gate structure. The first test structure is used to test the sum of the first and second parasitic capacitances. In the first test structure, the contact hole structures are located on a portion of the source / drain structures and the number of contact hole structures does not exceed two. The contact hole structures have a first parasitic capacitance with respect to the gate structure. A first test structure is used to test the second parasitic capacitance. In the second test structure, the contact hole structure is located on a portion of the source / drain structure and the number of contact holes is no more than two. The contact hole structure and the gate structure have a first horizontal spacing. The substrate on the side of the contact hole structure away from the gate structure has a second width, and the second width is less than the first width. A third test structure is used to test the second parasitic capacitance. In the third test structure, the contact hole structure is located on a portion of the substrate and the number of contact holes is more than two. The contact hole structure and the gate structure have a second horizontal spacing, and the second horizontal spacing is greater than the first horizontal spacing. The substrate on the side of the contact hole structure away from the gate structure has a second width.

[0006] In some embodiments of this application, the first horizontal spacing is 28 nm to 0.5 μm.

[0007] In some embodiments of this application, the first width is 0.01 μm to 5 μm.

[0008] In some embodiments of this application, the second width is 0.01 μm to 0.05 μm.

[0009] In some embodiments of this application, the second horizontal spacing is not less than 5 μm.

[0010] In some embodiments of this application, the test structure further includes a fourth test structure for testing the sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance, wherein the fourth test structure differs from the first test structure only in the number of contact hole structures, and the fourth test structure and the third test structure have the same number of contact hole structures.

[0011] This application also provides a method for testing parasitic capacitance, which tests the test structure described in any of the preceding claims. The testing method includes: testing the first test structure to obtain the sum of the first parasitic capacitance and the second parasitic capacitance; testing the second test structure to obtain the second parasitic capacitance, and then obtaining the first parasitic capacitance; testing the third test structure to obtain the second parasitic capacitance; obtaining the sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance; and combining the sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance with the first parasitic capacitance and the second parasitic capacitance to obtain the third parasitic capacitance.

[0012] In some embodiments of this application, when performing a capacitance test, the first test pad is grounded and a bias voltage is applied to the second test pad.

[0013] In some embodiments of this application, the bias voltage is the operating voltage of the structure under test.

[0014] In some embodiments of this application, a fourth test structure is tested to obtain the sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance. The fourth test structure differs from the first test structure only in the number of contact hole structures, while the fourth test structure and the third test structure have the same number of contact hole structures.

[0015] Compared with the prior art, the test structure and test method for parasitic capacitance in this application have the following advantages:

[0016] The test structure for parasitic capacitance includes a first test structure and a second test structure. The first test structure is used to test the sum of the first parasitic capacitance and the second parasitic capacitance, and the second test structure is used to test the second parasitic capacitance. Therefore, the first parasitic capacitance can be obtained by combining the test results of the first test structure and the second test structure.

[0017] The test structure for parasitic capacitance includes a third test structure, which can test the second parasitic capacitance.

[0018] Meanwhile, the sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance can be obtained through traditional test structures and methods. Combined with the first parasitic capacitance and the second parasitic capacitance measured above, the third parasitic capacitance can be obtained.

[0019] The parasitic capacitance test structure described above is used for capacitance testing. The test method is simple and easy to operate, and can obtain individual parasitic capacitances separately. This overcomes the problem that traditional test structures and methods can only obtain the total parasitic capacitance, and provides data support for subsequent analysis of the impact of individual parasitic capacitances on device performance. Attached Figure Description

[0020] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0021] Figure 1 This is a top view of the first test structure (with dielectric layer removed) according to an embodiment of this application;

[0022] Figure 2 for Figure 1 Cross-sectional view of location AA (with added dielectric layer);

[0023] Figure 3 This is a schematic diagram of the structure of the first test structure connected to the test pad according to an embodiment of this application;

[0024] Figure 4 This is a top view of the second test structure (with dielectric layer removed) according to an embodiment of this application;

[0025] Figure 5 for Figure 4 Cross-sectional view of the BB location (with added dielectric layer);

[0026] Figure 6 This is a schematic diagram of the second test structure connected to the test pad according to an embodiment of this application;

[0027] Figure 7 This is a top view of the third test structure (with dielectric layer removed) according to an embodiment of this application;

[0028] Figure 8 for Figure 7 Cross-sectional view of the CC position (with added dielectric layer);

[0029] Figure 9 This is a schematic diagram of the third test structure connected to the test pad in an embodiment of this application;

[0030] Figure 10 This is a top view of the fourth test structure (with the dielectric layer removed) according to an embodiment of this application. Detailed Implementation

[0031] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0032] This application provides a test structure for parasitic capacitance, used to test C. GT-CT C GT-AA And C GT-SD It includes a first test structure, a second test structure, and a third test structure. The parasitic capacitances tested by these three test structures are not exactly the same. By combining the test results of these three test structures, a single parasitic capacitance can be obtained, which solves the problem that the current test structure can only obtain the sum of the above three parasitic capacitances and cannot obtain a single parasitic capacitance.

[0033] The three test structures of the technical solution of this application will be described below with reference to the accompanying drawings and specific embodiments.

[0034] Figure 1 This is a top view of the first test structure according to an embodiment of this application. Figure 2 for Figure 1 A sectional view at position AA, where Figure 1 The dielectric layer has been omitted to clearly show the relative positional relationships between the various structures. Figure 2 The location of the dielectric layer is shown in the figure. The first test structure of this application embodiment includes a gate structure 102, a source / drain structure 103, and a contact hole structure 104. The gate structure 102 is located on a substrate 101, and the gate structure 102 can be a conventional structure. For example, the gate structure 102 may include a gate oxide layer on the substrate 101 and a gate layer on the surface of the gate oxide layer. The sidewalls of the gate structure 102 may also include sidewall structures. The source / drain structure 103 may be located in the substrate 101 on both sides of the gate structure 102. The source / drain structure 103 includes a conventional source and drain, which are not distinguished in the figure. A dielectric layer 105 for electrical insulation is also formed on the surfaces of the substrate 101, the gate structure 102, and the source / drain structure 103. The contact hole structure 104 is located on a portion of the source / drain structure 103. Specifically, the contact hole structure 104 is located in the dielectric layer 105 on the surface of the source / drain structure 103.

[0035] refer to Figure 3The gate structure 102 is electrically connected to the first test pad 106, and the contact hole structure 104 is electrically connected to the second test pad 107. The gate structure 102 and the contact hole structure 104 are electrically connected to their respective test pads via conventional interconnect structures. The specific structure of these interconnect structures is designed according to actual conditions and will not be specifically described here. A first parasitic capacitance C is formed between the gate structure 102 and the substrate 101. GT-AA A second parasitic capacitance C is formed between the source / drain structure 103 and the gate structure 102. GT-SD A third parasitic capacitance C is formed between the contact hole structure 104 and the gate structure 102. GT-CT Under normal circumstances, a capacitance meter is used to test the first test pad 106 and the second test pad 107, and the measurement result is the first parasitic capacitance C. GT-AA Second parasitic capacitance C GT-SD and the third parasitic capacitance C GT-CT sum.

[0036] Continue to refer to Figure 1 In the first test structure, the contact hole structure 104 and the gate structure 102 have a first horizontal spacing d1, and the substrate 101 on the side of the contact hole structure 104 away from the gate structure 102 has a first width W1. The first horizontal spacing d1 and the first width W1 can be of conventional sizes; for example, the first horizontal spacing d1 can be from 28 nm to 0.5 μm. The first width W1 can be from 0.01 μm to 5 μm. The number of contact hole structures 104 does not exceed two. As an example, the number of contact hole structures 104 is two.

[0037] According to the capacitance calculation formula In the formula, C represents capacitance, ε represents the dielectric constant of the interplanar medium, S represents the area of ​​the plane, and d represents the interplanar spacing. Since the number of contact hole structures 104 is small, and the area of ​​the opposing surfaces of a single contact hole structure 104 and the gate structure 102 is very small, within the tolerance range, S in the capacitance calculation formula can be considered to be 0. Therefore, when the interplanar spacing d is not 0, the capacitance C should be 0. In this embodiment, the third parasitic capacitance C between the contact hole structure 104 and the gate structure 102... GT-CT Since the value is 0, when performing capacitance testing using the first test structure, the obtained capacitance result is the first parasitic capacitance C. GT-AA and the second parasitic capacitance C GT-SD sum.

[0038] Figure 4 This is a top view of the second test structure according to an embodiment of this application, which omits the dielectric layer. Figure 5 for Figure 4 A cross-sectional view of the BB position is shown, and the dielectric layer is reconstructed. The second test structure includes a gate structure 202, a source / drain structure 203, and a contact hole structure 204. The gate structure 202 is located on the substrate 201 and may include a conventional structure, such as the gate structure 202 having a gate dielectric layer on the substrate 201 and a gate layer on the gate dielectric layer. The sidewalls of the gate structure 202 may also include sidewall structures. The source / drain structure 203 is located in the substrate 201 on both sides of the gate structure 202 and includes a source and a drain. The contact hole structure 204 is located on a portion of the source / drain structure 203. In this embodiment, the contact hole structure 204 is located in the dielectric layer 205 on the surface of a portion of the source / drain structure 203. The surfaces of the substrate 201, the source / drain structure 203, and the gate structure 202 also include the dielectric layer 205.

[0039] refer to Figure 6 The gate structure 202 is electrically connected to the first test pad 206, and the contact hole structure 204 is electrically connected to the second test pad 207. The gate structure 202 and the contact hole structure 204 are electrically connected to their respective test pads via conventional interconnect structures. The specific structure of these interconnect structures is designed according to actual conditions and will not be specifically described here. A first parasitic capacitance C is formed between the gate structure 202 and the substrate 201. GT-AA A second parasitic capacitance C is formed between the source / drain structure 203 and the gate structure 202. GT-SD A third parasitic capacitance C is formed between the contact hole structure 204 and the gate structure 202. GT-CT .

[0040] Continue to refer to Figure 4 In the second test structure, the contact hole structure 204 is located on a portion of the source / drain structure 203 and the number does not exceed two. The contact hole structure 204 and the gate structure 202 have a first horizontal spacing d1. Unlike the first test structure, the width of the substrate 201 on the side of the contact hole structure 204 away from the gate structure 202 is reduced from a first width W1 to a second width W2. The second width W2 can be a very small value, for example, 0.01 μm to 0.05 μm. In actual fabrication, the first width W1 can be reduced by etching the substrate 201 at the corresponding positions and filling the etched positions with insulating material.

[0041] According to the aforementioned capacitance calculation formula, the number of contact hole structures 204 is relatively small, and the area of ​​the opposing surfaces of a single contact hole structure 204 and the gate structure 202 is small. Therefore, the value of S in the formula can be considered to be 0, and thus the third parasitic capacitance C between the contact hole structure 204 and the gate structure 202 is... GT-CT It can be considered to be 0. Meanwhile, since the charge generated by voltage can easily travel a long distance in thinner materials, when the second width W2 is a small value, the dielectric constant ε of the substrate 201 will be very small, close to 0. Therefore, according to the capacitance calculation formula... The first parasitic capacitance C between the gate structure 202 and the substrate 201 GT-AA Within the tolerance range of capacitance testing, it can be considered to be 0. Therefore, when testing the second test structure, the second parasitic capacitance C is obtained. GT-SD The test results.

[0042] refer to Figure 7 and Figure 8 ,in Figure 7 This is a top view of the third test structure according to an embodiment of this application, with the dielectric layer omitted. Figure 8 for Figure 7 A cross-sectional view at the CC position is shown, illustrating the location of the dielectric layer. The third test structure includes a gate structure 302, a source / drain structure 303, and a contact hole structure 304. The gate structure 302 is located on the substrate 301. The gate structure 302 can be a conventional structure, for example, it may include a gate oxide layer on the substrate 301 and a gate layer on the surface of the gate oxide layer. The sidewalls of the gate structure 302 may also include sidewall structures. The source / drain structure 303 may be located in the substrate 301 on both sides of the gate structure 302. Unlike the first and second test structures, the contact hole structure 304 of the third test structure is located on a portion of the substrate 301. Specifically, the contact hole structure 304 is located in the dielectric layer 305 on a portion of the surface of the substrate 303. The surfaces of the substrate 301, the gate structure 302, and the source / drain structure 303 are also formed with a dielectric layer 305 for electrical insulation.

[0043] refer to Figure 9 The gate structure 302 is electrically connected to the first test pad 306, and the contact hole structure 304 is electrically connected to the second test pad 307. The gate structure 302 and the contact hole structure 304 are electrically connected to their respective test pads via conventional interconnect structures. The specific structure of these interconnect structures is designed according to actual conditions and will not be specifically described here. A first parasitic capacitance C is formed between the gate structure 302 and the substrate 301. GT-AAA second parasitic capacitance C is formed between the source / drain structure 303 and the gate structure 302. GT-SD A third parasitic capacitance C is formed between the contact hole structure 304 and the gate structure 302. GT-CT .

[0044] Continue to refer to Figure 7 Unlike the first and second test structures, the third test structure has more than two contact hole structures 304. For example, the number of contact hole structures 304 is nine. Simultaneously, the contact hole structures 304 of the third test structure have a second horizontal spacing d2 with the gate structure 302, and the second horizontal spacing d2 is greater than the first horizontal spacing d1, for example, the second horizontal spacing d2 is not less than 5 μm. In some embodiments, the second horizontal spacing d2 can be 5 μm to 10 μm. The substrate 301 on the side of the contact hole structure 304 away from the gate structure 302 has a second width W2, which is relatively narrow, for example, 0.01 μm to 0.05 μm.

[0045] According to the formula for calculating capacitance When the spacing d between the planes is large, the capacitance C tends to be 0. Therefore, when the second horizontal spacing d2 of the third test structure is large, the third parasitic capacitance C between the contact hole structure 304 and the gate structure 302 increases. GT-CT Within the tolerance range of capacitance testing, it can be considered to be 0. Meanwhile, similar to the second test structure, the width (i.e., the second width W2) of the substrate 301 on the side of the contact hole structure 304 away from the gate structure 302 is narrower, resulting in a narrower first parasitic capacitance C between the gate structure 302 and the substrate 301. GT-AA Within the tolerance range of capacitance testing, it can be considered to be 0. Therefore, when performing capacitance testing using the third test structure, the obtained value is the second parasitic capacitance C. GT-SD The test results.

[0046] In summary, the first parasitic capacitance C can be obtained through the first test structure. GT-AA and the second parasitic capacitance C GT-SD The sum of these values, along with the second parasitic capacitance C obtained through the second test structure, allows us to obtain the second parasitic capacitance C. GT-SD Therefore, it can be achieved through the first parasitic capacitance C GT-AA and the second parasitic capacitance C GT-SD The sum of the two parasitic capacitances C GT-SD The difference is used to obtain the first parasitic capacitance C. GT-AA .

[0047] The second parasitic capacitance C can be obtained through the third test structure.GT-SD The first parasitic capacitance C can be obtained through traditional test structures and methods. GT-AA Second parasitic capacitance C GT-SD and the third parasitic capacitance C GT-CT The sum of these values ​​will be used to calculate the first parasitic capacitance C. GT-AA Second parasitic capacitance C GT-SD and the third parasitic capacitance C GT-CT The sum of the first parasitic capacitance C GT-AA The second parasitic capacitance C GT-SD By subtracting the values, the third parasitic capacitance C can be obtained. GT-CT .

[0048] Therefore, the parasitic capacitance test structure of the present application embodiment can test a single parasitic capacitance, solving the problem that traditional test structures and methods can only test the sum of three parasitic capacitances.

[0049] In some embodiments, the test structure may further include a fourth test structure. (See reference) Figure 10 The fourth test structure differs from the first test structure only in the number of contact hole structures; all other structures are identical and will not be described further. The number of contact hole structures 404 in the fourth test structure is the same as the number of contact hole structures 304 in the third test structure. The first parasitic capacitance C can be obtained by testing the first and second test pads of the fourth test structure. GT-AA Second parasitic capacitance C GT-SD and the third parasitic capacitance C GT-CT Therefore, the fourth test structure, combined with the aforementioned first, second, and third test structures, can obtain the first parasitic capacitance C. GT-AA Second parasitic capacitance C GT-SD and the third parasitic capacitance C GT-CT Any type of capacitor in the system.

[0050] This application embodiment also provides a method for testing parasitic capacitance, which uses the aforementioned test structure for testing, and the test method includes:

[0051] Step S1: Test the first test structure to obtain the sum of the first parasitic capacitance and the second parasitic capacitance; test the second test structure to obtain the second parasitic capacitance; and then obtain the first parasitic capacitance.

[0052] Step S2: Test the third test structure to obtain the second parasitic capacitance;

[0053] Step S3: Obtain the sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance;

[0054] Step S4: Combine the sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance with the first parasitic capacitance and the second parasitic capacitance to obtain the third parasitic capacitance.

[0055] The order of steps S1 to S3 can be arbitrarily changed, as long as the first parasitic capacitance, the second parasitic capacitance, and the sum of the three parasitic capacitances are obtained before step S4.

[0056] When performing a capacitance test on the first test structure, the first test pad of the first test structure is grounded, and a bias voltage is applied to the second test pad. This bias voltage can be the operating voltage of the structure under test. In some embodiments, existing capacitance testing instruments, such as an LCR meter, can be used for the capacitance test. By connecting the first test pad of the first test structure to the ground terminal of the LCR meter and the second test pad to the voltage input terminal of the LCR meter, the first parasitic capacitance C can be measured. GT-AA and the second parasitic capacitance C GT-SD sum.

[0057] Similar to the testing method for the first test structure, when testing the second test structure, the first test pad of the second test structure is grounded (e.g., connected to the ground terminal of the LCR tester), and a bias voltage is applied to the second test pad of the second test structure (e.g., connected to the voltage input terminal of the LCR tester). The second parasitic capacitance C is then obtained. GT-SD .

[0058] Through the first parasitic capacitance C GT-AA and the second parasitic capacitance C GT-SD The sum minus the second parasitic capacitance C GTSD The first parasitic capacitance C can then be calculated. GT-AA .

[0059] The first parasitic capacitance C GT-AA Second parasitic capacitance C GT-SD and the third parasitic capacitance C GT-CT The sum can be obtained through conventional structures and testing methods, or it can be obtained by testing the aforementioned fourth test structure. The testing methods for the third and fourth test structures are similar to those for the first and second test structures, in which grounding is performed on the first test pad and a bias voltage is applied to the second test pad for testing.

[0060] Finally, the first parasitic capacitance C GT-AA Second parasitic capacitance C GT-SD and the third parasitic capacitance C GT-CTThe sum of the first parasitic capacitance C GT-AA The second parasitic capacitance C GT-SD By subtracting the values, the third parasitic capacitance C can be obtained. GT-CT .

[0061] In summary, the parasitic capacitance testing method using the embodiments of this application overcomes the problem that previous testing structures and methods could only obtain the sum of three types of parasitic capacitances and could not obtain individual parasitic capacitances. It can obtain the first parasitic capacitance C separately. GT-AA Second parasitic capacitance C GT-SD and the third parasitic capacitance C GT-CT This lays the foundation for subsequent analysis of the impact of individual parasitic capacitances on device performance.

[0062] After reading this application, those skilled in the art will understand that the foregoing content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0063] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. The terms "comprising," "containing," "including," or "comprises" as used in this application indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0064] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A test structure for parasitic capacitance, characterized in that, It includes a first test structure, a second test structure, and a third test structure; The first test structure, the second test structure, and the third test structure each include a gate structure located on a substrate, a source / drain structure located in the substrate, and a contact hole structure. The gate structure is electrically connected to a first test pad and forms a first parasitic capacitance with the substrate. The source / drain structure forms a second parasitic capacitance with the gate structure. The contact hole structure is electrically connected to a second test pad and forms a third parasitic capacitance with the gate structure. The first test structure is used to test the sum of the first parasitic capacitance and the second parasitic capacitance. In the first test structure, the contact hole structure is located on part of the source-drain structure and the number does not exceed two. The contact hole structure has a first horizontal spacing with the gate structure, and the substrate on the side of the contact hole structure away from the gate structure has a first width. The second test structure is used to test the second parasitic capacitance. In the second test structure, the contact hole structure is located on part of the source and drain structure and the number is no more than two. The contact hole structure has a first horizontal spacing with the gate structure. The substrate on the side of the contact hole structure away from the gate structure has a second width, and the second width is smaller than the first width. The third test structure is used to test the second parasitic capacitance. In the third test structure, the contact hole structure is located on a portion of the substrate and there are more than two of them. The contact hole structure and the gate structure have a second horizontal spacing, and the second horizontal spacing is greater than the first horizontal spacing. The substrate on the side of the contact hole structure away from the gate structure has the second width.

2. The test structure for parasitic capacitance according to claim 1, characterized in that, The first horizontal spacing is 28nm to 0.5μm.

3. The test structure for parasitic capacitance according to claim 1, characterized in that, The first width is 0.01μm to 5μm.

4. The test structure for parasitic capacitance according to claim 1, characterized in that, The second width is 0.01μm to 0.05μm.

5. The test structure for parasitic capacitance according to claim 1, characterized in that, The second horizontal spacing is not less than 5μm.

6. The test structure for parasitic capacitance according to claim 1, characterized in that, The test structure further includes a fourth test structure for testing the sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance, wherein the fourth test structure differs from the first test structure only in the number of contact hole structures, and the fourth test structure and the third test structure have the same number of contact hole structures.

7. A method for testing parasitic capacitance, characterized in that, The test structure according to any one of claims 1 to 5 is tested, and the test method includes: The first test structure is tested to obtain the sum of the first parasitic capacitance and the second parasitic capacitance. The second test structure is tested to obtain the second parasitic capacitance, and then the first parasitic capacitance is obtained. The third test structure is tested to obtain the second parasitic capacitance; The sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance is obtained; The third parasitic capacitance is obtained by combining the sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance, as well as the first parasitic capacitance and the second parasitic capacitance.

8. The method for testing parasitic capacitance according to claim 7, characterized in that, When performing a capacitance test, the first test pad is grounded and a bias voltage is applied to the second test pad.

9. The method for testing parasitic capacitance according to claim 8, characterized in that, The bias voltage is the operating voltage of the structure under test.

10. The method for testing parasitic capacitance according to claim 7, characterized in that, The fourth test structure is tested to obtain the sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance. The fourth test structure differs from the first test structure only in the number of contact hole structures, and the fourth test structure and the third test structure have the same number of contact hole structures.

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