Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate, a bit line contact structure, a first epitaxial layer, a bit line and a second epitaxial layer. The substrate has a bit line contact hole. The bit line contact structure is disposed in the bit line contact hole. The first epitaxial layer is epitaxially grown on a sidewall of the bit line contact structure. The bit line includes a connecting layer connected to the bit line contact structure. The second epitaxial layer is epitaxially grown on a sidewall of the connecting layer. The present disclosure can reduce the contact resistance and parasitic capacitance between the bit line contact structure and the bit line, thereby improving the electrical performance of the semiconductor structure, and increasing the reliability and yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers and other electronic devices, consisting of multiple memory cells. Each memory cell includes a storage capacitor and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The gate of the transistor is used to electrically connect to the word line. The source region of the transistor forms the bit line contact region to electrically connect to the bit line through a bit line contact structure. The drain region of the transistor forms the memory node contact region to electrically connect to the storage capacitor through a memory node contact structure.

[0003] However, with the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller and smaller. As semiconductor processes have entered the deep submicron stage, DRAM sizes are shrinking, and the dimensions of bit line contact structures and bit lines themselves are correspondingly reduced. For example, the aspect ratio of bit line contact holes is constantly increasing. After the bit line contact structure is formed, voids and other openings are prone to appear inside the bit line contact structure, affecting its electrical performance. Furthermore, the continuous miniaturization of bit line contact structures and bit lines also tends to result in larger contact resistance between the bit line contact structure and the bit line, and larger parasitic capacitances between the bit line contact structure and the bit line and their adjacent conductive structures, thus adversely affecting the electrical performance of semiconductor devices. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which can reduce the contact resistance between the bit line contact structure and the bit line, and reduce the parasitic capacitance between the bit line contact structure and the bit line and the adjacent conductive structure, thereby improving the electrical performance of the semiconductor structure and improving the reliability and yield of the semiconductor structure.

[0005] To achieve the above objectives, in one aspect, some embodiments of this disclosure provide a semiconductor structure. The semiconductor structure includes: a substrate, a bit line contact structure, a first epitaxial layer, a bit line, and a second epitaxial layer. The substrate has a bit line contact hole. The bit line contact structure is disposed within the bit line contact hole. The first epitaxial layer is epitaxial on the sidewall of the bit line contact structure. The bit line includes a connection layer connected to the bit line contact structure. The second epitaxial layer is epitaxial on the sidewall of the connection layer.

[0006] In some embodiments, the semiconductor structure further includes an isolation structure and sidewalls. The isolation structure is located on the sidewall of the first epitaxial layer. The sidewalls are located on the sidewall of the second epitaxial layer and the sidewall of the bit line not covered by the second epitaxial layer.

[0007] In some embodiments, the semiconductor structure further includes: a first silicide layer and a second silicide layer. The first silicide layer is located on the sidewall of the first epitaxial layer. The second silicide layer is located on the sidewall of the second epitaxial layer.

[0008] In some embodiments, the semiconductor structure further includes an isolation structure and sidewalls. The isolation structure is located on the sidewall of the first silicide layer. The sidewalls are located on the sidewall of the second silicide layer and the sidewall of the bit line not covered by the second epitaxial layer.

[0009] In some embodiments, the bit line further includes a conductive layer located on the side of the interconnect layer opposite to the substrate; wherein the orthographic projections of the first epitaxial layer and the second epitaxial layer on the substrate are at least within the orthographic projection range of the conductive layer on the substrate.

[0010] In some embodiments, the orthographic projection of the second epitaxial layer on the substrate lies within the orthographic projection of the conductive layer on the substrate, and there is a gap between the boundary of the orthographic projection of the second epitaxial layer on the substrate and the boundary of the orthographic projection of the conductive layer on the substrate.

[0011] In some embodiments, the semiconductor structure further includes a second silicide layer located on the sidewall of the second epitaxial layer; the orthogonal projection of the second silicide layer on the substrate is located within the orthogonal projection range of the conductive layer on the substrate.

[0012] In some embodiments, the thickness of the first epitaxial layer is greater than the thickness of the second epitaxial layer.

[0013] In some embodiments, the thickness of the second epitaxial layer is 2 nm to 10 nm.

[0014] In some embodiments, the height of the interconnect layer is 35% to 65% of the bit line height.

[0015] On the other hand, some embodiments of this disclosure provide a method for fabricating a semiconductor structure, used to fabricate the semiconductor structure described in the above embodiments. The fabrication method includes the following steps.

[0016] A substrate is provided on which a bit line contact structure and a bit line are sequentially formed; the bit line includes a connection layer connected to the bit line contact structure.

[0017] The bit line contact structure and the sidewalls of the connecting layer are re-etched back;

[0018] A first epitaxial layer is formed on the sidewall after the bit line contact structure is etched back, and a second epitaxial layer is formed on the sidewall after the connection layer is etched back.

[0019] In some embodiments, the preparation method further includes the following steps.

[0020] An isolation structure is formed on the sidewall of the first epitaxial layer.

[0021] Sidewalls are formed on the sidewalls of the second epitaxial layer and on the sidewalls of the bit lines not covered by the second epitaxial layer.

[0022] In some embodiments, the preparation method further includes the following steps.

[0023] A first silicide layer is formed covering the sidewalls of the first epitaxial layer.

[0024] A second silicide layer is formed covering the sidewalls of the second epitaxial layer.

[0025] In some embodiments, the preparation method further includes the following steps.

[0026] An isolation structure is formed on the sidewall of the first silicide layer.

[0027] Sidewalls are formed on the sidewalls of the second silicide layer and on the sidewalls of the bit lines not covered by the second epitaxial layer.

[0028] In some embodiments, the first epitaxial layer and the second epitaxial layer are formed by epitaxial growth using an evaporation growth process, a molecular beam epitaxy process, or a chemical vapor deposition process.

[0029] In some embodiments, the sidewall etch-back thickness of the bit line contact structure and the connection layer is 2nm to 10nm.

[0030] In some embodiments, the bit line further includes a conductive layer located on the side of the interconnect layer opposite to the substrate; the etchback of the bit line contact structure and the sidewalls of the interconnect layer is performed after the conductive layer is formed.

[0031] In some embodiments, after forming a first epitaxial layer on the sidewall of the bit line contact structure after etch-back and forming a second epitaxial layer on the sidewall of the interconnect layer after etch-back, the orthogonal projections of the first epitaxial layer and the second epitaxial layer on the substrate are at least within the orthogonal projection range of the conductive layer on the substrate.

[0032] In this embodiment, by etching back the sidewalls of the bit line contact structure and the sidewalls of the connecting layer in the bit line, the aforementioned pores can be exposed when internal pores are formed in the bit line contact structure and the connecting layer. These pores are then filled during the epitaxial growth of the first and second epitaxial layers, resulting in smooth-surfaced first and second epitaxial layers. This avoids the presence of pores within the bit line contact structure and the connecting layer, and also helps to reduce the contact resistance between the bit line contact structure and the bit line through the first and second epitaxial layers, as well as the parasitic capacitance between the bit line contact structure and the bit line and their adjacent conductive structures.

[0033] Furthermore, by forming a first silicide layer on the sidewall of the first epitaxial layer and a second silicide layer on the sidewall of the second epitaxial layer, the embodiments of this disclosure can effectively reduce the contact resistance between the bit line contact structure and the bit line, as well as the parasitic capacitance between the bit line contact structure and the bit line and their respective adjacent conductive structures. This further improves the electrical performance of the semiconductor structure, thereby enhancing its reliability and yield. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic cross-sectional view of a semiconductor structure provided in one embodiment;

[0036] Figure 2 This is a schematic diagram of another semiconductor structure provided in one embodiment;

[0037] Figure 3 for Figure 1 A schematic diagram of the fabrication process of the semiconductor structure shown.

[0038] Figure 4 This is a schematic cross-sectional view of the bit line contact structure and the structure obtained after forming the bit line, provided in one embodiment.

[0039] Figure 5 This is a cross-sectional schematic diagram of the structure obtained after the back-etching bit line contact structure and the connecting layer sidewall provided in one embodiment;

[0040] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming the first epitaxial layer and the second epitaxial layer in one embodiment;

[0041] Figure 7 This is a cross-sectional schematic diagram of the structure obtained after forming the first epitaxial layer and the second epitaxial layer in another embodiment;

[0042] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming the isolation structure and sidewalls in one embodiment;

[0043] Figure 9 for Figure 2 A schematic diagram of the fabrication process of the semiconductor structure shown.

[0044] Figure 10 This is a schematic cross-sectional view of the structure obtained after forming a first silicide layer and a second silicide layer in one embodiment.

[0045] Figure 11 This is a flowchart illustrating step S350 provided in one embodiment;

[0046] Figure 12 This is a schematic cross-sectional view of the structure obtained after forming a metal material layer in one embodiment;

[0047] Figure 13 This is a schematic cross-sectional view of the structure obtained after annealing a metal material layer, as provided in one embodiment.

[0048] Figure 14 This is a cross-sectional schematic diagram of the structure obtained after forming the isolation structure and sidewalls in another embodiment.

[0049] Explanation of reference numerals in the attached figures:

[0050] 1-Substrate, 10-Shallow trench isolation structure, 11-Bit line contact hole, 12-Dielectric layer,

[0051] 2-Bit line contact structure, 3-Bit line, 31-Connection layer, 32-First barrier layer, 33-Conductive layer

[0052] 34 - Top isolation layer, 41 - First epitaxial layer, 51 - Second epitaxial layer, 42 - First silicide layer,

[0053] 52 - Second silicide layer, 401 - Metal material layer, 402 - Residual metal material layer

[0054] 6-Isolation structure, 7-Sidewall, 8-Storage node contact structure, 80-Storage node contact hole

[0055] 81-First conductive layer, 82-Conductive transition layer, 83-Second barrier layer, 84-Second conductive layer, 9-Insulating layer

[0056] H - Height of the bit line, H1 - Height of the connector layer, H2 - Height of the first barrier layer

[0057] H3 - Height of the conductive layer, H4 - Height of the top insulating layer 34

[0058] T1 - Etching back thickness of the bit line contact structure sidewall; T2 - Etching back thickness of the connector layer sidewall.

[0059] D1 - Thickness of the first epitaxial layer, D2 - Thickness of the second epitaxial layer. Detailed Implementation

[0060] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0062] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0063] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0064] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0065] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0066] Please see Figure 1 This disclosure provides a semiconductor structure in some embodiments. The semiconductor structure includes: a substrate 1, a bit line contact structure 2, a bit line 3, a first epitaxial layer 41, and a second epitaxial layer 51. The substrate 1 has a bit line contact (BLC) via 11. The bit line contact structure 2 is disposed within the bit line contact via 11. The first epitaxial layer 41 is disposed on the sidewall of the bit line contact structure 2. The bit line 3 includes a connection layer 31 connected to the bit line contact structure 2. The second epitaxial layer 51 is disposed on the sidewall of the connection layer 31.

[0067] In some embodiments, substrate 1 may be composed of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 may be a single-layer structure or a multi-layer structure. For example, substrate 1 may be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0068] Optionally, substrate 1 is a silicon substrate or a silicon-based substrate, and substrate 1 has a shallow trench isolation structure 10, which isolates active regions within substrate 1. The shallow trench isolation structure 10 is, for example, a silicon oxide (SiO2) isolation structure. The shallow trench isolation structure 10 can isolate multiple active regions arranged in an array within substrate 1. Bit line contact holes 11 are disposed within the active regions of substrate 1. Bit line contact structures 2 fill the corresponding bit line contact holes 11. Bit line contact holes 11 can be circular holes, square holes, or irregularly shaped holes. This disclosure does not limit the shape and size of the bit line contact holes 11.

[0069] Optionally, the bit line 3 includes a connection layer 31, a first barrier layer 32, a conductive layer 33 and a top isolation layer 34 disposed sequentially along a direction away from the substrate 1.

[0070] In some embodiments, the connection layer 31 of the bit line 3 may be a doped polysilicon layer or a germanium-silicon layer with conductive properties. The bit line contact structure 2 may be the same as or different from the structure of the connection layer 31 in the bit line 3.

[0071] In one example, the connection layer 31 in bit line 3 and the bit line contact structure 2 are both doped polysilicon layers, and their doping concentrations can be the same.

[0072] In one example, the first barrier layer 32 is a titanium nitride layer or a titanium layer.

[0073] In one example, the conductive layer 33 is a tungsten metal layer, a copper metal layer, or a gold metal layer.

[0074] In one example, the top isolation layer 34 is a silicon nitride layer or a silicon oxynitride layer.

[0075] In one example, the portion of bit line 3 outside the connection layer 31 and bit line contact structure 2 is insulated from the substrate 1 by the dielectric layer 12. Optionally, the dielectric layer 12 can be an insulating layer such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. The thickness of the dielectric layer 12 can be selected and set according to actual needs.

[0076] In some embodiments, the height of the connection layer 31 is 35% to 65% of the height of the bit line 3. For example, the height of the connection layer 31 is 35%, 40%, 45%, 50%, 55%, 60%, or 65% of the height of the bit line 3.

[0077] In some embodiments, the first epitaxial layer 41 and the second epitaxial layer 51 can be formed by epitaxial growth on the corresponding sidewalls using evaporation growth, molecular beam epitaxy, or chemical vapor deposition. Furthermore, the first epitaxial layer 4 and the second epitaxial layer 5 can be epitaxial layers of the same material or epitaxial layers of different materials. The first epitaxial layer 4 and the second epitaxial layer 5 can be formed simultaneously or in stages.

[0078] Optionally, the first epitaxial layer 41 and the second epitaxial layer 51 can be a single-crystal silicon layer or a silicon germanide layer, respectively. However, they are not limited to this.

[0079] Optionally, the orthographic projections of the first epitaxial layer 41 and the second epitaxial layer 51 on the substrate 1 are at least within the orthographic projection range of the conductive layer 33 on the substrate 1.

[0080] Here, the orthographic projections of the first epitaxial layer 41 and the second epitaxial layer 51 on the substrate 1 are at least within the orthographic projection range of the conductive layer 33 on the substrate 1, including: both the first epitaxial layer 41 and the second epitaxial layer 51 include a portion located directly below (i.e., vertically below) the conductive layer 33, or, in addition to the portion located directly below (i.e., vertically below) the conductive layer 33, the first epitaxial layer 41 and / or the second epitaxial layer 51 also include a portion whose orthographic projection is located outside the orthographic projection of the conductive layer 33 on the substrate 1.

[0081] In one example, the orthographic projection of the second epitaxial layer 51 on the substrate 1 lies within the orthographic projection of the conductive layer 33 on the substrate 1, and there is a gap between the boundary of the orthographic projection of the second epitaxial layer 51 on the substrate 1 and the boundary of the orthographic projection of the conductive layer 33 on the substrate 1.

[0082] Therefore, the thickness of the first epitaxial layer 41 and the thickness of the second epitaxial layer 51 can be the same or different.

[0083] In one example, the thickness of the first epitaxial layer 41 is equal to the thickness of the second epitaxial layer 51.

[0084] In one example, the thickness of the first epitaxial layer 41 is greater than the thickness of the second epitaxial layer 51.

[0085] Optionally, the thickness of the second epitaxial layer 51 is in the range of 2nm to 10nm. For example, the thickness of the second epitaxial layer 51 is 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm.

[0086] Please continue reading. Figure 1 In some embodiments, the semiconductor structure further includes an isolation structure 6 and a sidewall 7. The isolation structure 6 is disposed on the sidewall of the first epitaxial layer 41. The sidewall 7 is disposed on the sidewall of the second epitaxial layer 51 and on the sidewall of the bit line 3 not covered by the second epitaxial layer 51.

[0087] Optionally, the isolation structure 6 is formed of a dielectric material with a high dielectric constant, such as a single dielectric layer or a stack of multiple dielectric layers. The isolation structure 6 is used to insulate the corresponding bit line contact structure 2, and the isolation structure 6 is disposed on the sidewall of the first epitaxial layer 41; that is, the first epitaxial layer 41 can be a component of the equivalent bit line contact structure to ensure that the dimensions of the equivalent bit line contact structure can meet the design requirements. (The equivalent bit line contact structure can be formed by the bit line contact structure 2 and the first epitaxial layer 41 together).

[0088] Optionally, the sidewall 7 can be formed of a dielectric material with a low dielectric constant, such as a single dielectric layer or a stack of multiple dielectric layers. The sidewall 7 serves to insulate the corresponding bit line 3, and it covers the second epitaxial layer 51 and the sidewall of the bit line 3; that is, the second epitaxial layer 51 can be a component of the equivalent bit line to ensure that the dimensions of the equivalent bit line meet design requirements. (The equivalent bit line can be formed by the bit line 3 and the second epitaxial layer 51 together). Furthermore, the thickness of the sidewall 7 can be selected according to actual needs.

[0089] In one example, the isolation structure 6 and the sidewall 7 are respectively constructed by stacking a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer.

[0090] Please continue reading. Figure 1 In some embodiments, the semiconductor structure further includes a memory node contact structure 8. The memory node contact structure 8 is insulated from the first epitaxial layer 41 through the isolation structure 6, and is insulated from the second epitaxial layer 51 through the sidewall 7.

[0091] Optionally, the storage node contact structure 8 includes a first conductive layer 81, a conductive transition layer 82, a second barrier layer 83, and a second conductive layer 84 sequentially stacked along a direction away from the substrate 1. However, it is not limited to this. The first conductive layer 81 is, for example, a doped polysilicon layer. The conductive transition layer 82 is, for example, a cobalt silicide layer. The second barrier layer 83 is, for example, a titanium nitride layer. The second conductive layer 84 is, for example, a tungsten metal layer.

[0092] Optionally, an insulating layer 9 is further provided between adjacent storage node contact structures 8. The insulating layer 9 can be a silicon nitride layer, such as one or more silicon nitride layers. Here, the insulating layer 9 refers to the entire insulating portion located between adjacent storage node contact structures 8.

[0093] In this embodiment, by etching back the sidewalls of the bit line contact structure 2 and the sidewalls of the connecting layer 31 in the bit line 3, the aforementioned pores (unnecessary pores caused by the fabrication process) can be easily exposed in the event that the bit line contact structure 2 and the connecting layer 31 have internal pores. These pores are then filled during the epitaxial growth of the first epitaxial layer 41 and the second epitaxial layer 51, resulting in smooth surfaces on the first epitaxial layer 41 and the second epitaxial layer 51. This avoids the presence of pores inside the bit line contact structure 2 and the connecting layer 31, and also helps to reduce the contact resistance between the bit line contact structure 2 and the bit line 3 through the first epitaxial layer 41 and the second epitaxial layer 51, as well as the parasitic capacitance between the bit line contact structure 2 and the bit line 3 and their adjacent conductive structures. This improves the electrical performance of the semiconductor structure, thereby increasing its reliability and yield.

[0094] Furthermore, in this embodiment, by controlling the epitaxial thickness of the first epitaxial layer 41 and the second epitaxial layer 51, while ensuring that the design dimensions of the bit line 3 and the bit line contact hole 11 remain unchanged, not only can the contact resistance between the bit line 3 and the bit line contact structure 2 be reduced, but the distance between the bit line contact structure 2 and the bit line 3 and the adjacent conductive structure can also be increased, thereby effectively reducing parasitic capacitance. This further improves the electrical performance of the semiconductor structure, thereby further enhancing the reliability and yield of the semiconductor structure.

[0095] Please see Figure 2 This disclosure also provides a semiconductor structure in some embodiments. The semiconductor structure includes: a substrate 1, a bit line contact structure 2, a bit line 3, a first epitaxial layer 41, a second epitaxial layer 51, a first silicide layer 42, and a second silicide layer 52. The arrangement of the substrate 1, bit line contact structure 2, bit line 3, first epitaxial layer 41, and second epitaxial layer 51 can be found in the descriptions in the foregoing embodiments, and will not be detailed here. The first silicide layer 42 is located on the sidewall of the first epitaxial layer 41. The second silicide layer 52 is located on the sidewall of the second epitaxial layer 51.

[0096] Based on this, in embodiments where the semiconductor structure also includes an isolation structure 6 and a sidewall 7, the isolation structure 6 is located on the sidewall of the first silicide layer 42. The sidewall 7 is located on the sidewall of the second silicide layer 52 and the sidewall of the bit line 3 not covered by the second epitaxial layer 51. Furthermore, the structures of the isolation structure 6 and the sidewall 7 can be found in the relevant descriptions of some of the foregoing embodiments, and will not be detailed further.

[0097] Correspondingly, the bit line contact structure 2, the first epitaxial layer 41, and the first silicide layer 42 can together constitute an equivalent bit line contact structure. The bit line 3, the second epitaxial layer 51, and the second silicide layer 52 can together constitute an equivalent bit line.

[0098] This embodiment of the disclosure forms a first silicide layer 42 on the sidewall of the first epitaxial layer 41 and a second silicide layer 52 on the sidewall of the second epitaxial layer 51. The first silicide layer 42 and the second silicide layer 52 can effectively reduce the contact resistance between the bit line contact structure 2 and the bit line 3, as well as the parasitic capacitance between the bit line contact structure 2 and the bit line 3 and their respective adjacent conductive structures. This further improves the electrical performance of the semiconductor structure, thereby enhancing its reliability and yield.

[0099] The first silicide layer 42 and the second silicide layer 52 can be the same silicide layer or different silicide layers. Accordingly, the first silicide layer 42 and the second silicide layer 52 can be formed simultaneously or in stages. This embodiment does not limit this.

[0100] In some embodiments, the orthographic projections of the first silicide layer 42 and the second silicide layer 52 onto the substrate 1 are at least within the orthographic projection range of the conductive layer 33 onto the substrate 1.

[0101] Optionally, the orthographic projection of the second silicide layer 52 onto the substrate 1 lies within the orthographic projection range of the conductive layer 33 onto the substrate 1. For example, there is a gap between the boundary of the orthographic projection of the second silicide layer 52 onto the substrate 1 and the boundary of the orthographic projection of the conductive layer 33 onto the substrate 1.

[0102] In this embodiment of the disclosure, by setting the thickness of the first silicide layer 42 and the second silicide layer 52, while ensuring that the design dimensions of the bit line 3 and the bit line contact hole 11 remain unchanged, not only can the contact resistance between the bit line 3 and the bit line contact structure 2 be reduced, but the distance between the bit line contact structure 2 and the bit line 3 and the adjacent conductive structure can also be increased, so as to effectively reduce parasitic capacitance.

[0103] Please continue reading. Figure 2 In embodiments where the semiconductor structure also includes a memory node contact structure 8, the memory node contact structure 8 is insulated from the first silicide layer 42 by an isolation structure 6, and is insulated from the second silicide layer 52 by a sidewall 7. An insulating layer 9 is also provided between adjacent memory node contact structures 8. The structures of the memory node contact structure 8 and the insulating layer 9 can be found in the relevant descriptions of some of the foregoing embodiments, and will not be detailed here.

[0104] Please see Figure 3 This disclosure provides a method for fabricating a semiconductor structure, using some embodiments thereof, for preparing such a semiconductor structure. Figure 1 The semiconductor structure shown is fabricated using the following steps.

[0105] S100, a substrate is provided, on which bit line contact structures and bit lines are sequentially formed. The bit lines include a connection layer connected to the bit line contact structures.

[0106] S200, the sidewall of the back-etching line contact structure and the connecting layer.

[0107] S300, a first epitaxial layer is formed on the sidewall after the bit line contact structure is etched back, and a second epitaxial layer is formed on the sidewall after the connecting layer is etched back.

[0108] In this embodiment, by etching back the sidewalls of the bit line contact structure and the sidewalls of the connecting layer in the bit line, the aforementioned pores can be exposed when internal pores are formed in the bit line contact structure and the connecting layer. These pores are then filled during the epitaxial growth of the first and second epitaxial layers, resulting in smooth-surfaced first and second epitaxial layers. This avoids the presence of pores within the bit line contact structure and the connecting layer, and also helps to reduce the contact resistance between the bit line contact structure and the bit line through the first and second epitaxial layers, as well as the parasitic capacitance between the bit line contact structure and the bit line and their adjacent conductive structures.

[0109] In step S100, please refer to Figure 3 S100 and Figure 4 A substrate 1 is provided, on which bit line contact structures 2 and bit lines 3 are sequentially formed. The bit line 3 includes a connection layer 31 connected to the bit line contact structure 2.

[0110] In one example, substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate. Substrate 1 has a shallow trench isolation structure 10, which isolates active regions within substrate 1. Optionally, the shallow trench isolation structure 10 is a silicon oxide (SiO2) isolation structure. The shallow trench isolation structure 10 can isolate multiple active regions arranged in an array within substrate 1.

[0111] It is understood that in some embodiments, please refer to [the documentation / reference]. Figure 4 Bit line contact (BLC) holes 11 are disposed in the active region on the substrate 1, and bit line contact structures 2 fill the corresponding bit line contact holes 11. The bit line contact holes 11 can be round holes, square holes, or irregularly shaped holes. The embodiments of this disclosure do not limit the shape and size of the bit line contact holes 11.

[0112] In some embodiments, the connection layer 31 of the bit line 3 can be formed using a conductive material such as doped polysilicon or germanium-silicon. The material of the bit line contact structure 2 can be the same as or different from the material of the connection layer 31 in the bit line 3. Alternatively, the material of the bit line contact structure 2 can be the same as the material of the connection layer 31 in the bit line 3, but the doping concentrations of the two can be different, the etching rates during their formation can be different, and the etching rates when their sidewalls are etched back can also be different. The specific settings can be selected according to actual needs. This disclosure does not limit these aspects, nor does it limit the shape of the bit line contact structure 2 and the connection layer 31 after etching.

[0113] In one example, please refer to [link / reference]. Figure 4 The portion of bit line 3 outside the connection between the connecting layer 31 and the bit line contact structure 2 is insulated from the substrate 1 by the dielectric layer 12. Optionally, the dielectric layer 12 can be an insulating layer such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. The thickness of the dielectric layer 12 can be selected and set according to actual needs.

[0114] In one example, the connection layer 31 in bit line 3 and the bit line contact structure 2 are both doped polysilicon layers, and their doping concentrations can be the same.

[0115] It is understood that in some embodiments, please refer to [the documentation / reference]. Figure 4 The bit line 3 also includes a first barrier layer 32, a conductive layer 33 and a top isolation layer 34, which are sequentially disposed on one side of the connection layer 31 along the direction away from the substrate 1.

[0116] Optionally, the first barrier layer 32 may include, but is not limited to, a titanium nitride layer. For example, the first barrier layer 32 may also be a titanium layer.

[0117] Optionally, the conductive layer 33 may include, but is not limited to, a tungsten metal layer. For example, the conductive layer 33 may also be a copper metal layer or a gold metal layer.

[0118] Optionally, the top isolation layer 34 may include, but is not limited to, a silicon nitride layer. For example, the top isolation layer 34 may also be a silicon oxynitride layer.

[0119] The first barrier layer 32, the conductive layer 33, and the top isolation layer 34 can all be obtained by patterning each material layer after deposition using a patterning process. Optionally, the top isolation layer 34 can be formed using a hard mask material to serve as a hard mask during the formation of the conductive layer 33, the first barrier layer 32, and the connecting layer 31.

[0120] Here, the deposition process includes, but is not limited to, low-pressure chemical vapor deposition (LPCVD), high-density plasma chemical vapor deposition (HDPCVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer chemical vapor deposition (ALCVD). The patterning process includes, but is not limited to, wet etching or dry etching, wherein dry etching includes at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-concentration plasma etching (HDP).

[0121] In some embodiments, the height of the connection layer 31 is 35% to 65% of the height of the bit line 3. For example, the height of the connection layer 31 is 35%, 40%, 45%, 50%, 55%, 60%, or 65% of the height of the bit line 3.

[0122] Please see here. Figure 4 In the example where bit line 3 adopts the aforementioned structure, the height H of bit line 3 refers to the sum of the heights of the connecting layer 31, the first barrier layer 32, the conductive layer 33, and the top isolation layer 34; that is, H = H1 + H2 + H3 + H4, where H1 is the height of the connecting layer 31, H2 is the height of the first barrier layer 32, H3 is the height of the conductive layer 33, and H4 is the height of the top isolation layer 34.

[0123] In step S200, please refer to Figure 3 S200 and Figure 5 The sidewalls of the back-etched position line contact structure 2 and the connecting layer 31.

[0124] Here, based on the materials used to form the bit line contact structure 2 and the connecting layer 31, an appropriate etching process can be selected for the etch-back process. The etching process includes, but is not limited to, wet etching or dry etching. Among them, dry etching can include at least any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-concentration plasma etching (HDP).

[0125] Furthermore, the etching thickness of the sidewalls of both the bit line contact structure 2 and the connecting layer 31 can be selected according to actual needs. Also, the etching thickness of the sidewalls of both the bit line contact structure 2 and the connecting layer 31 can be the same or different.

[0126] Optionally, the etch-back thickness of the sidewalls of the bit line contact structure 2 and the connecting layer 31 ranges from 2 nm to 10 nm. For example, please refer to... Figure 2 The etch-back thickness T1 of the sidewall of bit line contact structure 2 is 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, or 10nm. For example, the etch-back thickness T2 of the sidewall of interconnect layer 31 is 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, or 10nm.

[0127] In addition, please combine Figure 5 It is understood that the bit line contact structure 2 is formed within the bit line contact hole 11, and the etching of the sidewall of the bit line contact structure 2 can be performed by forming a trench G on its side, which is used, for example, to fill the isolation material to form an isolation structure corresponding to the bit line contact structure 2.

[0128] In step S300, please refer to Figure 3 S300 and Figure 6 A first epitaxial layer 41 is formed on the sidewall after the bit line contact structure 2 is etched, and a second epitaxial layer 51 is formed on the sidewall after the connecting layer 31 is etched.

[0129] Here, the first epitaxial layer 41 and the second epitaxial layer 51 can be epitaxial layers of the same material or epitaxial layers of different materials. Correspondingly, the first epitaxial layer 41 and the second epitaxial layer 51 can be formed simultaneously or in stages. This embodiment of the present disclosure does not limit this.

[0130] Optionally, the first epitaxial layer 41 and the second epitaxial layer 51 are formed by epitaxial growth using evaporation, molecular beam epitaxy, or chemical vapor deposition. However, they are not limited to these methods. The first epitaxial layer 41 and the second epitaxial layer 51 can form smooth surfaces through epitaxial growth.

[0131] In some embodiments, please combine Figure 6 and Figure 7 It is understood that the bit line 3 also includes a conductive layer 33 located on the side of the interconnect layer 31 opposite to the substrate 1. The first epitaxial layer 41 is formed on the sidewall of the bit line contact structure 2 after it has been etched back, and the second epitaxial layer 51 is formed on the sidewall of the interconnect layer 31 after it has been etched back. The orthogonal projections of the first epitaxial layer 41 and the second epitaxial layer 51 on the substrate 1 are at least within the orthogonal projection range of the conductive layer 33 on the substrate 1.

[0132] Here, the orthographic projections of the first epitaxial layer 41 and the second epitaxial layer 51 on the substrate 1 are at least within the orthographic projection range of the conductive layer 33 on the substrate 1, including: both the first epitaxial layer 41 and the second epitaxial layer 51 include a portion located directly below (i.e., vertically below) the conductive layer 33, or, in addition to the portion located directly below (i.e., vertically below) the conductive layer 33, the first epitaxial layer 41 and / or the second epitaxial layer 51 also include a portion whose orthographic projection is located outside the orthographic projection of the conductive layer 33 on the substrate 1.

[0133] In one example, such as Figure 7 As shown, the orthographic projection of the second epitaxial layer 51 on the substrate 1 is located within the orthographic projection of the conductive layer 33 on the substrate 1, and there is a gap W between the boundary of the orthographic projection of the second epitaxial layer 51 on the substrate 1 and the boundary of the orthographic projection of the conductive layer 33 on the substrate 1.

[0134] From the above, we can combine Figure 6 and Figure 7 Understand that the thickness D1 of the first epitaxial layer 41 and the thickness D2 of the second epitaxial layer 51 can be the same or different. See one example. Figure 6 The thickness D1 of the first epitaxial layer 41 is equal to the thickness D2 of the second epitaxial layer 51. See [example example] for details. Figure 7 The thickness D1 of the first epitaxial layer 41 is greater than the thickness D2 of the second epitaxial layer 51. Here, the thickness D1 of the first epitaxial layer 41 is greater than the thickness D2 of the second epitaxial layer 51, which can be achieved by adjusting the corresponding process parameters, such as controlling the growth temperature, the pressure inside the reaction chamber, the concentration of the reaction gas source, and the gas flow rate, thereby achieving precise control of the epitaxial layer thickness.

[0135] In this embodiment, by adjusting the thickness of the first epitaxial layer 41 and the second epitaxial layer 51, the contact resistance between the bit line 3 and the bit line contact structure 2 can be reduced while ensuring that the design dimensions of the bit line 3 and the bit line contact hole 11 remain unchanged. Furthermore, the distance between the bit line contact structure 2 and the bit line 3 and adjacent conductive structures can be increased, thereby effectively reducing parasitic capacitance. This further improves the electrical performance of the semiconductor structure, thereby enhancing its reliability and yield.

[0136] Please continue reading. Figure 3 In some embodiments, after forming the first epitaxial layer 41 and the second epitaxial layer 51 in step S300, the preparation method further includes the following steps.

[0137] S400, an isolation structure is formed on the sidewall of the first epitaxial layer.

[0138] S500, sidewalls are formed on the sidewalls of the second epitaxial layer and on the sidewalls of the bit lines that are not covered by the second epitaxial layer.

[0139] It should be understood here that there is no strict order restriction for the execution of steps S400 and S500; these steps can be executed simultaneously or in other orders. Furthermore, in this embodiment of the invention, at least a portion of each step in the preparation method may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0140] In step S400, please refer to Figure 8 An isolation structure 6 is formed on the sidewall of the first epitaxial layer 41.

[0141] The aforementioned isolation structure 6 can be formed using a dielectric material with a high dielectric constant. For example, the isolation structure 6 can be a single dielectric layer or a stack of multiple dielectric layers. The isolation structure 6 can be formed by filling the trench G in the aforementioned example. The isolation structure 6 is used to insulate the corresponding bit line contact structure 2, and the isolation structure 6 covers the sidewall of the first epitaxial layer 41; that is, the first epitaxial layer 41 can be a component of the equivalent bit line contact structure to ensure that the dimensions of the equivalent bit line contact structure meet the design requirements. (The equivalent bit line contact structure can be formed by the bit line contact structure 2 and the first epitaxial layer 41 together).

[0142] In step S500, please continue reading. Figure 8 Sidewalls 7 are formed on the sidewalls of the second epitaxial layer 51 and on the sidewalls of the position line 3 that are not covered by the second epitaxial layer 51.

[0143] The sidewall 7 can be formed of a dielectric material with a low dielectric constant, such as a single dielectric layer or a stack of multiple dielectric layers. The sidewall 7 is used to insulate the corresponding bit line 3, and it covers the second epitaxial layer 51 and the sidewall of the bit line 3; that is, the second epitaxial layer 51 can be a component of the equivalent bit line to ensure that the dimensions of the equivalent bit line meet design requirements. Furthermore, the thickness of the sidewall 7 can be selected according to actual needs.

[0144] Optionally, the isolation structure 6 and the sidewall 7 are respectively constructed by stacking a first silicon nitride layer, a silicon oxide layer, and a second silicon nitride layer. The isolation structure 6 and the sidewall 7 can be formed simultaneously.

[0145] In this embodiment, the formation of the first epitaxial layer 41 and the second epitaxial layer 51 is arranged before the formation of the isolation structure 6 corresponding to the bit line contact structure 2 and the sidewall 7 corresponding to the bit line 3. This simplifies the semiconductor structure fabrication process and reduces the difficulty of semiconductor structure fabrication, thereby improving the production efficiency and yield of semiconductor structures.

[0146] Please combine Figure 1 , Figure 3 and Figure 8 It is understood that in some embodiments, the fabrication method further includes: S600, forming a storage node contact structure 8. The storage node contact structure 8 is insulated from the first epitaxial layer 41 by an isolation structure 6, and the storage node contact structure 8 is insulated from the second epitaxial layer 51 by a sidewall 7.

[0147] It is understood that the storage node contact structure 8 is typically formed within the corresponding storage node contact hole 80. For example, the storage node contact hole 80 can be formed on the resulting structure after the isolation structure 6 and the sidewall 7 are formed, so as to form the storage node contact structure 8 within the storage node contact hole 80, and to form an insulating layer 9 between adjacent storage node contact structures 8, so as to effectively insulate adjacent storage node contact structures 8 using the insulating layer 9.

[0148] Optionally, the storage node contact structure 8 includes a first conductive layer 81, a conductive transition layer 82, a second barrier layer 83, and a second conductive layer 84 sequentially stacked along a direction away from the substrate 1. However, it is not limited to this. The first conductive layer 81 is, for example, a doped polysilicon layer. The conductive transition layer 82 is, for example, a cobalt silicide layer. The second barrier layer 83 is, for example, a titanium nitride layer. The second conductive layer 84 is, for example, a tungsten metal layer.

[0149] Optionally, the insulating layer 9 can be a silicon nitride layer, such as one or more silicon nitride layers. Furthermore, the insulating layer 9 can be formed in one step or gradually stacked during the fabrication of other layer structures. That is, the insulating layer 9 here refers to the entire insulating portion located between adjacent memory node contact structures 8.

[0150] Please see Figure 9 This disclosure also provides another method for fabricating semiconductor structures, such as... Figure 2 The semiconductor structure shown is fabricated using the following steps.

[0151] S100, a substrate is provided, on which bit line contact structures and bit lines are sequentially formed. The bit lines include a connection layer connected to the bit line contact structures.

[0152] S200, the sidewall of the back-etching line contact structure and the connecting layer.

[0153] S300, a first epitaxial layer is formed on the sidewall after the bit line contact structure is etched back, and a second epitaxial layer is formed on the sidewall after the connecting layer is etched back.

[0154] S350, a first silicide layer is formed covering the sidewalls of the first epitaxial layer; a second silicide layer is formed covering the sidewalls of the second epitaxial layer.

[0155] This embodiment of the disclosure forms a first silicide layer on the sidewall of the first epitaxial layer and a second silicide layer on the sidewall of the second epitaxial layer. The first and second silicide layers effectively reduce the contact resistance between the bit line contact structure and the bit lines, as well as the parasitic capacitance between the bit line contact structure and each bit line and its adjacent conductive structure. This further improves the electrical performance of the semiconductor structure, thereby enhancing its reliability and yield.

[0156] The steps S100 to S300 described above can be performed by referring to the corresponding steps in some of the foregoing embodiments. The following only describes the differences between this embodiment and the foregoing embodiments.

[0157] In step S350, please refer to Figure 9 S350 and Figure 10 A first silicide layer 42 is formed covering the sidewalls of the first epitaxial layer 41; a second silicide layer 52 is formed covering the sidewalls of the second epitaxial layer 51.

[0158] The first silicide layer 42 and the second silicide layer 52 can be the same silicide layer or different silicide layers. Accordingly, the first silicide layer 42 and the second silicide layer 52 can be formed simultaneously or in stages. This embodiment does not limit this.

[0159] In some embodiments, please continue reading Figure 10 The orthographic projections of the first silicide layer 42 and the second silicide layer 52 onto the substrate 1 are at least within the orthographic projection range of the conductive layer 33 onto the substrate 1.

[0160] Here, the orthographic projection of the first silicide layer 42 and the second silicide layer 52 on the substrate 1 is at least within the orthographic projection range of the conductive layer 33 on the substrate 1, including: both the first silicide layer 42 and the second silicide layer 52 include a portion located directly below (i.e. vertically below) the conductive layer 33, or, in addition to the portion located directly below (i.e. vertically below) the conductive layer 33, the first silicide layer 42 and / or the second silicide layer 52 also include a portion whose orthographic projection is located outside the orthographic projection of the conductive layer 33 on the substrate 1.

[0161] Optionally, the orthographic projection of the second silicide layer 52 on the substrate 1 lies within the orthographic projection of the conductive layer 33 on the substrate 1. For example, there is a gap between the boundary of the orthographic projection of the second silicide layer 52 on the substrate 1 and the boundary of the orthographic projection of the conductive layer 33 on the substrate 1.

[0162] Optionally, the thickness of the first silicide layer 42 and the thickness of the second silicide layer 52 can be the same or different. For example, the thickness of the first silicide layer 42 is equal to the thickness of the second silicide layer 52. Or, for example, the thickness of the first silicide layer 42 is greater than the thickness of the second silicide layer 52.

[0163] In this embodiment, by adjusting the thickness of the first silicide layer 42 and the second silicide layer 52, the contact resistance between the bit line 3 and the bit line contact structure 2 can be reduced while ensuring that the design dimensions of the bit line 3 and the bit line contact hole 11 remain unchanged. Furthermore, the distance between the bit line contact structure 2 and the bit line 3 and adjacent conductive structures can be increased, thereby effectively reducing parasitic capacitance. This further improves the electrical performance of the semiconductor structure, thereby enhancing its reliability and yield.

[0164] It is worth mentioning that the first silicide layer 42 and the second silicide layer 52 can be formed simultaneously or in stages. Furthermore, the first silicide layer 42 and the second silicide layer 52 can be deposited directly or obtained by performing a metallization process on a silicon-based material (such as single-crystal silicon or silicon germanide). In addition, the first silicide layer 42 and the second silicide layer 52 can be a single-layer structure or a multi-layer structure, which can be selected according to actual needs.

[0165] For ease of description, the following embodiments use single-crystal silicon layers as examples to illustrate the preparation process of the first silicide layer 42 and the second silicide layer 52.

[0166] Please see Figure 11 In some embodiments, step S350, forming a first silicide layer covering the sidewalls of the first epitaxial layer and forming a second silicide layer covering the sidewalls of the second epitaxial layer, includes the following steps.

[0167] S351, a metallic material layer is deposited on the sidewalls of the first epitaxial layer and the second epitaxial layer.

[0168] S352, the obtained structure is annealed to obtain a first silicide layer and a second silicide layer.

[0169] S353, removes residual metal material layers.

[0170] In step S351, please refer to Figure 11 S351 and Figure 12 A metal material layer 401 is deposited on the sidewalls of the first epitaxial layer 41 and the second epitaxial layer 51.

[0171] Here, the metal material layer 401 is, for example, a single metal layer or a metal compound layer. Alternatively, the metal material layer 401 may be a single material layer or multiple material layers. Optionally, the metal material layer 401 may be a tantalum (Ta) metal layer, a stack of tantalum (Ta) and tantalum titanate (TaTi), a tungsten nitride (WN) material layer, or a cobalt (Co) metal layer, etc.

[0172] In step S352, please refer to Figure 11 S352 and Figure 13 ,right Figure 12 The structure shown is subjected to annealing to obtain a first silicide layer 42 and a second silicide layer 52.

[0173] Here, it can be understood that, in relation to Figure 12 After the structure shown is annealed, the portion of the metal material layer 401 located on the sidewalls of the first epitaxial layer 41 and the second epitaxial layer 51 can be converted into a silicide layer.

[0174] Optionally, the annealing temperature for annealing the obtained structure is 300℃ to 700℃. For example, the annealing temperature can be 300℃, 400℃, 500℃, 600℃ or 700℃.

[0175] In step S353, please refer to Figure 11 S353 and Figure 13 Remove the residual metal material layer 402.

[0176] Here, the residual metal material layer 402 refers to the portion of the metal material layer 401 that is transformed to form the first silicide layer 42 and the second silicide layer 52.

[0177] It is worth mentioning that, in some embodiments, the first silicide layer 42 and the second silicide layer 52 can be made of different materials and formed in steps. Based on this, the deposition of a metal material layer 401 on the sidewalls of the first epitaxial layer 41 and the second epitaxial layer 51 in step S351 can include: depositing a first metal material layer on the sidewall of the first epitaxial layer 41; and depositing a second metal material layer on the sidewall of the second epitaxial layer 51; wherein the first metal material layer or the second metal material layer includes: a single metal material layer or a stack of multiple metal material layers. Correspondingly, after forming the first metal material layer and the second metal material layer, steps S352 and S353 in the aforementioned embodiments can be referred to to prepare the first silicide layer 42 and the second silicide layer 52. This disclosure will not elaborate further on these aspects.

[0178] Please continue reading. Figure 9 In some embodiments, after forming a first silicide layer covering the sidewalls of the first epitaxial layer and a second silicide layer covering the sidewalls of the second epitaxial layer in step S350, the preparation method further includes the following steps.

[0179] S400' forms an isolation structure on the sidewall of the first silicide layer.

[0180] S500', sidewalls are formed on the sidewalls of the second silicide layer and the sidewalls of the bit lines that are not covered by the second epitaxial layer.

[0181] It should be understood here that there is no strict order restriction on the execution of steps S400' and S500'; these steps can be executed simultaneously or in other orders.

[0182] In step S400', please refer to Figure 14 An isolation structure 6 is formed on the sidewall of the first silicide layer 42.

[0183] The aforementioned isolation structure 6 can be formed using a dielectric material with a high dielectric constant. For example, the isolation structure 6 can be a single dielectric layer or a stack of multiple dielectric layers. The isolation structure 6 can be formed by filling the trench G in the aforementioned example. The isolation structure 6 is used to insulate the corresponding bit line contact structure 2, and the isolation structure 6 covers the sidewall of the first silicide layer 42, which in turn covers the sidewall of the first epitaxial layer 41. This means that both the first silicide layer 42 and the first epitaxial layer 41 can be components of the equivalent bit line contact structure to ensure that the dimensions of the equivalent bit line contact structure meet the design requirements. (The equivalent bit line contact structure can be composed of the bit line contact structure 2, the first epitaxial layer 41, and the first silicide layer 42).

[0184] In step S500', please continue reading. Figure 14 Sidewalls 7 are formed on the sidewalls of the second silicide layer 52 and the sidewalls of the bit line 3 that are not covered by the second epitaxial layer 51.

[0185] The sidewall 7 can be formed using a dielectric material with a low dielectric constant. For example, the sidewall 7 can be a single dielectric layer or a stack of multiple dielectric layers. The sidewall 7 is used to insulate the corresponding bit line 3, and it covers the second silicide layer 52 and the sidewalls of the bit line 3 not covered by the second epitaxial layer 51. The second silicide layer 52 covers the sidewalls of the second epitaxial layer 51; that is, the second silicide layer 52 and the second epitaxial layer 51 can be integral parts of the equivalent bit line to ensure that the dimensions of the equivalent bit line meet design requirements. Furthermore, the thickness of the sidewall 7 can be selected according to actual needs.

[0186] Optionally, the isolation structure 6 and the sidewall 7 are respectively constructed by stacking a first silicon nitride layer, a silicon oxide layer, and a second silicon nitride layer. The isolation structure 6 and the sidewall 7 can be formed simultaneously.

[0187] In this embodiment, the formation of the first epitaxial layer 41 and the second epitaxial layer 51 is performed before the formation of the first silicide layer 42 and the second silicide layer 52. The formation of the first silicide layer 42 and the second silicide layer 52 is performed before the formation of the isolation structure 6 corresponding to the bit line contact structure 2 and the sidewall 7 corresponding to the bit line 3. This simplifies the semiconductor structure fabrication process and reduces the difficulty of semiconductor structure fabrication, thereby improving the production efficiency and yield of semiconductor structures.

[0188] Please combine Figure 2 , Figure 9 and Figure 14 It is understood that, in some embodiments, the fabrication method further includes: S600', forming a storage node contact structure 8. The storage node contact structure 8 is insulated from the first silicide layer 42 by an isolation structure 6, and is insulated from the second silicide layer 52 by a sidewall 7.

[0189] It is understood that the storage node contact structure 8 is typically formed within the corresponding storage node contact hole 80. For example, the storage node contact hole 80 can be formed on the resulting structure after the isolation structure 6 and the sidewall 7 are formed, so as to form the storage node contact structure 8 within the storage node contact hole 80, and to form an insulating layer 9 between adjacent storage node contact structures 8, so as to effectively insulate adjacent storage node contact structures 8 using the insulating layer 9.

[0190] Optionally, the storage node contact structure 8 includes a first conductive layer 81, a conductive transition layer 82, a second barrier layer 83, and a second conductive layer 84 sequentially stacked along a direction away from the substrate 1. However, it is not limited to this. The first conductive layer 81 is, for example, a doped polysilicon layer. The conductive transition layer 82 is, for example, a cobalt silicide layer. The second barrier layer 83 is, for example, a titanium nitride layer. The second conductive layer 84 is, for example, a tungsten metal layer.

[0191] Optionally, the insulating layer 9 can be a silicon nitride layer, such as one or more silicon nitride layers. Furthermore, the insulating layer 9 can be formed in one step or gradually stacked during the fabrication of other layer structures. That is, the insulating layer 9 here refers to the entire insulating portion located between adjacent memory node contact structures 8.

[0192] The semiconductor fabrication method provided in this disclosure is used to fabricate the semiconductor structures described in some of the above embodiments. This fabrication method also possesses all the technical advantages of the aforementioned semiconductor structures, and will not be detailed here.

[0193] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0194] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate with bit line contact holes; The bit line contact structure is disposed within the bit line contact hole; The first epitaxial layer is epitaxially formed on the sidewall of the bit line contact structure after etching. Bit line, the bit line including a connection layer connected to the bit line contact structure; And a second epitaxial layer, epitaxial on the sidewall of the connecting layer after etching.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: An isolation structure is located on the sidewall of the first epitaxial layer; Sidewalls are located on the sidewalls of the second epitaxial layer and on the sidewalls of the bit lines not covered by the second epitaxial layer.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: The first silicide layer is located on the sidewall of the first epitaxial layer; The second silicide layer is located on the sidewall of the second epitaxial layer.

4. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure also includes: An isolation structure is located on the sidewall of the first silicide layer; Sidewalls are located on the sidewalls of the second silicide layer and on the sidewalls of the bit lines not covered by the second epitaxial layer.

5. The semiconductor structure according to claim 1, characterized in that, The bit line further includes a conductive layer located on the side of the interconnect layer opposite to the substrate; wherein the orthographic projections of the first epitaxial layer and the second epitaxial layer on the substrate are at least within the orthographic projection range of the conductive layer on the substrate.

6. The semiconductor structure according to claim 5, characterized in that, The orthographic projection of the second epitaxial layer on the substrate lies within the orthographic projection of the conductive layer on the substrate, and there is a gap between the boundary of the orthographic projection of the second epitaxial layer on the substrate and the boundary of the orthographic projection of the conductive layer on the substrate.

7. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure further includes a second silicide layer located on the sidewall of the second epitaxial layer; the orthogonal projection of the second silicide layer on the substrate is within the orthogonal projection range of the conductive layer on the substrate.

8. The semiconductor structure according to claim 1, characterized in that, The thickness of the first epitaxial layer is greater than the thickness of the second epitaxial layer.

9. The semiconductor structure according to claim 8, characterized in that, The thickness of the second epitaxial layer is 2nm to 10nm.

10. The semiconductor structure according to claim 1, characterized in that, The height of the connection layer is 35% to 65% of the bit line height.

11. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which a bit line contact structure and a bit line are sequentially formed; the bit line includes a connection layer connected to the bit line contact structure. The bit line contact structure and the sidewalls of the connecting layer are re-etched back; A first epitaxial layer is formed on the sidewall after the bit line contact structure is etched back, and a second epitaxial layer is formed on the sidewall after the connection layer is etched back.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The preparation method further includes: An isolation structure is formed on the sidewall of the first epitaxial layer; Sidewalls are formed on the sidewalls of the second epitaxial layer and on the sidewalls of the bit lines not covered by the second epitaxial layer.

13. The method for preparing a semiconductor structure according to claim 11, characterized in that, The preparation method further includes: A first silicide layer is formed covering the sidewalls of the first epitaxial layer; A second silicide layer is formed covering the sidewalls of the second epitaxial layer.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The preparation method further includes: An isolation structure is formed on the sidewall of the first silicide layer; Sidewalls are formed on the sidewalls of the second silicide layer and on the sidewalls of the bit lines not covered by the second epitaxial layer.

15. The method for preparing a semiconductor structure according to claim 11, characterized in that, The first epitaxial layer and the second epitaxial layer are formed by epitaxial growth using evaporation growth process, molecular beam epitaxy process or chemical vapor deposition process.

16. The method for preparing a semiconductor structure according to claim 11, characterized in that, The sidewall etch-back thickness of the bit line contact structure and the connecting layer is 2nm to 10nm.

17. The method for preparing a semiconductor structure according to claim 11, characterized in that, The bit line also includes a conductive layer located on the side of the interconnect layer opposite to the substrate; the etchback of the bit line contact structure and the sidewalls of the interconnect layer is performed after the conductive layer is formed.

18. The method for preparing a semiconductor structure according to claim 17, characterized in that, After a first epitaxial layer is formed on the sidewall of the bit line contact structure after being etched back, and a second epitaxial layer is formed on the sidewall of the interconnect layer after being etched back, the orthogonal projections of the first epitaxial layer and the second epitaxial layer on the substrate are at least within the orthogonal projection range of the conductive layer on the substrate.

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