Waveform Injection Optimization Method and Device for Voltage-Time Type Feeder Automation Test Master Station

Abstract

The present invention discloses a waveform injection optimization method and device for a voltage-time type feeder automation test master station, including: obtaining each fault handling time section of the voltage-time type feeder automation test and the voltage and current waveform data of each corresponding fault handling time section; according to each of the fault handling time sections, sequentially injecting the voltage and current waveform data of each corresponding fault handling time section from the test master station layer in the voltage-time type feeder automation test system into the terminal layer in the voltage-time type feeder automation test system, and determining the time constraint boundaries of each hierarchical component in the voltage-time type feeder automation test system under each of the fault handling time sections, so as to obtain the total constraint of the waveform injection time window; controlling the waveform injection time of the feeder automation test according to the total constraint of the waveform injection time window. The present invention realizes more accurate control of the waveform injection time of the voltage-time type feeder automation test master station.

Description

Technical Field

[0001] The present invention relates to the field of feeder automation test optimization, and particularly to a waveform injection optimization method and device for the master station of voltage-time type feeder automation test. Background Art

[0002] Due to problems such as defects in the protection and control principles of feeder automation (FA), coordination between different manufacturers or different versions of terminals, communication interference or interruption, terminal parameter errors, inconsistency between the master station topology and the actual situation, and congestion of the master station front-end machine, the success rate of actual FA operation has decreased, and manual intervention often occurs. Therefore, power grid companies mostly carry out warehouse adjustment or on-site FA logic function tests before the operation of distribution automation.

[0003] Existing FA test methods mainly include the master station injection test method, the terminal injection test method, and the master station and secondary synchronous injection test method. Among them, the master station and secondary synchronous injection test method is affected by continuous and discrete events such as network communication between the test master station and the tester, tester processing, distribution terminal processing, and FA fault handling logic. If the time window for injecting the test master station waveform into the tester is incorrectly set, it will lead to phenomena such as the inability to advance the test and test errors. Therefore, an optimization method for waveform injection of the master station of voltage-time type feeder automation test considering the time window is needed. Summary of the Invention

[0004] The present invention provides a waveform injection optimization method and device for the master station of voltage-time type feeder automation test, which realizes more accurate control of the waveform injection time of the master station of voltage-time type feeder automation test.

[0005] To solve the above technical problems, an embodiment of the present invention provides a waveform injection optimization method for the master station of voltage-time type feeder automation test, including:

[0006] Obtaining each fault handling time section of the voltage-time type feeder automation test and the voltage and current waveform data of each corresponding fault handling time section;

[0007] According to each of the fault handling time sections, injecting the voltage and current waveform data of each corresponding fault handling time section into the terminal layer in the voltage-time type feeder automation test system from the test master station layer in the voltage-time type feeder automation test system in sequence, and determining the time constraint boundaries of each hierarchical component in the voltage-time type feeder automation test system under each fault handling time section, so as to obtain the total constraint of the waveform injection time window;

[0008] Controlling the waveform injection time of the feeder automation test according to the total constraint of the waveform injection time window.

[0009] It is understandable that, compared with the prior art, the method provided by the present invention determines the time constraint boundaries of each hierarchical component at different fault handling time sections by analyzing waveform data and the fault handling time section, which helps to ensure the correctness and stability of each component in terms of timing. By controlling the waveform injection time, it is ensured that the time constraints of each hierarchical component are met during the fault handling process, avoiding faults or errors caused by time constraint violations, and achieving more accurate completion of feeder automation testing.

[0010] Further, determining the time constraint boundaries of each component in the voltage-time type feeder automation test system at each of the fault handling time sections to obtain the total constraint of the waveform injection time window specifically includes:

[0011] Obtaining the first time window constraint according to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer makes the first opening;

[0012] Obtaining the second time window constraint according to the first reclosing delay of the relay protection device in the terminal layer and the total time from the first reclosing of the relay protection device in the terminal layer until the first circuit breaker in the test master station layer completes the first reclosing;

[0013] Obtaining the third time window constraint according to the sum of the information processing and transmission times of each component when the first load switch of the distribution line in the test master station layer gets voltage and closes;

[0014] Obtaining the fourth time window constraint according to the sum of the information processing and transmission times of each component when the second load switch of the distribution line in the test master station layer gets voltage and closes;

[0015] Obtaining the fifth time window constraint according to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer makes the second opening;

[0016] Obtaining the sixth time window constraint according to the second reclosing delay of the relay protection device in the terminal layer and the total time from the second reclosing of the relay protection device in the terminal layer until the first circuit breaker in the test master station layer completes the second reclosing;

[0017] Taking the first time window constraint, the second time window constraint, the third time window constraint, the fourth time window constraint, the fifth time window constraint, and the sixth time window constraint as the total constraint of the waveform injection time window.

[0018] It is understandable that the method provided by the present invention combines each fault handling time section in the voltage-time type feeder automation test to determine the information processing and transmission times between different hierarchical components in each fault handling time section, obtaining the time window constraints between different waveform injections, and being able to promote the normal and accurate progress of the feeder automation test.

[0019] Further, obtaining a first time window constraint according to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer trips for the first time specifically includes:

[0020] Taking the time interval between the first injected voltage and current waveform data and the first injected voltage and current waveform data to be greater than or equal to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer trips for the first time as the first time window constraint;

[0021] Wherein, the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer trips for the first time is the sum of the first waveform data injection time, the first terminal action time, the first terminal extension time, the first tester processing time, the first test master station simulation action topology time, and twice the first network delay.

[0022] It can be understood that the method provided by the present invention simulates a short - circuit fault occurring on the line between the second load switch and the third load switch in the test master station layer, and the test master station layer outputs the fault voltage and current waveform data for the first time. To ensure the coordinated advancement of the test dynamic process, after the first circuit breaker in the test master station layer has tripped, the second waveform injection should be carried out. Therefore, the time interval between the second waveform injection and the first waveform injection in the test master station layer should be greater than or equal to the sum of the information processing and transmission times of each component during the first opening operation of the first circuit breaker.

[0023] Further, obtaining a second time window constraint according to the first reclosing delay of the relay protection device in the terminal layer and the total time from the first reclosing of the relay protection device in the terminal layer until the first reclosing of the first circuit breaker in the test master station layer is completed specifically includes:

[0024] Obtaining the total time from the first reclosing of the relay protection device in the terminal layer until the first reclosing of the first circuit breaker in the test master station layer is completed according to the sum of the third terminal extension time, the third tester processing time, the third test master station simulation action topology time, and the third network delay;

[0025] Adding the first reclosing delay of the relay protection device in the terminal layer to the total time from the first reclosing of the relay protection device in the terminal layer until the first reclosing of the first circuit breaker in the test master station layer is completed, and subtracting the sum of the first terminal extension time, the first tester processing time, the first network delay, and the first test master station simulation action topology time to obtain a second intermediate time;

[0026] Taking the time interval between the second injected voltage and current waveform data and the third injected voltage and current waveform data being greater than or equal to the second intermediate time as the second time window constraint.

[0027] It can be understood that by setting the time interval between the fifth injected voltage and current waveform data and the sixth injected voltage and current waveform data to be greater than or equal to the second intermediate time, the method provided by the present invention can ensure that during the test, the information of each component has been processed and transmitted, thereby avoiding test errors caused by information delay.

[0028] Further, obtaining the third time window constraint according to the sum of the information processing and transmission times of each component when the first load switch of the distribution line in the test master station layer is energized and closed specifically includes:

[0029] Taking the time interval between the third injected voltage and current waveform data and the fourth injected voltage and current waveform data being greater than or equal to the sum of the information processing and transmission times of each component when the first load switch of the distribution line in the test master station layer is energized and closed as the third time window constraint;

[0030] Wherein, the sum of the information processing and transmission times of each component when the first load switch of the distribution line in the test master station layer is energized and closed is the sum of the fourth waveform data injection time, the fourth terminal action time, the fourth terminal extension time, the fourth tester processing time, the fourth test master station simulation action topology time, and twice the fourth network delay.

[0031] It can be understood that by setting the time interval between the third injected voltage and current waveform data and the fourth injected voltage and current waveform data to be greater than or equal to the sum of the information processing and transmission times of each component when the first load switch of the distribution line in the test master station layer is energized and closed, the method provided by the present invention can ensure that during the energization and closing of the first load switch of the distribution line, the information of each component has been processed and transmitted, thereby avoiding test errors caused by information delay.

[0032] Further, obtaining the fourth time window constraint according to the sum of the information processing and transmission times of each component when the second load switch of the distribution line in the test master station layer is energized and closed specifically includes:

[0033] Taking the time interval between the fourth injected voltage and current waveform data and the fifth injected voltage and current waveform data being greater than or equal to the sum of the information processing and transmission times of each component when the second load switch of the distribution line in the test master station layer is energized and closed as the third time window constraint;

[0034] Among them, the sum of the information processing and transmission times of each component when the second load switch of the distribution line in the test master station layer is energized and closed is the sum of the fifth waveform data injection time, the fifth terminal action time, the fifth terminal extension time, the fifth tester processing time, the fifth test master station simulation action topology time, and twice the fifth network delay.

[0035] It can be understood that by setting the time interval between the fourth injection voltage and current waveform data and the fifth injection voltage and current waveform data to be greater than or equal to the sum of the information processing and transmission times of each component when the second load switch of the distribution line in the test master station layer is energized and closed, the method provided by the present invention can ensure that the information of each component has been processed and transmitted when the second load switch of the distribution line is energized and closed, thereby avoiding test errors caused by information delay.

[0036] Further, obtaining the sixth time window constraint according to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer is tripped for the second time specifically includes:

[0037] Setting the time interval between the fifth injection voltage and current waveform data and the sixth injection voltage and current waveform data to be greater than or equal to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer is tripped for the second time as the sixth time window constraint;

[0038] Among them, the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer is tripped for the second time is the sum of the sixth waveform data injection time, the sixth terminal action time, the sixth terminal extension time, the sixth tester processing time, the sixth test master station simulation action topology time, and twice the sixth network delay.

[0039] It can be understood that by setting the time interval between the fifth injection voltage and current waveform data and the sixth injection voltage and current waveform data to be greater than or equal to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer is tripped for the second time, the method provided by the present invention can ensure that the information of each component has been processed and transmitted when the first circuit breaker is tripped for the second time, thereby avoiding test errors caused by information delay.

[0040] Further, obtaining the seventh time window constraint according to the second reclosing delay of the relay protection device in the terminal layer and the total time from the second reclosing of the relay protection device in the terminal layer until the second reclosing of the first circuit breaker in the test master station layer is completed specifically includes:

[0041] Based on the sum of the eighth terminal expansion time, the eighth tester processing time, the eighth test master station simulation action topology time, and the eighth network delay, obtain the total time from the second reclosing of the relay protection device in the terminal layer until the second reclosing of the first circuit breaker in the test master station layer is completed;

[0042] Add the second reclosing delay of the relay protection device in the terminal layer to the total time from the second reclosing of the relay protection device in the terminal layer until the second reclosing of the first circuit breaker in the test master station layer is completed, and subtract the sum of the sixth terminal expansion time, the sixth tester processing time, the sixth network delay, and the sixth test master station simulation action topology time to obtain the sixth intermediate time;

[0043] Take the time interval between the second injected voltage and current waveform data and the third injected voltage and current waveform data being greater than or equal to the sixth intermediate time as the sixth time window constraint.

[0044] It can be understood that by making the time interval between the second injected voltage and current waveform data and the third injected voltage and current waveform data greater than or equal to the sixth intermediate time, the method provided by the present invention can ensure that in the testing process, the information of each component has been processed and transmitted, thereby avoiding testing errors caused by information delay.

[0045] Correspondingly, an embodiment of the present invention also provides a waveform injection optimization device for a voltage-time type feeder automation test master station, including:

[0046] A data acquisition module, configured to acquire each fault processing time section of the voltage-time type feeder automation test and the voltage and current waveform data corresponding to each fault processing time section;

[0047] A time window constraint analysis module, configured to sequentially inject the voltage and current waveform data corresponding to each fault processing time section from the test master station layer in the voltage-time type feeder automation test system into the terminal layer in the voltage-time type feeder automation test system according to each fault processing time section, and determine the time constraint boundaries of each hierarchical component in the voltage-time type feeder automation test system under each fault processing time section to obtain the total constraint of the waveform injection time window;

[0048] A control time module, configured to control the waveform injection time of the feeder automation test according to the total constraint of the waveform injection time window.

[0049] It can be understood that, compared with the prior art, the system provided by the present invention determines the time constraint boundaries of components at each level under different fault handling time sections by analyzing waveform data and fault handling time sections, which helps to ensure the correctness and stability of each component in terms of timing. By controlling the waveform injection time, it is ensured that the time constraints of components at each level are met during the fault handling process, avoiding faults or errors caused by time constraint violations, and achieving more accurate completion of feeder automation testing.

[0050] Furthermore, the time window constraint analysis module specifically includes: a time window constraint determination sub-module, and the time window constraint determination sub-module includes:

[0051] A first time window constraint determination unit, configured to obtain a first time window constraint according to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer makes the first opening;

[0052] A second time window constraint determination unit, configured to obtain a second time window constraint according to the first reclosing delay of the relay protection device in the terminal layer and the total time from the first reclosing of the relay protection device in the terminal layer until the first circuit breaker in the test master station layer completes the first reclosing;

[0053] A third time window constraint determination unit, configured to obtain a third time window constraint according to the sum of the information processing and transmission times of each component when the first load switch of the distribution line in the test master station layer gets voltage and closes;

[0054] A fourth time window constraint determination unit, configured to obtain a fourth time window constraint according to the sum of the information processing and transmission times of each component when the second load switch of the distribution line in the test master station layer gets voltage and closes;

[0055] A fifth time window constraint determination unit, configured to obtain a fifth time window constraint according to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer makes the second opening;

[0056] A sixth time window constraint determination unit, configured to obtain a sixth time window constraint according to the second reclosing delay of the relay protection device in the terminal layer and the total time from the second reclosing of the relay protection device in the terminal layer until the first circuit breaker in the test master station layer completes the second reclosing;

[0057] A time window total constraint determination unit, configured to use the first time window constraint, the second time window constraint, the third time window constraint, the fourth time window constraint, the fifth time window constraint, and the sixth time window constraint as the total waveform injection time window constraint.

[0058] It can be understood that the system provided by the present invention combines the time sections of various fault handling in the voltage-time type feeder automation test, determines the information processing and transmission time between components at different levels in each fault handling time section, and obtains the time window constraints between different waveform injections, which can promote the normal and accurate progress of the feeder automation test. Description of the Drawings

[0059] Figure 1 : It is a flowchart of the steps of a method for optimizing waveform injection of the main station in the voltage-time type feeder automation test provided by an embodiment of the present invention;

[0060] Figure 2 : It is a diagram of the data frame composition of one cycle of data in the waveform injection of the main station in the voltage-time type feeder automation test provided by an embodiment of the present invention;

[0061] Figure 3 : It is an architecture diagram of a voltage-time type feeder automation test system provided by an embodiment of the present invention;

[0062] Figure 4 : It is a process diagram of fault handling in the voltage-time type feeder automation test provided by an embodiment of the present invention;

[0063] Figure 5 : It is a schematic diagram of the key processing time in the voltage-time type feeder automation test provided by an embodiment of the present invention;

[0064] Figure 6 : It is a diagram of the meaning of the second time window constraint in the method for optimizing waveform injection of the main station in the voltage-time type feeder automation test provided by an embodiment of the present invention;

[0065] Figure 7 : It is a diagram of the meaning of the sixth time window constraint in the method for optimizing waveform injection of the main station in the voltage-time type feeder automation test provided by an embodiment of the present invention;

[0066] Figure 8 : It is a schematic structural diagram of a device for optimizing waveform injection of the main station in the voltage-time type feeder automation test provided by an embodiment of the present invention. Detailed Embodiments

[0067] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0068] The voltage-time type FA test system mainly consists of a test master station, a communication network, a tester, a relay protection device, a distribution terminal, etc. The system architecture is as shown in Figure 3 Figure [not provided in the original]. The test master station is the brain of the FA test, building the 10kV primary equipment network to be tested, with the function of dynamically simulating the topology of the distribution network grid. It outputs the voltage and current waveforms of the distribution network to the tester through the network and receives the analog breaker position change information. The tester is used to receive the transient and steady-state waveform information from the test master station and convert it into analog quantity for output to the distribution terminal. At the same time, it has the function of an analog breaker, transmitting the switch position change information to the test master station. Relay protection devices are installed on the substation outlet breakers CB1 and CB2, usually configured with functions such as current protection I-II, zero-sequence current protection, and secondary reclosing. Distribution terminal units are installed on the load switches FS1-FS3 and tie switches LS of the distribution line, configured with the voltage-time type FA function.

[0069] Embodiment 1

[0070] Please refer to Figure 1 Figure [not provided in the original], which is the step flowchart of a waveform injection optimization method for a voltage-time type feeder automation test master station provided by an embodiment of the present invention, including S101-S103. The specific steps are as follows.

[0071] S101: Obtain the voltage and current waveform data of each fault handling time section and the corresponding fault handling time section in the voltage-time type feeder automation test.

[0072] In this embodiment, the voltage-time type FA fault handling process section is as shown in Figure 4 Figure [not provided in the original]. From time t0 to t1, the test master station injects normal operating voltage and current waveform data into the relay protection device and the distribution terminal. At time t1, a permanent fault occurs on the line, and the test master station injects fault voltage and current waveforms into the relay protection device and the distribution terminal. In the present invention, the recorded waveform data method is adopted. A total of seven waveform injections are required for the voltage-time type FA test, and the time intervals between each waveform injection are Δt1-Δt6 respectively.

[0073] S102: According to the voltage and current waveform data of each corresponding fault handling time section, inject the voltage and current waveform data of each corresponding fault handling time section from the test master station layer in the voltage-time type feeder automation test system into the terminal layer in the voltage-time type feeder automation test system in sequence, and determine the time constraint boundaries of each hierarchical component in the voltage-time type feeder automation test system under each fault handling time section, obtaining the total constraint of the waveform injection time window.

[0074] Table 1 Relay protection device and FTU setting

[0075]

[0076] As a preferred solution, the key setting values of the relay protection device and the feeder terminal are shown in Table 1. Without loss of generality, the corresponding time window constraint boundaries can be obtained for different setting values based on the method of this patent.

[0077] Since network communication is used between the test master station and the tester, delay is inevitably generated. The network delay τ includes: transmission delay τ s , propagation delay τ p and switching delay τ b , that is:

[0078] τ = τ s + τ p + τ b (1)

[0079] Among them, the transmission delay τ s refers to the time required for the test master station to send a data frame. Let L represent the size of the data frame to be sent and R represent the bandwidth, then there is:

[0080]

[0081] Based on sampling 24 points in one cycle (20 ms), single-phase voltage or current data occupies 4 bytes. Therefore, the data size of a group of three-phase voltage and current is 24 bytes, and the data size Lw of the three-phase voltage and current waveforms in one cycle is 576 bytes. The data frame composition is as Figure 2 shown, and the total data frame size L is 602 bytes.

[0082] When using optical fiber communication, a bandwidth of 2 Mbit / s is usually configured. Then, the transmission delay of the three-phase voltage and current waveform data in one cycle:

[0083]

[0084] When using wireless communication, the worst 4G downlink rate is UE Category1, with a bandwidth of 10 Mbit / s. Then, the transmission delay of the three-phase voltage and current waveform data in one cycle:

[0085]

[0086] The propagation delay τ s refers to the time required for an electromagnetic signal or an optical signal to propagate a certain distance in the channel. Let v represent the propagation rate and s represent the channel length, then there is:

[0087]

[0088] When using optical fiber communication, v is taken as the propagation speed of the optical signal in the optical fiber (v≈2×105 km / s). When using wireless communication, v is taken as the propagation speed of the electromagnetic wave in free space (v≈3×105 km / s), and s is taken as the total length of the channel optical cable (km). When testing the optical cable or the spatial distance between the master station and the tester in the city, it generally does not exceed 100 km, then τ p ≤0.5 ms.

[0089] The switching delay τ b refers to the hop time between communication devices through intermediate communication nodes, including: the processing delay τ sdh and the queuing delay τ queue The sum. Among them, the processing delay τ sdh is the delay required for the switch to check the packet header and determine the packet transmission path when receiving the packet. Generally, it is between 50 and 125 us and can be ignored; the queuing delay τ queue refers to the time when the data packet waits for processing and transmission in the queuing queue. The queuing delay during the transmission process is related to the current state of the network node. The calculation formula is as follows:

[0090]

[0091] In the formula: is the size of the i-th data packet queuing in the k-th node queue; L k is the size of the data packet being sent at the k-th node; R k is the transmission rate passing through the k-th device port.

[0092] If the optical fiber communication method is adopted and the 2 Mbit / s bandwidth is exclusive, then only n waveform data of the measured protection or terminal need to queue up for a single waveform injection. For example Figure 1 , when n = 6, the queuing delay is at the us level and can be ignored; if the wireless communication method is adopted, the queuing delay of 4G is uncertain and is usually less than 10 ms.

[0093] In this embodiment, please refer to Figure 5 , which is a schematic diagram of the key processing time for the voltage-time type feeder automation test provided by the embodiment of the present invention. Among them, the subscript n represents the section corresponding to the FA test waveform injection. n = 1 represents the first waveform injection link, n = 2 represents the second waveform injection link, and so on.

[0094] 1) The communication response time of the tester: Referring to the regulations of DL / T 624-2010 and DL / T 2178-2020, the response speed of the tester to output AC voltage and current should be less than 100 us and can be ignored.

[0095] 2) Cable transmission time between the tester, relay protection device, and distribution terminal: Since they are in the same space and the transmission distance is within 10m, it can be ignored.

[0096] 3) Action time of the relay protection device: The action and outlet times of the current I - II segments and zero-sequence protection are usually ≤60ms.

[0097] 4) Action time of the distribution terminal: It includes the FA logic judgment time + action outlet time, usually ≤60ms.

[0098] 5) Voltage loss tripping opening time of the distribution terminal: Referring to the trial standard for parameter setting and setting value setting of a company's distribution automation terminal device, it is usually <1000ms.

[0099] 6) Switching time of the tester as a simulated circuit breaker: Taking the spring energy storage operating mechanism switch as an example, its inherent closing time ≤60ms, and its inherent opening time ≤40ms. Considering the influence of factors such as switch operation loss and aging, the inherent switching time will increase. The switching time of the simulated circuit breaker is taken as 100ms.

[0100] 7) Test master station network topology dynamic simulation time: After the tester sends the switch status information to the test master station, the test master station will act on the corresponding circuit breakers, load switches, and tie switches in the network topology according to the information. Since the fault recording method is used for testing, the simulation action time is taken as 50ms.

[0101] As a preferred solution, since the processing time of the above key processes is uncertain in the actual operation of FA, the most unfavorable case is taken as the basic condition for the analysis of the voltage time - type FA test time constraint boundary in this embodiment.

[0102] As a preferred solution, when a short - circuit fault occurs on the line between load switches FS2 and FS3, the test master station outputs the fault voltage and current waveform data for the first time. Based on one cycle (20ms), two cycles are injected into each relay protection device and distribution terminal, that is Circuit breaker CB1 will perform the first opening, and the other switches will not act. The sum t1 of the information processing and transmission times of each component is as follows:

[0103]

[0104] To ensure the coordinated progress of the test dynamic process, it should be ensured that after the opening of switch CB1 in the test master station network topology is completed, the second waveform injection is carried out. Therefore, the time interval Δt1 between the second waveform injection and the first waveform injection of the test master station should be greater than or equal to the sum t1 of the information processing and transmission times of each component during the first opening operation of CB1 in the test system, and there is a constraint:

[0105] Δt1≥t1 (8)

[0106] Substitute the time of each link in Figure 5 into equations (7) and (8). Also, both are the network delays between the test master station and the tester, so let we can get:

[0107]

[0108] As an optimal solution, after the test master station's network simulation completes the opening of circuit breaker CB1, it outputs the waveform for the second time and injects two cycles into the relay protection device and the distribution terminal, that is, section switches FS1, FS2, and FS3 trip due to single-sided voltage loss, and the other switches do not operate. The sum Δt2 of the information processing and transfer times of each component is as follows:

[0109]

[0110] After the test master station's network simulation completes the first voltage-loss tripping of load switches FS1, FS2, and FS3, CB1 makes the first reclosing. Since the relay protection device will automatically perform the first reclosing 5 s after the first opening, no waveform injection is required for this link. To ensure that the first voltage-loss tripping operation of load switches FS1, FS2, and FS3 and the information transfer of the test system are completed before the first reclosing of CB1, there is a constraint:

[0111]

[0112] In the formula, is the moment of the first opening of the relay protection device; is the moment when the test master station's network completes the voltage-loss tripping of load switches FS1, FS2, and FS3. Substitute the known times into equation (11), and we can get:

[0113]

[0114] After simplification, it can be obtained that there is a constraint on the network delay T between the test master station and the tester in this link:

[0115] T<1133.3ms (13)

[0116] The meaning of the time interval Δt2 between the third waveform injection and the second waveform injection by the test master station is as Figure 6 shown, and the constraint is as shown in equation (14).

[0117]

[0118] In the formula, The total time for the on-site relay protection device to send the switch status information to the test master station after the first reclosing until the grid switch reclosing is completed. Substituting the known time, we get:

[0119]

[0120] As a preferred solution, after the test master station grid simulation completes the first reclosing of CB1, the third output waveform is generated. Since FS1 needs to close the switch after obtaining voltage for X time (7s), 350 cycles of voltage waveform are injected into the distribution terminal corresponding to FS1, and 2 cycles are injected into the remaining devices. Take the maximum value, that is It will cause the sectional switch FS1 to close the switch with voltage on one side, and the remaining switches will not operate. The sum of the information processing and transfer times t4 of each component is as follows:

[0121]

[0122] The time interval Δt3 between the fourth injection waveform and the third injection waveform of the test master station should be greater than or equal to the sum of the information processing and transfer times of each component during the operation of FS1 to close the switch with voltage. Therefore, there is a constraint:

[0123] Δt3≥t4 (17)

[0124] Substituting the known time into equations (16) and (17), we get:

[0125]

[0126] As a preferred solution, after the test master station grid simulation completes the operation of FS1 to close the switch with voltage, the fourth output waveform is generated. Since FS2 needs to close the switch after obtaining voltage for X time (7s), 350 cycles of voltage waveform are injected into the distribution terminal corresponding to FS2, and 2 cycles are injected into the remaining devices. Take the maximum value, that is It will cause the sectional switch FS2 to close the switch with voltage on one side, and the remaining switches will not operate. The sum of the information processing and transfer times t5 of each component is as follows:

[0127]

[0128] The time interval Δt4 between the fifth injection waveform and the fourth injection waveform of the test master station should be greater than or equal to the sum of the information processing and transfer times of each component during the operation of FS2 to close the switch with voltage. Therefore, there is a constraint:

[0129] Δt≥t(20)

[0130] Substituting the known time into equations (19) and (20), we get:

[0131]

[0132] As a preferred solution, after the simulation of the main test substation grid is completed and the sectionalizing switch FS2 is closed on a fault, for the fifth output waveform, FS3 will start to sense the residual voltage. Considering the residual voltage discrimination time (>50 ms), a voltage waveform of 5 cycles will be injected into the distribution terminal corresponding to FS3, and a voltage waveform of 2 cycles will be injected into the remaining devices. The maximum value is taken, that is It will cause the circuit breaker CB1 to trip for the second time. FS3 senses the residual voltage, and the other switches do not operate. The total sum t6 of the information processing and transmission times of each component is:

[0133]

[0134] The time interval Δt5 between the sixth injected waveform and the fifth injected waveform by the main test station should be greater than or equal to the total sum of the information processing and transmission times of each component for the second CB1 tripping operation of the test system. Therefore, there is a constraint:

[0135] Δt5≥t6 (23)

[0136] Substituting the times of each link into equations (22) and (23), we can obtain:

[0137]

[0138] As a preferred solution, after the simulation of the main test substation grid is completed and the circuit breaker CB1 trips for the second time, for the sixth output waveform, at this time the residual voltage at FS3 will disappear, and a voltage waveform of 2 cycles will be injected into each protection device and distribution terminal, that is It will cause the sectionalizing switches FS1 and FS2 to trip due to loss of voltage for the second time. FS2 locks out closing on voltage acquisition on its own side, and FS3 locks out closing on voltage acquisition on the other side. The other switches do not operate. The total sum t7 of the information processing and transmission times of each component is as shown in the equation:

[0139]

[0140] Since FS2 loses voltage again within the Y time (5 s) after closing on voltage acquisition, FS2 will lock out closing on voltage acquisition on its own side after tripping. Therefore, the total time of information processing and transmission of the test system between the first closing on voltage acquisition and the second tripping due to loss of voltage of the distribution terminal corresponding to FS2 should be within the Y time limit (5 s), and the constraint is as shown in the equation:

[0141]

[0142] In the formula, is the moment of the first closing on voltage acquisition of the distribution terminal corresponding to FS2; is the moment of the second tripping due to loss of voltage of the distribution terminal corresponding to FS2.

[0143] Substituting the times of each link into equation (26), we can obtain:

[0144]

[0145] Simplification gives the constraint for the network delay T between the test master station and the tester in this step:

[0146] T ≤ 1060 ms (28)

[0147] Theoretically analyzed, the sectionalizing switch FS3 should start to sense the residual voltage after the sectionalizing switch FS2 is energized and closed for the first time (closed on a fault), and the residual voltage should disappear after the circuit breaker CB1 is de-energized and tripped for the second time. However, due to the limitations of information transmission during the FA test process, the moment when the distribution terminal corresponding to FS3 senses the residual voltage should be the fifth waveform injection moment, and the moment when the residual voltage disappears should be the sixth waveform injection moment. The total operation time between the moment when the distribution terminal corresponding to FS3 senses the residual voltage waveform and the moment when the residual voltage waveform disappears should be kept within the residual voltage discrimination time (0.05 s - 3 s), and the constraint is as follows:

[0148]

[0149] In the formula, is the moment when the distribution terminal corresponding to FS3 starts to sense the residual voltage; is the moment when the distribution terminal corresponding to FS3 senses the disappearance of the residual voltage.

[0150] Substituting the times of each step into formula (29), we get:

[0151]

[0152] Simplification gives the constraint for the network delay T between the test master station and the tester in this step:

[0153] T ≤ 1295 ms (31)

[0154] As an optimal solution, after the test master station network simulation completes the second tripping of the sectionalizing switches FS1 and FS2, FS2 locks out the voltage closing on its own side, and FS3 locks out the voltage closing on the other side, the circuit breaker CB1 will perform the second reclosing. Since the relay protection device will automatically perform the second reclosing 60 s after the second tripping. Therefore, no waveform injection is required in this step. To ensure that the loss-of-voltage tripping of the load switches FS1 and FS2 is completed before the second reclosing of CB1, the voltage closing of FS2 and FS3 is locked out and the information transmission of the test system is blocked. The total time of the above operations in the test system should be controlled within 60 s. Therefore, there is a constraint:

[0155]

[0156] In the formula, is the moment of the second tripping of the relay protection device; is the moment when the test master station network completes the loss-of-voltage tripping of the load switches FS1 and FS2, and the voltage closing of FS2 and FS3 is locked out.

[0157] Substituting the time of each link into Equation (32), we can obtain:

[0158]

[0159] After simplification, it can be obtained that there is a constraint on the network delay T between the test master station and the tester in this link:

[0160] T < 19466.7 ms (34)

[0161] The meaning of the time interval Δt6 between the seventh injection waveform and the sixth injection waveform of the test master station is as Figure 7 shown, and the constraint is as shown in Equation (35).

[0162]

[0163] In the formula, is the total time from the second reclosing of the on-site relay protection device to sending the switch status information to the test master station until the grid switch reclosing is completed.

[0164] Substituting the known parameters, we can obtain:

[0165]

[0166] As an optimal solution, after the grid simulation in the test master station completes the second reclosing of CB1, the seventh output waveform is generated. Since FS1 needs to close the switch after obtaining voltage for X time (7 s), 350 cycle voltage waveforms are injected into the distribution terminal corresponding to FS1, and 2 cycles are injected into the other devices. Take the maximum value, that is It will cause the sectional switch FS1 to close the switch with single-sided voltage, and the other switches will not operate. The total sum t9 of the information processing and transmission time of each component:

[0167]

[0168] As an optimal solution, when the tie switch LS detects that one side is energized and the other side is not energized, it starts the XL delayed closing. Therefore, from the moment when the distribution terminal corresponding to LS receives the single-sided loss-of-voltage information and starts the XL timing to the moment when the sectional switch FS2 completes the second voltage acquisition and closing to restore power supply, the total operation time should be less than XL. Therefore, there is a constraint:

[0169]

[0170] In the formula:

[0171] t r1 is the remaining waiting time for the first reclosing:

[0172]

[0173] t r2 It is the remaining waiting time for the second reclosing:

[0174]

[0175] Substituting the known time into Equation (38), we can get:

[0176]

[0177] After simplification, it can be obtained that there is a constraint on the network delay T between the master station and the tester in this test session:

[0178] T < 1251.4 ms (40)

[0179] As an optimal solution, by analyzing the reclosing time, Y time, residual voltage discrimination time, and closing delay time XL of the tie switch in the voltage-time type FA, the network delay constraints between the master station and the tester in the five test sessions of Equations (13), (28), (31), (34), and (40) can be obtained. To achieve the orderly and coordinated advancement of the test dynamic process, the intersection of the above five equations is taken as the final constraint on the network delay between the master station and the tester, as shown in the equation:

[0180] T < 1060 ms (41)

[0181] As an optimal solution, the maximum number of cycles of the injected waveform during the voltage-time type FA test is 350 cycles (7000 ms). When using fiber optic communication, its theoretical maximum network delay τ = 2.30×350 + 0.5 = 805.5 ms; when using 4G wireless communication, its theoretical maximum network delay τ = 0.46×350 + 10 + 0.5 = 171.5 ms. In summary, the theoretical delays of both communication methods satisfy the constraint of Equation (42) analyzed in this article. Therefore, substituting the most unfavorable network delay T = 1060 ms into the waveform injection time interval constraints in each test session of the voltage-time type FA and simplifying, we can get:

[0182]

[0183] Simplifying from Equation (38), we can get:

[0184]

[0185] In summary, after sorting out, the waveform injection time window constraints are as follows:

[0186]

[0187] S103: According to the total constraint of the waveform injection time window, control the waveform injection time of the feeder automation test.

[0188] It can be understood that, according to the total constraint of the waveform injection time window, controlling the waveform injection time of the feeder automation test can orderly and coordinately promote the dynamic process of the FA test.

[0189] The method provided by the present invention determines the time constraint boundaries of components at each level under different fault handling time sections by analyzing waveform data and fault handling time sections, which helps to ensure the correctness and stability of each component in terms of time sequence. By controlling the waveform injection time, it is ensured that the time constraints of components at each level are met during the fault handling process, avoiding faults or errors caused by time constraint violations, and achieving more accurate completion of the feeder automation test.

[0190] Embodiment 2

[0191] Please refer to Figure 8 , which is a schematic structural diagram of an optimized device for waveform injection of a voltage-time type feeder automation test master station provided by an embodiment of the present invention. The device includes: a data acquisition module 201, a time window constraint analysis module 202, and a control time module 203.

[0192] The data acquisition module 201 is used to acquire each fault handling time section of the voltage-time type feeder automation test and the voltage and current waveform data corresponding to each corresponding fault handling time section;

[0193] The time window constraint analysis module 202 is used to sequentially inject the voltage and current waveform data corresponding to each corresponding fault handling time section from the test master station layer in the voltage-time type feeder automation test system into the terminal layer in the voltage-time type feeder automation test system according to each fault handling time section, and determine the time constraint boundaries of components at each level in the voltage-time type feeder automation test system under each fault handling time section, so as to obtain the total constraint of the waveform injection time window;

[0194] The control time module 203 is used to control the waveform injection time of the feeder automation test according to the total constraint of the waveform injection time window.

[0195] In this embodiment, the time window constraint analysis module specifically includes: a time window constraint determination sub-module, and the time window constraint determination sub-module includes: a first time window constraint determination unit, a second time window constraint determination unit, a third time window constraint determination unit, a fourth time window constraint determination unit, a fifth time window constraint determination unit, a sixth time window constraint determination unit, and a time window total constraint determination unit.

[0196] In this embodiment, the first time window constraint determining unit is configured to obtain a first time window constraint according to the sum of the element information processing and transmission times when the first circuit breaker in the test master station layer trips for the first time. Specifically, it includes: taking the time interval between the first injection of voltage and current waveform data and the first injection of voltage and current waveform data being greater than or equal to the sum of the element information processing and transmission times when the first circuit breaker in the test master station layer trips for the first time as the first time window constraint; where the sum of the element information processing and transmission times when the first circuit breaker in the test master station layer trips for the first time is the sum of the first waveform data injection time, the first terminal action time, the first terminal extension time, the first tester processing time, the first test master station simulation action topology time, and twice the first network delay.

[0197] In this embodiment, the second time window constraint determining unit is configured to obtain a second time window constraint according to the first reclosing delay of the relay protection device in the terminal layer and the total time from the first reclosing of the relay protection device in the terminal layer until the first reclosing of the first circuit breaker in the test master station layer is completed. Specifically, it includes: obtaining the total time from the first reclosing of the relay protection device in the terminal layer until the first reclosing of the first circuit breaker in the test master station layer is completed according to the sum of the third terminal extension time, the third tester processing time, the third test master station simulation action topology time, and the third network delay; adding the first reclosing delay of the relay protection device in the terminal layer to the total time from the first reclosing of the relay protection device in the terminal layer until the first reclosing of the first circuit breaker in the test master station layer is completed, and subtracting the sum of the first terminal extension time, the first tester processing time, the first network delay, and the first test master station simulation action topology time to obtain a second intermediate time; taking the time interval between the second injection of voltage and current waveform data and the third injection of voltage and current waveform data being greater than or equal to the second intermediate time as the second time window constraint.

[0198] In this embodiment, the third time window constraint determining unit is configured to obtain a third time window constraint according to the sum of the element information processing and transmission times when the first load switch of the distribution line in the test master station layer closes under voltage. Specifically, it includes: taking the time interval between the third injection of voltage and current waveform data and the fourth injection of voltage and current waveform data being greater than or equal to the sum of the element information processing and transmission times when the first load switch of the distribution line in the test master station layer closes under voltage as the third time window constraint; where the sum of the element information processing and transmission times when the first load switch of the distribution line in the test master station layer closes under voltage is the sum of the fourth waveform data injection time, the fourth terminal action time, the fourth terminal extension time, the fourth tester processing time, the fourth test master station simulation action topology time, and twice the fourth network delay.

[0199] In this embodiment, the fourth time window constraint determining unit is configured to obtain a fourth time window constraint according to the sum of the processing and transmission times of each element information when the second load switch of the distribution line in the test master station layer is energized and closed, specifically including: taking the time interval between the fourth injected voltage and current waveform data and the fifth injected voltage and current waveform data being greater than or equal to the sum of the processing and transmission times of each element information when the second load switch of the distribution line in the test master station layer is energized and closed as the third time window constraint; wherein, the sum of the processing and transmission times of each element information when the second load switch of the distribution line in the test master station layer is energized and closed is the sum of the fifth waveform data injection time, the fifth terminal action time, the fifth terminal extension time, the fifth tester processing time, the fifth test master station simulation action topology time, and twice the fifth network delay.

[0200] In this embodiment, the fifth time window constraint determining unit is configured to obtain a fifth time window constraint according to the sum of the processing and transmission times of each element information when the first circuit breaker in the test master station layer is tripped for the second time, specifically including: taking the time interval between the fifth injected voltage and current waveform data and the sixth injected voltage and current waveform data being greater than or equal to the sum of the processing and transmission times of each element information when the first circuit breaker in the test master station layer is tripped for the second time as the fifth time window constraint; wherein, the sum of the processing and transmission times of each element information when the first circuit breaker in the test master station layer is tripped for the second time is the sum of the sixth waveform data injection time, the sixth terminal action time, the sixth terminal extension time, the sixth tester processing time, the sixth test master station simulation action topology time, and twice the sixth network delay.

[0201] In this embodiment, the sixth time window constraint determination unit is configured to obtain the sixth time window constraint according to the second reclosing delay of the relay protection device in the terminal layer and the total time from the second reclosing of the relay protection device in the terminal layer until the second reclosing of the first circuit breaker in the test master station layer is completed. Specifically, it includes: obtaining the total time from the second reclosing of the relay protection device in the terminal layer until the second reclosing of the first circuit breaker in the test master station layer is completed according to the sum of the eighth terminal expansion time, the eighth tester processing time, the eighth test master station simulation action topology time, and the eighth network delay; adding the second reclosing delay of the relay protection device in the terminal layer to the total time from the second reclosing of the relay protection device in the terminal layer until the second reclosing of the first circuit breaker in the test master station layer is completed, and subtracting the sum of the sixth terminal expansion time, the sixth tester processing time, the sixth network delay, and the sixth test master station simulation action topology time to obtain the sixth intermediate time; taking the time interval between the second injected voltage and current waveform data and the third injected voltage and current waveform data being greater than or equal to the sixth intermediate time as the sixth time window constraint.

[0202] In this embodiment, the total time window constraint determination unit is configured to use the first time window constraint, the second time window constraint, the third time window constraint, the fourth time window constraint, the fifth time window constraint, and the sixth time window constraint as the total waveform injection time window constraint.

[0203] The system provided by the present invention determines the time constraint boundaries of components at each level under different fault handling time sections by analyzing waveform data and fault handling time sections, which helps to ensure the correctness and stability of each component in terms of time sequence. By controlling the waveform injection time, it is ensured that the time constraints of components at each level are satisfied during the fault handling process, avoiding faults or errors caused by time constraint violations, and achieving more accurate feeder automation testing.

[0204] The above specific embodiments have further elaborated on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the protection scope of the present invention. In particular, it is pointed out that for those skilled in the art, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An optimization method for waveform injection of the main station of voltage-time type feeder automation test, characterized in that, Including: Obtaining the voltage and current waveform data of each fault handling time section and each corresponding fault handling time section for the voltage-time type feeder automation test; According to each of the fault handling time sections, sequentially injecting the voltage and current waveform data of each corresponding fault handling time section from the test master station layer in the voltage-time type feeder automation test system into the terminal layer in the voltage-time type feeder automation test system, and determining the time constraint boundaries of each hierarchical component in the voltage-time type feeder automation test system under each fault handling time section, to obtain the total constraint of the waveform injection time window; Controlling the waveform injection time of the feeder automation test according to the total constraint of the waveform injection time window; The determining the time constraint boundaries of each component in the voltage-time type feeder automation test system under each fault handling time section to obtain the total constraint of the waveform injection time window specifically includes: Obtaining the first time window constraint according to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer makes the first opening; Obtaining the second time window constraint according to the first reclosing delay of the relay protection device in the terminal layer and the total time from the first reclosing of the relay protection device in the terminal layer until the first circuit breaker in the test master station layer completes the first reclosing; Obtaining the third time window constraint according to the sum of the information processing and transmission times of each component when the first load switch of the distribution line in the test master station layer gets voltage and closes; Obtaining the fourth time window constraint according to the sum of the information processing and transmission times of each component when the second load switch of the distribution line in the test master station layer gets voltage and closes; Obtaining the fifth time window constraint according to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer makes the second opening; Obtaining the sixth time window constraint according to the second reclosing delay of the relay protection device in the terminal layer and the total time from the second reclosing of the relay protection device in the terminal layer until the first circuit breaker in the test master station layer completes the second reclosing; Taking the first time window constraint, the second time window constraint, the third time window constraint, the fourth time window constraint, the fifth time window constraint, and the sixth time window constraint as the total constraint of the waveform injection time window.

2. The optimization method for waveform injection of the main station of voltage-time type feeder automation test according to claim 1, characterized in that, The obtaining the first time window constraint according to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer makes the first opening specifically includes: Taking the time interval between the first injection of the voltage and current waveform data and the first injection of the voltage and current waveform data being greater than or equal to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer makes the first opening as the first time window constraint; Wherein, the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer makes the first opening is the sum of the first waveform data injection time, the first terminal action time, the first terminal extension time, the first tester processing time, the first test master station simulation action topology time, and twice the first network delay.

3. The optimization method for waveform injection of the main station of voltage-time type feeder automation test according to claim 1, characterized in that, Obtaining a second time window constraint based on the first reclosing delay of the relay protection device in the terminal layer and the total time from the first reclosing of the relay protection device in the terminal layer until the first reclosing of the first circuit breaker in the test master station layer is completed, specifically including: Obtaining the total time from the first reclosing of the relay protection device in the terminal layer until the first reclosing of the first circuit breaker in the test master station layer is completed according to the sum of the third terminal extension time, the third tester processing time, the third test master station simulation action topology time, and the third network delay; Adding the first reclosing delay of the relay protection device in the terminal layer to the total time from the first reclosing of the relay protection device in the terminal layer until the first reclosing of the first circuit breaker in the test master station layer is completed, and subtracting the sum of the first terminal extension time, the first tester processing time, the first network delay, and the first test master station simulation action topology time to obtain a second intermediate time; Taking the time interval between the second injected voltage and current waveform data and the third injected voltage and current waveform data being greater than or equal to the second intermediate time as the second time window constraint.

4. The optimization method for waveform injection of the main station of voltage-time type feeder automation test according to claim 1, characterized in that, Obtaining a third time window constraint based on the total time of processing and transmitting each element information when the first load switch of the distribution line in the test master station layer gets voltage and closes the switch, specifically including: Taking the time interval between the third injected voltage and current waveform data and the fourth injected voltage and current waveform data being greater than or equal to the total time of processing and transmitting each element information when the first load switch of the distribution line in the test master station layer gets voltage and closes the switch as the third time window constraint; Wherein, the total time of processing and transmitting each element information when the first load switch of the distribution line in the test master station layer gets voltage and closes the switch is the sum of the fourth waveform data injection time, the fourth terminal action time, the fourth terminal extension time, the fourth tester processing time, the fourth test master station simulation action topology time, and twice the fourth network delay.

5. The optimization method for waveform injection of the main station of voltage-time type feeder automation test according to claim 1, characterized in that, Obtaining a fourth time window constraint based on the total time of processing and transmitting each element information when the second load switch of the distribution line in the test master station layer gets voltage and closes the switch, specifically including: Taking the time interval between the fourth injected voltage and current waveform data and the fifth injected voltage and current waveform data being greater than or equal to the total time of processing and transmitting each element information when the second load switch of the distribution line in the test master station layer gets voltage and closes the switch as the third time window constraint; Wherein, the total time of processing and transmitting each element information when the second load switch of the distribution line in the test master station layer gets voltage and closes the switch is the sum of the fifth waveform data injection time, the fifth terminal action time, the fifth terminal extension time, the fifth tester processing time, the fifth test master station simulation action topology time, and twice the fifth network delay.

6. The optimization method for waveform injection of the main station of voltage-time type feeder automation test according to claim 1, characterized in that, Obtaining a fifth time window constraint based on the total time of processing and transmitting each element information when the first circuit breaker in the test master station layer makes a second opening, specifically including: The time interval between the fifth injected voltage and current waveform data and the sixth injected voltage and current waveform data is greater than or equal to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer trips for the second time, which is used as the fifth time window constraint; Among them, the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer trips for the second time is the sum of the sixth waveform data injection time, the sixth terminal action time, the sixth terminal extension time, the sixth tester processing time, the sixth test master station simulation action topology time, and twice the sixth network delay.

7. The waveform injection optimization method for the master station of voltage-time type feeder automation test according to claim 1, wherein, Obtaining the sixth time window constraint according to the second reclosing delay of the relay protection device in the terminal layer and the total time from the second reclosing of the relay protection device in the terminal layer until the first circuit breaker in the test master station layer completes the second reclosing specifically includes: Obtaining the total time from the second reclosing of the relay protection device in the terminal layer until the first circuit breaker in the test master station layer completes the second reclosing according to the sum of the eighth terminal extension time, the eighth tester processing time, the eighth test master station simulation action topology time, and the eighth network delay; Adding the second reclosing delay of the relay protection device in the terminal layer to the total time from the second reclosing of the relay protection device in the terminal layer until the first circuit breaker in the test master station layer completes the second reclosing, and subtracting the sum of the sixth terminal extension time, the sixth tester processing time, the sixth network delay, and the sixth test master station simulation action topology time to obtain the sixth intermediate time; The time interval between the second injected voltage and current waveform data and the third injected voltage and current waveform data is greater than or equal to the sixth intermediate time, which is used as the sixth time window constraint.

8. A waveform injection optimization device for the master station of voltage-time type feeder automation test, wherein, Including: A data acquisition module for acquiring each fault processing time section of the voltage time-type feeder automation test and the voltage and current waveform data of each corresponding fault processing time section; A time window constraint analysis module for sequentially injecting the voltage and current waveform data of each corresponding fault processing time section from the test master station layer in the voltage time-type feeder automation test system into the terminal layer in the voltage time-type feeder automation test system according to each fault processing time section, and determining the time constraint boundaries of each hierarchical component in the voltage time-type feeder automation test system under each fault processing time section to obtain the total constraint of the waveform injection time window; A control time module for controlling the waveform injection time of the feeder automation test according to the total constraint of the waveform injection time window; The time window constraint analysis module specifically includes: a time window constraint determination sub-module, and the time window constraint determination sub-module includes: A first time window constraint determination unit for obtaining the first time window constraint according to the sum of the information processing and transmission times of each component when the first circuit breaker in the test master station layer trips for the first time; The second time window constraint determination unit is configured to obtain a second time window constraint according to the first reclosing delay of the relay protection device in the terminal layer and the total time from the first reclosing of the relay protection device in the terminal layer until the first reclosing of the first circuit breaker in the test master station layer is completed; The third time window constraint determination unit is configured to obtain a third time window constraint according to the sum of the element information processing and transmission times when the first load switch of the distribution line in the test master station layer is energized and closed; The fourth time window constraint determination unit is configured to obtain a fourth time window constraint according to the sum of the element information processing and transmission times when the second load switch of the distribution line in the test master station layer is energized and closed; The fifth time window constraint determination unit is configured to obtain a fifth time window constraint according to the sum of the element information processing and transmission times when the first circuit breaker in the test master station layer trips for the second time; The sixth time window constraint determination unit is configured to obtain a sixth time window constraint according to the second reclosing delay of the relay protection device in the terminal layer and the total time from the second reclosing of the relay protection device in the terminal layer until the second reclosing of the first circuit breaker in the test master station layer is completed; The total time window constraint determination unit is configured to use the first time window constraint, the second time window constraint, the third time window constraint, the fourth time window constraint, the fifth time window constraint, and the sixth time window constraint as the total waveform injection time window constraint.

Images