System and method for tier management in a memory tiered environment

Abstract

Systems and methods are provided for tier management in a memory hierarchical environment. In some embodiments, a method includes accessing, by a first processing, a first page of the first processing in a non-uniform memory access memory of a first tier; and locking, by a first thread, the first page against demotion. The first thread can be a tier management thread of the first processing, and the step of locking the first page can be based on a service level of the first processing.

Description

[0001] This application claims priority to and the benefit of U.S. Provisional Application No. 63 / 408,783, filed September 21, 2022, and U.S. Application No. 18 / 055,760, filed November 15, 2022, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] One or more aspects of embodiments in accordance with the present disclosure relate to computing systems, and more particularly, to systems and methods for tier management in a memory tiered environment. BACKGROUND

[0003] In computing systems with non-uniform memory access (NUMA) memory, several tiers of memory can be available, with different tiers exhibiting different performance characteristics. For example, a first tier of non-uniform memory access memory can exhibit higher throughput or lower latency than a second tier of non-uniform memory access memory.

[0004] In relation to this general technical environment, aspects of the present disclosure are relevant. SUMMARY

[0005] According to embodiments of the present disclosure, a method is provided, the method comprising: accessing, by a first process, a first page of the first process in a first tier of non-uniform memory access memory; and locking, by a first thread, the first page against demotion, the first thread being a tier management thread of the first process, and the step of locking the first page being based on a service level of the first process.

[0006] In some embodiments, the step of locking the first page is further based on a first rank of pages of the first process, the first rank of pages including the first page.

[0007] In some embodiments, the method comprises: locking a plurality of pages of the first process including the first page, wherein the plurality of pages is based on the service level of the first process.

[0008] In some embodiments, the plurality of pages is further based on a total number of pages of the first process.

[0009] In some embodiments, the method further comprises: accessing, by the first process, a second page of the first process in the first tier of non-uniform memory access memory; and locking, by the first thread, the second page against demotion.

[0010] In some embodiments, the method further comprises: unlocking the first page, wherein the step of unlocking the first page is based on the service level of the first process.

[0011] In some embodiments, the step of unlocking the first page is further based on a second ranking of pages of the first process, the second ranking of pages including the first page and a second page.

[0012] In some embodiments, in the second ranking, the second page is ranked higher than the first page.

[0013] In some embodiments, the first thread is dedicated to the first process.

[0014] According to embodiments of the present disclosure, a system is provided, the system comprising: a processing circuitry; and a memory operably connected to the processing circuitry and storing instructions that, when executed by the processing circuitry, cause the system to perform a method, the method comprising: accessing, by a first process, a first page of the first process in a first tier of a non-uniform memory access memory; and locking, by a first thread, the first page against demotion, the first thread being a tier management thread of the first process, and the step of locking the first page is based on a service level of the first process.

[0015] In some embodiments, the step of locking the first page is further based on a first ranking of pages of the first process, the first ranking of pages including the first page.

[0016] In some embodiments, the method comprises: locking a plurality of pages of the first process including the first page, wherein the plurality of pages is based on the service level of the first process.

[0017] In some embodiments, the plurality of pages is further based on a total number of pages of the first process.

[0018] In some embodiments, the method further comprises: accessing, by the first process, a second page of the first process in the first tier of the non-uniform memory access memory; and locking, by the first thread, the second page against demotion.

[0019] In some embodiments, the method further comprises: unlocking the first page, wherein the step of unlocking the first page is based on the service level of the first process.

[0020] In some embodiments, the step of unlocking the first page is further based on a second ranking of pages of the first process, the second ranking of pages including the first page and a second page.

[0021] In some embodiments, in the second ranking, the second page is ranked higher than the first page.

[0022] In some embodiments, the first thread is dedicated to the first process.

[0023] According to embodiments of the disclosure, a system is provided, the system comprising: means for processing; and a memory operatively connected to the means for processing and storing instructions that, when executed by the means for processing, cause the system to perform a method, the method comprising: accessing, by a first processing, a first page of the first processing in a non-uniform memory access memory of a first tier; and locking, by the first processing, the first page against demotion, the first processing being a tier management thread of the first processing, and the processing of locking the first page being based on a service level of the first processing.

[0024] In some embodiments, the step of locking the first page is further based on a first rank of the page of the first processing, the first rank of the page comprising the first page. BRIEF DESCRIPTION OF DRAWINGS

[0025] These and other features and advantages of the present disclosure will be appreciated and understood by reference to the detailed description, claims, and accompanying drawings, in which:

[0026] Figure 1 is a block diagram of a computing system according to embodiments of the disclosure;

[0027] Figure 2A is a diagram of a first example of a memory configuration at a first point in time according to embodiments of the disclosure;

[0028] Figure 2B is a diagram of a first example of a memory configuration at a second point in time according to embodiments of the disclosure;

[0029] Figure 3A is a diagram of a second example of a memory configuration at a first point in time according to embodiments of the disclosure;

[0030] Figure 3B is a diagram of a second example of a memory configuration at a second point in time according to embodiments of the disclosure;

[0031] Figure 3C is a diagram of a second example of a memory configuration at a third point in time according to embodiments of the disclosure;

[0032] Figure 3D is a diagram of a second example of a memory configuration at a fourth point in time according to embodiments of the disclosure;

[0033] Figure 4 is a diagram of a least recently used list at four points in time according to embodiments of the disclosure; and

[0034] Figure 5 is a flowchart of a method according to embodiments of the disclosure. DETAILED DESCRIPTION

[0035] The detailed description set forth below, in connection with the appended drawings, is intended as a description of exemplary embodiments of systems and methods for tier management in a memory hierarchical environment provided in accordance with the present disclosure and is not intended to represent the only forms in which the present disclosure can be constructed or utilized. The description sets forth the features of the present disclosure in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent features can be utilized in other embodiments that are also intended to be encompassed within the scope of the present disclosure. As shown elsewhere herein, like numbers in the figures intend to identify like components or features.

[0036] A computing system with non-uniform memory access memory can include several central processors (CPUs) and multiple tiers of non-uniform memory access memory connected to the central processors. The tiers can have different performance characteristics, with higher tiers performing better than lower tiers. For example, a first tier (which can be a top tier) can have certain latency characteristics and throughput characteristics, a second tier (a tier immediately below the first tier) can have higher latency or lower throughput than the first tier, and a third tier (a tier immediately below the second tier) can have higher latency or lower throughput than the second tier. Each of the central processors can be capable of and configured to run several processes simultaneously. For example, each such process can be a respective application run by a user, or it can be an application running on a server (e.g., to retrieve or process data stored on the server and send the data or results of the data processing to a client).

[0037] The non-uniform memory access memory of each tier can be arranged as a set of pages. Each process can be allocated a certain number of pages (e.g., zero pages or multiple pages) in the non-uniform memory access memory of each tier by an operating system running on the central processor. Generally, when a page is frequently used, the operating system (e.g., a kernel) can place it in a higher tier (e.g., in the first tier), and if a page is rarely used, the operating system can place it in a lower tier (e.g., in the third tier). The operating system (e.g., a kernel of the operating system) can periodically or continuously reevaluate the placement of pages in tiers, and if a page is relatively frequently used (e.g., more frequently than other pages in the tier in which the page is located), the page is promoted (e.g., moved to a higher tier), or if a page is relatively infrequently used (e.g., less frequently than other pages in the tier in which the page is located), the page is demoted (e.g., moved to a lower tier). The functionality of automatically promoting pages based on usage patterns by the operating system (e.g., by the kernel) can be referred to as automatic non-uniform memory access balancing or as “automatic NUMA.”

[0038] To assess the frequency of accesses, the kernel task can routinely sample a subset of the memory allocated to each process on each non-uniform memory access node and clear the current bit on their flags. When a CPU accesses a page, a small page fault (which can be referred to as a NUMA hint fault) is generated. In the page fault, which CPU tried to access the page can be recorded. Pages accessed from a remote CPU can be migrated to the local memory node of that CPU.

[0039] The promotion of some pages can be linked to the demotion of other pages. For example, if a tier (e.g., a first tier) is full, before another page can be promoted to the first tier, at least one page can need to be demoted from the first tier to free up space in the first tier. Thus, in some cases, the performance of memory provided to one process by a computing system can be affected by another process. For example, if a first process frequently accesses memory, the pages of the first process can be promoted, which can cause the pages of a second process to be demoted if the second process accesses memory relatively infrequently.

[0040] The ability of one process to affect the performance of another process in this way can be an obstacle to guaranteeing the performance of any given process. For example, an operator managing a set of servers can wish to offer customers (e.g., in exchange for payment) the opportunity to run processes on the servers; such customers (or “tenants”) can expect guarantees of a particular level of service (e.g., a particular number of pages in a first tier will be allocated to the process, or a particular portion of the pages of the process (e.g., half of the pages of the process) will remain in the first tier); if some processes that are active in accessing memory are able to cause the pages of other processes that are less active in accessing memory to be demoted, it can be difficult to provide such guarantees.

[0041] In this way, in some embodiments, a process running on a computing system can have associated with it a tier management thread running on the computing system. The tier management thread can monitor memory accesses performed by the process and lock pages of the process against demotion in order to maintain a particular service level for the process. The service level can require, for example, (i) that a particular number of pages of the process be kept in a first tier, or (ii) that a particular portion of the pages of the process be kept in the first tier. For example, the tier management thread can lock a number of most recently accessed pages of the process against demotion, the number of most recently accessed pages being selected to ensure that the service level requirements of the process are met. As pages of the process are promoted into the first tier, and as the access pattern of the process changes, the tier management thread can unlock some pages and lock other pages so that the most recently used pages of the process remain locked against demotion. As used herein, a "service level" is a set of one or more requirements that affect the performance of a process running in a computing system. Such requirements can include, for example, (i) a requirement that a particular number of pages of the process be kept in a first tier, or (ii) a requirement that a particular portion of the pages of the process be kept in the first tier.

[0042] In this way, some embodiments can perform: (i) create fairness between processes, where each process is guaranteed a percentage of the first tier; (ii) create performance isolation between different tenants and processes, where the activity of one process does not cause promotion of its own pages and demotion of pages of other processes; and (iii) guarantee that there are no memory shortages and performance degradations that can otherwise occur (e.g., if all pages of one process are demoted to a lower, slower tier).

[0043] Figure 1 A computing system is shown having two central processors (e.g., CPU 1 and CPU 2) 105 and four non-uniform memory access nodes, two of which are top tier (e.g., first tier) non-uniform memory access nodes (e.g., NUMA 0 and NUMA 2) 110 and two of which are lower tier (e.g., second tier) non-uniform memory access nodes (e.g., NUMA 1 and NUMA 3) 115. As shown by the legend of the figure, dashed lines show that when a page is promoted, the page can move from one non-uniform memory access node to another non-uniform memory access node, and solid lines show that when a page is demoted, the page can move from one non-uniform memory access node to another non-uniform memory access node. Figure 1

[0044] Figure 2A Figure 2B Movement of pages is shown when some pages are promoted and other pages are demoted. In this example, page 1 is promoted from NUMA 1 to NUMA 0, page 2 is demoted from NUMA 0 to NUMA 1, page 3 is promoted from NUMA 2 to NUMA 0, and page 4 is demoted from NUMA 0 to NUMA 2.​​Figure 2A and Figure 2B In the example shown, three processes (a first process, a second process, and a third process) each have pages in one or more non-uniform memory access nodes (including a first-tier non-uniform memory access node 110, a second-tier non-uniform memory access node 115, and a third-tier non-uniform memory access node 205). In this example, the first-tier non-uniform memory access node 110 is implemented as a dynamic random access memory (DRAM) that is directly connected (via an address bus and a data bus) to the CPU 105. In this example, the second-tier non-uniform memory access node 115 is implemented as a dynamic random access memory (DRAM) (e.g., a CXL-DRAM) that is connected to the CPU 105 by a compute express link (CXL) connection (e.g., with a CXL root complex connected to the CPU 105, and one or more CXL lanes (e.g., peripheral component interconnect express (PCIe) lanes) connecting the CXL root complex to a CXL endpoint that can include multiple DRAM chips or modules). In this example, the third-tier non-uniform memory access node 205 is implemented as a persistent memory device (PMEM) (e.g., a flash memory that can be part of a solid state drive).

[0045] In the example shown in FIG. 1, at a first point in time, all of the pages for the first process (labeled “pl”) are in the first-tier non-uniform memory access node 110. The first-tier non-uniform memory access node 110 also stores several pages for the second process (labeled “p2”) and several pages for the third process (labeled “p3”). Between the first point in time and a second point in time, because the first process and the third process perform fewer memory accesses within the shown pages than the second process, all of the pages for the first process and all but one of the pages for the third process are demoted to the second-tier non-uniform memory access node 115, resulting in the configuration shown in FIG. 1 at the second point in time. Figure 2A and Figure 2B In the example shown in FIG. 1, at a first point in time, all of the pages for the first process (labeled “pl”) are in the first-tier non-uniform memory access node 110. The first-tier non-uniform memory access node 110 also stores several pages for the second process (labeled “p2”) and several pages for the third process (labeled “p3”). Between the first point in time and a second point in time, because the first process and the third process perform fewer memory accesses within the shown pages than the second process, all of the pages for the first process and all but one of the pages for the third process are demoted to the second-tier non-uniform memory access node 115, resulting in the configuration shown in FIG. 1 at the second point in time. Figure 2B According to a service level expected for the first process, such demotion of the pages for the first process to the second-tier non-uniform memory access node 115 can result in the service level not being met.

[0046] As mentioned above, such results can be avoided through the use of a tier management thread. The tier management thread can be started concurrently when processing begins. Each tier management thread can be dedicated to a single process, or in some embodiments, a tier management thread can perform tier management for several processes. In some embodiments, a tier management thread is started for each process when the process begins; in some embodiments, some processes can run with an associated tier management thread, and some processes can run without an associated tier management thread. Various mechanisms can be employed to determine whether a tier management thread is started when a process begins. For example, when a process begins, it can call an operating system function that starts a tier management thread. As another example, a policy file for a process can contain a flag indicating whether a tier management thread is to run with the process; when the process begins, the operating system can read the flag, and if the flag indicates that such a thread is to be started, the tier management thread is started. As used herein, a "tier management thread" for a process is a thread that is configured to manage the location of pages for the process in the non-uniform memory access memory of one or more tiers.

[0047] In operation, the tier management thread can create a list (e.g., a least recently used (LRU) list) for the process, and shuffle the pages with the list based on the hotness or coldness of each page. The least recently used list can be a list of pages that the process has in the non-uniform memory access memory ordered according to how long ago the page was last accessed by the process. Pages that were recently accessed can be at the bottom of the least recently used list, and pages that were least recently accessed can be at the top of the least recently used list. The tier management thread can then lock (e.g., using the mlock() operating system call) particular pages to prevent demotion (e.g., lock particular pages so that they are protected from demotion by automatic non-uniform memory access balancing). The locking can be performed based on a service level for the process. For example, if a requirement of the service level is to keep a particular number of recently used pages in the first tier, the tier management thread can ensure that the number of recently used pages for the process (e.g., the number of pages at the bottom of the least recently used list) are always locked. The tier management thread can also unlock any pages that have moved up in the recently used list (e.g., because they have been accessed only rarely recently) so that it is no longer in the set of pages at the bottom of the least recently used list that should not be allowed to be demoted. In some embodiments, the tier management thread can also promote or force promote some pages for the process if, for example, the process has too few pages in the first tier.

[0048] Figures 3A to 4 An example of page promotion and page demotion, as well as page locking, is shown in some embodiments. Figures 3A to 3DThe diagram shows the page locations in the first-level non-uniform memory access nodes and the second-level non-uniform memory access nodes at four time points. Figure 4 This shows a list of the most recent uses at four different points in time. Figures 3A to 4 In the example, the service level of the process requires that at least half of the pages of the process be stored in the first-level non-uniform memory access node 110. For simplicity, the process is shown as having 10 pages; in other cases, the process may have a different number of pages. Figure 3A As shown, at the first time point, all pages numbered 1 to 10 are in the first-level non-uniform memory access node 110. Figure 4 As shown in the first list 405, pages 10, 1, 4, 6 and 7 are the last five pages in the most recently used list and have been locked by the hierarchy management thread to prevent downgrading (as indicated by the padlock symbol in the figure).

[0049] like Figure 3B and Figure 4 As shown in the second list 410, at the second time point, the operating system (e.g., the kernel's automatic non-uniform memory access balancing function) has downgraded pages 3, 2, and 9, which are not locked and are not among the five most recently used pages. At this time point, because the seven pages involved in the processing exist in the first-level non-uniform memory access node 110, the service level continues to be satisfied. Figure 3C and Figure 4 As shown in the third list 415, at the third time point, pages 2 and 9 are promoted and placed at the bottom of the furthest recently used list, and the hierarchy management thread locks pages 2 and 9 to prevent demotion and unlocks pages 6 and 7. As... Figure 3D and Figure 4 As shown in the fourth list 420, at the fourth time point, the operating system (e.g., the kernel's automatic non-uniform memory access balancing function) has degraded pages 5, 6, 7, and 8, which are no longer locked. Throughout... Figures 3A to 4 The sequence shown in the figure continues to satisfy the service level because at any given time the five pages at the bottom of the most recently used list are in the first-level non-uniform memory access node 110.

[0050] Figure 5 This is a flowchart of a method in some embodiments. The method includes: at 505, a first process accessing a first page of the first process in memory via a first-level non-uniform memory access; and at 510, a first thread locking the first page to prevent degradation. The first thread may be a hierarchy management thread of the first process, and the locking of the first page may be based on the service level of the first process.

[0051] As used herein, a "portion" of something means "at least some" of the thing, which can mean less than the whole thing or can mean the whole thing. As such, as a special case, a "portion" of a thing includes the whole thing (i.e., the whole thing is an example of a portion of the thing). As used herein, when a second quantity is "within Y of a first quantity X," this means that the second quantity is at least X-Y and at most X+Y. As used herein, when a second number is "within Y% of a first number," this means that the second number is at least (1-Y / 100) times the first number and at most (1+Y / 100) times the first number. As used herein, the term "or" is to be interpreted as "and / or," such that, for example, "A or B" means "A" or "B" or "A and B."

[0052] The background technology provided in the Background section of this disclosure is included only to provide a context for the disclosure and the contents of this section are not admitted to be prior art. Any component or any combination of components described (e.g., in any system diagram included herein) can be used to perform one or more of the operations of any flow diagram included herein. Moreover, (i) the operations are example operations and can involve various additional steps not explicitly covered, and (ii) the temporal ordering of the operations can be changed.

[0053] Each of the terms "processing circuitry" and "means for processing" is used herein to mean any combination of hardware, firmware, and software employed to process data or digital signals. The processing circuitry hardware can include, for example, an application specific integrated circuit (ASIC), a general purpose or special purpose central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), and a programmable logic device such as a field programmable gate array (FPGA). In the processing circuitry, each function is performed by hardware configured (i.e., hardwired) to perform that function, or by more general purpose hardware (such as a CPU) configured to execute instructions stored in a non-transitory storage medium. The processing circuitry can be manufactured on a single printed circuit board (PCB) or distributed among several interconnected PCBs. The processing circuitry can contain other processing circuitry; for example, the processing circuitry can include two processing circuitries (an FPGA and a CPU) interconnected on a PCB.

[0054] As used herein, when a method (e.g., adjustment) or a first quantity (e.g., a first variable) is said to be "based on" a second quantity (e.g., a second variable), this means that the second quantity is an input to the method or influences the first quantity (e.g., the second quantity can be an input (e.g., the only input or one of several inputs) to a function that computes the first quantity), or the first quantity can equal the second quantity, or the first quantity can be the same as the second quantity (e.g., stored in the same location or locations in a memory).

[0055] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“first” element, component, region, layer or section discussed herein could be termed a“second” element, component, region, layer or section without departing from the spirit and scope of the inventive concept.

[0056] For ease of description, spatial relative terms, such as“below,”“under,”“lower,”“beneath,”“above,”“upper” and the like, can be used herein for describing the relationship of one element or feature to another element or feature as shown in the drawings. It will be understood that such spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the drawings. For example, if the device in the drawings is turned over, elements described as“below” or“beneath” or“under” other elements or features would then be“above” or“over” the other elements or features. Thus, the example term“below” can encompass both an orientation of“above” and an orientation of“below.” The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will be understood that, when a layer is referred to as being“between” two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the terms“substantially,”“approximately” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0058] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when preceding a list of two or more items, cover all of the individual items in the list, as well as any combination of the individual items. Further, the use of "may" when describing embodiments of the present inventive concept indicates that one or more embodiments of the present disclosure include the stated feature, but does not require this feature, of the present disclosure. Further, the term "exemplary" is intended to indicate an example or an illustration. As used herein, the term "using" and variations thereof are considered synonymous with the term "utilizing" and variations thereof.

[0059] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to", or "adjacent to" another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "directly on", "directly connected to", "directly coupled to", or "immediately adjacent to" another element or layer, there are no intervening elements or layers present.

[0060] Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of "1.0 to 10.0" is intended to include all sub-ranges between (and including) the recited minimum and maximum values, i.e., all sub-ranges having a minimum value of equal to or greater than 1.0 and a maximum value of equal to or less than 10.0, so e.g. 2.4 to 7.6. Similarly, a range of "less than 10%" is intended to include all sub-ranges of less than 10% having a minimum of equal to or greater than 0%, e.g. 1%, and a maximum of equal to or less than 10%, e.g. 9%. Also, as is apparent from the above examples, the disclosure is intended to cover "combined ranges" where the upper limit of the range is greater than the lower limit of the range. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein.

[0061] Some embodiments include features recited in the numbered clauses below.

[0062] 1. A method comprising:

[0063] accessing, by a first process, a first page of the first process in a first tier of a non-uniform memory access memory; and

[0064] locking, by a first thread, the first page against demotion,

[0065] wherein the first thread is a tier management thread of the first process, and

[0066] the step of locking the first page is based on a service level of the first process.

[0067] 2. The method of claim 1, wherein the step of locking the first page is further based on a first rank of pages of the first process, the first page included in the first rank of pages.

[0068] 3. The method of claim 1 or claim 2, comprising locking a plurality of pages of the first process including the first page, wherein a number of the plurality of pages is based on the service level of the first process.

[0069] 4. The method of claim 3, wherein the number of the plurality of pages is further based on a total number of pages of the first process.

[0070] 5. The method of any of the preceding claims, further comprising:

[0071] accessing, by the first process, a second page of the first process in the first tier of the non-uniform memory access memory; and

[0072] locking, by the first thread, the second page against demotion.

[0073] 6. The method of claim 5, further comprising unlocking the first page, wherein the step of unlocking the first page is based on the service level of the first process.

[0074] 7. The method of claim 6, wherein the step of unlocking the first page is further based on a second rank of pages of the first process, the second rank of pages including the first page and the second page.

[0075] 8. The method of claim 7, wherein the second page is ranked higher than the first page in the second rank.

[0076] 9. The method of any of the preceding claims, wherein the first thread is dedicated to the first process.

[0077] 10. A system comprising:

[0078] processing circuitry; and

[0079] a memory, operatively connected to the processing circuitry and storing instructions that, when executed by the processing circuitry, cause the system to perform a method comprising:

[0080] accessing, by the first process, a first page of the first process in the first tier of non-uniform memory access memory; and

[0081] locking, by the first thread, the first page against demotion,

[0082] wherein the first thread is a tier management thread of the first process, and

[0083] the step of locking the first page is based on a service level of the first process.

[0084] 11. The system of statement 10, wherein the step of locking the first page is further based on a first rank of pages of the first process, the first page included in the first rank of pages.

[0085] 12. The system of statement 10 or statement 11, wherein the method comprises locking a plurality of pages of the first process, the plurality of pages including the first page, wherein a number of the plurality of pages is based on the service level of the first process.

[0086] 13. The system of any of the preceding statements, wherein the number of the plurality of pages is further based on a total number of pages of the first process.

[0087] 14. The system of any of the preceding statements, wherein the method further comprises:

[0088] accessing, by the first process, a second page of the first process in the first tier of non-uniform memory access memory; and

[0089] locking, by the first thread, the second page against demotion.

[0090] 15. The system of statement 14, wherein the method further comprises unlocking the first page, wherein the step of unlocking the first page is based on the service level of the first process.

[0091] 16. The system of statement 15, wherein the step of unlocking the first page is further based on a second rank of pages of the first process, the second rank of pages including the first page and the second page.

[0092] 17. The system of statement 16, wherein the second page is ranked higher than the first page in the second rank.

[0093] 18. The system of any of the preceding statements, wherein the first thread is dedicated to the first process.

[0094] 19. A system comprising:

[0095] an apparatus for processing; and

[0096] a memory operatively connected to the apparatus for processing and storing instructions that, when executed by the apparatus for processing, cause the system to perform a method comprising:

[0097] accessing, by the first processing, a first page of the first processing in a first tier of non-uniform memory access memory; and

[0098] locking, by the first thread, the first page against demotion,

[0099] the first thread is a tier management thread of the first processing, and

[0100] the step of locking the first page is based on a service level of the first processing.

[0101] 20. The system of statement 19, wherein the step of locking the first page is further based on a first rank of pages of the first processing, the first rank of pages including the first page.

[0102] While example embodiments of systems and methods for tier management in a memory tiering environment have been described and shown herein in particular embodiments, it will be apparent to those skilled in the art that numerous modifications and variations can be made. Thus, it will be understood that systems and methods for tier management in a memory tiering environment constructed according to the principles of the present disclosure can be implemented in a different manner than specifically described herein. The application is further defined and warranted only by the claims and their equivalents.

Claims

1. A method comprising the following steps: The first process accesses the first page of the first process in the non-uniform memory of the first level; and The first page is locked by the first thread to prevent downgrading. Its features are: in, The first thread is the first level of management thread that handles processing. The process of locking the first page is based on the service level of the first process, and Service level is a set of one or more requirements that affect the performance of processing running in a computing system.

2. The method according to claim 1, wherein, The step of locking the first page is also based on the first ranking of the first page processed, which includes the first page.

3. The method according to claim 1 or 2, comprising the step of: locking a plurality of pages, including a first page, in the first processing, wherein, The multiple pages are based on the service level of the first processing.

4. The method according to claim 3, wherein, The multiple pages are also based on the total number of pages processed in the first step.

5. The method according to any one of the preceding claims further includes the following steps: The first process accesses the second page of the first process in the non-uniform memory of the first level; and The first thread locks the second page to prevent downgrading.

6. The method according to claim 5 further comprises the step of: unlocking the first page, wherein, The steps to unlock the first page are based on the service level of the first process.

7. The method according to claim 6, wherein, The step of unlocking the first page is also based on the second ranking of the pages processed in the first process, which includes the first page and the second page.

8. The method according to claim 7, wherein, In the second ranking, the second page ranks higher than the first page.

9. The method according to any one of the preceding claims, wherein, The first thread is dedicated to the first processing.

10. A system comprising: Processing circuitry; as well as A memory, operatively connected to processing circuitry and storing instructions, which, when executed by the processing circuitry, cause the system to perform a method comprising the following steps: The first process accesses the first page of the first process in the non-uniform memory of the first level; and The first page is locked by the first thread to prevent downgrading. Its features are: Among them, the first thread is the first hierarchical management thread for processing. The process of locking the first page is based on the service level of the first process, and Service level is a set of one or more requirements that affect the performance of processing running in a computing system.

11. The system according to claim 10, wherein, The step of locking the first page is also based on the first ranking of the first page processed, which includes the first page.

12. The system according to claim 10 or 11, wherein, The method includes the following steps: locking multiple pages, including a first page, in the first process, wherein the multiple pages are based on the service level of the first process.

13. The system according to claim 12, wherein, The multiple pages are also based on the total number of pages processed in the first step.

14. The system according to any one of claims 10 to 13, wherein, The method further includes the following steps: The first process accesses the second page of the first process in the non-uniform memory of the first level; and The first thread locks the second page to prevent downgrading.

15. The system according to claim 14, wherein, The method further includes the following step: unlocking the first page, wherein the step of unlocking the first page is based on the service level of the first process.

16. The system according to claim 15, wherein, The step of unlocking the first page is also based on the second ranking of the pages processed in the first process, which includes the first page and the second page.

17. The system according to claim 16, wherein, In the second ranking, the second page ranks higher than the first page.

18. The system according to any one of the preceding claims, wherein, The first thread is dedicated to the first processing.

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