A superconducting storage-computing integrated architecture based on memristor

Abstract

The application discloses a superconducting memory and calculation integrated architecture based on a memristor, which comprises a memory and calculation unit, the memory and calculation unit comprises a superconducting layer and a memristor, the memristor comprises an intermediate layer and a top layer, and the superconducting layer is connected with the top layer of the memristor through the intermediate layer; a plurality of rows of memory and calculation units and a plurality of columns of memory and calculation units are cross-connected to form a cross array structure, input voltage signals of each row of the cross array structure are used as matrix input signals, the cross array structure realizes matrix multiplication and addition operation, and the last memory and calculation unit of each column outputs a matrix multiplication and addition operation result, wherein the superconducting layer is used to improve operation speed; and the application has the advantages that the memory and calculation integrated architecture solves the problems of insufficient calculation speed and high energy consumption and the like by using the memory capacity of the memristor and the characteristics of high-speed reading and writing and low power consumption of the superconducting layer.

Description

Technical Field

[0001] This invention relates to the field of superconducting electronics and in-memory computing architecture design, specifically to a superconducting in-memory computing architecture based on memristors. Background Technology

[0002] With the rapid development of technologies such as cloud computing, big data, and artificial intelligence, the amount of data is growing exponentially, bringing about a series of problems such as massive computing power demands and energy consumption. However, traditional semiconductor-based storage and computing architectures have some bottlenecks, such as low data transfer efficiency between storage and computing, excessive energy consumption, and corresponding heat dissipation challenges. Therefore, research on in-memory computing chips based on low power consumption and high computing power is of extremely important scientific and strategic significance.

[0003] Currently, memristor-based in-memory computing architectures have been extensively studied and have broad application potential, including in fields such as artificial intelligence, edge computing, and the Internet of Things. However, in practical applications, this architecture still faces some challenges, such as insufficient computing speed and high energy consumption. For example, Chinese Patent Publication No. CN114861902A discloses a processing unit and its operation method, as well as a computing chip. This processing unit includes: a memristor array configured to be mapped as a weight matrix for a neural network layer; an input module configured to receive input data and convert the input data into an input signal for input into the memristor array; and an output module configured to receive the output signal obtained after the memristor array performs computational processing on the input signal and convert the output signal into output data. This patent application proposes a superconducting-memristor in-memory computing architecture based on the memristor energy consumption problem, combining the advantages of low superconducting energy consumption and memristor neuromorphic computing to achieve a novel ultra-low power in-memory computing architecture. Summary of the Invention

[0004] The technical problem to be solved by this invention is that the existing memristor-based in-memory computing architecture suffers from insufficient computing speed and high energy consumption.

[0005] This invention solves the above-mentioned technical problems through the following technical means: a superconducting in-memory computing architecture based on memristors, including a computing unit, the computing unit including a superconducting layer and a memristor, the memristor including an intermediate layer and a top layer, the superconducting layer being connected to the top layer of the memristor through the intermediate layer; a cross array structure is formed by cross-connecting several rows of computing units and several columns of computing units, each row of the cross array structure inputs a voltage signal as a matrix input signal, the cross array structure realizes matrix multiplication and addition operations, and the last computing unit of each column outputs the matrix multiplication and addition operation result, wherein the superconducting layer is used to improve the computing speed.

[0006] Furthermore, the superconducting circuit material used in the superconducting layer includes niobium or aluminum.

[0007] Furthermore, the memristor is a metal oxide layer, wherein the material of the intermediate layer is titanium oxide or niobium oxide.

[0008] Furthermore, the top layer of the memristor includes a top electrode, and the material of the top electrode includes platinum and gold.

[0009] Furthermore, the storage unit can perform multiplication operations, expressed by the formula [output voltage state] = I b R s *[Input Voltage State]*[Resistance State], where input voltage state refers to the high / low level state of the voltage input to the memory unit, output voltage state refers to the high / low level state of the voltage output to the memory unit, and resistance state refers to the high / low resistance state of the memristor. b For bias current, R s This refers to the quench resistance of the superconducting layer.

[0010] Furthermore, multiple memory computing units are linearly connected to form an array unit. The array unit connects the superconducting layers of each memory computing unit in series. Each memory computing unit's memristor receives the input voltage signal individually. The voltage of the superconducting electrode of the superconducting layer in the entire circuit serves as the output voltage of the array unit. The output voltage of the array unit increases linearly with the number of memory computing units.

[0011] Furthermore, each column of the cross array structure is an array unit, and each row receives the same input voltage signal, thus connecting all the memory units in each row together. The input voltage signals received from the first row to the m-th row are V1 to V2, respectively. m The last memory cell in each column outputs the output voltage of a single array cell, which is V. o1 To V on .

[0012] Furthermore, the cross array structure is applied to a convolutional neural network as the hardware circuit for convolution operations in the convolutional neural network.

[0013] Furthermore, each convolutional layer of the convolutional neural network corresponds to a memristor in each memory unit of the cross array structure. The convolutional neural network updates the weights in the convolutional layers through backpropagation based on the gradient descent method of the loss function, and continuously trains the convolutional neural network. The weight values ​​output by the convolutional layers in the trained convolutional neural network are mapped to the corresponding memristors.

[0014] Furthermore, when the cross array structure is applied to a convolutional neural network, the formula for its convolution operation is as follows:

[0015]

[0016] Among them, wnm It is the weight value corresponding to the memristor of the storage unit in the m-th row and n-th column of the cross array structure.

[0017] Furthermore, the power consumption calculation formula for the memristor-based superconducting in-memory computing architecture is as follows:

[0018]

[0019] Among them, R n R is the resistance in the normal state of the superconducting layer. LRS This is the resistance value of the memristor in its low-resistance state.

[0020] The advantages of this invention are:

[0021] (1) This invention utilizes the storage capacity of memristors and the high-speed read / write and low-power characteristics of superconducting layers to combine memristors and superconducting layers, giving full play to their respective advantages, integrating the advantages of memristors and superconducting circuits into one, realizing a new in-memory computing architecture with high processing speed and low power consumption, and solving the problems of insufficient computing speed and high energy consumption in the current in-memory computing architecture.

[0022] (2) The superconducting in-memory computing architecture proposed in this invention effectively avoids the large number of logic gate units required for multiplication and addition operations in traditional semiconductor chips. By utilizing the multiplication and addition operations and parallel computing capabilities of the in-memory computing unit, the overall performance can be effectively improved, and the integration of the chip application direction can be greatly enhanced.

[0023] (3) This invention applies the cross array structure to the convolutional neural network as a hardware circuit for the convolution operation in the convolutional neural network, and realizes a neural network hardware accelerator for neuromorphic computing.

[0024] (4) The superconducting in-memory computing architecture based on memristors of the present invention has been experimentally verified to have a power consumption of only 1.6μW, while the power consumption of existing memristor-based systems is above 77.5mW. Therefore, the present invention has a power efficiency advantage of ~48400 times. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure and circuit symbols of a memory computing unit in a memristor-based superconducting in-memory computing architecture disclosed in an embodiment of the present invention. Figure 1 (a) is a schematic diagram of the storage unit. Figure 1 (b) is a schematic diagram of the circuit symbol of the memory computing unit;

[0026] Figure 2 This is a current-voltage characteristic diagram of the memristor and superconducting layer in a memristor-based superconducting in-memory computing architecture disclosed in an embodiment of the present invention; wherein, Figure 2(a) is a schematic diagram of the current-voltage characteristics of a memristor. Figure 2 (b) is a schematic diagram of the current-voltage characteristics of the superconducting layer;

[0027] Figure 3 This is a schematic diagram illustrating the implementation of multiplication operations by the in-memory computing unit in a memristor-based superconducting in-memory computing architecture according to an embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram illustrating the accumulation operation of the output signal by the array unit in a memristor-based superconducting in-memory computing architecture, as disclosed in an embodiment of the present invention; wherein, Figure 4 (a) is a schematic diagram of the array cell structure. Figure 4 (b) is a schematic diagram of the output voltage of the linearly accumulated array units;

[0029] Figure 5 This is a schematic diagram illustrating the multiply-accumulate operation of a signal using a cross-array structure in a memristor-based superconducting in-memory computing architecture, as disclosed in an embodiment of the present invention.

[0030] Figure 6 This is a schematic diagram of the convolution operation of a convolutional neural network in a memristor-based superconducting in-memory computing architecture disclosed in an embodiment of the present invention.

[0031] Figure 7 This is a schematic diagram illustrating a handwritten digit recognition task implemented using a memristor-based superconducting in-memory computing architecture, as disclosed in an embodiment of the present invention. Figure 7 (a) is a schematic diagram of the image flattening input cross array structure. Figure 7 (b) is a schematic diagram of the training results on the MNIST dataset.

[0032] Figure 8 This is a comparison chart of the energy consumption of a memristor-based superconducting in-memory computing array architecture and a memristor array architecture as disclosed in an embodiment of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] like Figure 1As shown, this invention provides a memristor-based superconducting in-memory computing architecture, including a computing unit. The computing unit includes a superconducting layer 1 and a memristor 2. The memristor 2 includes an intermediate layer 21 and a top layer 22. The superconducting layer 1 is connected to the top layer 22 of the memristor 2 through the intermediate layer 21. The memristor 2 can use a metal oxide layer, such as titanium oxide (TiOx) or niobium oxide (NbOx), as the intermediate layer 21. The top electrode can be made of materials such as platinum or gold. The superconducting layer 1 can be made of metals such as niobium or aluminum as the superconducting circuit material. The computing unit as a whole is a three-layer structure composed of the memristor 2 and the superconducting electrode. A schematic diagram of the structure and circuit symbol of the computing unit is shown below. Figure 1 As shown, where, Figure 1 (a) is a schematic diagram of the storage unit. Figure 1 (b) is a schematic diagram of the circuit symbol of the memory unit.

[0035] The memory unit has current-voltage characteristics, wherein the current-voltage characteristics of memristor 2 and superconducting layer 1 are as follows: Figure 2 As shown, Figure 2 (a) is a schematic diagram of the current-voltage characteristics of a memristor. Figure 2 (b) is a schematic diagram of the current-voltage characteristics of the superconducting layer. Memristor 2 is initially in a high-resistivity state, and no conductive filaments have yet formed inside. When an external voltage is applied greater than the threshold voltage, the vacancy inside memristor 2 will gradually form conductive filaments under the influence of the electric field. At this time, memristor 2 will be positioned in a low-resistivity state, forming a conductive channel. Similarly, when a reverse voltage is applied to a certain value, memristor 2 will reset to a high-resistivity state under the influence of the reverse electric field, realizing the transition and storage of high and low resistance states. For superconducting layer 1, when there is no external energy, the superconducting electrode exhibits superconductivity at low temperatures. At this time, when the applied bias current is less than the superconducting critical current, the voltage across superconducting layer 1 is zero, i.e., V = 0. However, when external energy, such as heat, is applied greater than the critical heat (P > P0), the voltage across the superconducting layer 1 is zero. th When the superconducting layer 1 is in the normal metallic state, a voltage signal, V = 1, will be generated at both ends when a bias current is applied externally.

[0036] The storage unit can perform multiplication operations, such as... Figure 3 As shown, the input voltage (high level '0' or low level '1'), the resistance state of memristor 2 (high resistance '0' or low resistance '1'), and the output voltage (high level '0' or low level '1') are represented in binary. When memristor 2 stores a low resistance state '1' and the input voltage is high level '1', the applied power P on the superconducting electrode of the device is greater than the critical heat P. thWhen the superconducting layer 1 enters a resistive state due to the thermionic effect, it outputs a high-level signal '1' under the bias current. When the input voltage is low-level '0', there is no external power applied to the superconducting electrode, and it remains in the superconducting state, outputting a low-level signal '0' under the bias current. When the memristor 2 stores a high-resistance state '0': when the input voltage is high-level '1', the applied power P to the superconducting electrode is less than the critical heat P. th The device remains in the superconducting state, and under the influence of bias current, the output is a low-level signal '0'. When the input voltage is low-level '0', there is no external power applied to the superconducting electrodes, and the device remains in the superconducting state, outputting a low-level signal '0' under the influence of bias current. In summary, the memory-based computing unit can perform multiplication operations, expressed by the formula [output voltage state] = I. b R s *[Input Voltage State]*[Resistance State], where input voltage state refers to the high / low level state of the voltage input to the memory unit, output voltage state refers to the high / low level state of the voltage output to the memory unit, and resistance state refers to the high / low resistance state of memristor 2. b For bias current, R s This refers to the quench resistance of the superconducting layer.

[0037] like Figure 4 As shown, multiple in-memory computing units are linearly connected to form an array unit. Figure 4 (a) is a schematic diagram of the array unit structure. The array unit is formed by connecting the superconducting layers 1 of each memory computing unit in series. Each memory computing unit's memristor 2 receives the input voltage signal independently. The voltage of the superconducting electrode of the superconducting layer 1 in the entire circuit serves as the output voltage of the array unit. The output voltage of the array unit increases linearly with the number of memory computing units. Figure 4 (b) is a schematic diagram of the linearly accumulated output voltage of the array units. Specifically, the input and output signals of the device circuit are calculated using LTSpice simulation software. The parameters used in the circuit simulation correspond to the actual device parameters, where the device bias current Is is 10 microamps, and the high-voltage state input voltage V of memristor 2 is... m The voltage is 0.032V, and the low-impedance state of memristor 2 is 10. 5 The superconducting circuit has a superresistance of 10 ohms. Through LTSpice simulation, when the cell input voltage state is '1' and the low-resistance state is '1', the linear accumulation process of the superconducting electrode output voltage with the number of cells was obtained. In summary, the array cell proposed in this invention can realize the accumulation operation of the output signal.

[0038] By arranging the above array units into a cross array structure, signal multiplication and addition operations can be achieved, such as... Figure 5As shown, each column of the cross array structure is an array unit, and each row receives the same input voltage signal, thus connecting all the memory units in each row together. The input voltage signals received from the first row to the m-th row are V1 to V2, respectively. m The last memory cell in each column outputs the output voltage of a single array cell, which is V. o1 To V on Specifically, the weighted resistive state w ij Stored in memristor 2, combined with the input signal (V1…V m By controlling the voltage state of superconducting layer 1, and connecting the voltage signals in series in superconducting layer 1, voltage addition can be achieved. Through this process, the signal matrix multiplication and addition operation can be completed, and the output signal (V) is obtained. o1 …V on This is equal to the cross product of the memristor 2 weighted array (i.e., high and low impedance states) and the input signal (V1…V). m Therefore, the superconducting architecture based on memristor 2 proposed in this invention can be used to realize the core operation in in-memory computing chips - signal matrix multiplication and addition.

[0039] The matrix multiplication and addition in the aforementioned cross-array structure can realize the edge applications of artificial neural networks. A specific implementation scheme is as follows... Figure 6 As shown, the invention mainly consists of two parts. First, a convolutional neural network framework is built in the software using the proposed model. The computation process is completed through forward propagation, and the weights in the convolutional layers are updated through backpropagation based on the gradient descent method of the loss function. Second, the weights in the trained convolutional layers are mapped to the proposed superconducting in-memory computing architecture framework through the inference mapping rule of memristor 2. When a signal is input from the input end, it passes through the array of memristor 2 and superconducting layer 1 to realize the convolution operation (i.e., matrix multiplication and addition) to obtain the output signal, thus realizing the hardware circuit implementation of the convolution operation in the convolutional neural network algorithm. Specifically, each convolutional layer of the convolutional neural network corresponds to a memristor 2 in each in-memory unit of the cross array structure. The convolutional neural network updates the weights in the convolutional layers through backpropagation based on the gradient descent method of the loss function, continuously training the convolutional neural network. The weights output by the convolutional layers in the trained convolutional neural network are mapped to the corresponding memristor 2. The formula for the convolution operation of the convolutional neural network is as follows:

[0040]

[0041] Among them, w nm It is the weight value corresponding to memristor 2 of the storage unit in the m-th row and n-th column of the cross array structure.

[0042] To verify the effectiveness of the present invention, Figure 7This invention demonstrates that the proposed superconducting in-memory computing architecture can be used to implement handwritten digit recognition tasks. Figure 7 (a) is a schematic diagram of the image flattening input cross array structure. Figure 7 (b) is a schematic diagram of the training results on the MNIST dataset. A 3x3 pixel matrix is ​​extracted from the 28x28 pixel MNIST dataset image and flattened before being input into the array of this invention to perform convolution multiplication and addition operations. Starting from the top left corner of the image, the entire image is scanned row by row and column by column by continuously sliding the 3x3 convolution window, thereby achieving convolution operations on the entire image. Using the above process, the MNIST dataset was trained and tested. After 50 iterations, the in-memory array of this invention achieved a handwritten digit recognition accuracy of 97.1%.

[0043] The memristor-based superconducting in-memory computing architecture of this invention combines the resistance storage principle of memristor 2 with the hot electron control principle of superconducting materials to achieve in-memory computing functionality. In common Ag electrode-based memristors 2, the absence of vacancies in the oxide layer generates conductive filaments. These filaments can be controlled by the amplitude of voltage pulses, thereby enabling the storage of high and low resistance states in memristor 2. The second key working principle of this invention utilizes the control mechanism of superconducting materials. When the external heat exceeds the superconducting Cooper pair binding energy, the superconducting Cooper pairs are broken up by hot electrons, entering a resistive state. Thus, by controlling the external heat, the conversion between the superconducting and resistive states can be achieved. Combined with the externally input voltage signal and the internal resistance state of memristor 2, the information storage and computing operation is completed.

[0044] In this invention, the summation process of the output signal of the cross array structure applies Kirchhoff's voltage law to the superconducting circuit. In the cross array structure, the input signal of each row generates a corresponding voltage (high level or low level) on the superconducting circuit after passing through memristor 2. According to Kirchhoff's voltage law, the output voltage is the sum of series voltage signals. Therefore, the output signal of each column is the product of the state of the input signal of each row and the state stored in memristor 2.

[0045] Finally, this invention highlights the potential advantages of the superconductor-memristor array architecture in artificial intelligence systems. To evaluate the performance difference between the superconductor-memristor-based system and the conventional memristor-based system, power consumption was assessed for both systems. For the first convolutional layer in the simulation, the power consumption (PS) of the superconductor-memristor architecture was calculated as follows:

[0046]

[0047] Among them, the bias current I is set. b The normal-state resistance R of the bottom superconductor is 10 μA. nThe resistance is 10Ω, and the applied high potential V m 0.033V, low resistance R LRS 1×10 5 Ω.

[0048] Similarly, the power consumption (PM) of a memristor-based architecture is calculated as follows:

[0049]

[0050] Among them, V M This is the input high potential of the memristor array (set to 0.1V), and the line resistance R of the bottom electrode. L The array structure of this invention is configured to be 1000Ω. For example... Figure 8 As shown, the superconductor-memristor-based system exhibits a significant power consumption advantage, consuming only 1.6 μW for a 25*64 array, with most of the power consumption occurring in the memristor's low-resistance state (LRS). In contrast, a typical memristor system is estimated to consume 77.5 mW on the same 25*64 array, with the majority of power consumption occurring in the current flow within the normal bottom electrode. That is, document CN114861902A, mentioned in the background art, consumes at least 77.5 mW under the same configuration conditions as this invention, while document CN109657787A, in addition to including the aforementioned memristor architecture, also incorporates a CPU-like processor. Therefore, under the same configuration conditions as this invention, its power consumption is 77.5 mW plus the inherent losses of the CPU. Therefore, the superconductor-memristor-based memory computing system proposed in this invention exhibits an astonishing advantage of approximately 48,400 times in power efficiency, demonstrating a significant computational advantage compared to typical memristor systems.

[0051] Through the above technical solutions, this invention utilizes the storage capacity of memristor 2 and the high-speed read / write and low-power characteristics of superconducting layer 1 to combine memristor 2 and superconducting layer 1, giving full play to their respective advantages and integrating the advantages of memristor 2 and superconducting circuits into one, realizing a new in-memory computing architecture with high processing speed and low power consumption, and solving the problems of insufficient computing speed and high energy consumption in the current in-memory computing architecture.

[0052] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A superconducting in-memory computing architecture based on memristors, characterized in that, The system includes a storage unit comprising a superconducting layer and a memristor. The memristor includes an intermediate layer and a top layer, with the superconducting layer connected to the top layer of the memristor via the intermediate layer. Several rows and columns of storage units are cross-connected to form a cross-array structure. Each row of the cross-array structure receives a voltage signal as a matrix input signal. The cross-array structure performs matrix multiplication and addition operations. The last storage unit in each column outputs the result of the matrix multiplication and addition operation. The superconducting layer is used to improve the computation speed. The storage unit is capable of multiplication operations, expressed by the formula [output voltage state] = [Input Voltage State] [Resistance State], where input voltage state refers to the high or low level state of the voltage input to the memory unit, output voltage state refers to the high or low level state of the voltage output to the memory unit, and resistance state refers to the high or low resistance state of the memristor. For bias current, The superconducting layer has a quench resistance; multiple memory cells are linearly connected to form an array cell, where the superconducting layers of each memory cell are connected in series. Each memory cell's memristor receives an input voltage signal individually. The voltage of the superconducting electrode of the superconducting layer in the entire circuit serves as the output voltage of the array cell, which linearly accumulates with the number of memory cells. Each column of the cross-array structure is an array cell, and each row receives the same input voltage signal, thus connecting all memory cells in each row together. The input voltage signals received from the first row to the m-th row are respectively... to The last memory unit in each column outputs the output voltage of a single array unit, which is respectively to .

2. The superconducting in-memory computing architecture based on memristors according to claim 1, characterized in that, The superconducting layer uses superconducting circuit materials including niobium or aluminum.

3. The superconducting in-memory computing architecture based on memristors according to claim 1, characterized in that, The memristor is a metal oxide layer, and the material of its intermediate layer is titanium oxide or niobium oxide.

4. The superconducting in-memory computing architecture based on memristors according to claim 1, characterized in that, The top layer of the memristor includes a top electrode, and the material of the top electrode includes platinum and gold.

5. The superconducting in-memory computing architecture based on memristors according to claim 1, characterized in that, The cross array structure is applied to a convolutional neural network as a hardware circuit for convolution operations. Each convolutional layer of the convolutional neural network corresponds to a memristor in each memory unit of the cross array structure. The convolutional neural network updates the weights in the convolutional layers through backpropagation based on the gradient descent method of the loss function, and continuously trains the convolutional neural network. The weight values ​​output by the convolutional layers in the trained convolutional neural network are mapped to the corresponding memristors.

6. The superconducting in-memory computing architecture based on memristors according to claim 5, characterized in that, When the cross-array structure is applied to a convolutional neural network, the formula for its convolution operation is as follows: in, It is the weight value corresponding to the memristor of the storage unit in the m-th row and n-th column of the cross array structure.

7. The superconducting in-memory computing architecture based on memristors according to claim 6, characterized in that, The power consumption calculation formula for the memristor-based superconducting in-memory computing architecture is as follows: in, The resistance of the superconducting layer in its normal state. This is the resistance value of the memristor in its low-resistance state.

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