Chip and method for triggering and verifying an interrupt

Abstract

The embodiment of the present application provides a chip, an interrupt triggering device and a verification method, the device comprises: an interrupt receiving unit, which is used for setting a first indication signal of an interrupt in an interrupt register of any module of the chip when any interrupt triggering pulse of any module of the chip is generated; an interrupt triggering unit, which is used for generating a first state signal of the interrupt in the interrupt register according to the first indication signal and a shielding signal of the first indication signal in the interrupt register, and setting a second triggering signal of the module when the first state signal is set; and an interrupt merging unit, which is used for generating a third triggering signal of the chip when the second triggering signal is set, so as to generate an interrupt pin signal of the chip through an interrupt controller. The embodiment of the present application unifies the triggering mode of each interrupt in the chip, and improves the design and verification efficiency of the interrupt triggering of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design, in particular to a chip and a triggering device and verification method of interrupt. BACKGROUND

[0002] At present, the implementation of interrupt is mainly realized by the mode of sending to the interrupt processing module on the module.

[0003] This mode has the following problems:

[0004] 1) In the design stage, there are many interrupt sources, and there are more interfaces of modules, and different modules are usually completed by different engineers, the instances of triggering to the chip interrupt pin are not unified, the design is complex and the workload is large;

[0005] 2) In the verification stage, the interrupts scattered to each module are triggered to the chip interrupt pin through different instances, and it is impossible to verify through a unified verification method, and it is necessary to query each module, and the verification workload is large. SUMMARY

[0006] Therefore, the embodiments of the present application provide a chip and a triggering device and verification method of interrupt. The technical scheme of the embodiments of the present application is used to trigger the chip interrupt to the chip interrupt pin, unifies the triggering mode of each interrupt in the chip, improves the efficiency of the triggering design of the chip interrupt, and the unified triggering mode can be verified through a unified component, thereby improving the efficiency of the verification of the chip interrupt.

[0007] In a first aspect, the embodiments of the present application provide a triggering device of chip interrupt, comprising: an interrupt receiving unit, configured to set a first indication signal of an interrupt in an interrupt register of a module when a triggering pulse of any interrupt of any module of a chip is generated; an interrupt triggering unit, configured to generate a first state signal of the interrupt in the interrupt register according to the first indication signal and a shielding signal thereof in the interrupt register, and set a second triggering signal of the module when the first state signal is set; and an interrupt merging unit, configured to generate a third triggering signal of the chip when the second triggering signal is set, so as to generate a chip interrupt pin signal through an interrupt controller.

[0008] According to the above, the device realizes the unified triggering mode of each interrupt from the pulse signal to the chip interrupt pin signal, improves the efficiency of the triggering design of the chip interrupt, and the unified triggering mode can be verified through a unified component, thereby improving the efficiency of the verification of the chip interrupt.

[0009] In a possible implementation mode of the first aspect, the device further comprises an address obtaining unit, configured to obtain the address of the interrupt register and the offset address of each signal thereof according to the interrupt register table of the module.

[0010] According to the above, the interrupt register address of each module and the offset address of each signal thereof are obtained through the table of the interrupt register of each module, so that the implementation logic of the trigger device of the present application is the same and can be used for interrupt triggering of each module, and each module only needs to query the table of the interrupt register to obtain the corresponding address.

[0011] In a possible implementation of the first aspect, during chip back-end testing, the interrupt triggering unit is further configured to generate the first status signal according to the simulation signal and the mask signal of the first indication signal in the interrupt register.

[0012] According to the above, the interrupt triggering verification mode during chip back-end testing is unified through the simulation signal of the first indication signal in the interrupt register.

[0013] In a possible implementation of the first aspect, the first status signal of each interrupt is the result of the AND operation between the first indication signal of the interrupt and the result of the OR operation between the simulation signal of the first indication signal of the interrupt and the non-operation result of the mask signal of the first indication signal of the interrupt.

[0014] According to the above, the generation of the first status signal of the interrupt in any scenario is unified through the operation between the first indication signal, the simulation signal and the mask signal thereof, and the implementation of the interrupt triggering is further unified.

[0015] In a possible implementation of the first aspect, the interrupt merging unit comprises: a module receiving unit configured to convert the second trigger signal into a pulse signal when the second trigger signal is set to be on, and use the pulse signal to set the second indication signal of the module to be on by hardware; and a module triggering unit configured to generate a second status signal of the module according to the second indication signal and a mask signal thereof, so as to generate the third trigger signal.

[0016] According to the above, the unified triggering mode of the merged module interrupt is implemented through the module receiving unit and the module triggering unit.

[0017] In a possible implementation of the first aspect, the interrupt merging unit further comprises: a chip triggering unit configured to set the third trigger signal to be on when the second status signal is set to be on.

[0018] According to the above, the unified triggering mode from the module to the chip is implemented through the chip triggering unit.

[0019] In a possible implementation of the first aspect, during chip back-end testing, the module triggering unit is further configured to generate the second status signal according to the simulation signal and the mask signal of the second indication signal.

[0020] According to the above, the second state signal of each module is generated by the second indication signal of the module, the simulation signal of the second indication signal of the module, and the simulation signal of the second indication signal of the module and the mask signal of the second indication signal of the module.

[0021] In a possible implementation of the first aspect, the second state signal of each module is the result of the AND operation between the second indication signal of the module and the result of the OR operation between the simulation signal of the second indication signal of the module and the result of the NOT operation of the mask signal of the second indication signal of the module.

[0022] According to the above, the second state signal of each module is generated by the second indication signal of the module, the simulation signal of the second indication signal of the module, and the simulation signal of the second indication signal of the module and the mask signal of the second indication signal of the module.

[0023] In a possible implementation of the first aspect, the third trigger signal of the chip and the interrupt trigger signal of the third-party IP module integrated in the chip are input to the interrupt controller to generate the interrupt pin signal.

[0024] According to the above, the third trigger signal of the chip and the interrupt trigger signal of the third-party IP module integrated in the chip are processed to be compatible with the interrupt trigger of the third-party IP module.

[0025] In the second aspect, an embodiment of the present application provides a chip interrupt verification method, which is verified by the device of any one of the first aspect, and includes: setting an excitation signal of an interrupt to be verified according to a test case, wherein the excitation signal includes an interrupt pulse signal of the interrupt and a mask signal of a first indication signal of the interrupt; obtaining a first state signal of the interrupt, a second trigger signal of a module where the interrupt is located, a third trigger signal of the chip, and an interrupt pin signal by the device, and comparing the signals with expected signals to obtain a verification result.

[0026] According to the above, the unified trigger mode of each interrupt from the pulse signal to the interrupt pin signal of the chip improves the efficiency of chip interrupt verification.

[0027] In a possible implementation of the second aspect, the interrupt register address and the offset address of each signal of the interrupt register are obtained according to the interrupt register table of each module, and the addresses are used to obtain the addresses of the corresponding excitation signals.

[0028] According to the above, the addresses of the corresponding excitation signals are obtained by the interrupt register table of each module to be set, which improves the efficiency of chip interrupt verification.

[0029] In a possible implementation of the second aspect, in the chip back-end test verification, the excitation signal comprises an analog signal of a first indication signal of an interrupt to be verified and a mask signal, and the first status signal of the interrupt obtained by the device is a signal generated by the interrupt trigger unit according to the analog signal and the mask signal.

[0030] In this way, the interrupt trigger verification mode in the chip back-end test is unified by the analog signal of the first indication signal in the interrupt register.

[0031] In a possible implementation of the second aspect, when the device of the first aspect is further configured to: convert the second trigger signal into a pulse signal when the second trigger signal is set, and use the pulse signal to set a second indication signal of the module by hardware, and generate a second status signal of the module according to the second indication signal and a mask signal of the second indication signal, to generate the third trigger signal, and the excitation signal further comprises a second trigger signal and a second indication signal of the module to be verified.

[0032] In this way, the verification of the unified trigger mode of the merged interrupt of the module is implemented by the excitation signal further comprising the second trigger signal and the second indication signal of the module to be verified.

[0033] In a possible implementation of the second aspect, in the chip back-end test, the device of the first aspect is further configured to: generate the second status signal according to an analog signal of the second indication signal and a mask signal of the second indication signal.

[0034] In this way, the interrupt trigger verification mode in the chip back-end test is unified by the analog signal of the second indication signal at the module level.

[0035] In a third aspect, an embodiment of the present application provides a chip comprising the device of any of the embodiments of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 FIG. 1 is a structural schematic diagram of an interrupt trigger device in a chip according to an embodiment of the present application;

[0037] Figure 2 FIG. 2 is a structural schematic diagram of an interrupt trigger device in a chip according to another embodiment of the present application;

[0038] Figure 3 FIG. 3 is a signal flow schematic diagram of the interrupt trigger device in the chip according to the embodiment of the present application in a module;

[0039] Figure 4 FIG. 4 is a signal flow schematic diagram of interrupt merging of a plurality of modules in the interrupt trigger method according to the embodiment of the present application;

[0040] Figure 5A flowchart of a verification method of a chip interrupt according to an embodiment of the present application;

[0041] Figure 6 A flowchart of a verification method of a chip interrupt according to an embodiment of the present application;

[0042] Figure 7 A flowchart of a verification method of a chip interrupt according to an embodiment of the present application; DETAILED DESCRIPTION

[0043] In the following description, reference is made to the "some embodiments", which describe a subset of all possible embodiments, but it can be understood that the "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0044] In the following description, the terms "first\second\third, etc." or modules A, B, C, etc. are used only to distinguish similar objects or to distinguish different embodiments, and do not represent a specific order for the objects. It can be understood that the specific order or sequence can be interchanged as permitted, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein.

[0045] In the following description, the labels indicating steps, such as S110, S120, etc., do not necessarily mean that the steps are executed in this order, and the order of the steps can be interchanged or executed simultaneously as permitted.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0047] The embodiments of the present application provide a chip and an interrupt triggering device and a verification method. The device comprises: an interrupt receiving unit, configured to set a first indication signal of an interrupt in an interrupt register of a module when any module of the chip generates a triggering pulse of any interrupt; an interrupt triggering unit, configured to generate a first state signal of the interrupt in the interrupt register according to the first indication signal and a shielding signal thereof in the interrupt register, and set a second triggering signal of the module when the first state signal is set; and an interrupt merging unit, configured to generate a third triggering signal of the chip when the second triggering signal is set, so as to generate an interrupt pin signal of the chip through an interrupt controller.

[0048] The technical scheme of the embodiment of the present application is used for triggering the chip interrupt to the chip interrupt pin, unifies the triggering mode of each interrupt in the chip, improves the efficiency of the design engineer in the triggering design of the chip interrupt, and the unified triggering mode can be verified through the unified component, thereby improving the efficiency of the verification engineer in the verification of the chip interrupt.

[0049] The embodiments of the present application will be described below with reference to the accompanying drawings. First, the interrupt registers of the embodiments of the present application are introduced based on Table 1.

[0050] Each module in the present application has an interrupt register, which stores the signals of each interrupt (the interrupt of each channel) of the module, including the first indication signal of each interrupt of the module, the masking signal of the first indication signal, and the first state signal of each interrupt, each signal occupying one bit in the interrupt register.

[0051] The first indication signal of each interrupt is a sticky signal, which is set by hardware and cleared by software, and is set when the trigger pulse of the interrupt is received.

[0052] The masking signal of the first indication signal of each interrupt is the masking signal of the interrupt, which is set and cleared by software, and is used for masking the interrupt, and is effective in high level. When the masking signal is 0, the interrupt has no masking effect. The first indication signal of each interrupt is used for querying the hardware related event corresponding to the interrupt.

[0053] The first state signal of each interrupt is effective in high level, and is used for generating the interrupt pin signal of the chip, which is effective in high level. The first state signal of each interrupt is equal to the result of the and operation between the first indication signal of the interrupt and the not signal of the masking signal. The first state signal of each interrupt is used for marking the state of the hardware related event corresponding to the interrupt after processing, and the processing is masking.

[0054] In some embodiments, the interrupt register of each module also stores the analog signal of the first indication signal of each interrupt of the module. At this time, the first state signal of each interrupt is equal to the result of the and operation between the first indication signal of the interrupt and the not signal of the masking signal.

[0055] In some embodiments, the interrupt register table in the module includes the addresses of the signals.

[0056] Table 1 shows an example of the signal addresses of the interrupt register of a module.

[0057]

[0058] Wherein, XXX_Intr_Stricky0 and XXX_Intr_Stricky1 represent the first indication signal of the 0th and the first channel of the module XXX, the attribute (Attribute) column Sticky represents a sticky signal, hardware set up and software clear 0; XXX_Intr_Stat0 and XXX_Intr_Stat1 represent the first state signal of the 0th and the first channel of the module XXX, which is a readable signal; XXX_Intr_Mask0 and XXX_Intr_Mask1 represent the first indication signal of the 0th and the first channel of the module XXX, which is a mask signal, and is a readable and writable signal; XXX_Intr_set0 and XXX_Intr_set1 represent the first indication signal of the 0th and the first channel of the module XXX, which is an analog signal, and is a readable and writable signal.

[0059] Wherein, in Table 1, the number of interrupts in the actual scene is designed based on the demand.

[0060] Wherein, in Table 1, the base address (base_Addr) of the interrupt register of the module and the offset address (Offset_Addr) of each signal of each channel are also included.

[0061] In some embodiments, the interrupt register of each module also saves the second indication signal of the module, and the analog signal and the mask signal thereof, and the second indication signal of each interrupt is used to query whether there is any hardware related event corresponding to the interrupt in the module. The second state signal of each module is used to mark the state of the hardware related event corresponding to each interrupt of the module after the state is combined and processed, and the processing is masking.

[0062] The following is based on Figure 1 An embodiment one of a chip interrupt triggering device of the application is introduced.

[0063] Figure 1 An embodiment one of a chip interrupt triggering device is shown, which includes an interrupt receiving unit 110, an interrupt triggering unit 120 and an interrupt combining unit 130.

[0064] The interrupt receiving unit 110 is used to set up the first indication signal of the interrupt in the interrupt register of the module when any module of the chip generates a trigger pulse of any interrupt.

[0065] Wherein, the first indication signal is a sticky signal, which is saved in the interrupt register of the module, and the high level is effective.

[0066] Wherein, each interrupted trigger pulse is an upward or downward pulse signal, and the uniform high level effective sticky signal is obtained by the sticky signal.

[0067] Wherein, each module has multiple channels, and each channel has its own interrupt. The chip of the embodiment is a physical chip or a code module for implementing a physical chip.

[0068] The interrupt trigger unit 120 is configured to generate a first state signal of each interrupt in the interrupt register according to the first indication signal of each interrupt of each module and the masking signal of the interrupt in the interrupt register of the module, and to set the second trigger signal of the module when the first state signal is set.

[0069] Wherein, the first state signal of each interrupt is used to indicate the state of the interrupt, and the second trigger signal of each module is used to indicate whether the interrupt of the module is triggered.

[0070] In some embodiments, the second trigger signal of each module is also stored in the interrupt register of the module.

[0071] In some embodiments, the trigger device of the embodiment further comprises an address obtaining module configured to obtain the address of the interrupt register and the offset address of each signal of the interrupt register according to the interrupt register table of each module.

[0072] In some embodiments, the second trigger signal of each module is equal to the or operation result of the first state signals of each interrupt of the module, so that the second trigger signal of the module is set when the first state signal of any interrupt of the module is set.

[0073] In some embodiments, the interrupt register of each module also stores the analog signal of the first indication signal of each interrupt of the module, and the trigger device of the embodiment is used for interrupt verification in chip back-end testing. The interrupt trigger unit 120 is further configured to generate the first state signal of the verification interrupt according to the analog signal of the first indication signal and the masking signal. At this time, the first state signal of each interrupt is the and operation result between the or operation result between the first indication signal of the interrupt and the analog signal of the first indication signal of the interrupt, and the not operation result of the masking signal of the first indication signal of the interrupt. Because the first indication signal of each interrupt cannot be set by software in back-end testing, it is in an invalid state, and the first state signal of each interrupt can be simplified as the and operation result between the analog signal of the first indication signal and the not operation result of the masking signal of the first indication signal.

[0074] The interrupt merging unit 130 is configured to generate a third trigger signal of the chip when the second trigger signal of one module is set, so as to generate the interrupt pin signal of the chip through the interrupt controller.

[0075] The third trigger signal of the chip is used to indicate whether an interrupt is triggered in the chip.

[0076] In some embodiments, the third trigger signal of the chip is set up when the second trigger signal of any module is set up.

[0077] In some embodiments, the interrupt merging unit 130 comprises a module receiving unit, which is used to convert the second trigger signal of each module into a pulse signal when the second trigger signal of each module is set up, and set up the second indication signal of the module by hardware using the pulse signal; and a module triggering unit, which is used to generate the second state signal of the module according to the second indication signal and the masking signal thereof, so as to generate the third trigger signal of the chip, wherein the second state signal of each module is the result of the and operation between the non-signal of the second indication signal of the module and the masking signal of the second indication signal of the module.

[0078] In some embodiments, the second indication signal and the second state signal of each module are also in the interrupt register of the module, so as to facilitate the inquiry of whether there is an interrupt in the module according to the interrupt register.

[0079] In some embodiments, when the device of the present embodiment is used for the interrupt verification in the back-end test of the chip, the module triggering unit is further used to generate the second state signal of the module according to the analog signal of the second indication signal of each module and the masking signal, wherein the second state signal of each module is the result of the and operation between the or operation result of the second indication signal of the module and the analog signal of the second indication signal of the module and the non operation result of the masking signal of the second indication signal of the module, because the second indication signal of each module cannot be set up by software in the back-end test and is in an invalid state, the second state signal of each module can be simplified as the result of the and operation between the analog signal of the second indication signal and the non operation result of the masking signal of the second indication signal.

[0080] In some embodiments, the analog signal of the second indication signal of each module is also in the interrupt register of the module.

[0081] In some embodiments, the interrupt merging unit 130 further comprises a chip triggering unit, which is used to set up the third trigger signal of the chip when the second state signal of one module is set up, wherein the third trigger signal of the chip is equal to the or operation result of the second state signal of the module.

[0082] In some embodiments, the third trigger signal is input into the interrupt controller together with the interrupt trigger signal of the three-party IP module integrated in the chip, so as to generate the interrupt pin signal of the chip.

[0083] In some embodiments, the device of the present embodiment is implemented by hardware generated by interrupt register code, which is called by the processing module of each interrupt, and the interrupt register code integrates the table of interrupt registers of each module at compile time, and the table of interrupt registers of each module saves the base address of the interrupt register of the module and the offset address of each signal of each channel.

[0084] In other embodiments, the device of the present embodiment is implemented by hardware generated by interrupt register code of each module, which is called by the processing module of each interrupt, and the interrupt register code integrates the table of interrupt registers of the module at compile time

[0085] In summary, the technical solution of the first embodiment of the chip interrupt triggering device is used for triggering chip interrupts, unifies the triggering mode of each interrupt in the chip, improves the design and verification efficiency of chip interrupt triggering, and improves the design and verification quality of chip interrupt processing, and the use interface is more friendly.

[0086] The following is based on Figures 2 to 4 The second embodiment of the chip interrupt triggering device of the present application is introduced.

[0087] The second embodiment of the chip interrupt triggering device inherits all the structures of the first embodiment of the chip interrupt triggering device, has all the advantages thereof, and can not only be used for interrupt verification during chip front-end testing, but also can be used for interrupt verification during chip back-end testing.

[0088] The definition and implementation method of each signal of the present embodiment are referred to the definition of the first embodiment of the chip interrupt triggering method.

[0089] Figure 2 The structure of the second embodiment of the chip interrupt triggering device is shown, which includes an interrupt receiving unit 210, an interrupt triggering unit 220, a module receiving unit 230, a module triggering unit 240, a chip triggering unit 250, and a pin triggering unit 260.

[0090] The interrupt receiving unit 210 is used to set the first indication signal of any interrupt in the interrupt register of the module when any module of the chip generates a triggering pulse of any interrupt.

[0091] Wherein, the working principle and advantages refer to the interrupt receiving unit 110 of the first embodiment of the chip interrupt triggering device.

[0092] The interrupt triggering unit 220 is used to generate the first state signal of each interrupt in the interrupt register according to the first indication signal of each interrupt of each module and the shielding signal and simulation signal of the interrupt in the interrupt register of the module, and set the second triggering signal of the module when the first state signal is set.

[0093] wherein each first status signal of an interrupt is the result of an AND operation between the result of an OR operation between the first indication signal of the interrupt and the analog signal of the first indication signal of the interrupt, and the result of a NOT operation of the masking signal of the first indication signal of the interrupt. The second trigger signal of each module is equal to the result of an OR operation of the first status signals of the interrupts of the module.

[0094] Figure 3 An implementation is shown in which the interrupt receiving unit 210 and the interrupt triggering unit 220 are combined together, and the same aggregation from interrupts to modules is implemented, which is completed by the same instance method for all modules.

[0095] In the figure, xxx represents a module, and the interrupt sources xxx_intr_p0-n (n is a channel) are pulse signals of each interrupt, which will set the first indication signal of the corresponding interrupt in the XXX_REG_INST module, which is the STICKY signal in the figure.

[0096] In the figure, the SET signal is the analog signal of the first indication signal of each interrupt of the channels 0-n of the XXX module, which is readable and writable by software, and is used for software to initiate interrupt path testing during chip back-end testing.

[0097] In the figure, the MASK signal is the analog signal of the first indication signal of each interrupt of the channels 0-n of the XXX module, which is used to mask the hardware interrupt, and when the software does not need to process some interrupts, this register can be used to close.

[0098] In the figure, the STAT signal is the first status signal of each interrupt of the channels 0-n of the XXX module after being processed by software and hardware, which is used to mark event information and is represented as XXX_Intr_0-n.

[0099] In the figure, the first status signal of each interrupt of the XXX module is subjected to an OR operation for one-level aggregation, and the output 1bit XXX_Int is the second trigger signal of the module.

[0100] The module receiving unit 230 is used to convert the second trigger signal of any module into a pulse signal when the second trigger signal is set, and to set the second indication signal of the module in the interrupt register according to the pulse signal.

[0101] In the figure, the second indication signal is also a sticky signal that is set by hardware and cleared by software.

[0102] The module triggering unit 240 is used to obtain the second status signal of the module according to the second indication signal, the masking signal of the module in the interrupt register, and the analog signal.

[0103] The second status signal of each module is the result of the AND operation between the result of the OR operation between the second indication signal of the module and the analog signal of the second indication signal of the module and the result of the NOT operation of the mask signal of the second indication signal of the module.

[0104] The second indication signal, the second status signal, the analog signal of the second status signal and the mask signal of each module are also stored in the register of the module.

[0105] The third trigger signal of the chip is set up when the second status signal of one module is set up. The third trigger signal of the chip is equal to the result of the OR operation of the second status signals of all modules.

[0106] The third trigger signal is input into the interrupt controller together with the interrupt trigger signal of the three-party IP module integrated in the chip to generate the interrupt pin signal of the chip.

[0107] Figure 4 The implementation mode in which the module receiving unit 230, the module trigger unit 240, the chip trigger unit 250 and the pin trigger unit 260 are combined together is the top-level implementation mode from the module to the chip interrupt pin. Each module is implemented through the same instance method.

[0108] The int_0-n in the figure is the second trigger signal of the module 0-n, which is a level signal, i.e. continuously high or continuously low. The TOP_REG_INST converts it into a pulse signal and sets up the STICKY signal. The STICKY signal is the second indication signal of the module.

[0109] The SET signal, the MASK signal and the STAT signal in the figure are respectively the analog signal, the mask signal and the second status signal of each module. The STAT signal is equal to the result of the AND operation between the result of the OR operation of the SET signal and the STICKY signal and the result of the NOT operation of the MASK signal.

[0110] The int_circuit signal in the figure is the third trigger signal of the chip, which is equal to the result of the OR operation of the second status signals int_0-n of all modules.

[0111] The ip_intn and ip_intm in the figure are the interrupt trigger signals of the three-party IP module integrated in the chip. The third trigger signal of the chip and the interrupt trigger signal of the three-party IP module are input into the interrupt controller to generate the signal of the chip interrupt pin.

[0112] In summary, the technical scheme of the second embodiment of the chip interrupt triggering device can be used not only for interrupt verification in chip front-end testing, but also for interrupt verification in chip back-end testing, and can be applied to chips with multiple modules and integrated third-party IP modules, so as to trigger multiple module interrupts and third-party IP integrated interrupts, further unify the triggering mode of the interrupts of the modules in the chip, and further improve the design and verification efficiency of the chip interrupt triggering.

[0113] A chip interrupt verification method embodiment is described below based on the accompanying drawings.

[0114] The first embodiment of the chip interrupt verification method verifies interrupt triggering through the first embodiment of the chip interrupt triggering device, and has all the advantages of the first embodiment of the chip interrupt triggering device.

[0115] Figure 5 The flow of the first embodiment of the chip interrupt verification method is shown, which includes steps S510 and S520.

[0116] S510: Set the excitation signal of the interrupt to be verified according to the test case.

[0117] In chip front-end testing verification, the excitation signal includes the interrupt pulse signal of the interrupt and the shielding signal of the first indication signal of the interrupt. At this time, the code of the chip interrupt triggering device is verified, and the generation of the pulse signal of the interrupt can be simulated.

[0118] In some embodiments, in chip back-end testing verification, the excitation signal includes the simulation signal of the first indication signal of the interrupt and the shielding signal. At this time, the chip is directly tested, the pulse signal of the interrupt cannot be directly simulated, the first indication signal is always low, and only the simulation signal of the first indication signal can be verified.

[0119] In some embodiments, the interrupt register address of the module and the offset address of each signal thereof are obtained according to the interrupt register table of the module where the interrupt to be verified is located, so as to obtain the address of the related signal of the excitation signal in the interrupt register.

[0120] S520: Obtain the first state signal of the interrupt, the second triggering signal of the module where the interrupt is located, the third triggering signal of the chip, and the interrupt pin signal through the device of the first embodiment of the chip interrupt triggering device, and compare them with the expected signal to obtain the verification result.

[0121] Wherein, in the chip front-end test verification, the first indication signal of the interrupt to be verified is obtained through the interrupt receiving unit; the first state signal of the interrupt to be verified is the result of the operation between the first indication signal of the interrupt and the non-signal of its mask signal, and is obtained through the interrupt triggering unit. When the interrupt to be verified is masked, the mask signal is set to be valid, for example, in the high level state.

[0122] In some embodiments, in the chip back-end test verification, the first state signal of the interrupt is the signal generated by the interrupt triggering unit according to the analog signal of the first indication signal when the mask signal is invalid, which is essentially equal to the first indication signal. When the interrupt to be verified is masked, the mask signal is set to be valid, for example, in the high level state.

[0123] Wherein, the second triggering signal of the module, the third triggering signal of the chip and the interrupt pin signal are obtained through the interrupt merging unit in the chip front-end test or back-end test.

[0124] A chip interrupt verification method embodiment two verifies the interrupt triggering through a chip interrupt triggering device embodiment two, which has all the advantages of the chip interrupt triggering device embodiment one.

[0125] Figure 6 A flow of the chip interrupt verification method embodiment two is shown, which includes steps S610 to S630.

[0126] S610: Set the excitation signal according to the test case, wherein the test case is divided into interrupt verification and module verification; the interrupt verification and the module verification are further divided into chip front-end test and chip back-end test.

[0127] Wherein, in the interrupt verification of the chip front-end test, the excitation signal includes the interrupt pulse signal of the interrupt, the mask signal and the analog signal of the first indication signal of the interrupt, the mask signal and the analog signal of the second indication signal of the module, and the mask signal and the analog signal of the second indication signal of the module are all set to be invalid, for example, in the low level state.

[0128] Wherein, in the interrupt verification of the chip back-end test, the excitation signal includes the mask signal and the analog signal of the first indication signal of the interrupt, the mask signal and the analog signal of the second indication signal of the module, and the mask signal and the analog signal of the second indication signal of the module are all set to be invalid.

[0129] Wherein, in the module verification of the chip front-end test, the excitation signal includes the second triggering signal of the module, the mask signal and the analog signal of the second indication signal, and the pulse signal and the analog signal of the first indication signal of any interrupt of the module are all set to be invalid.

[0130] Wherein, in the module test of the chip back-end test, the excitation signal includes the shielding signal and the analog signal of the second indication signal of the module, and the analog signal of any first indication signal of the module is in the invalid state.

[0131] Wherein, the interrupt register address of the module and the offset address of each signal thereof are obtained according to the module where the interrupt to be verified is located or the interrupt register table form to be verified, so as to obtain the address of the related signal of the excitation signal in the interrupt register.

[0132] Wherein, when verifying the interrupt, the next step is to execute step S620, and when verifying the module, the next step is to execute step S630.

[0133] S620: The device of the second embodiment of the triggering device of the chip interrupt obtains the first state signal of the interrupt to be verified, the second state signal of the module where the interrupt is located, the third triggering signal of the chip and the interrupt pin signal, and compares them with the expected signal to obtain the verification result.

[0134] Wherein, the first state signal of the interrupt is obtained by the interrupt triggering unit, the second state signal of the module where the interrupt is located is obtained by the module triggering unit, the third triggering signal of the chip is obtained by the chip triggering unit, and the interrupt pin signal is obtained by the pin triggering unit.

[0135] S630: The device of the second embodiment of the triggering device of the chip interrupt obtains the second state signal of the module to be verified, the third triggering signal of the chip and the interrupt pin signal, and compares them with the expected signal to obtain the verification result.

[0136] Wherein, the second state signal of the module is obtained by the module triggering unit, the third triggering signal of the chip is obtained by the chip triggering unit, and the interrupt pin signal is obtained by the pin triggering unit.

[0137] Embodiments of the present application also provide an implementation method of the triggering device of the chip interrupt, which is used to implement the first embodiment of the triggering device of the chip interrupt or the second embodiment of the triggering device of the chip interrupt.

[0138] The following is based on Figure 7 An implementation method of the triggering device of the chip interrupt is introduced. Figure 7 A flow of the implementation method of the triggering device of the chip interrupt is shown, which includes steps S710 to S770.

[0139] S710: Obtain the interrupt source code of each module.

[0140] S720: Fill in the interrupt register table form of each module.

[0141] The interrupt register table of each module is used to store the address of each signal in the interrupt register of the module. The content of the interrupt register table of each module can refer to the embodiment one of the chip interrupt triggering device.

[0142] S730: obtaining a code generation tool.

[0143] The code generation tool generates the interrupt register code of each module by a unified implementation method, and the interrupt register code is used to implement the embodiment one or the embodiment two of the chip interrupt triggering device.

[0144] S740: obtaining a common verification tool.

[0145] The verification method of the common verification tool for each interrupt of each module is the same.

[0146] The steps S710 to S740 are run in parallel.

[0147] S750: generating the interrupt register code of each module.

[0148] The interrupt register code of each module is generated by the code generation tool according to the interrupt register table.

[0149] The interrupt register code of each module is implemented by a set of code generation tools, the logic of the interrupt register code of each module is the same, the verification method is the same, and the only difference is the signal address given by the interrupt register table.

[0150] S760: instantiating the connection between the interrupt register code and the interrupt source code.

[0151] The interrupt register code and the interrupt source code of each module of the chip are instantiated and connected to generate the device in the embodiment one or two of the chip interrupt triggering device.

[0152] The interrupt register code and the interrupt source code of each module of the chip are instantiated and connected, and the interrupt source code of each module directly calls the interrupt register code of the module when generating an interrupt.

[0153] S770: generating a verification code.

[0154] The corresponding signal of each interrupt of the interrupt register of each module is set by the common verification tool, and the interrupt register code of the corresponding module is verified.

[0155] Because the implementation method of the interrupt register code of each module is the same, the common verification tool can be used for verification.

[0156] The embodiment of the application also provides a chip, which comprises the device of the embodiment one or the embodiment two of the trigger device of the chip interruption.

[0157] It should be noted that the above only describes the preferred embodiments of the application and the principles of the applied technology. Those skilled in the art will understand that the application is not limited to the specific embodiments described herein, and that various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the scope of the application. Therefore, although the application has been described in detail through the above embodiments, the application is not limited to the above embodiments, and more other equivalent embodiments can be included without departing from the concept of the application, and all belong to the protection scope of the application.

Claims

1. An apparatus for triggering a chip interrupt, the apparatus comprising: The device comprises: an interrupt receiving unit, configured to set a first indication signal of an interrupt in an interrupt register of a module when a trigger pulse of any interrupt of the module is generated; an interrupt triggering unit, configured to generate a first status signal of the interrupt in the interrupt register according to the first indication signal and a mask signal of the first indication signal in the interrupt register, and set a second trigger signal of the module when the first status signal is set; an interrupt merging unit, configured to generate a third trigger signal of a chip when the second trigger signal is set, so as to generate an interrupt pin signal of the chip through an interrupt controller; wherein the interrupt merging unit comprises: a module receiving unit, configured to convert the second trigger signal into a pulse signal when the second trigger signal is set, and set a second indication signal of the module through hardware by using the pulse signal; a module triggering unit, configured to generate a second status signal of the module according to the second indication signal and a mask signal of the second indication signal, so as to generate the third trigger signal; a chip triggering unit, configured to set the third trigger signal when the second status signal is set.

2. The apparatus of claim 1, wherein The device further comprises: an address obtaining unit, configured to obtain an address of the interrupt register and an offset address of each signal stored in the interrupt register according to a table of the interrupt register of the module.

3. The apparatus of claim 1, wherein During back-end testing of the chip, the interrupt triggering unit is further configured to generate the first status signal according to a simulation signal of the first indication signal in the interrupt register and the mask signal.

4. The apparatus of claim 3, wherein The first status signal of each interrupt is a result of AND operation between an or operation result between the first indication signal of the interrupt and a simulation signal of the first indication signal of the interrupt, and a non-operation result of the mask signal of the first indication signal of the interrupt.

5. The apparatus of claim 1, wherein During back-end testing of the chip, the module triggering unit is further configured to generate the second status signal according to a simulation signal of the second indication signal and a mask signal.

6. The apparatus of claim 5, wherein The second status signal of each module is a result of AND operation between an or operation result between the second indication signal of the module and a simulation signal of the second indication signal of the module, and a non-operation result of the mask signal of the second indication signal of the module.

7. The apparatus of claim 1, wherein The third trigger signal is input to the interrupt controller together with an interrupt trigger signal of a third-party IP module integrated in the chip, so as to generate the interrupt pin signal.

8. A method of verifying a chip interrupt, the method comprising: Verification is performed by the device according to any one of claims 1 to 7, comprising: setting an excitation signal of an interrupt to be verified according to a test case, wherein the excitation signal comprises an interrupt pulse signal of the interrupt and a mask signal of the first indication signal of the interrupt during front-end testing verification of the chip; obtaining the first status signal of the interrupt, the second trigger signal of the module where the interrupt is located, the third trigger signal of the chip and the interrupt pin signal through the device, and comparing the signals with expected signals to obtain a verification result.

9. The method of claim 8, wherein, The device further comprises: obtaining the address of the interrupt register of the module and the offset address of each signal stored in the interrupt register according to a table of the interrupt register of the module where the interrupt to be verified is located, so as to obtain the addresses of related signals of the excitation signal in the interrupt register.

10. The method of claim 8, wherein, In the chip back-end test, the excitation signal comprises an analog signal of a first indication signal of an interrupt to be verified and a shielding signal, and the first status signal of the interrupt obtained by the device is a signal generated by the interrupt trigger unit according to the analog signal and the shielding signal.

11. A chip, characterized by Comprise: The device of any one of claims 1 to 7. The device of any one of claims 1 to 7.

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