RRAM reading circuit and reading method of RRAM reading circuit
By designing an RRAM reading circuit including multiple modules, the problems of insufficient reading margin and complex structure in the prior art are solved, and the RRAM reading effect with high reliability and high density is achieved.
Patent Information
- Application Number
- CN202311862202.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-04-11
- Estimated Expiration
- 2043-12-29
AI Technical Summary
After the process node is reduced, the existing RRAM reading circuit has insufficient reading margin, which can easily lead to reading failure, and has a complex structure and large area occupancy, which affects the memory density of the chip.
A RRAM reading circuit including a switching module, a self-biasing module, a cross-coupling module, a precharge module and an output module is designed. Through the discharge, precharge and comparison steps, the read enable voltage and precharge voltage are reasonably set to increase the read margin and shorten the read time.
By increasing the read margin and shortening the read time, the reliability of RRAM reading data is enhanced, and the power consumption and footprint of the power supply are reduced, thereby improving the storage density of the chip.
Smart Images
Figure CN117746946B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a RRAM reading circuit and a reading method of the RRAM reading circuit. Background Art
[0002] Resistive Random Access Memory (RRAM) is an emerging non-volatile storage technology based on the reversible conversion of the resistance of non-conductive materials between high resistance and low resistance under the action of an external electric field. It has the high-speed read and write capabilities of static random access memory, the high integration of dynamic random access memory, and can basically achieve unlimited data writing. After applying different voltage conditions, RRAM can show two resistance states of high and low resistance and can permanently retain stored data after power failure. RRAM is currently mainly used in IoT devices, neural networks, artificial intelligence and other fields. In terms of commercialization, RRAM has two main application directions-storage applications and storage and computing applications. In terms of storage applications, some manufacturers have applied RRAM to the MCU field; in terms of storage and computing integration, some companies are currently trying to realize AI high-computing chips based on RRAM through a storage and computing integrated architecture, and apply them in application scenarios on the center and edge sides.
[0003] The way to read RRAM storage information is to convert its resistance signal into a current or voltage signal that can be read by the peripheral circuit. Figure 1 As shown. The transistors M0 and M1 of the same size are used as switch tubes to connect the read circuit and the array resistors during the period when the read enable voltage Vread is pulled high. The LDO (Low Dropout Regulaor) structure composed of the transistors M2 and M3 of the same size and two identical OTAs (Operational Transconductance Amplifiers) clamps the voltages at points A and B, and converts the information of the variable resistor of the RRAM and the information of the reference resistor into current information. The two currents generated at points A and B are respectively sent to the transistors M4 and M5 of the same size. The transistors M4 and M5 are PMOS transistors connected as diodes, which can convert the current information into voltage information and send it to the two ends of the comparator CMP for comparison, and then output the read data Dout. Summary of the invention
[0004] Although the above RRAM read circuit can realize the reading of RRAM resistance information, the structure has the following defects. First, as the process node continues to shrink, the window between the high resistance and low resistance of RRAM is also shrinking; the above RRAM read circuit only generates two comparison currents in the storage unit and the reference unit and then converts them into comparison voltages, which does not increase the reading margin. As the resistance window decreases, there is a risk of reading failure. Secondly, in general, in order to make the resistance of transistor M0 and transistor M1 smaller when they are turned on and the adaptation error generated smaller, the size requirements of transistor M0 and transistor M1 are relatively large, which leads to the jump level when Vread is pulled high. Through the gate-drain parasitic capacitance of transistor M0 and transistor M1, the potential of point A is raised, that is, the read voltage is increased. The role of Vclamp is to clamp the read voltage of RRAM, and if the read voltage is too high, RRAM may be miswritten, changing the resistance state of RRAM, and causing reliability problems for RRAM. In addition, the memory generally requires more than 8 bits of output, which means that an RRAM memory requires at least 8 read circuits to output data in parallel. The structure of the above RRAM read circuit will occupy the area of at least 16 operational transconductance amplifiers (OTAs) and their bias circuits, which will affect the storage density of the chip.
[0005] The present invention is proposed in view of the above situation, and its purpose is to provide an RRAM reading circuit, which includes multiple transistors, a reference resistor, and a comparator. Through a discharge step, a pre-charge step, and a comparison step, the RRAM reading circuit sets a read enable voltage, a voltage opposite to the read enable voltage, a pre-charge voltage, and a voltage opposite to the pre-charge voltage so that the RRAM reading circuit can be used for reading, so as to convert the resistance value signal of the variable resistor of the RRAM into a signal that can be read.
[0006] Technical solutions to technical problems
[0007] In order to solve the above problem, the RRAM reading circuit involved in the first aspect of the present invention includes:
[0008] Reference resistor;
[0009] A switch module, one side of which is connected to the reference resistor and the variable resistor of the RRAM, and is used to control the on-off between the reference resistor and the variable resistor of the RRAM and the self-bias module;
[0010] A self-bias module, one side of which is connected to the other side of the switch module, and is used to clamp the voltage of the node between the self-bias module and the switch module in the pre-charging step;
[0011] A cross-coupling module, one side of which is connected to the other side of the self-bias module, and is used to amplify the current difference formed in the pre-charging step through positive feedback to convert it into a comparison voltage;
[0012] a pre-charging module, the pre-charging module being connected to the other side of the cross-coupling module and being used for pre-charging the RRAM reading circuit; and
[0013] An output module is connected to the other side of the cross-coupling module and is used for comparing the comparison voltage amplified by the cross-coupling module and outputting a comparison result.
[0014] Furthermore, the RRAM reading circuit performs the following steps when reading:
[0015] A discharge step, the discharge step being used to discharge the node between the output module and the cross-coupling module and the clamping node in the self-bias module;
[0016] a pre-charging step for charging a node between the output module and the cross-coupling module to a power supply voltage and charging the clamping node in the self-biasing module to a clamping voltage; and
[0017] A comparison step is used to amplify the current difference formed in the pre-charging step through positive feedback to convert it into a comparison voltage, compare the comparison voltage amplified by the cross-coupling module, and output a comparison result.
[0018] Furthermore, the switch module includes a first transistor and a twelfth transistor.
[0019] The self-bias module includes a second transistor, a third transistor, a tenth transistor and an eleventh transistor,
[0020] The cross-coupling module includes a fourth transistor, a fifth transistor, an eighth transistor and a ninth transistor,
[0021] The pre-charging module includes a sixth transistor and a seventh transistor,
[0022] The output module includes a comparator,
[0023] The source of the twelfth transistor is connected to the variable resistor of the RRAM, the gate of the twelfth transistor is connected to the gate of the first transistor, and the drain of the twelfth transistor is connected to the source of the second transistor.
[0024] The source of the first transistor is connected to the reference resistor, the drain of the first transistor is connected to the source of the third transistor,
[0025] The gate of the second transistor is connected to the drain of the tenth transistor, the source of the eleventh transistor, and the gate of the third transistor, and the drain of the second transistor is connected to the source of the fourth transistor.
[0026] The gate of the third transistor is connected to the drain of the tenth transistor, the source of the eleventh transistor, and the gate of the second transistor, and the drain of the third transistor is connected to the drain of the eleventh transistor and the source of the fifth transistor.
[0027] The gate of the fourth transistor is connected to one input terminal of the comparator, the drain of the fifth transistor, the drain of the seventh transistor, and the drain of the ninth transistor. The drain of the fourth transistor is connected to the drain of the eighth transistor, the drain of the sixth transistor, the other input terminal of the comparator, and the gate of the fifth transistor.
[0028] The gate of the fifth transistor is connected to the other input terminal of the comparator, the drain of the fourth transistor, the drain of the sixth transistor, and the drain of the eighth transistor. The drain of the fifth transistor is connected to the drain of the ninth transistor, the drain of the seventh transistor, one input terminal of the comparator, and the gate of the fourth transistor. The source of the fifth transistor is connected to the drain of the third transistor and the drain of the eleventh transistor.
[0029] The drain of the sixth transistor is connected to the drain of the eighth transistor, the drain of the fourth transistor, the other input terminal of the comparator, and the gate of the fifth transistor, the gate of the sixth transistor is connected to the gate of the seventh transistor, and a power supply voltage is applied to the source of the sixth transistor.
[0030] The drain of the seventh transistor is connected to the drain of the ninth transistor, the drain of the fifth transistor, one input terminal of the comparator, and the gate of the fourth transistor, and a power supply voltage is applied to the source of the seventh transistor.
[0031] The source of the eighth transistor is grounded, and the drain of the eighth transistor is connected to the drain of the fourth transistor, the drain of the sixth transistor, the other input terminal of the comparator, and the gate of the fifth transistor.
[0032] The source of the ninth transistor is grounded, and the drain of the ninth transistor is connected to the drain of the fifth transistor, the drain of the seventh transistor, one input terminal of the comparator, and the gate of the fourth transistor.
[0033] The source of the tenth transistor is grounded, and the drain of the tenth transistor is connected to the gate of the second transistor, the gate of the third transistor, and the source of the eleventh transistor.
[0034] The drain of the eleventh transistor is connected to the drain of the third transistor and the source of the fifth transistor, and the source of the eleventh transistor is connected to the gate of the second transistor, the gate of the third transistor, and the drain of the tenth transistor.
[0035] A read enable voltage is applied to the gate of the twelfth transistor and the gate of the first transistor, and a voltage having an opposite phase to the read enable voltage is applied to the gates of the eighth transistor, the ninth transistor, and the tenth transistor,
[0036] A precharge voltage is applied to the gate of the eleventh transistor, and a voltage having an opposite phase to the precharge voltage is applied to the gates of the sixth transistor and the seventh transistor.
[0037] The read enable voltage, the voltage opposite to the read enable voltage, the precharge voltage, and the voltage opposite to the precharge voltage are set so as to enable reading by the RRAM read circuit to convert the resistance signal of the variable resistor of the RRAM into a signal that can be read.
[0038] Further, a node between the drain of the twelfth transistor and the source of the second transistor is set to L1, a node between the drain of the first transistor and the source of the third transistor is set to L2, a node between the drain of the fourth transistor and the drain of the sixth transistor is set to L3, a node between the drain of the fifth transistor and the drain of the seventh transistor is set to L4, and a node between the gate of the second transistor and the gate of the third transistor is set to L5,
[0039] The RRAM reading circuit performs the following steps when reading:
[0040] a discharging step, in which the read enable voltage is set to a low voltage, a voltage inverted with the read enable voltage is set to a high voltage, the precharge voltage is set to a low voltage, and a voltage inverted with the precharge voltage is set to a high voltage, so that the eighth transistor, the ninth transistor, and the tenth transistor are turned on, so that L3, L4, and L5 are discharged;
[0041] a precharging step, in which the read enable voltage is set to a high voltage, a voltage inverted with the read enable voltage is set to a low voltage, the precharging voltage is set to a high voltage, and a voltage inverted with the precharging voltage is set to a low voltage, so that the twelfth transistor, the first transistor, the sixth transistor, the seventh transistor, and the eleventh transistor are turned on, so that L3 and L4 are charged to the power supply voltage, and L5 is charged to the clamping voltage; and
[0042] A comparison step, in which the read enable voltage is maintained at a high voltage, the voltage opposite to the read enable voltage is maintained at a low voltage, the pre-charge voltage is set to a low voltage, and the voltage opposite to the pre-charge voltage is set to a high voltage, so that the twelfth transistor and the first transistor remain turned on, and the sixth transistor, the seventh transistor, and the eleventh transistor are turned off, so as to compare the voltage difference formed between L3 and L4 through the comparator.
[0043] Further, in the comparison step, when the resistance value of the variable resistor of the RRAM is lower than the resistance value of the reference resistor, the voltage drop rate of L4 is faster than the voltage drop rate of L3; when the resistance value of the variable resistor of the RRAM is higher than the resistance value of the reference resistor, the voltage drop rate of L3 is faster than the voltage drop rate of L4.
[0044] Furthermore, the lowest value of the high resistance of the variable resistor of the RRAM is set to R H , the maximum value of the low resistance of the variable resistor of the RRAM is set to R L , set the resistance of the reference resistor to R ref , the resistance of the reference resistor is calculated by the following formula:
[0045]
[0046] Further, the high resistance range of the variable resistor of the RRAM is 500KΩ to 2MΩ, and the low resistance range of the variable resistor of the RRAM is 10KΩ to 100KΩ.
[0047] Furthermore, the resistance of the reference resistor is 167KΩ.
[0048] Further, the specification of the twelfth transistor is the same as that of the first transistor,
[0049] The specification of the second transistor is the same as that of the third transistor,
[0050] The specification of the fourth transistor is the same as that of the fifth transistor,
[0051] The specification of the sixth transistor is the same as the specification of the seventh transistor.
[0052] Further, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are NMOS transistors, and the sixth transistor and the seventh transistor are PMOS transistors.
[0053] In the reading method of the RRAM reading circuit involved in the second aspect of the present invention, the RRAM reading circuit comprises:
[0054] Reference resistor;
[0055] A switch module, one side of which is connected to the reference resistor and the variable resistor of the RRAM, and is used to control the on-off between the reference resistor and the variable resistor of the RRAM and the self-bias module;
[0056] A self-bias module, one side of which is connected to the other side of the switch module, and is used to clamp the voltage of the node between the self-bias module and the switch module in the pre-charging step;
[0057] A cross-coupling module, one side of which is connected to the other side of the self-bias module, and is used to amplify the current difference formed in the pre-charging step through positive feedback to convert it into a comparison voltage;
[0058] a pre-charging module, the pre-charging module being connected to the other side of the cross-coupling module and being used for pre-charging the RRAM reading circuit; and
[0059] an output module, which is connected to the other side of the cross-coupling module and is used to compare the comparison voltage amplified by the cross-coupling module and output the comparison result,
[0060] The RRAM reading circuit performs the following steps when reading:
[0061] A discharge step, the discharge step being used to discharge the node between the output module and the cross-coupling module and the clamping node in the self-bias module;
[0062] a pre-charging step for charging a node between the output module and the cross-coupling module to a power supply voltage and charging the clamping node in the self-biasing module to a clamping voltage; and
[0063] A comparison step is used to amplify the current difference formed in the pre-charging step through positive feedback to convert it into a comparison voltage, compare the comparison voltage amplified by the cross-coupling module, and output a comparison result.
[0064] Effects of the Invention
[0065] According to the RRAM reading circuit of the present invention, the process of reading the RRAM resistance value is mainly divided into two stages: a pre-charging stage and an amplification and comparison stage. In the pre-charging stage, since only the parasitic capacitance of the MOS transistor exists, a stable I L1 ,I L2 , and except for the power consumption of the comparator, the structure of the RRAM reading circuit of the present invention will only produce lower power consumption in the pre-charging stage. In addition, in the amplification and comparison stage, the cross-coupled MOS transistor pair composed of the transistor M4 and the transistor M5 will convert the current signal into a voltage signal through positive feedback, which can increase the reading margin, and the positive feedback conversion of the current and voltage in the amplification and comparison stage accelerates the comparison process, thereby shortening the reading time and increasing the reliability of the RRAM reading data.
[0066] In addition, since the reference resistor R ref The present invention can also set the voltage of node L5 in the pre-charging stage by setting the size of transistors M1, M3, M5, and M7, and limit the voltage of nodes L1 and L2 in a self-biased clamping voltage manner, thereby preventing miswriting caused by excessive voltage applied to the RRAM. In addition, since the voltage of node L5 is discharged to 0V before the read enable voltage Vread is pulled up, there will be no miswriting problem caused by the clamping voltage being raised.
[0067] In addition, in the RRAM read circuit structure of the present invention, the transistors M8, M9, M10, and M11 only need to complete the switching function, so the minimum size area can be used, and since there is no operational transconductance amplifier, the RRAM read circuit structure of the present invention occupies a smaller area. BRIEF DESCRIPTION OF THE DRAWINGS
[0068] Figure 1 FIG. 4 is a circuit diagram showing the structure of a RRAM read circuit in the prior art.
[0069] Figure 2 Schematic diagram showing various modules of the RRAM reading circuit according to the embodiment of the present invention.
[0070] Figure 3 is a circuit diagram showing a specific structure of an RRAM reading circuit according to an embodiment of the present invention.
[0071] Figure 42 is a waveform diagram showing a generation process of a comparison voltage in an RRAM reading circuit according to an embodiment of the present invention.
[0072] Description of symbols
[0073] 101 Switch Module
[0074] 102 Self-bias module
[0075] 103 Cross-coupling modules
[0076] 104 Pre-charge module
[0077] 105 Output Module
[0078] M1 first transistor
[0079] M2 Second transistor
[0080] M3 The third transistor
[0081] M4 The fourth transistor
[0082] M5 Fifth transistor
[0083] M6 Sixth transistor
[0084] M7 Seventh transistor
[0085] M8 Eighth transistor
[0086] M9 Ninth transistor
[0087] M 10 The tenth transistor
[0088] M 11 Transistor 11
[0089] M0 12th transistor
[0090] CMP Comparator
[0091] V read Read Enable Voltage
[0092] V readn A voltage that is opposite to the read enable voltage
[0093] V sa_pre Pre-charge voltage
[0094] V sa_pren Voltage that is opposite to the pre-charge voltage
[0095] V core Supply voltage
[0096] R cell Variable resistance of RRAM
[0097] R ref Reference resistor Specific implementation manner
[0098] The present invention will be described in detail below with reference to the accompanying drawings and specific implementation manners. This implementation manner is carried out on the premise of the technical solution of the present invention, and detailed implementation manners and specific operation processes are given, but the protection scope of the present invention is not limited to the following implementation manners.
[0099] For convenience of description, spatial relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures. It should be understood that the spatial relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, an element described as "beneath" or "below" other elements or features will be oriented "above" the other elements or features.
[0100] Unless otherwise defined, the terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention pertains. The terms should be understood to have a meaning consistent with the context of the related art and should not be understood in an idealized or overly formal sense unless clearly so defined herein.
[0101] <Structure of the RRAM read circuit>
[0102] Figure 2 is a schematic diagram showing each module of the RRAM read circuit according to the embodiment of the present invention. Next, with reference to Figure 2 , each module of the RRAM read circuit according to the embodiment of the present invention will be described in detail.
[0103] As Figure 2 shown, the RRAM read circuit according to the embodiment of the present invention includes a reference resistor R ref , a switch module 101, a self - bias module 102, a cross - coupling module 103, a pre - charge module 104, and an output module 105.
[0104] Among them, one side of the switch module 101 is connected to the reference resistor R ref and the variable resistor R of the RRAM cell , and the switch module 101 is used to connect the reference resistor R ref and the variable resistor R of the RRAM cellThe on-off between the self-bias module 102 and the self-bias module 102 is controlled. One side of the self-bias module 102 is connected to the other side of the switch module 101, and the self-bias module 102 is used to clamp the voltage of the node between the self-bias module 102 and the switch module 101 in the pre-charging step. One side of the cross-coupling module 103 is connected to the other side of the self-bias module 102, and the cross-coupling module 103 is used to amplify the current with a smaller difference formed in the pre-charging step through positive feedback to convert it into a comparison voltage with a larger difference. The pre-charging module 104 is connected to the other side of the cross-coupling module 103, and the pre-charging module 104 is used to pre-charge the RRAM read circuit. The output module 105 is connected to the other side of the cross-coupling module 103, and the output module 105 is used to compare the comparison voltage amplified by the cross-coupling module 103 and output the comparison result.
[0105] The RRAM read circuit performs the following steps when reading. First, a discharge step is performed to discharge the node between the output module 105 and the cross-coupling module 103 and the clamp node in the self-bias module 102. Then, a pre-charge step is performed to charge the node between the output module 105 and the cross-coupling module 103 to the power supply voltage, and to charge the clamp node in the self-bias module 102 to the clamp voltage. Then, a comparison step is performed to amplify the current with a smaller difference formed in the pre-charge step through positive feedback to convert it into a comparison voltage with a larger difference, and compare the comparison voltage amplified by the cross-coupling module 103, and output the comparison result.
[0106] Specifically, in the RRAM read circuit according to the embodiment of the present invention, the switch module 101 includes a first transistor M1 and a twelfth transistor M0, and the self-bias module 102 includes a second transistor M2, a third transistor M3, a tenth transistor M 10 and an eleventh transistor M 11 The cross-coupling module 103 includes a fourth transistor M4, a fifth transistor M5, an eighth transistor M8 and a ninth transistor M9, the pre-charging module 104 includes a sixth transistor M6 and a seventh transistor M7, and the output module 105 includes a comparator CMP.
[0107] Figure 3 1 is a circuit diagram showing a specific structure of an RRAM reading circuit according to an embodiment of the present invention. Figure 3 , the specific structure of the RRAM reading circuit involved in the embodiment of the present invention is described in detail.
[0108] like Figure 3 As shown, the source of the twelfth transistor M0 is connected to the variable resistor R cellThe gate of the twelfth transistor M0 is connected to the gate of the first transistor M1, and the drain of the twelfth transistor M0 is connected to the source of the second transistor M2. The source of the first transistor M1 is connected to the reference resistor R ref The drain of the first transistor M1 is connected to the source of the third transistor M3.
[0109] The gate of the second transistor M2 is connected to the gate of the tenth transistor M 10 The drain of the eleventh transistor M 11 The source of the third transistor M3 is connected to the gate of the third transistor M3, and the drain of the second transistor M2 is connected to the source of the fourth transistor M4. 10 The drain of the eleventh transistor M 11 The source of the third transistor M3 is connected to the gate of the second transistor M2, and the drain of the third transistor M3 is connected to the eleventh transistor M 11 The drain of is connected to the source of the fifth transistor M5.
[0110] The gate of the fourth transistor M4 is connected to one input terminal (-) of the comparator CMP, the drain of the fifth transistor M5, the drain of the seventh transistor M7, and the drain of the ninth transistor M9. The drain of the fourth transistor M4 is connected to the drain of the eighth transistor M8, the drain of the sixth transistor M6, another input terminal (+) of the comparator CMP, and the gate of the fifth transistor M5. The gate of the fifth transistor M5 is connected to another input terminal (+) of the comparator CMP, the drain of the fourth transistor M4, the drain of the sixth transistor M6, and the drain of the eighth transistor M8. The drain of the fifth transistor M5 is connected to the drain of the ninth transistor M9, the drain of the seventh transistor M7, one input terminal (-) of the comparator CMP, and the gate of the fourth transistor M4. The source of the fifth transistor M5 is connected to the drain of the third transistor M3, the drain of the eleventh transistor M6, and the drain of the eleventh transistor M7. 11 Drain connection.
[0111] The drain of the sixth transistor M6 is connected to the drain of the eighth transistor M8, the drain of the fourth transistor M4, another input terminal (+) of the comparator CMP, and the gate of the fifth transistor M5. The gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7. The source of the sixth transistor M6 is applied with the power supply voltage V core The drain of the seventh transistor M7 is connected to the drain of the ninth transistor M9, the drain of the fifth transistor M5, an input terminal (-) of the comparator CMP, and the gate of the fourth transistor M4, and the source of the seventh transistor M7 is applied with the power supply voltage V core .
[0112] The source of the eighth transistor M8 is grounded, and the drain of the eighth transistor M8 is connected to the drain of the fourth transistor M4, the drain of the sixth transistor M6, the other input terminal (+) of the comparator CMP, and the gate of the fifth transistor M5. The source of the ninth transistor M9 is grounded, and the drain of the ninth transistor M9 is connected to the drain of the fifth transistor M5, the drain of the seventh transistor M7, one input terminal (-) of the comparator CMP, and the gate of the fourth transistor M4.
[0113] The tenth transistor M 10 The source of the tenth transistor M is grounded. 10 The drain of the second transistor M2, the gate of the third transistor M3 and the gate of the eleventh transistor M 11 The source of the eleventh transistor M 11 The drain of the eleventh transistor M is connected to the drain of the third transistor M3 and the source of the fifth transistor M5. 11 The source of the second transistor M2, the gate of the third transistor M3 and the gate of the tenth transistor M 11 Drain connection.
[0114] The gate of the twelfth transistor M0 and the gate of the first transistor M1 are applied with a read enable voltage V read , the gate of the eighth transistor M8, the gate of the ninth transistor M9 and the gate of the tenth transistor M 10 The gate is applied with a voltage V that is opposite to the read enable voltage. readn . The eleventh transistor M 11 The gate is pre-charged with a voltage V sa_pre , a voltage V inverse to the pre-charge voltage is applied to the gate of the sixth transistor M6 and the gate of the seventh transistor M7. sa_pren .
[0115] Among them, the read enable voltage V read , a voltage V that is opposite to the read enable voltage readn , pre-charge voltage V sa_pre , a voltage V that is opposite to the pre-charge voltage sa_pren is set so that it can be read by the RRAM reading circuit to change the variable resistance of the RRAM Rcell The resistance signal is converted into a readable signal.
[0116] In the present invention, preferably, the specification of the twelfth transistor M0 is the same as that of the first transistor M1, the specification of the second transistor M2 is the same as that of the third transistor M3, the specification of the fourth transistor M4 is the same as that of the fifth transistor M5, and the specification of the sixth transistor M6 is the same as that of the seventh transistor M7, but the present invention is not limited thereto. Furthermore, preferably, the first transistor M1, the second transistor M2, the third transistor M1, the fourth transistor M4, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, the tenth transistor M 10 , the eleventh transistor M 11 The twelfth transistor M0 is an NMOS transistor, the sixth transistor M6 and the seventh transistor M7 are PMOS transistors, but the present invention is not limited thereto.
[0117] Next, the reading operation of the RRAM reading circuit according to the embodiment of the present invention will be described in detail. Figure 4 1 is a waveform diagram showing a generation process of a comparison voltage in an RRAM reading circuit according to an embodiment of the present invention.
[0118] Here, the node between the drain of the twelfth transistor M0 and the source of the second transistor M2 is set to L1, the node between the drain of the first transistor M1 and the source of the third transistor M3 is set to L2, the node between the drain of the fourth transistor M4 and the drain of the sixth transistor M6 is set to L3, the node between the drain of the fifth transistor M5 and the drain of the seventh transistor M7 is set to L4, and the node between the gate of the second transistor M2 and the gate of the third transistor M3 is set to L5.
[0119] Specifically, in the present invention, the RRAM reading circuit performs the following steps when reading.
[0120] (1) First, the discharge step (corresponding to Figure 3 That is, the read enable voltage V read Set to low voltage, the voltage V readn Set to high voltage, the precharge voltage V sa_pre Set to low voltage, the voltage V sa_pren The eighth transistor M8, the ninth transistor M9, and the tenth transistor M 10 is turned on to discharge the nodes L3, L4 and L5.
[0121] (2) Then, a pre-charge step is performed (corresponding to Figure 3 That is, the read enable voltage V read Set to high voltage, the voltage V readnSet to low voltage, the precharge voltage V sa_pre Set to high voltage, the voltage V sa_pren is set to a low voltage, so that the twelfth transistor M0, the first transistor M1, the sixth transistor M6, the seventh transistor M7, the eleventh transistor M 11 It is turned on so that the nodes L3 and L4 are charged to the power supply voltage, and the node L5 is charged to the clamp voltage.
[0122] (3) Then, a comparison step is performed (corresponding to Figure 3 That is, the read enable voltage V read Keep it at a high voltage, so that the voltage V readn Keep it low voltage, the pre-charge voltage V sa_pre Set to low voltage, the voltage V sa_pren The voltage is set to a high voltage, so that the twelfth transistor M0 and the first transistor M1 remain turned on, and the sixth transistor M6, the seventh transistor M7, and the eleventh transistor M 11 The voltage difference formed between the node L3 and the node L4 is compared by the comparator CMP.
[0123] In addition, after the comparison step, the read enable voltage V read Set to low voltage, the voltage V readn Set to high voltage, so that the pre-charge voltage V sa_pre Keep it at a low voltage, so that the voltage V sa_pren The voltage is kept high to end the current reading operation and start the next reading operation.
[0124] In particular, when the variable resistance R cell The resistance value is greater than the reference resistor R ref The resistance value should be high (R cell >R ref ), since the current flowing through nodes L1 and L2 depends on R cell and R ref The resistance of I L1 L2 The stable current makes the voltage drop speed of node L4 faster than that of node L3, resulting in the conduction degree of transistor M5 being higher than that of transistor M4, which in turn causes the voltage drop speed of node L3 to slow down further. Finally, the voltage of node L4 drops to a level that is not enough to support the conduction of transistor M4, and the voltage of node L3 remains constant. Node L4 continues to discharge the remaining charge through transistor M5. As a result, a large voltage difference (L3>L4) is formed between node L3 and node L4 for comparison by comparator CMP, so that the output signal D of comparator CMP is out At high level.
[0125] When the variable resistance R cell The resistance value is greater than the reference resistor R ref The resistance value should be low (R cell <R ref ), since the current flowing through nodes L1 and L2 depends on R cell and R ref The resistance of I L1 >I L2 The stable current makes the voltage drop speed of node L3 faster than that of node L4, resulting in the conduction degree of transistor M4 being higher than that of transistor M5, which in turn causes the voltage drop speed of node L4 to slow down further. Finally, the voltage of node L3 drops to a level that is not enough to support the conduction of transistor M5, and the voltage of node L4 remains constant. Node L3 continues to discharge the remaining charge through transistor M4. As a result, a large voltage difference (L4>L3) is formed between node L4 and node L3 for comparison by comparator CMP, so that the output signal D of comparator CMP is out At low level.
[0126] Thus, the RRAM can be read by the RRAM reading circuit to change the variable resistance of the RRAM to Rcell The resistance signal is converted into a readable signal.
[0127] In addition, in the present invention, if the variable resistor R cell The minimum value of the high impedance is set to R H , the variable resistor R cell The maximum value of the low resistance is set to R L , set the reference resistor value to R ref , then the resistance of the reference resistor can be calculated by the following formula:
[0128]
[0129] In addition, as an example, the variable resistance R of RRAM cellThe high resistance range is 500KΩ to 2MΩ, and the variable resistance R of RRAM cell The low resistance range is 10KΩ to 100KΩ, but the present invention is not limited thereto. Also, preferably, the resistance of the reference resistor is 167KΩ, but the present invention is not limited thereto.
[0130] Therefore, according to the RRAM reading circuit of the present invention, the process of reading the RRAM resistance value is mainly divided into two stages: the pre-charging stage and the amplification and comparison stage. In the pre-charging stage, since only the parasitic capacitance of the MOS transistor exists, a stable I L1 ,I L2 , and except for the power consumption of the comparator CMP, the structure of the RRAM reading circuit of the present invention will only produce lower power consumption in the pre-charging stage. In addition, in the amplification and comparison stage, the cross-coupled MOS transistor pair composed of the transistor M4 and the transistor M5 will convert the current signal into a voltage signal through positive feedback, which can increase the reading margin, and the positive feedback conversion of the current and voltage in the amplification and comparison stage accelerates the comparison process, thereby shortening the reading time and increasing the reliability of the RRAM reading data.
[0131] In addition, since the reference resistor R ref The present invention can also set the voltage of node L5 in the pre-charge stage by setting the size of transistors M1, M3, M5, and M7, and limit the voltage of nodes L1 and L2 in a self-biased clamping voltage manner, thereby preventing miswriting caused by excessive voltage applied to the RRAM. In addition, since the voltage of node L5 is discharged to 0V before the read enable voltage Vread is pulled up, there will be no miswriting problem caused by the clamping voltage being raised. In addition, although node L5 is at V sa_pre When pulled low, it will become floating, and the floating point will be affected by the parasitic capacitance of the gate end, causing the voltage to drop. However, since nodes L3 and L4 are affected by positive feedback, the time used to form a sufficiently large voltage difference is very short, so the impact caused by the floating node L5 can be ignored.
[0132] In addition, in the RRAM read circuit structure of the present invention, the transistors M8, M9, M10, and M11 only need to complete the switching function, so the minimum size area can be used, and since there is no operational transconductance amplifier, the RRAM read circuit structure of the present invention occupies a smaller area.
[0133] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present invention, many modifications can be made to adapt specific conditions or materials to the teachings of the various embodiments of the present invention. Although the size and type of the material described herein are used to define the parameters of the various embodiments of the present invention, the various embodiments are not meant to be restrictive, but exemplary embodiments. In the case of reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of the various embodiments of the present invention should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.
[0134] Industrial Applicability
[0135] The RRAM reading circuit and the reading method thereof of the present invention can be applied to reading of RRAM memory, etc.
Claims
1. A RRAM reading circuit, characterized in that: include: Reference resistor; A switch module, one side of which is connected to the reference resistor and the variable resistor of the RRAM, and is used to control the on-off between the reference resistor and the variable resistor of the RRAM and the self-bias module; A self-bias module, one side of which is connected to the other side of the switch module, and is used to clamp the voltage of the node between the self-bias module and the switch module in the pre-charging step; A cross-coupling module, one side of which is connected to the other side of the self-bias module, and is used to amplify the current difference formed in the pre-charging step through positive feedback to convert it into a comparison voltage; a pre-charging module, the pre-charging module being connected to the other side of the cross-coupling module and being used for pre-charging the RRAM reading circuit; as well as an output module, the output module being connected to the other side of the cross-coupling module and being used for comparing the comparison voltage amplified by the cross-coupling module and outputting the comparison result, The switch module includes a first transistor and a twelfth transistor. The self-bias module includes a second transistor, a third transistor, a tenth transistor and an eleventh transistor, The source of the twelfth transistor is connected to the variable resistor of the RRAM, the gate of the twelfth transistor is connected to the gate of the first transistor, and the drain of the twelfth transistor is connected to the source of the second transistor. The source of the first transistor is connected to the reference resistor, the drain of the first transistor is connected to the source of the third transistor, The gate of the second transistor is connected to the drain of the tenth transistor, the source of the eleventh transistor, and the gate of the third transistor. The source of the tenth transistor is grounded, A drain of the eleventh transistor is connected to a drain of the third transistor.
2. The RRAM reading circuit according to claim 1, characterized in that: The RRAM reading circuit performs the following steps when reading: A discharge step, the discharge step being used to discharge the node between the output module and the cross-coupling module and the clamping node in the self-bias module; A pre-charging step, the pre-charging step being used to charge the node between the output module and the cross-coupling module to a power supply voltage, and to charge the clamping node in the self-biasing module to a clamping voltage; as well as A comparison step is used to amplify the current difference formed in the pre-charging step through positive feedback to convert it into a comparison voltage, compare the comparison voltage amplified by the cross-coupling module, and output a comparison result.
3. The RRAM reading circuit according to claim 1, characterized in that: The cross-coupling module includes a fourth transistor, a fifth transistor, an eighth transistor and a ninth transistor, The pre-charging module includes a sixth transistor and a seventh transistor, The output module includes a comparator, The drain of the second transistor is connected to the source of the fourth transistor, The drain of the third transistor is also connected to the source of the fifth transistor, The gate of the fourth transistor is connected to one input terminal of the comparator, the drain of the fifth transistor, the drain of the seventh transistor, and the drain of the ninth transistor. The drain of the fourth transistor is connected to the drain of the eighth transistor, the drain of the sixth transistor, the other input terminal of the comparator, and the gate of the fifth transistor. The gate of the fifth transistor is connected to the other input terminal of the comparator, the drain of the fourth transistor, the drain of the sixth transistor, and the drain of the eighth transistor. The drain of the fifth transistor is connected to the drain of the ninth transistor, the drain of the seventh transistor, one input terminal of the comparator, and the gate of the fourth transistor. The source of the fifth transistor is connected to the drain of the third transistor and the drain of the eleventh transistor. The drain of the sixth transistor is connected to the drain of the eighth transistor, the drain of the fourth transistor, the other input terminal of the comparator, and the gate of the fifth transistor, the gate of the sixth transistor is connected to the gate of the seventh transistor, and a power supply voltage is applied to the source of the sixth transistor. The drain of the seventh transistor is connected to the drain of the ninth transistor, the drain of the fifth transistor, one input terminal of the comparator, and the gate of the fourth transistor, and a power supply voltage is applied to the source of the seventh transistor. The source of the eighth transistor is grounded, and the drain of the eighth transistor is connected to the drain of the fourth transistor, the drain of the sixth transistor, the other input terminal of the comparator, and the gate of the fifth transistor. The source of the ninth transistor is grounded, and the drain of the ninth transistor is connected to the drain of the fifth transistor, the drain of the seventh transistor, one input terminal of the comparator, and the gate of the fourth transistor. The drain of the eleventh transistor is also connected to the source of the fifth transistor, A read enable voltage is applied to the gate of the twelfth transistor and the gate of the first transistor, and a voltage having an opposite phase to the read enable voltage is applied to the gates of the eighth transistor, the ninth transistor, and the tenth transistor, A precharge voltage is applied to the gate of the eleventh transistor, and a voltage having an opposite phase to the precharge voltage is applied to the gates of the sixth transistor and the seventh transistor. The read enable voltage, the voltage opposite to the read enable voltage, the precharge voltage, and the voltage opposite to the precharge voltage are set so as to enable reading by the RRAM read circuit to convert the resistance signal of the variable resistor of the RRAM into a signal that can be read.
4. The RRAM reading circuit according to claim 3, characterized in that: A node between the drain of the twelfth transistor and the source of the second transistor is set to L1, a node between the drain of the first transistor and the source of the third transistor is set to L2, a node between the drain of the fourth transistor and the drain of the sixth transistor is set to L3, a node between the drain of the fifth transistor and the drain of the seventh transistor is set to L4, and a node between the gate of the second transistor and the gate of the third transistor is set to L5, The RRAM reading circuit performs the following steps when reading: a discharging step, in which the read enable voltage is set to a low voltage, a voltage inverted with the read enable voltage is set to a high voltage, the precharge voltage is set to a low voltage, and a voltage inverted with the precharge voltage is set to a high voltage, so that the eighth transistor, the ninth transistor, and the tenth transistor are turned on, so that L3, L4, and L5 are discharged; a precharging step, in which the read enable voltage is set to a high voltage, a voltage inverted with the read enable voltage is set to a low voltage, the precharging voltage is set to a high voltage, and a voltage inverted with the precharging voltage is set to a low voltage, so that the twelfth transistor, the first transistor, the sixth transistor, the seventh transistor, and the eleventh transistor are turned on, so that L3 and L4 are charged to the power supply voltage, and L5 is charged to the clamping voltage; as well as A comparison step, in which the read enable voltage is maintained at a high voltage, the voltage opposite to the read enable voltage is maintained at a low voltage, the pre-charge voltage is set to a low voltage, and the voltage opposite to the pre-charge voltage is set to a high voltage, so that the twelfth transistor and the first transistor remain turned on, and the sixth transistor, the seventh transistor, and the eleventh transistor are turned off, so as to compare the voltage difference formed between L3 and L4 through the comparator.
5. The RRAM reading circuit according to claim 4, characterized in that: In the comparison step, when the resistance value of the variable resistor of the RRAM is lower than the resistance value of the reference resistor, the voltage drop speed of L4 is faster than the voltage drop speed of L3; when the resistance value of the variable resistor of the RRAM is higher than the resistance value of the reference resistor, the voltage drop speed of L3 is faster than the voltage drop speed of L4.
6. The RRAM reading circuit according to any one of claims 1 to 5, characterized in that: The lowest value of the high resistance of the variable resistor of the RRAM is set to R H , the maximum value of the low resistance of the variable resistor of the RRAM is set to R L , set the resistance of the reference resistor to R ref , The resistance of the reference resistor is calculated by the following formula:
7. The RRAM reading circuit according to claim 6, characterized in that: The high resistance range of the variable resistor of the RRAM is 500KΩ to 2MΩ, and the low resistance range of the variable resistor of the RRAM is 10KΩ to 100KΩ.
8. The RRAM reading circuit according to claim 7, characterized in that: The resistance of the reference resistor is 167KΩ.
9. The RRAM reading circuit according to any one of claims 3 to 5, characterized in that: The specification of the twelfth transistor is the same as that of the first transistor, The specification of the second transistor is the same as that of the third transistor, The specification of the fourth transistor is the same as that of the fifth transistor, The specification of the sixth transistor is the same as the specification of the seventh transistor.
10. The RRAM reading circuit according to any one of claims 3 to 5, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are NMOS transistors, and the sixth transistor and the seventh transistor are PMOS transistors.
11. A method for reading an RRAM reading circuit, the RRAM reading circuit comprising: Reference resistor; A switch module, one side of which is connected to the reference resistor and the variable resistor of the RRAM, and is used to control the on-off between the reference resistor and the variable resistor of the RRAM and the self-bias module; A self-bias module, one side of which is connected to the other side of the switch module, and is used to clamp the voltage of the node between the self-bias module and the switch module in the pre-charging step; A cross-coupling module, one side of which is connected to the other side of the self-bias module, and is used to amplify the current difference formed in the pre-charging step through positive feedback to convert it into a comparison voltage; a pre-charging module, the pre-charging module being connected to the other side of the cross-coupling module and being used for pre-charging the RRAM reading circuit; as well as an output module, which is connected to the other side of the cross-coupling module and is used to compare the comparison voltage amplified by the cross-coupling module and output the comparison result, The switch module includes a first transistor and a twelfth transistor. The self-bias module includes a second transistor, a third transistor, a tenth transistor and an eleventh transistor, The source of the twelfth transistor is connected to the variable resistor of the RRAM, the gate of the twelfth transistor is connected to the gate of the first transistor, and the drain of the twelfth transistor is connected to the source of the second transistor. The source of the first transistor is connected to the reference resistor, the drain of the first transistor is connected to the source of the third transistor, The gate of the second transistor is connected to the drain of the tenth transistor, the source of the eleventh transistor, and the gate of the third transistor. The source of the tenth transistor is grounded, The drain of the eleventh transistor is connected to the drain of the third transistor, The RRAM reading circuit performs the following steps when reading: A discharge step, the discharge step being used to discharge the node between the output module and the cross-coupling module and the clamping node in the self-bias module; A pre-charging step, the pre-charging step being used to charge the node between the output module and the cross-coupling module to a power supply voltage, and to charge the clamping node in the self-biasing module to a clamping voltage; as well as A comparison step is used to amplify the current difference formed in the pre-charging step through positive feedback to convert it into a comparison voltage, compare the comparison voltage amplified by the cross-coupling module, and output a comparison result.
Citation Information
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