Semiconductor device, method for manufacturing semiconductor device, and chip

Abstract

The application provides a semiconductor device, a manufacturing method of the semiconductor device and a chip, which comprises a substrate layer, a first field effect transistor, a separation layer and a second field effect transistor; the first field effect transistor comprises a first channel, the second field effect transistor comprises a second channel, the composition of the first channel is different from that of the second channel; the second field effect transistor, the separation layer and the first field effect transistor are sequentially stacked along the height direction of the substrate layer, and the first field effect transistor is stacked on the surface of the substrate layer; the composition content of the separation layer gradually changes along the direction perpendicular to the substrate layer, the composition of the separation layer is related to the composition of the first channel and the composition of the second channel, and the composition of the separation layer is a semiconductor material. Through the above device, the application can reduce the lattice mismatch degree between the N-type FET and the P-type FET.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a method for manufacturing a semiconductor device, and a chip. Background Technology

[0002] The device size of field-effect transistors (FETs) is approaching the limit set by Moore's Law. To further reduce the device size of FETs, new device structures are required.

[0003] To date, the device structure of FETs has evolved from fin field-effect transistors (Fin FETs) to gate-all-around field-effect transistors (GAAFETs), and then from GAAFETs to complementary field-effect transistors (CFETs).

[0004] Specifically, a CFET can be understood as a stack of N-type FETs and P-type FETs. The N-type FETs and P-type FETs are separated by a sacrificial layer. However, existing sacrificial layers tend to cause significant lattice mismatch problems between the N-type and P-type FETs. Summary of the Invention

[0005] This application provides a semiconductor device, a method for manufacturing the semiconductor device, and a chip that can reduce the degree of lattice mismatch between N-type FETs and P-type FETs.

[0006] In a first aspect, a semiconductor device is provided, comprising: a substrate layer, a first FET, a separator layer, and a second FET; the first FET includes a first channel, the second FET includes a second channel, and the composition of the first channel is different from that of the second channel; the second FET, the separator layer, and the first FET are stacked sequentially along the height direction of the substrate layer, and the first FET is stacked on the surface of the substrate layer; the composition content of the separator layer gradually changes along a direction perpendicular to the substrate layer, and the composition of the separator layer is related to the composition of the first channel and the composition of the second channel, and the composition of the separator layer is a semiconductor material.

[0007] Specifically, the second FET, the separator layer, and the first FET are stacked sequentially along the height direction of the substrate layer, which may include: the second FET being stacked on the surface of the separator layer, the separator layer being stacked on the surface of the first FET, and the first FET being stacked on the surface of the substrate layer.

[0008] By employing a gradual variation in composition within the separator layer of the CFET, this application can improve the interface flatness between N-type FETs and P-type FETs, thereby reducing the degree of lattice mismatch between N-type FETs and P-type FETs.

[0009] The first FET can be either an N-type FET or a P-type FET, and the second FET can also be either an N-type FET or a P-type FET, but of a different type than the first FET.

[0010] By reducing the degree of lattice mismatch between N-type FETs and P-type FETs, the number of dislocations at the interface between N-type FETs and P-type FETs can be reduced, thereby improving the interface flatness between N-type FETs and P-type FETs.

[0011] In conjunction with the first aspect, in certain implementations of the first aspect, the separator layer comprises silicon germanium; the first channel comprises at least one of the following: silicon, germanium, or silicon germanium; and the second channel comprises at least one of the following: silicon, germanium, or silicon germanium.

[0012] By employing a gradual change in composition in the separator layer of the CFET, this application can improve the interface flatness between N-type FET and P-type FET, and reduce the number of dislocations caused by silicon-germanium lattice mismatch.

[0013] Specifically, by using a method where the composition of the separator layer gradually changes along the height direction of the substrate layer, the material of the first channel can smoothly transition to the material of the second channel, resulting in better interface flatness between N-type FET and P-type FET, reducing the number of dislocations, and also reducing the degree of lattice mismatch between N-type FET and P-type FET.

[0014] In conjunction with the first aspect, in certain implementations of the first aspect, the separating layer includes a first layer and a second layer, the second layer being on top of the first layer, and the composition content of the separating layer gradually changing along the height direction of the substrate layer, including: the first channel being composed of silicon, the second channel being composed of silicon-germanium, and the germanium content of the second layer being greater than the germanium content of the first layer; or, the first channel being composed of silicon, the second channel being composed of germanium, and the germanium content of the second layer being greater than the germanium content of the first layer; or, the first channel being composed of silicon-germanium, the second channel being composed of silicon, and the germanium content of the second layer being less than the germanium content of the first layer; or, the first channel being composed of silicon-germanium, the second channel being composed of germanium, and the germanium content of the second layer being greater than the germanium content of the first layer; or, the first channel being composed of germanium, the second channel being composed of silicon-germanium, and the germanium content of the second layer being less than the germanium content of the first layer; or, the first channel being composed of germanium, the second channel being composed of silicon-germanium, and the germanium content of the second layer being less than the germanium content of the first layer.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the composition of the separator layer also includes doped materials.

[0016] By introducing doped materials that can improve the corrosion selectivity of the separator layer, the corrosion degree of some structures of the separator layer can be improved in subsequent manufacturing processes, avoiding problems such as over-corrosion or incomplete corrosion.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the doped material includes at least one of the following: phosphorus, arsenic, nitrogen, or antimony.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the semiconductor device further includes: a first gate for covering the first channel; and a second gate for covering the second channel.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the first channel includes a vertical structure and the second channel includes a horizontal structure.

[0020] Specifically, a vertical structure refers to a channel that is positioned along the height (vertical) direction of the substrate layer, while a horizontal structure refers to a channel that is positioned along the horizontal (planar) direction of the substrate layer.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the first channel is an N-type channel and the second channel is a P-type channel; or, the first channel is a P-type channel and the second channel is an N-type channel.

[0022] This allows two FETs with different channel structures to be stacked together, which can improve device integration.

[0023] In a second aspect, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate layer, the surface of which includes at least one first structure, the first structure including: a first unit for forming a first channel of a first FET, the first unit including a first channel material; a second unit for forming a second channel of a second FET, the second unit including a second channel material; a separator layer disposed between the first unit and the second unit, wherein the first channel material and the second channel material are different, the composition of the separator layer is related to the first channel material and the second channel material, the composition content of the separator layer gradually changes along a direction perpendicular to the substrate layer, and the composition of the separator layer is a semiconductor material; and etching at least one of the first channel material, the second channel material, and the separator layer in the first structure.

[0024] In conjunction with the second aspect, in some implementations of the second aspect, the separator layer comprises silicon germanium; the first channel material comprises at least one of the following: silicon, germanium, or silicon germanium; the second channel material comprises at least one of the following: silicon, germanium, or silicon germanium.

[0025] In conjunction with the second aspect, in some implementations of the second aspect, the separating layer includes a first layer and a second layer, with the second layer above the first layer. The composition content of the separating layer gradually changes along the height direction of the substrate layer, including: the first channel material includes silicon, the second channel material includes silicon-germanium, and the germanium content of the second layer is greater than the germanium content of the first layer; or, the composition of the first channel includes silicon, the composition of the second channel includes germanium, and the germanium content of the second layer is greater than the germanium content of the first layer; or, the first channel material includes silicon-germanium, the second channel material includes silicon, and the germanium content of the second layer is less than the germanium content of the first layer; or, the first channel material includes silicon-germanium, the second channel material includes germanium, and the germanium content of the second layer is greater than the germanium content of the first layer; or, the first channel material includes germanium, the second channel material includes silicon-germanium, and the germanium content of the second layer is less than the germanium content of the first layer; or, the first channel material includes germanium, the second channel material includes silicon-germanium, and the germanium content of the second layer is less than the germanium content of the first layer.

[0026] In conjunction with the second aspect, in some implementations of the second aspect, the composition of the separator layer includes doped materials.

[0027] In conjunction with the second aspect, in some implementations of the second aspect, the doping material includes at least one of the following: phosphorus, arsenic, nitrogen, or antimony.

[0028] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: forming a first gate around a first channel material for covering the first channel; and forming a second gate around a second channel material for covering the second channel.

[0029] In conjunction with the second aspect, in some implementations of the second aspect, the first channel includes a vertical structure and the second channel includes a horizontal structure.

[0030] In conjunction with the second aspect, in some implementations of the second aspect, the first channel is an N-type channel and the second channel is a P-type channel; or, the first channel is a P-type channel and the second channel is an N-type channel.

[0031] Thirdly, a chip is provided that includes the semiconductor device described in any one of the first aspects and any possible implementations of the first aspect. Attached Figure Description

[0032] Figure 1 This is a schematic diagram illustrating an application scenario of an embodiment of this application.

[0033] Figure 2 This is a schematic diagram of a CFET structure.

[0034] Figure 3 This is a schematic diagram of a CFET structure according to an embodiment of this application.

[0035] Figure 4 This is another schematic diagram of the CFET structure according to an embodiment of this application.

[0036] Figure 5 This is a schematic flowchart of a CFET manufacturing method according to an embodiment of this application.

[0037] Figure 6 This is another schematic flowchart of the manufacturing method of CFET according to an embodiment of this application. Detailed Implementation

[0038] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0039] FETs are one of the fundamental building blocks of computers, mobile phones, and all other modern electronic circuits. Due to their fast response and high accuracy, FETs can be used to implement a wide variety of digital and analog functions, such as amplification, switching, voltage regulation, signal modulation, and oscillators. The applications of FETs are very broad; for details, please refer to… Figure 1 .

[0040] Figure 1 This is a schematic diagram illustrating an application scenario of an embodiment of this application. For example... Figure 1As shown, FETs can be applied in fields such as integrated circuits, logic circuits, memories, and optical instruments. Integrated circuits can include very large-scale integrated (VLSI) circuits and super large-scale integrated (SLSI) circuits.

[0041] The device size of FETs is approaching the limit set by Moore's Law. To further shrink the device size, new device structures are needed. To date, FET device structures have evolved from FinFETs to GAAFETs, and then from GAAFETs to CFETs. A CFET can be understood as a stack of N-type and P-type FETs. The N-type and P-type FETs can be separated by a sacrificial layer; see [link to documentation] for details. Figure 2 .

[0042] Figure 2 This is a schematic diagram of a CFET structure. Specifically, Figure 2 (a) shows the overall structure of CFET#200. Figure 2 (b) shows the material composition of CFET#200.

[0043] exist Figure 2 In (a), CFET#200 includes a substrate (210), an N-type FET (220), a sacrificial layer (230), and a P-type FET (240). The N-type FET (220) is stacked on the upper surface of the substrate (210), the sacrificial layer (230) is stacked on the upper surface of the N-type FET (220), and the P-type FET (240) is stacked on the upper surface of the sacrificial layer (230). The sacrificial layer (230) is used to separate the N-type FET (220) and the P-type FET (240).

[0044] exist Figure 2 In (b), the substrate (210) is made of silicon, the N-type FET (220) is made of silicon (mainly referring to the channel material of the N-type FET (220) being silicon), the sacrificial layer (230) is made of silicon-germanium, and the P-type FET (240) is made of silicon-germanium (mainly referring to the channel material of the P-type FET (240) being silicon-germanium). Since the atomic radius of germanium is larger than that of silicon, a germanium-silicon lattice mismatch will occur at the interface between the N-type FET (220) and the sacrificial layer (230), which may easily lead to an uneven interface between the N-type FET (220) and the sacrificial layer (230) and between the P-type FET (240) and the sacrificial layer (230), potentially affecting the performance of CFET#200.

[0045] In view of the above-mentioned technical problems, this application provides a semiconductor device, a method for manufacturing a semiconductor device, and a chip, which can reduce the degree of lattice mismatch between N-type FETs and P-type FETs.

[0046] The semiconductor devices of embodiments of this application will be described below with reference to the accompanying drawings.

[0047] Figure 3 This is a schematic diagram of a CFET structure according to an embodiment of this application. It should be understood that... Figure 3 The CFET shown may include a partial structure, not all of the structures. For example... Figure 3 As shown, the CFET includes:

[0048] The substrate (310), the first FET (320), the separator (330) (which may be the aforementioned sacrificial layer), and the second FET (340).

[0049] Specifically, a first FET (320) is stacked on the surface of the substrate (310), a separator layer (330) is stacked on the surface of the first FET (320), and a second FET (340) is stacked on the surface of the separator layer (330). In other words, the first FET (320), the separator layer (330), and the second FET (340) are stacked sequentially along the height direction of the substrate (310). The composition of the separator layer (330) is not fixed but gradually varies along a direction perpendicular to the surface of the substrate (310), i.e., the composition of the separator layer (330) varies gradually along a direction perpendicular to the substrate (310) (i.e., it can vary along the height direction of the substrate (310)). The separator layer (330) is composed of semiconductor material.

[0050] The separator layer (330) may comprise multiple layers, with variations in the composition of each layer. For example, the first layer of the separator layer (330) comprises silicon and germanium, with a germanium content of 20% and a silicon content of 80%; the second layer of the separator layer (330) comprises silicon and germanium, with a germanium content of 40% and a silicon content of 60%. A comparison shows that the germanium content (40%) of the second layer of the separator layer (330) is greater than the germanium content (20%) of the first layer. The second layer is positioned above the first layer.

[0051] exist Figure 3 In the CFET shown, the first FET (320) includes a first channel (3201), and the second FET (340) includes a second channel (3401). The composition of the first channel (3201) is different from that of the second channel (3401), and the composition of the separator layer (330) is related to the composition of both the first channel (3201) and the second channel (3401).

[0052] In the embodiments of this application, semiconductor materials are a class of electronic materials that have semiconductor properties (conductivity between conductor and insulator, resistivity in the range of about 1 mΩ·cm to 1 GΩ·cm) and can be used to make semiconductor devices and integrated circuits.

[0053] One possible implementation is that the composition of the first channel (3201) includes at least one of the following: silicon, germanium, or silicon-germanium; the composition of the second channel (3401) includes at least one of the following: silicon, germanium, or silicon-germanium; and the composition of the separator layer (330) includes silicon-germanium.

[0054] For example, the first channel (3201) is composed of silicon, the second channel (3401) is composed of silicon and germanium, the separator layer (330) is composed of silicon and germanium, and the germanium content of the first layer is less than that of the second layer.

[0055] For example, the first channel (3201) is composed of silicon, the second channel (3401) is composed of germanium, the separator layer (330) is composed of silicon and germanium, and the germanium content of the first layer is less than that of the second layer.

[0056] For example, the first channel (3201) is composed of silicon and germanium, the second channel (3401) is composed of silicon, the separator layer (330) is composed of silicon and germanium, and the germanium content of the first layer is greater than that of the second layer.

[0057] For example, the first channel (3201) is composed of silicon and germanium, the second channel (3401) is composed of germanium, the separator layer (330) is composed of silicon and germanium, and the germanium content of the first layer is less than that of the second layer.

[0058] For example, the first channel (3201) is composed of germanium, the second channel (3401) is composed of silicon, the separator layer (330) is composed of silicon and germanium, and the germanium content of the first layer is greater than that of the second layer.

[0059] For example, the first channel (3201) is composed of germanium, the second channel (3401) is composed of silicon germanium, the separator layer (330) is composed of silicon germanium, and the germanium content of the first layer is greater than that of the second layer.

[0060] Alternatively, the above description of the change in germanium content also applies to the change in silicon content, and will not be repeated here.

[0061] The first FET (320) can be either an N-type FET or a P-type FET, and the second FET (340) can also be either an N-type FET or a P-type FET, but is of a different type than the first FET (320).

[0062] For ease of description, the following description will take the first channel (3201) as being composed of silicon, the second channel (3401) as being composed of silicon and germanium, and the separator layer as including five layers.

[0063] Figure 4 This is a schematic diagram of another CFET structure according to an embodiment of this application. Figure 4 As shown, the second channel (3401) is composed of silicon and germanium, with a germanium content of 70% and a silicon content of 30%. In existing CFETs #200, the separator layer (220) is composed of silicon and germanium with a fixed content (e.g., Si: 50%, Ge: 50%). However, this fixed content can easily lead to uneven interfaces between the N-type FET and the sacrificial layer, as well as between the P-type FET and the sacrificial layer, potentially affecting the performance of the CFET. To address the issue of interface flatness between the N-type FET and the P-type FET, this application employs a method where the content of the separator layer (330) gradually varies along the height direction of the substrate layer (310).

[0064] For example, the separator layer (330) includes a first layer (3301), a second layer (3302), a third layer (3303), a fourth layer (3304), and a fifth layer (3305). The second layer (3302) is stacked on the surface of the first layer (3301), the third layer (3303) is stacked on the surface of the second layer (3302), the fourth layer (3304) is stacked on the surface of the third layer (3303), the fifth layer (3305) is stacked on the surface of the fourth layer (3304), the first layer (3301) is stacked on the surface of the first channel (3201), and the second channel (3401) is stacked on the surface of the fifth layer (3305). In addition, the germanium content of the first layer (3301) is 5%, the germanium content of the second layer (3302) is 20%, the germanium content of the third layer (3303) is 35%, the germanium content of the fourth layer (3304) is 50%, and the germanium content of the fifth layer (3305) is 65%.

[0065] In this way, by gradually changing the composition of the separator layer (330) along the height direction of the substrate layer (310), the silicon (100%) of the first channel (3201) can smoothly transition to the silicon-germanium (Si:30%, Ge:70%) of the second channel (3401). This can result in better interface flatness between N-type FET and P-type FET, and can reduce the number of dislocations, thereby reducing the degree of lattice mismatch between N-type FET and P-type FET.

[0066] The above describes a regular gradient in the germanium content of each layer in the separator layer (330). However, the germanium content of each layer in the separator layer (330) can also be irregularly varied. For example, the germanium content of the first layer (3301) is 5%, the germanium content of the second layer (3302) is 20%, the germanium content of the third layer (3303) is 40%, the germanium content of the fourth layer (3304) is 45%, and the germanium content of the fifth layer (3305) is 69%, and so on.

[0067] Although the above description is based on the example that the first channel (3201) is composed of silicon and the second channel (3401) is composed of silicon and germanium, the above description is also applicable to scenarios where the first channel (3201) is composed of silicon and germanium and the second channel (3401) is composed of germanium, etc., which will not be repeated here.

[0068] In summary, the embodiments of this application do not limit the gradient method of the component content of the separator layer (330). It can be gradient, arithmetic sequence, or non-arithmetic sequence, as long as the component content of the separator layer (330) can be gradually changed along the height direction of the substrate layer (310).

[0069] By employing a gradual change in composition in the separator layer (320) of the CFET, this application can improve the interface flatness between the N-type FET and the P-type FET, and also reduce the number of dislocations caused by silicon-germanium lattice mismatch, thereby reducing the degree of lattice mismatch between the N-type FET and the P-type FET.

[0070] One possible implementation is that the separator layer (330) also includes doped materials. By introducing doped materials to improve the corrosion selectivity of the separator layer (330), the corrosion degree of certain structures of the separator layer can be improved during subsequent manufacturing processes, avoiding problems such as over-corrosion or incomplete corrosion.

[0071] Optionally, the doping material includes at least one of the following: phosphorus, arsenic, nitrogen, or antimony. Among them, phosphorus, arsenic, nitrogen, and antimony are all N-type doping materials, which can be used to better improve the corrosion selectivity of the separator layer (330).

[0072] One possible implementation method, Figure 4 The CFET shown may further include: a first gate (350) for covering a first channel (3201); and a second gate (360) for covering a second channel (3401).

[0073] Specifically, the first gate (350) is used to cover the first channel (3201). This coverage can be full coverage, i.e., covering the channel in the manner of the gate covering the channel in a GAAFET, or partial coverage, i.e., covering the channel in the manner of the gate covering the channel in a FinFET. Similarly, the second gate (360) is used to cover the second channel (3201), and this coverage can be full coverage, i.e., covering the channel in the manner of the gate covering the channel in a GAAFET, or partial coverage, i.e., covering the channel in the manner of the gate covering the channel in a FinFET.

[0074] In summary, the embodiments of this application are not limited. Figure 3 and Figure 4 The specific way the gate covers the channel in the CFET is shown.

[0075] One possible implementation is that the first channel (3201) includes a vertical structure and the second channel (3401) includes a horizontal structure.

[0076] Specifically, a vertical structure refers to a channel that is positioned along the height (vertical) direction toward the substrate (310), while a horizontal structure refers to a channel that is positioned along the horizontal (planar) direction of the substrate (310).

[0077] One possible implementation is that the first channel (3201) is an N-type channel and the second channel (3401) is a P-type channel; or, the first channel (3201) is a P-type channel and the second channel (3401) is an N-type channel. In this way, two FETs with different channel structures can be stacked one on top of the other, thereby improving the device integration density.

[0078] Optionally, both the first FET (320) and the second FET (340) are GAAFETs.

[0079] Although the exemplary embodiments of this application focus on silicon and silicon-germanium, this focus is for convenience and not for limitation. The technical solutions disclosed in the embodiments of this application can also be used with any epitaxial growth material or doped epitaxial growth material.

[0080] For example, the material may include: P- or B-doped silicon, doped silicon germanium, and any other doped or undoped epitaxially grown channel material, etc.

[0081] In the embodiments of this application, the first FET (320) may include a plurality of first channels (3201), and the second FET (340) may also include a plurality of second channels (3401). For ease of description, the embodiments of this application are described only as follows: the first FET (320) includes one first channel (3201) and the second FET (340) includes one second channel (3401), but the number of first channels (3201) in the first FET (320) and the number of second channels (3401) in the second FET (340) are not limited.

[0082] The manufacturing method of the semiconductor device according to the embodiments of this application will be described below with reference to the accompanying drawings.

[0083] Figure 5 This is a schematic flowchart of a CFET manufacturing method according to an embodiment of this application. It should be understood that... Figure 5 The flowchart shown may include a portion of the process flow, but not all of it. For example... Figure 5 As shown, the manufacturing method includes:

[0084] S510. A substrate layer (310) is provided. The surface of the substrate layer (310) includes at least one first structure. The first structure includes: a first unit for forming a first channel of a first FET (320), the first unit including a first channel material; a second unit for forming a second channel of a second FET (340), the second unit including a second channel material; and a separator layer (330) for being disposed between the first unit and the second unit. The first channel material and the second channel material are different. The composition of the separator layer (330) is related to the first channel material and the second channel material. The composition content of the separator layer (330) gradually changes along a direction perpendicular to the substrate layer (310). The composition of the separator layer (330) is a semiconductor material.

[0085] The above description is based on the example of a first channel (3201) of a first unit used to form a first FET (320) and a second channel (3401) of a second unit used to form a second FET (340), but the number of first channels and second channels is not limited.

[0086] The first channel material, the separator material (material used to form the separator layer), and the second channel material described above can be deposited on the surface of the substrate layer (310) by thin film deposition, and deposited sequentially along the height direction of the substrate layer (310). For example, the first channel material is first deposited on the surface of the substrate layer (310), then the material of multiple separator layers is deposited on the surface of the first channel material, and then the second channel material is deposited on the surface of the separator layer (330).

[0087] Optionally, a first sacrificial material may be deposited between the substrate (310) and the first channel material to separate the first channel material from the substrate (310). In subsequent manufacturing processes, the first sacrificial material may be etched away.

[0088] The aforementioned first channel material, separator layer material, and second channel material can be exposed, which facilitates subsequent etching processes.

[0089] For a description of the separator layer (330), please refer to the above description, and it will not be repeated here.

[0090] S520, at least one of the first channel material, the second channel material, and the separator layer in the first structure is etched.

[0091] Specifically, the initial volume of the second channel material can be selectively reduced by a predetermined amount relative to the initial volume of the first channel material using an etching process such as isotropic etching. This reduction can be achieved by etching a portion of the second channel material to "trim" it. The predetermined reduction in the volume of the second channel material creates the second channel. Alternatively, the initial volume of the first channel material can be selectively reduced by a predetermined amount relative to the initial volume of the second channel material using an etching process such as isotropic etching. This reduction can be achieved by etching a portion of the first channel material to "trim" it. In this case, the predetermined reduction in the volume of the first channel material creates the first channel.

[0092] It should be noted that the etching process for the first and second channel materials can be found in existing processes, and will not be elaborated here.

[0093] Alternatively, a portion of the material of the separator layer (330) between the first channel and the second channel can be etched away, thus freeing up the space between the first channel and the second channel.

[0094] It should be understood that this application supports retaining the two ends of the separator layer (330), so that the two ends of the separator layer (330) can support the first FET (320) and the second FET (340) that have been stacked together. For ease of description, the description of the separator layer (330) will be omitted in the following description, but this description does not mean that the structure of the separator layer (330) has disappeared.

[0095] Through the etching process described above, the embodiments of this application can realize the formation of the first channel of the first FET and the second channel of the second FET.

[0096] The following will combine Figure 6 The manufacturing method of the semiconductor device according to the embodiments of this application will be further described.

[0097] Figure 6 This is another schematic flowchart of the CFET manufacturing method according to an embodiment of this application. The embodiments of this application are described using silicon as the first channel material, silicon-germanium as the second channel material, and silicon-germanium as the separator material.

[0098] like Figure 6 As shown in (a), the material disposed between the first channel (320) and the substrate layer (310) can be regarded as a first sacrificial material, which is used to separate the first channel (320) and the substrate layer (310). Here, 320 can be used to represent the first channel material, 330 can be used to represent the separator layer material, and 340 can be used to represent the second channel material.

[0099] In one possible implementation, the first channel material 310, the second channel material 320, and the separator material 330 may have different etch resistances to a particular etchant.

[0100] like Figure 6 As shown in (a), the first structure prior to etching includes: a separator layer material 330, a first channel material 320, and a second channel material 340. The first channel material 320 is disposed above the second channel material 340, and the separator layer material 330 is used to separate the two channel materials.

[0101] like Figure 6 As shown in (b), a portion of the material in the separator layer 330 and the first sacrificial material can be etched using a first etching process. Specifically, the portion of material at both ends of the separator layer 330 used to support the first FET (320) and the second FET (340) can be preserved. Figure 6 (Not shown), only the central portion of the material in the separator layer 330 is etched.

[0102] Optionally, the first etching process may include isotropic etching, vapor phase etching, chemical oxide removal etching, atomic layer etching (ALE), or quasi-ALE etching, etc. Among them, isotropic etching can ensure uniform etching in any direction.

[0103] Figure 6 (b) shows an example after the first structure has been etched. The first sacrificial material is etched away. Optionally, the first channel material and the second channel material can also be etched. For the process of etching the first channel material and the second channel material, please refer to the existing process, which will not be described in detail here.

[0104] Alternatively, the separator layer material 330 can be etched away to expose the first channel (3201) and the second channel (3401).

[0105] Optionally, the material at both ends of the separator layer 330 can also be retained in the unexposed portion to enable it to support the stacked first FET (320) and second FET (340).

[0106] like Figure 6 As shown in (c), after etching the first structure, a high-k dielectric (62), a first-type channel work function metal (61), a second-type channel work function metal (63), and a gate fill metal (64) can be deposited on the etched first structure to form a first channel (3201) and a second channel (3201).

[0107] In this embodiment, the high-k dielectric (62) includes hafnium oxide and gate oxide, etc. The first type channel work function metal (61) includes titanium nitride, etc. The second type channel work function metal (63) includes titanium aluminum nitride and titanium aluminum carbide, etc. The gate fill metal (64) includes tungsten, cobalt, or ruthenium.

[0108] In this embodiment, a gate oxide may be deposited around the first channel (3201) and the second channel (3401). A high-k dielectric (62) may be deposited around the first channel (3201) and the second channel (3401). A first-type channel work function metal (61) may be deposited around the high-k dielectric (62). A first-type channel work function metal (61) may be deposited around the first channel (3201). A second-type channel work function metal (63) may be deposited around the second channel (3401). A first-type channel work function metal (61) may be deposited around the first channel (3201) and the second channel (3401). A gate fill metal (64) may be deposited.

[0109] When the composition of the separator layer (330) includes a doped material, embodiments of this application can form a doped separator layer (330) by incorporating a doped material into silicon and silicon-germanium epitaxial technology (or other technologies), with a doping concentration reaching 1e. 18 atom / cm 3 The above are all possible, and the doping concentration is controllable.

[0110] Alternatively, the above etching process may also include: wet etching (e.g., H3PO4, H2SO4+NH4OH), dry etching (e.g., Cl2+ plasma), etc.

[0111] It should be noted that the epitaxial growth equipment (or deposition equipment) involved in the embodiments of this application may include: chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), and metal-organic chemical vapor deposition (MOCVD), etc.

[0112] It should be noted that any processes not mentioned in the above description of the CFET manufacturing method can be found in existing process flows. This application does not limit the specific manufacturing processes of the first FET (320) and the second FET (340), but the separator layer (330) used to separate the first FET (320) and the second FET (340) can adopt a method of gradually changing the composition content to reduce the degree of lattice mismatch between the first FET (320) and the second FET (340).

[0113] Optionally, this application also provides a chip that may include the aforementioned components. Figure 3 Similar to the CFET shown in the figure.

[0114] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. Additionally, the character " / " generally indicates an "or" relationship between the preceding and following related objects, but it may also indicate an "and / or" relationship; please refer to the context for a more accurate understanding.

[0115] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0116] In the embodiments of this application, prefixes such as "first" and "second" are used only to distinguish different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. For example, if the described object is "FET", then the ordinal numbers preceding "first FET" and "second FET" do not restrict the position, order, or priority of "FET".

[0117] In the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0118] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0119] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0120] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0121] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0122] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0123] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate layer, a first field effect transistor, a separation layer and a second field effect transistor; the first field effect transistor comprises a first channel, and the second field effect transistor comprises a second channel, a composition of the first channel is different from a composition of the second channel; the second field effect transistor, the separation layer and the first field effect transistor are sequentially stacked along a height direction of the substrate layer, and the first field effect transistor is stacked on a surface of the substrate layer; a composition of the separation layer gradually changes along a direction perpendicular to the substrate layer, the composition of the separation layer is related to the composition of the first channel and the composition of the second channel, and the composition of the separation layer is a semiconductor material.

2. The semiconductor device according to claim 1, wherein The composition of the separation layer comprises silicon germanium. The composition of the first channel comprises at least one of: silicon, germanium, or silicon germanium; The composition of the second channel comprises at least one of: silicon, germanium, or silicon germanium.

3. The semiconductor device of claim 2, wherein, The separation layer comprises a first layer and a second layer, the second layer is above the first layer, and the composition of the separation layer gradually changes along the height direction, comprising: The composition of the first channel comprises silicon, the composition of the second channel comprises silicon germanium, and the germanium content of the second layer is greater than the germanium content of the first layer; or The composition of the first channel comprises silicon, the composition of the second channel comprises germanium, and the germanium content of the second layer is greater than the germanium content of the first layer; or The composition of the first channel comprises silicon germanium, the composition of the second channel comprises silicon, and the germanium content of the second layer is less than the germanium content of the first layer; or The composition of the first channel comprises silicon germanium, the composition of the second channel comprises germanium, and the germanium content of the second layer is greater than the germanium content of the first layer; or The composition of the first channel comprises germanium, the composition of the second channel comprises silicon, and the germanium content of the second layer is less than the germanium content of the first layer; or The composition of the first channel comprises germanium, the composition of the second channel comprises silicon germanium, and the germanium content of the second layer is less than the germanium content of the first layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein The composition of the separation layer further comprises a doping material.

5. The semiconductor device of claim 4, wherein, The doping material comprises at least one of: phosphorus, arsenic, nitrogen, or antimony.

6. The semiconductor device according to any one of claims 1 to 5, wherein The semiconductor device further comprises: a first gate electrode for covering the first channel; a second gate electrode for covering the second channel.

7. A method of manufacturing a semiconductor device, characterized by The semiconductor device comprises: providing a substrate layer, a surface of the substrate layer comprises at least one first structure, the first structure comprises: a first unit for forming a first channel of a first field effect transistor, the first unit comprises a first channel material, a second unit for forming a second channel of a second field effect transistor, the second unit comprises a second channel material, a separation layer for being arranged between the first unit and the second unit, the first channel material is different from the second channel material, a composition of the separation layer is related to the first channel material and the second channel material, a composition content of the separation layer gradually changes along a direction perpendicular to the substrate layer, and the composition of the separation layer is a semiconductor material; At least one of the first channel material, the second channel material, and the separator layer in the first structure is etched.

8. The method of claim 7, wherein, The separator layer is composed of silicon and germanium; The first channel material includes at least one of the following: Silicon, germanium, or silicon-germanium; The second channel material includes at least one of the following: Silicon, germanium, or silicon-germanium.

9. The method of claim 8, wherein, The separator layer includes a first layer and a second layer, with the second layer on top of the first layer. The composition content of the separator layer gradually changes along the height direction of the substrate layer, including: The first channel material comprises silicon, the second channel material comprises silicon-germanium, and the germanium content of the second layer is greater than the germanium content of the first layer; or, The first channel is composed of silicon, the second channel is composed of germanium, and the germanium content of the second layer is greater than the germanium content of the first layer; or, The first channel material comprises silicon-germanium, the second channel material comprises silicon, and the germanium content of the second layer is less than the germanium content of the first layer; or... The first channel material includes silicon-germanium, the second channel material includes germanium, and the germanium content of the second layer is greater than the germanium content of the first layer; or... The first channel material includes germanium, the second channel material includes silicon, and the germanium content of the second layer is less than the germanium content of the first layer; or... The first channel material includes germanium, the second channel material includes silicon germanium, and the germanium content of the second layer is less than that of the first layer.

10. The method according to any one of claims 7 to 9, characterized in that, The separator layer also includes doped materials.

11. The method of claim 10, wherein, The doped material includes at least one of the following: Phosphorus, arsenic, nitrogen, or antimony.

12. The method according to any one of claims 7 to 11, characterized in that, The method further includes: A first gate is formed around the first channel material, the first gate being used to cover the first channel; A second gate is formed around the second channel material, the second gate being used to cover the second channel.

13. A chip, characterized by The chip comprises the semiconductor device according to any one of claims 1 to 6.

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