Method for manufacturing self-aligned quadruple patterned semiconductor device and semiconductor device

Abstract

The present application discloses a method for manufacturing a self-aligned quadruple-patterned semiconductor device and a semiconductor device. The method for manufacturing a self-aligned quadruple-patterned semiconductor device includes: sequentially forming a first anti-reflective layer, a first sacrificial layer, a second anti-reflective layer, and a first patterned hard mask layer on the surface of a layer to be etched; performing photolithography on the first patterned hard mask layer to form a second patterned hard mask layer; etching the second anti-reflective layer and the first sacrificial layer using the second patterned hard mask layer as a mask to form a second patterned sacrificial layer; removing the second patterned hard mask layer and the second anti-reflective layer, and forming a third patterned hard mask layer based on the second patterned sacrificial layer; performing photolithography on the third patterned hard mask layer to form a fourth patterned hard mask layer; etching the first anti-reflective layer and the layer to be etched based on the fourth patterned hard mask layer to form a patterned layer to be etched. Implementing the present application embodiment can increase the degree of freedom in circuit pattern design.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a method for fabricating a self-aligned quadruple patterned semiconductor device and the semiconductor device thereof. Background Technology

[0002] Multiple patterning is a technique currently used in photolithography to reduce the feature size of circuit patterns (such as line width and spacing) and increase the density of circuit patterns. A common self-aligned patterning technique in multiple patterning includes Self-Aligned Quadruple Patterning (SAQP). This technique involves transferring the circuit pattern of the printed mandrel onto a hard mask in a single exposure, then depositing two spacer sidewalls on the hard mask using atomic layer deposition (ALD), and finally etching the spacers from top to bottom to open the printed mandrel and the underlying layer. The spacing between the second spacer sidewalls is the spacing of the metal lines in the final circuit pattern.

[0003] However, the circuit patterns generated by the self-aligned quadruple patterning technique are defined by two spacer depositions. In existing technologies, the dimensions of the spacers formed during the fabrication process are relatively fixed and cannot be further reduced. This limits the characteristic dimensions of the circuit pattern (such as line width and spacing) to a certain range, and the density of the circuit pattern cannot be further increased. Furthermore, if circuit patterns are created using direct multiple exposures, the accuracy requirements for the overlay error of the circuit pattern during each exposure are extremely high. The design also requires careful consideration of pattern splitting, increasing the difficulty of circuit design and significantly restricting the design freedom of the circuit pattern.

[0004] Therefore, how to improve the density and freedom of circuit pattern design in self-aligned quadruple patterning technology is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a method for fabricating a self-aligned quadruple patterning semiconductor device and a semiconductor device, thereby improving the density and freedom of circuit pattern design.

[0006] In a first aspect, embodiments of this application provide a method for fabricating a self-aligned quadruple patterned semiconductor device, comprising:

[0007] Step 1: Sequentially form a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer, and a first patterned hard mask layer on the surface of the layer to be etched. The first patterned hard mask layer includes a first patterned sacrificial layer and a first sidewall layer covering all the sidewalls of the first patterned sacrificial layer.

[0008] Step 2: Photolithography is performed on the first patterned hard mask layer to form a second patterned hard mask layer;

[0009] Step 3: Based on the second patterned hard mask layer as a mask, the second anti-reflection layer and the first sacrificial layer are etched to form the second patterned sacrificial layer;

[0010] Step 4: Remove the second patterned hard mask layer and the second anti-reflection layer, and form a third patterned hard mask layer based on the second patterned sacrificial layer. The third patterned hard mask layer includes the second patterned sacrificial layer and a second sidewall layer covering all sidewalls of the second patterned sacrificial layer.

[0011] Step 5: Perform photolithography on the third patterned hard mask layer to form the fourth patterned hard mask layer;

[0012] Step 6: Using the fourth patterned hard mask layer as a mask, etch the first anti-reflection layer and the layer to be etched to form a patterned layer to be etched;

[0013] Step 7: Remove the fourth patterned hard mask layer and the first anti-reflection layer.

[0014] The method provided in the first aspect differs from the prior art in forming a patterned hard mask through two depositions of spacers. This application adds a pattern photolithography step between the sidewalls of the two spacer depositions. Specifically, circuit patterns are prepared through alternating photolithography and two spacer depositions, and finally, photolithography is used to define the pattern to be opened to form a patterned hard mask. Firstly, since adjacent metal lines cannot be placed very close together if they are fabricated on the same photomask layer, but can be placed very close together if they are fabricated on two different photomasks, this allows for multiple photolithography steps in the self-aligned quadruple patterning technique, distributing close metal lines on different photomasks, achieving the desired effect and increasing the density of the circuit pattern design. Secondly, since a sidewall layer is often deposited within the patterned hard mask layer after a single photolithography step, based on the pattern formed during photolithography, using spacers, the etching rate differs between the hard mask layer and the sidewall layer materials during subsequent photolithography. This significantly reduces the precision requirements for overlay error in the circuit pattern during the second photolithography step, thus lowering the difficulty of circuit design. Furthermore, the final circuit pattern is formed by defining multiple photolithography patterns, and its length, width, and spacing can be freely adjusted compared to the pattern defined by the spacers.

[0015] In one possible implementation, the step of sequentially forming a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer, and a first patterned hard mask layer on the surface of the layer to be etched includes: sequentially depositing and forming the first anti-reflection layer, the first sacrificial layer, the second anti-reflection layer, the second sacrificial layer, and a first patterned photolithography layer on the surface of the layer to be etched; etching the second sacrificial layer based on the first patterned photolithography layer as a mask to form the first patterned sacrificial layer on the second sacrificial layer; removing the first patterned photolithography layer; and depositing and etching a first sidewall layer covering all sidewalls of the first patterned sacrificial layer on the first patterned sacrificial layer. Implementing the embodiments of this application, the second sacrificial layer is opened by photolithography and spacer deposition to form the first patterned hard mask layer, thus creating the pattern corresponding to the first patterned photolithography layer.

[0016] In one possible implementation, the first patterned photolithography layer comprises: a spin-coated carbon layer, a spin-coated glass layer, and a patterned photoresist layer stacked sequentially, wherein the spin-coated carbon layer is stacked on the side of the second sacrificial layer away from the second anti-reflective layer, and the spin-coated glass layer is located between the spin-coated carbon layer and the patterned photoresist layer. In this embodiment, the three-layer structure of the photoresist allows for stable and precise transfer of the pattern formed by the photoresist to the second sacrificial layer through a photolithography process.

[0017] In one possible implementation, the step of photolithographically forming a second patterned hard mask layer from the first patterned hard mask layer includes: depositing a second patterned photolithographic layer covering the first patterned hard mask layer; etching the first patterned hard mask layer using the second patterned photolithographic layer as a mask to form the second patterned hard mask layer; and removing the second patterned photolithographic layer. In embodiments of this application, the photolithography process may first form a patterned photolithographic layer covering the patterned hard mask layer, then further open a sacrificial layer using the patterned photolithographic layer as a mask, and finally remove the patterned photolithographic layer.

[0018] In one possible implementation, the step of photolithographically forming the fourth patterned hard mask layer from the third patterned hard mask layer includes: photolithographically forming the fourth patterned hard mask layer from the third patterned photolithography layer. In embodiments of this application, the photolithography process may first form a patterned photolithography layer covering the patterned hard mask layer, then further open a sacrificial layer using the patterned photolithography layer as a mask, and finally remove the patterned photolithography layer.

[0019] In one possible implementation, the step of photolithographically forming the fourth patterned hard mask layer from the third patterned hard mask layer includes: photolithographically forming the fifth patterned hard mask layer from the third patterned hard mask layer according to the third patterned photolithography layer; and photolithographically forming the fourth patterned hard mask layer from the fifth patterned hard mask layer according to the fourth patterned photolithography layer. In embodiments of this application, if the case is complex, multiple photolithography steps can be chosen to form the fourth patterned hard mask layer. Multiple photolithography steps can ensure the freedom of circuit pattern design.

[0020] In one possible implementation, in the horizontal direction, the linewidths of the patterns in the third and fourth patterned photolithography layers are equal to or greater than twice the width of the second sidewall layer. Unlike the prior art where the linewidth of the pattern must be equal to the width of the second sidewall layer, in this embodiment, the linewidth of the pattern can also be greater than twice the width of the second sidewall layer.

[0021] In one possible implementation, the linewidths of the patterns of the second, third, and fourth patterned photolithographic layers are less than or equal to the spacing between adjacent first sidewall layers or adjacent second sidewall layers in the horizontal direction. In embodiments of this application, the linewidth of the circuit pattern fabricated after the first sidewall layer cannot exceed the spacing between the first sidewall layer and the adjacent second sidewall layer.

[0022] In one possible implementation, the second patterned photolithography layer includes one or more first trenches; prior to the step of depositing and etching the first patterned sacrificial layer to form a first sidewall layer covering all sidewalls of the first patterned sacrificial layer, the method further includes: forming a fifth patterned photolithography layer on the surface of the first patterned sacrificial layer, the fifth patterned photolithography layer including one or more second trenches, the position of each second trench being the same as the position of each first trench; based on the fifth patterned photolithography layer as a mask, etching the first patterned sacrificial layer according to the second trenches to form an etched first patterned sacrificial layer; and removing the fifth patterned photolithography layer. Implementing the embodiments of this application, since the positions of the first trenches and the second trenches are different, and after the step of removing the first patterned photolithography layer, when preparing the first sidewall layer, the insulating material of the sidewall layer will cover the etched first patterned sacrificial layer, thereby also covering the second trenches. Consequently, when subsequently preparing the pattern formed by the first trenches, the insulating material at the second trench will block the pattern lines formed by the first trenches, resulting in one or more discontinuous trenches of varying lengths, and thus obtaining circuit pattern lines of different lengths.

[0023] In one possible implementation, the first patterned photolithography layer includes one or more third trenches; after the step of depositing and etching the first sidewall layer covering all sidewalls of the first patterned sacrificial layer, the method further includes: depositing a sixth patterned photolithography layer covering the first patterned hard mask layer, the sixth patterned photolithography layer including one or more fourth trenches, each fourth trench being located at the same position as each third trench; etching the first patterned hard mask layer based on the sixth patterned photolithography layer as a mask to form an etched first patterned hard mask layer; depositing an oxide layer covering the sixth patterned photolithography layer and the etched first patterned hard mask layer; removing the sixth patterned photolithography layer and the oxide layer covering the sixth patterned photolithography layer; the step of photolithography to form a second patterned hard mask layer on the first patterned hard mask layer includes: photolithography to form the second patterned hard mask layer on the etched first patterned hard mask layer and the remaining oxide layer. By implementing the embodiments of this application, since the position of the third trench is the same as that of the fourth trench, the oxide deposited at the position of the fourth trench can block the third trench, thereby forming multiple trenches of different lengths, and thus obtaining circuit pattern lines of different lengths.

[0024] In a second aspect, embodiments of this application provide a self-aligned quadruple patterned semiconductor device, including a substrate and a semiconductor device fabricated by the method described in the first aspect and in combination with any implementation of the first aspect, stacked on the substrate.

[0025] Thirdly, embodiments of this application provide an electronic device that includes the semiconductor device and circuit board provided in accordance with the first aspect and any implementation thereof. The semiconductor device is electrically connected to the circuit board, and the electronic device is used to implement the functions of the semiconductor device involved in the first aspect. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0027] Figure 1 A flowchart illustrating the steps of a method for fabricating a self-aligned quadruple patterned semiconductor device provided in an embodiment of this application.

[0028] Figure 2 This is a set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in the embodiments of this application.

[0029] Figure 3 and Figure 4This is another set of cross-sectional views of a device for fabricating a semiconductor device using self-aligned quadruple patterning, provided in the embodiments of this application.

[0030] Figure 5 This is a cross-sectional view of a set of patterned photolithography layers provided in the embodiments of this application.

[0031] Figure 6 This is a set of cross-sectional views of a semiconductor device for fabricating a first sidewall layer provided in the embodiments of this application.

[0032] Figures 7-10 This is a set of cross-sectional views of a semiconductor device for fabricating Cut line A, provided in an embodiment of this application.

[0033] Figure 11 This is another set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in the embodiments of this application.

[0034] Figure 12 This is another set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in the embodiments of this application.

[0035] Figures 13-15 This is a set of cross-sectional views of a semiconductor device for fabricating Cut line B, provided in an embodiment of this application.

[0036] Figure 16 This is a cross-sectional view of a device for fabricating a semiconductor device using a set of self-aligned quadruple patterning, as provided in an embodiment of this application.

[0037] Figure 17 This is another set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in the embodiments of this application.

[0038] Figure 18 This is another set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in the embodiments of this application.

[0039] Figure 19 This is a cross-sectional view of a device for fabricating a semiconductor device using a set of self-aligned quadruple patterning, as provided in an embodiment of this application.

[0040] Figure 20 This is a cross-sectional view of a device for fabricating a semiconductor device using a set of self-aligned quadruple patterning, as provided in an embodiment of this application.

[0041] Figure 21 This is another set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in the embodiments of this application.

[0042] Figures 22-24 This is a set of cross-sectional views of a semiconductor device for fabricating Cut line C, provided in the embodiments of this application.

[0043] Figure 25 This is a cross-sectional view of a device for fabricating a semiconductor device using a set of self-aligned quadruple patterning, as provided in an embodiment of this application.

[0044] Figures 26-30 This application provides a set of cross-sectional views of a semiconductor device for fabricating line D and cut line D.

[0045] Explanation of reference numerals in the attached figures:

[0046] 10. Semiconductor devices;

[0047] 101 Layer to be etched; 102 First anti-reflection layer; 103 First sacrificial layer; 104 Second anti-reflection layer; 105 First patterned hard mask layer; 106 Second sacrificial layer; 107 First patterned photolithography layer;

[0048] First sidewall layer 1052; First patterned sacrificial layer 1051;

[0049] 1071 Spin-coated carbon layer; 1072 Spin-coated glass layer; 1073 Patterned photoresist layer;

[0050] 108 Sixth patterned photolithography layer; 109 Oxide layer;

[0051] 115 Second patterned hard mask layer; 1031 Second patterned sacrificial layer; 1032 Third patterned hard mask layer; 1033 Second sidewall layer; 1132 Fourth patterned hard mask layer;

[0052] 201 Second patterned photolithography layer; 202 Fifth patterned photolithography layer;

[0053] 203 Third patterned photolithography layer; 204 Seventh patterned photolithography layer;

[0054] 205 Fourth patterned photolithography layer;

[0055] 111 Patterned layers to be etched;

[0056] LA third trench; CA fourth trench;

[0057] LB first groove; CB second groove;

[0058] LC fifth trench; CC sixth trench;

[0059] LD seventh groove; CD eighth groove. Detailed Implementation

[0060] The embodiments of this application will now be described with reference to the accompanying drawings.

[0061] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0062] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0063] For ease of description, embodiments of this application may use spatial relation terms such as "below," "below," "lower than," "below," "above," "upper," etc., to describe the relationship between an element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings. For example, if the device in the drawings is flipped, the orientation of an element described as "below," "below," or "below" other elements or features will change to "above" said other elements or features. Thus, the exemplary terms "below" and "below" can encompass both up and down directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0064] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0065] First, to facilitate understanding of the embodiments of this application, the following detailed analysis of the technical problems to be solved and the application scenarios of the embodiments of this application.

[0066] Multiple patterning is a technique currently used in photolithography to reduce the feature size of circuit patterns (such as line width and spacing) and increase the density of circuit patterns. A common self-aligned patterning technique in multiple patterning includes Self-Aligned Quadruple Patterning (SAQP). This technique uses a single exposure to transfer the circuit pattern of the printed mandrel onto a hard mask, then uses atomic layer deposition to deposit two spacer sidewalls, and finally etches the spacers from top to bottom to open the printed mandrel and the underlying layer. The spacing between the second spacer sidewalls is the linewidth of the final circuit pattern's metal lines.

[0067] For example: Please refer to steps one through eight, which are the process flow steps of the self-aligned quadruple patterning technology in the prior art. Among them:

[0068] Step 1: Sequentially deposit the first anti-reflection layer, the first sacrificial layer, the second anti-reflection layer, and the second sacrificial layer on the surface of the layer to be etched;

[0069] Step 2: Perform photolithography on the second sacrificial layer to form a patterned second sacrificial layer;

[0070] Step 3: Remove the patterned photolithography layer; deposit and etch the patterned second sacrificial layer to form the first sidewall layer;

[0071] Step 4: Remove the patterned second sacrificial layer;

[0072] Step 5: Using the first sidewall layer as a mask, etch the second antireflection layer and the first sacrificial layer to form a patterned first sacrificial layer;

[0073] Step 6: Remove the second anti-reflective layer; deposit and etch the patterned second sacrificial layer to form the second sidewall layer;

[0074] Step 7: Remove the patterned first sacrifice layer;

[0075] Step 8: Using the second sidewall layer as a mask, etch the first anti-reflection layer and the layer to be etched to form a patterned layer to be etched.

[0076] As can be seen from the above steps, the circuit pattern generated by the self-aligned quadruple patterning technique is ultimately defined by the spacer deposited in the second deposition (i.e., the second sidewall layer). However, the size of the spacers formed in the existing spacer fabrication process is relatively fixed and cannot be further reduced. This results in the feature dimensions (such as line width and spacing) of the final circuit pattern being fixed. Therefore, the line width of the circuit pattern needs to be determined from the initial design stage by considering the size of the spacer that can be deposited. Moreover, if the circuit pattern is fabricated by direct multiple exposures, the accuracy requirements for the overlay error of the circuit pattern during each exposure are particularly high. The pattern splitting problem also needs to be carefully considered in the design, increasing the difficulty of circuit design and significantly limiting the design freedom of the circuit pattern.

[0077] Therefore, in order to improve the density and freedom of circuit pattern design in self-aligned quadruple patterning technology and avoid being limited by the fabrication process of spacers, this application embodiment adds a pattern photolithography step between the sidewalls of the two spacer depositions. That is, the circuit pattern is prepared by alternating between multiple photolithography steps and two spacer depositions, and finally, photolithography is used to define the pattern to be opened to form a patterned hard mask. First, since adjacent metal lines cannot be made very close together if they are fabricated on the same photomask layer, but can be made very close together if they are fabricated on two different photomasks, the desired effect can be achieved by performing multiple photolithography steps in self-aligned quadruple patterning technology and distributing close metal lines on different photomasks, thus improving the density of circuit pattern design. Secondly, since a sidewall layer is often deposited within the patterned hard mask layer after a single photolithography step, based on the pattern formed during photolithography, using spacers, the etching rate differs between the hard mask layer and the sidewall layer materials during subsequent photolithography. This significantly reduces the precision requirements for overlay error in the circuit pattern during the second photolithography step, thus lowering the difficulty of circuit design. Furthermore, the final circuit pattern is formed by defining multiple photolithography patterns, and its length, width, and spacing can be freely adjusted compared to the pattern defined by the spacers.

[0078] Furthermore, the self-aligned quadruple patterning technology and the semiconductor device using this technology, implemented in the embodiments of this application, can be applied to semiconductor devices that fabricate various circuit patterns using this technology. By adding photolithography to define the pattern to be opened between and after the two spacer deposition and etching processes in the self-aligned quadruple patterning technology flow, the final circuit pattern is formed, improving the density and freedom of circuit design and greatly reducing the difficulty of circuit design. Specific implementation methods can be referred to in the following embodiments, which will not be elaborated upon here.

[0079] Secondly, the semiconductor device fabrication method provided in this application can increase the density and freedom of circuit design, and reduce the difficulty of circuit design. Since adjacent metal lines in a circuit pattern cannot be made very close together if they are fabricated on the same photomask layer, but can be very close if they are fabricated on two different photomasks, this allows for multiple photolithography steps in the self-aligned quadruple patterning technique, distributing close metal lines on different photomasks, achieving the desired effect and increasing the density of the circuit pattern design. Next, taking the process of dividing the lines in a circuit pattern formed by three photolithography steps into three pattern lines—line A, line B, and line C—as an example, the method for fabricating a self-aligned quadruple patterned semiconductor device provided in this application is illustrated. Here, line A, line B, and line C are pattern lines fabricated at different photolithography stages.

[0080] Please see Figure 1 , Figure 1 A flowchart illustrating the steps of a method for fabricating a self-aligned quadruple patterned semiconductor device provided in this application embodiment, the method comprising:

[0081] Step S1: A first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer, and a first patterned hard mask layer are sequentially formed on the surface of the layer to be etched.

[0082] Specifically, a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer, and a first patterned hard mask layer are sequentially formed on the surface of the layer to be etched. The first patterned hard mask layer includes a first patterned sacrificial layer and a first sidewall layer covering all sidewalls of the first patterned sacrificial layer. The process used can be a selective deposition process, such as electroless plating; or it can be a physical vapor deposition, chemical vapor deposition, or atomic layer deposition method. It should be noted that step S1 is for the fabrication of the first sidewall layer and line A in the circuit pattern.

[0083] Please refer to the attached document. Figure 2 , Figure 2 This application provides a set of cross-sectional views of a self-aligned quadruple patterning semiconductor device, including a top view and a side view. It should be noted that, as... Figure 2 The schematic diagram of the semiconductor device 10 shown illustrates that, in the semiconductor device 10, a first anti-reflection layer 102, a first sacrificial layer 103, a second anti-reflection layer 104, and a first patterned hard mask layer 105 are stacked on the surface of the layer 101 to be etched. The first patterned hard mask layer 105 includes a first patterned sacrificial layer 1051 and a first sidewall layer 1052 covering all sidewalls of the first patterned sacrificial layer. Optionally, the layer 101 to be etched is stacked on a substrate 100. The first patterned hard mask layer 105 includes one or more trenches LA (corresponding to line A), which can be used to create patterned lines corresponding to line A. The first patterned hard mask layer 105 includes a first patterned sacrificial layer 1051 and a first sidewall layer 1052 covering all sidewalls of the first patterned sacrificial layer.

[0084] Additionally, it should be noted that in the semiconductor device 10, the horizontal direction (i.e., the left-right direction) is the X-axis, the direction perpendicular to the thickness of the layer to be etched 101 is the Y-axis (i.e., the vertical direction), and the front-back direction perpendicular to both the X-axis and Y-axis is the Z-axis. Along the X-axis is the width direction of the layer to be etched 101, the first anti-reflective layer 102, the first sacrificial layer 103, the second anti-reflective layer 104, and the first patterned hard mask layer 105; along the Y-axis is the thickness direction of the layer to be etched 101, the first anti-reflective layer 102, the first sacrificial layer 103, the second anti-reflective layer 104, and the first patterned hard mask layer 105; and along the Z-axis is the length direction of the layer to be etched 101, the first anti-reflective layer 102, the first sacrificial layer 103, the second anti-reflective layer 104, and the first patterned hard mask layer 105. Furthermore, the cross-sectional views, process flow diagrams, etc. of the semiconductor devices and other related devices in this application and the following related embodiments are also applicable to... Figure 2 The coordinate system shown (X-axis, X-axis, and Z-axis).

[0085] Optionally, the step of sequentially forming a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer, and a first patterned hard mask layer on the surface of the layer to be etched includes: sequentially depositing and forming the first anti-reflection layer, the first sacrificial layer, the second anti-reflection layer, the second sacrificial layer, and a first patterned photolithography layer on the surface of the layer to be etched; etching the second sacrificial layer using the first patterned photolithography layer as a mask to form the first patterned sacrificial layer on the second sacrificial layer; removing the first patterned photolithography layer; depositing and etching a first sidewall layer covering all sidewalls of the first patterned sacrificial layer on the first patterned sacrificial layer; and opening the second sacrificial layer through photolithography and spacer deposition to form the first patterned hard mask layer, thereby creating the pattern corresponding to the first patterned photolithography layer.

[0086] Please refer to the attached document. Figure 3 and attached Figure 4 , Figure 3 and Figure 4 This is another set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in the embodiments of this application. It should be noted that, as... Figure 3 As shown, the first antireflective layer 102, the first sacrificial layer 103, the second antireflective layer 104, the second sacrificial layer 106, and the first patterned photolithography layer 107 are sequentially deposited on the surface of the layer to be etched 101; as Figure 4 As shown, the second sacrificial layer 106 is etched using the first patterned photolithography layer 107 as a mask to form the first patterned sacrificial layer 1051 on the second sacrificial layer; the first patterned photolithography layer 107 is removed; and the first sidewall layer 1052 covering all sidewalls of the first patterned sacrificial layer is deposited and etched on the first patterned sacrificial layer 1051.

[0087] Optionally, the first patterned photolithography layer includes: a spin-coated carbon layer, a spin-coated glass layer, and a patterned photoresist layer stacked sequentially, wherein the spin-coated carbon layer is stacked on the side of the second sacrificial layer away from the second anti-reflective layer, and the spin-coated glass layer is located between the spin-coated carbon layer and the patterned photoresist layer. (See attached figure) Figure 5 , Figure 5 These are cross-sectional views of a set of patterned photolithographic layers provided in the embodiments of this application. For example... Figure 5As shown, the first patterned photolithography layer 107 includes a spin-coated carbon layer 1071, a spin-coated glass layer 1072, and a patterned photoresist layer 1073 stacked sequentially. It should be noted that the pattern formed by the patterned photoresist layer 1073 is part of the final circuit pattern. This patterned photoresist layer 1073 can be obtained through exposure or etching. The spin-coated carbon layer 1071 can be spin-coated carbon, the spin-coated glass layer 1072 is made of glass spin-coating material, and the patterned photoresist layer is photoresist with one or more trenches. The three-layer structure of the photoresist allows for stable and precise transfer of the pattern formed by the photoresist to the second sacrificial layer through photolithography. Furthermore, it should be noted that the embodiments of this application do not specifically limit the structural material of the patterned photolithography layer; for example, the patterned photolithography layer may include a spin-coated double-layer photoresist structure.

[0088] Optionally, the step of depositing and etching the first sidewall layer covering all sidewalls of the first patterned sacrificial layer includes: depositing an insulating material covering the first patterned sacrificial layer on the first patterned sacrificial layer, etching the insulating material covering the horizontal direction of the first patterned sacrificial layer, and retaining the first sidewall layer covering all sidewalls of the first patterned sacrificial layer. Wherein, the projection of the first sidewall layer in the vertical direction at least covers the projection of the first patterned sacrificial layer in the vertical direction. Please refer to the appendix. Figure 6 , Figure 6 This is a set of cross-sectional views of a semiconductor device for fabricating a first sidewall layer, provided in an embodiment of this application. It should be noted that, as... Figure 6 As shown, an insulating material covering the first patterned sacrificial layer 1051 is deposited; the insulating material covering the first patterned sacrificial layer 1051 in the horizontal direction is etched, as described above. Figure 2 As shown, the first sidewall layer 1052 retains all the sidewalls of the first patterned sacrificial layer 1051. The fabrication of the first sidewall layer can be carried out using a spacer process, which involves first depositing an insulating material in a conformal manner, and then using anisotropic etching to retain the insulating material of the sidewalls, exposing the bottom region (e.g., the second antireflective layer 104).

[0089] Furthermore, after the pattern line corresponding to line A is created, its length can be adjusted. In this embodiment, after preparing the pattern line corresponding to line A, the pattern line can be backfilled to adjust its length. Optionally, the first patterned photolithography layer includes one or more third trenches; after the step of depositing and etching the first sidewall layer covering all sidewalls of the first patterned sacrificial layer, the method further includes: depositing a sixth patterned photolithography layer covering the first patterned hard mask layer, the sixth patterned photolithography layer including one or more fourth trenches, the position of each fourth trench being the same as the position of each third trench; etching the first patterned hard mask layer based on the sixth patterned photolithography layer as a mask to form an etched first patterned hard mask layer; depositing an oxide layer covering the sixth patterned photolithography layer and the etched first patterned hard mask layer; removing the sixth patterned photolithography layer and the oxide layer covering the sixth patterned photolithography layer; the step of photolithography to form a second patterned hard mask layer on the first patterned hard mask layer includes: photolithography to form the second patterned hard mask layer on the etched first patterned hard mask layer and the remaining oxide layer. Since the third trench is located at the same position as the fourth trench, the oxide deposited at the location of the fourth trench can block the third trench, thereby forming multiple trenches of different lengths, and thus obtaining circuit pattern lines of different lengths.

[0090] It should be noted that the first patterned photolithography layer includes one or more third trenches (e.g., LA), which can be used to fabricate one or more pattern lines belonging to line A in the circuit pattern. Please refer to the appendix. Figures 7-10 , Figures 7-10 This is a set of cross-sectional views of a semiconductor device fabricating Cut line A provided in the embodiments of this application. After depositing and etching the first patterned sacrificial layer 1051 to form a first sidewall layer 1052 covering all sidewalls of the first patterned sacrificial layer 1051, the method further includes:

[0091] like Figure 7 As shown, a sixth patterned photolithography layer 108 is deposited to cover the first patterned hard mask layer 105. The sixth patterned photolithography layer 108 includes one or more fourth trenches CA (Cut line A). The position of each fourth trench CA is the same as the position of the third trench LA. That is, in order to adjust the line length (length in the Z-axis direction) of the line A pattern, the position of the fourth trench CA coincides with the position of the third trench LA.

[0092] like Figure 8As shown, the first patterned hard mask layer 105 is etched using the sixth patterned photolithography layer 108 as a mask to form the etched first patterned hard mask layer 105. That is, the first patterned hard mask layer 105 is etched according to the position of the fourth trench CA. In order to block the lines of the line A pattern, the line length of the line A pattern is adjusted. The width of the fourth trench CA in the X-axis direction can be greater than or equal to the width of the area in the third trench LA in the X-axis direction that is not covered by the first sidewall layer.

[0093] Additionally, to block the lines of pattern A, an oxide layer 109 needs to be deposited at the fourth trench CA to disconnect the electrical connection of line A. For example... Figure 9 As shown, an oxide layer 109 is deposited to cover the sixth patterned photolithography layer 108 and the etched first patterned hard mask layer 105. The oxide layer 109 at the fourth trench CA needs to cover the bottom region of the fourth trench CA and can act as a mask in subsequent processes. For example, the thickness of the oxide layer 109 in the vertical direction at the fourth trench CA is greater than or equal to the thickness of the first patterned hard mask layer 105.

[0094] like Figure 10 As shown, the sixth patterned photolithography layer 108 and the oxide layer 109 covering the sixth patterned photolithography layer are removed, that is, the oxide layer 109 at the fourth trench CA is retained to block the lines of the line A pattern. In this embodiment, the length of the fourth trench CA in the Z-axis direction is not specifically limited; for example, the length of the fourth trench CA in the Z-axis direction can be less than the length of the third trench LA in the Z-axis direction. Finally, the step of photolithographically forming the second patterned hard mask layer from the first patterned hard mask layer includes: photolithographically forming the second patterned hard mask layer 115 from the etched first patterned hard mask layer 105 and the remaining oxide layer 109 (at the fourth trench). This step can be referred to the relevant description of step S2 below, which will not be repeated here.

[0095] Step S2: Photolithography is performed on the first patterned hard mask layer to form the second patterned hard mask layer.

[0096] Specifically, a second patterned hard mask layer is formed by photolithography on the first patterned hard mask layer. Please refer to the appendix. Figure 11 , Figure 11 This is another set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in the embodiments of this application. For example... Figure 11 As shown, based on the above Figure 10The provided semi-solid cross-sectional view shows that the first patterned hard mask layer 105 is photolithographically formed to create the second patterned hard mask layer 115. It should be noted that the second patterned hard mask layer 115 includes one or more trenches LA (corresponding to line A) formed after the first photolithography and one or more trenches LB (corresponding to line B) formed after the current photolithography. These one or more trenches LB can be used to create the pattern lines corresponding to line B. That is, the second patterned hard mask layer 115 also includes a patterned sacrificial layer not covered by the sidewalls. It should be noted that step S2 is for the fabrication of line B in the circuit pattern. It should also be noted that, since the materials of the first sidewall layer 1052 and the first patterned sacrificial layer 1051 in the first patterned hard mask layer 105 formed after the first photolithography (preparing line A) are different, the etching speeds of the first sidewall layer 1052 and the first patterned sacrificial layer 1051 are different when photolithography is performed again (preparing line B). If the etching speed of the first patterned sacrificial layer 1051 is faster, the first patterned sacrificial layer 1051 will be etched preferentially during photolithography, avoiding a significant impact on line A when preparing line B. This greatly reduces the accuracy requirements for the overlay error of the circuit pattern during the second photolithography, and reduces the difficulty of circuit design.

[0097] Optionally, the step of photolithographically forming a second patterned hard mask layer from the first patterned hard mask layer includes: depositing a second patterned photolithographic layer covering the first patterned hard mask layer; etching the first patterned hard mask layer based on the second patterned photolithographic layer as a mask to form the second patterned hard mask layer; and removing the second patterned photolithographic layer. Please refer to the appendix. Figure 12 , Figure 12 This is another set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in the embodiments of this application. It should be noted that, as... Figure 12 As shown, a second patterned photolithography layer 201 is deposited to cover the first patterned hard mask layer 105; based on the second patterned photolithography layer 201 as a mask, the first patterned hard mask layer is etched to form the second patterned hard mask layer 115 (as described above). Figure 11 (as shown); remove the second patterned photolithography layer 201.

[0098] Furthermore, the length of the patterned lines corresponding to line B can be adjusted after the patterned lines corresponding to line B are fabricated. Unlike the adjustment of the backfilling method for line A in the embodiments of this application (preparing line A first and then preparing Cut line A), this application can prepare Cut line B by pre-cutting, that is, preparing Cut line B first and then preparing line B. Therefore, the patterned lines can be cut before preparing the patterned lines corresponding to line B, thereby achieving the adjustment of the length of the patterned lines. Since Cut line B is formed before preparing line B, in order to ensure that Cut line B can block the electrical connection of line B, Cut line B needs to be completed before preparing the spacer (i.e., forming the first sidewall layer) to ensure that insulating material can be deposited at Cut line B to block the electrical connection of line B. This application uses the preparation of Cut line B before preparing the first patterned hard mask layer as an example for illustrative explanation. Optionally, the second patterned photolithography layer includes one or more first trenches; before the step of depositing and etching the first patterned sacrificial layer to form the first sidewall layer covering all sidewalls of the first patterned sacrificial layer, the method further includes: forming a fifth patterned photolithography layer on the surface of the first patterned sacrificial layer, the fifth patterned photolithography layer including one or more second trenches, the position of each second trench being the same as the position of each first trench; based on the fifth patterned photolithography layer as a mask, etching the first patterned sacrificial layer according to the second trenches to form an etched first patterned sacrificial layer; and removing the fifth patterned photolithography layer.

[0099] It should be noted that the second patterned photolithography layer includes one or more first trenches (e.g., LB), which can be used to fabricate one or more pattern lines belonging to line B in the circuit pattern. Please refer to the appendix. Figures 13-15 , Figures 13-15 This application provides a set of cross-sectional views of a semiconductor device for fabricating Cut line B. Prior to the step of depositing and etching the first sidewall layer covering all sidewalls of the first patterned sacrificial layer, the method further includes: Figure 13 As shown, a fifth patterned photolithography layer 202 is formed on the surface of the first patterned sacrificial layer 1051. The fifth patterned photolithography layer 202 includes one or more second trenches CB. The position of each second trench CB is the same as the position of each first trench LB. In addition, the length of the second trench CB in the X-axis direction is greater than or equal to the length of the first trench LB in the X-axis direction.

[0100] like Figure 14As shown, based on the fifth patterned photolithography layer 202 as a mask, the first patterned sacrificial layer 1051 is etched according to the second trench CB to form the etched first patterned sacrificial layer 1051; then the fifth patterned photolithography layer 202 is removed. Since the pattern corresponding to the second trench CB is prepared in the first patterned sacrificial layer 1051 before the step of depositing and etching the first sidewall layer 1052 covering all sidewalls of the first patterned sacrificial layer 1051, therefore, as... Figure 15 As shown, when the first sidewall layer 1052 is fabricated, the insulating material of the sidewall layer will cover the first patterned sacrificial layer 1051 after etching, thereby also covering the second trench CB. Then, when the pattern formed by the first trench LB is subsequently fabricated, the insulating material at the second trench CB will block the pattern lines formed by the first trench LB, thereby obtaining one or more discontinuous trenches of different lengths, that is, obtaining circuit pattern lines of different lengths (for line B).

[0101] It should also be noted that the preparation process for Cut line B can also be performed before the formation of the first patterned sacrificial layer, that is, Cut line B is prepared before line A, Cut line A, and line B. For example: a fifth patterned photolithography layer is formed on the surface of the second sacrificial layer, the fifth patterned photolithography layer including one or more second trenches, the position of each second trench being the same as the position of each first trench; based on the fifth patterned photolithography layer as a mask, the second sacrificial layer is etched according to the second trenches to form an etched second sacrificial layer; the fifth patterned photolithography layer is removed. Then line A, Cut line A, and line B are prepared sequentially.

[0102] Because the preparation of Cut line B needs to be completed before the deposition of the first sidewall layer, line B can only be prepared after Cut line B has been prepared. Please refer to the appendix. Figure 16 , Figure 16 This is a cross-sectional view of a device for fabricating a semiconductor device using a set of self-aligned quadruple patterning, as provided in an embodiment of this application. Figure 16 As shown, based on the above Figure 15The provided semiconductor cross-sectional views (semiconductor cross-sectional views after the fabrication of line A, Cut line A, and Cut line B) show how a second patterned hard mask layer 115 is formed by photolithography based on the first patterned hard mask layer 105 formed after etching the second sacrificial layer. It should be noted that the first patterned hard mask layer 105 is formed after photolithography of the second sacrificial layer after etching. The second patterned hard mask layer 115 includes one or more trenches LA (corresponding to line A) formed after the first photolithography, one or more trenches LB (corresponding to line B) formed after the current photolithography, Cut line A for the patterned line corresponding to line A, and Cut line B for the patterned line corresponding to line B. The fabrication method of Cut line A can be referred to the above description. Figures 7 to 10 The relevant descriptions are not repeated here in the embodiments of this application.

[0103] Step S3: Based on the second patterned hard mask layer as a mask, the second anti-reflection layer and the first sacrificial layer are etched to form the second patterned sacrificial layer.

[0104] Specifically, the second anti-reflection layer and the first sacrificial layer are etched using the second patterned hard mask layer as a mask to form the second patterned sacrificial layer. Please refer to the appendix. Figure 17 , Figure 17 This is another set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in this application embodiment. Based on the second patterned hard mask layer 115 as a mask, the second anti-reflection layer 104 and the first sacrificial layer 103 are etched, as shown... Figure 17 As shown, a second patterned sacrificial layer 1031 is formed in the first sacrificial layer 103. The description of the second patterned sacrificial layer 1031 can be found in the description of the first patterned sacrificial layer 1051, and will not be repeated here. Figure 17 The semiconductor cross-sectional view shown is a schematic cross-sectional view after removing the second patterned hard mask layer 115 and the second anti-reflection layer 104.

[0105] Step S4: Remove the second patterned hard mask layer and the second anti-reflection layer, and form a third patterned hard mask layer based on the second patterned sacrificial layer.

[0106] For details, please refer to the appendix. Figure 18 , Figure 18 This is a cross-sectional view of a device for fabricating a semiconductor device using a set of self-aligned quadruple patterning, as provided in an embodiment of this application. Figure 18As shown, the second patterned hard mask layer 115 and the second anti-reflection layer 104 are removed, and a third patterned hard mask layer 1032 is formed based on the second patterned sacrificial layer 1031. The third patterned hard mask layer 1032 includes the second patterned sacrificial layer 1031 and a second sidewall layer 1033 covering all sidewalls of the second patterned sacrificial layer 1031. It should be noted that step S4 is for the fabrication of the second sidewall layer.

[0107] Optional, please refer to the appendix Figure 19 , Figure 19 This is a cross-sectional view of a device for fabricating a semiconductor device using a set of self-aligned quadruple patterning, as provided in an embodiment of this application. Figure 19 As shown, the step of forming a third patterned hard mask layer 1032 based on the second patterned sacrificial layer 1031 includes: depositing an insulating material covering the second patterned sacrificial layer 1031 on the second patterned sacrificial layer 1031; etching the insulating material covering the second patterned sacrificial layer 1031 in the horizontal direction, retaining the second sidewall layer 1033 covering all sidewalls of the second patterned sacrificial layer 1031. This process is the second spacer deposition process. The fabrication of the second sidewall layer 1033 also employs a spacer process, which refers to first depositing an insulating material conformally, and then using anisotropic etching to retain the insulating material on the sidewalls, exposing the bottom region (e.g., the first anti-reflective layer 102). The relevant description of the second sidewall layer 1033 can be referred to in the corresponding description of the first sidewall layer 1052, and will not be repeated here in this embodiment.

[0108] Step S5: Photolithography is performed on the third patterned hard mask layer to form the fourth patterned hard mask layer.

[0109] Specifically, the fourth patterned hard mask layer is formed by photolithography on the third patterned hard mask layer. Please refer to the appendix. Figure 20 , Figure 20 This is another set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in the embodiments of this application. For example... Figure 20 As shown, Figure 20 As shown, based on the above Figure 18The provided semiconductor cross-sectional view shows the photolithography used to form a fourth patterned hard mask layer 1132 from the third patterned hard mask layer 1032. It should be noted that the third patterned hard mask layer 1032 includes one or more trenches LA (corresponding to line A) formed after the first photolithography, one or more trenches LB (corresponding to line B) formed after the second photolithography, and a second sidewall layer 1033 formed after the second spacer deposition; the fourth patterned hard mask layer 1132 includes one or more trenches LA (corresponding to line A) formed after the first photolithography, one or more trenches LB (corresponding to line B) formed after the second photolithography, and a second sidewall layer 1033 formed after the second spacer deposition, as well as one or more trenches LC (corresponding to line C) formed after the current photolithography. These one or more trenches LC can be used to create the pattern line corresponding to line C. That is, the fourth patterned hard mask layer 1132 also includes a patterned sacrificial layer not covered by the sidewalls. It should be noted that step S5 is for the fabrication of line C in the circuit pattern.

[0110] When the circuit pattern is not complex, the circuit diagram can be formed by three photolithography steps (line A, line B, and line C). Optionally, the step of photolithographically forming the fourth patterned hard mask layer from the third patterned hard mask layer includes: photolithographically forming the fourth patterned hard mask layer from the third patterned photolithography layer. In the embodiments of this application, the photolithography process can first form a patterned photolithography layer covering the patterned hard mask layer, then further open the sacrificial layer using the patterned photolithography layer as a mask, and finally remove the patterned photolithography layer.

[0111] For example: Please refer to the appendix Figure 21 , Figure 21 This is a cross-sectional view of a device for fabricating a semiconductor device using a set of self-aligned quadruple patterning, as provided in an embodiment of this application. Figure 21 As shown, the step of forming the fourth patterned hard mask layer by photolithography of the third patterned hard mask layer according to the third patterned photolithography layer includes: depositing a third patterned photolithography layer 203 covering the third patterned hard mask layer 1032; etching the third patterned hard mask layer 1032 based on the third patterned photolithography layer 203 as a mask to form the fourth patterned hard mask layer 1132 (as described above). Figure 20 (as shown); remove the third patterned photolithography layer 203.

[0112] It should be noted that, optionally, in the horizontal direction (i.e., the X-axis direction), the linewidth of the third patterned photolithography layer is equal to or greater than twice the width of the second sidewall layer. That is, the pattern size defined by the second photolithography (the width of LB on the X-axis) is equal to or greater than twice the width of the second sidewall layer. Unlike the prior art where the linewidth of the pattern must be equal to the width of the second sidewall layer, in this embodiment, the linewidth of the pattern can also be greater than twice the width of the second sidewall layer.

[0113] It should also be noted that, optionally, in the horizontal direction (i.e., the X-axis direction), the linewidth of the patterns of the second, third, and fourth patterned photolithography layers is less than or equal to the spacing between adjacent first sidewall layers or adjacent second sidewall layers. In this embodiment, the linewidth of the circuit pattern fabricated after the first sidewall layer cannot exceed the spacing between the first sidewall layer and the adjacent second sidewall layer. It does not cross or exceed the spacing between corresponding positions of two spacers (i.e., the spacing between corresponding positions of adjacent first sidewall layers 1052 or adjacent second sidewall layers 1033).

[0114] Furthermore, the length of the patterned lines corresponding to line C can be adjusted after the patterned lines corresponding to line C are fabricated. Similar to the method of pre-cutting line B in the embodiments of this application, the embodiments of this application can similarly prepare line C by pre-cutting line C, thereby achieving the adjustment of the length of the patterned line line C. Since line C is formed before line B is fabricated, in order to ensure that line C can block the electrical connection of line C, line C needs to be completed before the spacer is fabricated (i.e., the second sidewall layer 1033 is formed) to ensure that insulating material can be deposited at line C to block the electrical connection of line C. For example, the third patterned photolithography layer 203 includes one or more fifth trenches (LC).

[0115] It should be noted that the third patterned photolithography layer 203 includes one or more fifth trenches (e.g., LC), which can be used to fabricate one or more pattern lines belonging to line C in the circuit pattern. Please refer to the appendix. Figures 22-24 , Figures 22-24 This is a set of cross-sectional views of a semiconductor device for fabricating Cut line C provided in an embodiment of this application. Before the step of depositing an insulating material covering the second patterned sacrificial layer 1031, the method further includes: Figure 22As shown, a seventh patterned photolithography layer 204 is formed on the surface of the second patterned sacrificial layer 1031. The seventh patterned photolithography layer 204 includes one or more sixth trenches CC, and the position of each sixth trench CC is the same as the position of each fifth trench LC. In addition, the length of the sixth trench CC in the X-axis direction is greater than or equal to the length of the fifth trench LC in the X-axis direction.

[0116] like Figure 23 As shown, based on the seventh patterned photolithography layer 204 as a mask, the second patterned sacrificial layer 1031 is etched according to the sixth trench CC to form the etched second patterned sacrificial layer 1031; the seventh patterned photolithography layer 204 is then removed. Since the pattern corresponding to the second trench CC is prepared in the second patterned sacrificial layer 1031 before the step of depositing and etching the second sidewall layer 1033 covering all sidewalls of the second patterned sacrificial layer 1031, therefore, as described above... Figure 19 As shown, when the second sidewall layer 1033 is fabricated, the insulating material of the sidewall layer will cover the etched second patterned sacrificial layer 1031, thereby also covering the second trench CC. Then, when the pattern formed by the first trench LC is subsequently fabricated, the insulating material at the second trench CC will block the pattern lines formed by the first trench LC, thereby obtaining one or more discontinuous trenches of different lengths, that is, obtaining circuit pattern lines of different lengths (for line C).

[0117] Since the preparation process of Cut line C (102) needs to be completed before the deposition of the second sidewall layer, line C can only be prepared after Cut line C is prepared. Based on the above... Figure 23 The provided cross-sectional views of the semiconductor (semiconductor cross-sections after fabrication of line A, line B, cut line A, cut line B, and cut line C) are as follows: Figure 24 As shown, a fourth patterned hard mask layer 1132 is formed by photolithography on the third patterned hard mask layer 1032 based on the etched second patterned sacrificial layer 1031. It should be noted that the preparation process of Cut line C can also refer to the preparation process of Cut line B described above, and will not be repeated in the embodiments of this application.

[0118] Step S6: Based on the fourth patterned hard mask layer as a mask, the first anti-reflection layer and the layer to be etched are etched to form a patterned layer to be etched.

[0119] Specifically, the first anti-reflective layer and the layer to be etched are etched using a fourth patterned hard mask layer as a mask to form a patterned layer to be etched. For example, when the layer to be etched is a metallic material, the circuit pattern on the fourth patterned hard mask layer can be transferred to the layer to be etched through etching to form multiple metal lines, thus forming electrical connections. Please refer to the appendix. Figure 25 , Figure 25 This is another set of cross-sectional views of a self-aligned quadruple patterning semiconductor device provided in the embodiments of this application. For example... Figure 25 As shown, the first anti-reflection layer 102 and the etchable layer 101 are etched using the fourth patterned hard mask layer 1132 as a mask to form a patterned etchable layer 111.

[0120] Step S7: Remove the fourth patterned hard mask layer and the first anti-reflection layer.

[0121] Specifically, such as Figure 25 As shown, the fourth patterned hard mask layer 1132 and the first anti-reflection layer 102 are removed to obtain a patterned layer to be etched.

[0122] Unlike existing technologies that form patterned hard masks through two depositions of spacers, this application adds a pattern photolithography step between the sidewalls of the two spacer depositions. Specifically, circuit patterns are prepared through alternating photolithography and two spacer depositions, and finally, photolithography is used to define the pattern to be opened to form a patterned hard mask. First, adjacent metal lines cannot be placed very close together if they are fabricated on the same photomask layer, but they can be placed very close together if they are fabricated on two different photomasks. Thus, by performing multiple photolithography steps in self-aligned quadruple patterning and distributing close metal lines on different photomasks, the desired effect can be achieved, increasing the density of circuit pattern design. Second, since a sidewall layer is often formed in the patterned hard mask layer after the first photolithography step by depositing spacers based on the pattern during photolithography, the etching rate differs between the hard mask layer and the sidewall layer materials during subsequent photolithography. This significantly reduces the precision requirements for circuit pattern overlay during subsequent photolithography, reducing the difficulty of circuit design. Moreover, the circuit pattern is ultimately formed by multiple photolithography patterns, and the length, width, and spacing between them can be freely adjusted compared to the pattern formed by the spacers.

[0123] Steps S1-S7 above, taking the division of lines in a circuit pattern into three types of pattern lines—line A, line B, and line C—as an example, exemplify a method for fabricating a self-aligned quadruple patterned semiconductor device provided in this application. Furthermore, based on the self-aligned quadruple patterned semiconductor device fabrication method provided in the above embodiments, this application uses, for example, line A, line B, line C, and line D to fabricate pattern lines at different photolithography stages. Taking four steps as an example, please refer to the following description of the relevant steps:

[0124] Step 1: Sequentially deposit a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer, a second sacrificial layer, and a first patterned photolithography layer (to prepare the patterned photolithography layer for LA) on the surface of the layer to be etched. The first patterned photolithography layer includes one or more third trenches.

[0125] Step 2: Based on the first patterned photolithography layer as a mask, the second sacrificial layer is etched, and the second sacrificial layer is etched according to the third trench to form the first patterned mask layer on the second sacrificial layer.

[0126] Step 3: Remove the first patterned photolithography layer (LA preparation complete).

[0127] Step four, a fifth patterned photolithography layer (the patterned photolithography layer for preparing CB) is formed on the surface of the first patterned sacrificial layer. The fifth patterned photolithography layer includes one or more second trenches.

[0128] Step 5: Using the fifth patterned photolithography layer as a mask, etch the first patterned sacrificial layer according to the second trench to form the etched first patterned sacrificial layer.

[0129] Step six: Remove the fifth patterned photolithography layer.

[0130] Step 7: After etching, the first patterned sacrificial layer is deposited and etched to form a first sidewall layer covering all the sidewalls of the first patterned sacrificial layer, thus obtaining the first patterned hard mask layer (the first sidewall layer and CB are prepared).

[0131] Step 8: Deposit to form a sixth patterned photomask layer (preparing the patterned photomask layer of CA) covering the first patterned hard mask layer. The sixth patterned photomask layer includes one or more fourth trenches, the position of each fourth trench being the same as the position of each third trench.

[0132] Step nine: Based on the sixth patterned photolithography layer as a mask, the first patterned hard mask layer is etched to form the etched first patterned hard mask layer.

[0133] Step 10: Deposit an oxide layer covering the sixth patterned photolithography layer and the etched first patterned hard mask layer.

[0134] Step 11: Remove the sixth patterned photolithography layer and the oxide layer covering the sixth patterned photolithography layer (CA preparation complete).

[0135] Step 12: Deposit to form a second patterned photomask layer covering the etched first patterned hard mask layer and the remaining oxide layer (preparing the patterned photomask layer of LB). The second patterned photomask layer includes one or more first trenches, and the position of each second trench is the same as the position of each first trench.

[0136] Step 13: Using the second patterned photolithography layer as a mask, etch the etched first patterned hard mask layer and the remaining oxide layer to form the second patterned hard mask layer.

[0137] Step fourteen: Remove the second patterned photolithography layer (LB preparation complete).

[0138] Step 15: Based on the second patterned hard mask layer as a mask, the second anti-reflection layer and the first sacrificial layer are etched to form the second patterned sacrificial layer.

[0139] Step sixteen: Remove the second patterned hard mask layer and the second anti-reflection layer.

[0140] Step 17: Form a seventh patterned photolithography layer (for preparing CC and CD) on the surface of the second patterned sacrificial layer. The seventh patterned photolithography layer includes one or more sixth trenches and eighth trenches.

[0141] Step 18: Using the seventh patterned photolithography layer as a mask, etch the second patterned sacrificial layer according to the sixth trench to form the etched second patterned sacrificial layer.

[0142] Step nineteen: Remove the seventh patterned photolithography layer.

[0143] Step 20: After etching, the second patterned sacrificial layer is deposited and etched to form a second sidewall layer covering all the sidewalls of the second patterned sacrificial layer, thus obtaining the third patterned hard mask layer (the second sidewall layer, CC, and CD are now complete).

[0144] Step 21: Deposit to form a third patterned photolithography layer covering the third patterned hard mask layer (preparing the patterned photolithography layer of LC). The third patterned photolithography layer includes one or more fifth trenches, and the position of each fifth trench is the same as the position of each sixth trench.

[0145] Step 22: Based on the third patterned photolithography layer as a mask, etch the third patterned hard mask layer to form the fifth patterned hard mask layer.

[0146] Step 23: Remove the third patterned photolithography layer (LC fabrication complete).

[0147] Step 24: Deposit to form a fourth patterned photomask layer covering the fifth patterned hard mask layer (preparing the patterned photomask layer of the LD). The fourth patterned photomask layer includes one or more seventh trenches, the position of each seventh trench being the same as the position of each eighth trench.

[0148] Step 25: Etch the fifth patterned hard mask layer using the fourth patterned photolithography layer as a mask to form the fourth patterned hard mask layer.

[0149] Step 26: Remove the fourth patterned photolithography layer (LD fabrication complete).

[0150] Step 27: Using the fourth patterned hard mask layer as a mask, etch the first anti-reflection layer and the layer to be etched to form a patterned layer to be etched.

[0151] Step 28: Remove the fourth patterned hard mask layer and the first anti-reflection layer.

[0152] For steps 24 to 26, the step of photolithographically forming a fourth patterned hard mask layer from the third patterned hard mask layer includes: photolithographically forming a fifth patterned hard mask layer from the third patterned hard mask layer according to the third patterned photolithography layer; and photolithographically forming the fourth patterned hard mask layer from the fifth patterned hard mask layer according to the fourth patterned photolithography layer. The process of photolithographically forming the fifth patterned hard mask layer from the third patterned hard mask layer according to the third patterned photolithography layer is the fabrication of the line C pattern lines in the circuit pattern (as described above). Figures 20-21 (Related description); The fifth patterned hard mask layer is formed by photolithography according to the fourth patterned photolithography layer. This process is for the fabrication of line D pattern lines in the circuit pattern. In the embodiments of this application, the fabrication processes of line D and line C are similar. Please refer to the appendix. Figure 26 -Attached Figure 30 , Figures 26-30 These are cross-sectional views of a set of semiconductor devices for fabricating line D and cutting line D, provided in embodiments of this application.

[0153] like Figure 26 As shown, based on the above Figure 22According to the relevant description, a seventh patterned photolithography layer 204 is formed on the surface of the second patterned sacrificial layer 1031. The seventh patterned photolithography layer 204 includes one or more sixth trenches (CC) and one or more eighth trenches (CD) (simultaneously fabricating cut line C and cut line D). The position of each sixth trench (CC) is the same as the position of each fifth trench (LC), and the position of each eighth trench (CD) is the same as the position of each seventh trench (LD). Furthermore, the length of the sixth trench (CC) in the X-axis direction is greater than or equal to the length of the fifth trench (LC) in the X-axis direction, and the length of the eighth trench (CD) in the X-axis direction is greater than or equal to the length of the seventh trench (LD) in the X-axis direction.

[0154] like Figure 27 As shown, based on the above Figure 23 According to the relevant description, the seventh patterned photolithography layer 204 is a mask, and the second patterned sacrificial layer 1031 is etched according to the sixth trench CC and the eighth trench CD to form the etched second patterned sacrificial layer 1031; the seventh patterned photolithography layer 204 is removed.

[0155] like Figure 28 As shown, the fifth patterned hard mask layer is formed by photolithography using the fourth patterned photolithography layer. First, a fourth patterned photolithography layer 205 (patterned photolithography layer for fabricating LDs) is deposited to cover the fifth patterned hard mask layer. The fourth patterned photolithography layer 205 includes one or more seventh trench LDs, the position of each seventh trench LD being the same as the position of each eighth trench CD. Additionally, the fifth patterned hard mask layer is formed by photolithography using the third patterned photolithography layer. This process is for fabricating line C pattern lines in the circuit pattern (as described above). Figure 20 one Figure 21 The relevant descriptions (as described in the embodiments of this application) will not be repeated here.

[0156] like Figure 29 As shown, the fifth patterned hard mask layer is etched using the fourth patterned photolithography layer 205 as a mask to form the fourth patterned hard mask layer. The fourth patterned photolithography layer is then removed (LD fabrication complete).

[0157] like Figure 30 As shown above, Figure 29 The semiconductor device shown etches the first anti-reflection layer and the layer to be etched based on the fourth patterned hard mask layer as a mask to form a patterned layer to be etched, and then removes the fourth patterned hard mask layer and the first anti-reflection layer.

[0158] In the horizontal direction, the linewidths of the patterns in the third and fourth patterned photolithography layers are equal to or greater than twice the width of the second sidewall layer. Unlike the prior art where the linewidth of the pattern must be equal to the width of the second sidewall layer, the widths of the LC and LD prepared by the third and fourth photolithography processes, respectively, in the X-axis direction are equal to or greater than twice the width of the second sidewall layer.

[0159] It should be noted that steps one to twenty-three and steps twenty-seven to twenty-eight are one preparation method provided in the embodiments of this application. Please refer to the relevant descriptions of steps S1 to S7 above, and this application will not repeat them.

[0160] It should also be noted that the specific method of circuit pattern splitting and the number of photolithography steps during preparation need to be determined according to the specific circumstances, and the embodiments of this application do not impose specific limitations on this.

[0161] It should also be noted that the embodiments of this application also provide a semiconductor device fabricated based on the above-described self-aligned quadruple patterning semiconductor device fabrication method, including a substrate and any of the semiconductor devices fabricated by the above method stacked on the substrate. For example, patterned layers to be etched can also be stacked on the substrate to form electrical connections to achieve corresponding functions.

[0162] It should also be noted that this application embodiment also provides an electronic device, which includes any of the semiconductor devices and circuit boards provided in the above embodiments. The semiconductor device is electrically connected to the circuit board, and the electronic device is used to implement related functions.

[0163] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0164] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0165] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0166] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0167] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0168] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM).

[0169] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a self-aligned quadruple patterned semiconductor device, characterized in that, include: A first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer, and a first patterned hard mask layer are sequentially formed on the surface of the layer to be etched. The first patterned hard mask layer includes a first patterned sacrificial layer and a first sidewall layer that covers all the sidewalls of the first patterned sacrificial layer. The first patterned hard mask layer is photolithographically etched to form the second patterned hard mask layer; Based on the second patterned hard mask layer as a mask, the second anti-reflection layer and the first sacrificial layer are etched to form the second patterned sacrificial layer; Remove the second patterned hard mask layer and the second anti-reflection layer, and form a third patterned hard mask layer based on the second patterned sacrificial layer, the third patterned hard mask layer including the second patterned sacrificial layer and a second sidewall layer covering all sidewalls of the second patterned sacrificial layer; The third patterned hard mask layer is photolithographically formed to create the fourth patterned hard mask layer; Based on the fourth patterned hard mask layer as a mask, the first anti-reflection layer and the layer to be etched are etched to form a patterned layer to be etched. Remove the fourth patterned hard mask layer and the first anti-reflection layer.

2. The method according to claim 1, characterized in that, The step of sequentially forming a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer, and a first patterned hard mask layer on the surface of the layer to be etched includes: The first anti-reflection layer, the first sacrificial layer, the second anti-reflection layer, the second sacrificial layer, and the first patterned photolithography layer are sequentially deposited on the surface of the layer to be etched. The second sacrificial layer is etched using the first patterned photolithography layer as a mask to form the first patterned sacrificial layer on the second sacrificial layer; Remove the first patterned photolithography layer; The first sidewall layer is deposited and etched to form a first sidewall layer covering all sidewalls of the first patterned sacrificial layer.

3. The method according to claim 2, characterized in that, The first patterned photolithography layer includes: a spin-coated carbon layer, a spin-coated glass layer and a patterned photoresist layer stacked sequentially, wherein the spin-coated carbon layer is stacked on the side of the second sacrificial layer away from the second anti-reflection layer, and the spin-coated glass layer is between the spin-coated carbon layer and the patterned photoresist layer.

4. The method according to any one of claims 2, characterized in that, The step of photolithography to form a second patterned hard mask layer from the first patterned hard mask layer includes: A second patterned photolithography layer is deposited to cover the first patterned hard mask layer; The first patterned hard mask layer is etched using the second patterned photolithography layer as a mask to form the second patterned hard mask layer; Remove the second patterned photolithography layer.

5. The method according to claim 4, characterized in that, The step of photolithography to form the fourth patterned hard mask layer from the third patterned hard mask layer includes: The third patterned hard mask layer is photolithographically formed according to the third patterned photolithography layer to form the fourth patterned hard mask layer.

6. The method according to claim 4, characterized in that, The step of photolithography to form the fourth patterned hard mask layer from the third patterned hard mask layer includes: The third patterned hard mask layer is photolithographically formed according to the third patterned photolithography layer to form the fifth patterned hard mask layer; The fifth patterned hard mask layer is formed by photolithography according to the fourth patterned photolithography layer.

7. The method according to claim 6, characterized in that, In the horizontal direction, the linewidths of the patterns in the third patterned photolithography layer and the fourth patterned photolithography layer are equal to or greater than twice the width of the second sidewall layer, respectively.

8. The method according to claim 6 or 7, characterized in that, In the horizontal direction, the linewidth of the patterns of the second, third, and fourth patterned photolithography layers is less than or equal to the spacing between adjacent first sidewall layers or adjacent second sidewall layers.

9. The method according to claim 4, characterized in that, The second patterned photolithography layer includes one or more first trenches; Prior to the step of depositing and etching the first sidewall layer to form a first sidewall layer covering all sidewalls of the first patterned sacrificial layer, the method further includes: A fifth patterned photolithography layer is formed on the surface of the first patterned sacrificial layer. The fifth patterned photolithography layer includes one or more second trenches, and the position of each second trench is the same as the position of each first trench. Based on the fifth patterned photolithography layer as a mask, the first patterned sacrificial layer is etched according to the second trench to form the etched first patterned sacrificial layer; Remove the fifth patterned photolithography layer.

10. The method according to any one of claims 2-4, characterized in that, The first patterned photolithography layer includes one or more third trenches; The step of depositing and etching a first sidewall layer covering all sidewalls of the first patterned sacrificial layer after the first patterned sacrificial layer further includes: A sixth patterned photolithography layer is deposited to cover the first patterned hard mask layer. The sixth patterned photolithography layer includes one or more fourth trenches, the position of each fourth trench being the same as the position of each third trench. Based on the sixth patterned photolithography layer as a mask, the first patterned hard mask layer is etched to form the etched first patterned hard mask layer; An oxide layer is deposited to cover the sixth patterned photolithography layer and the etched first patterned hard mask layer; Remove the sixth patterned photolithography layer and the oxide layer covering the sixth patterned photolithography layer; The step of photolithography to form a second patterned hard mask layer from the first patterned hard mask layer includes: The etched first patterned hard mask layer and the remaining oxide layer are photolithographically formed to create the second patterned hard mask layer.

11. A self-aligned quadruple patterned semiconductor device, characterized in that, Includes a substrate and a semiconductor device fabricated by the method of any one of claims 1-10, stacked on the substrate.

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