A noise simulation circuit for a backplane power distribution network of an integrated circuit

Abstract

The application discloses a noise simulation circuit of a back surface power distribution network of an integrated circuit and relates to the technical field of integrated circuits.The method model comprises a power supply voltage source, a back surface power distribution network equivalent circuit model and an on-chip load equivalent current source.The back surface power distribution network equivalent circuit model specifically comprises a soldering point equivalent circuit, a back surface metal grid equivalent circuit, a micro-silicon through hole equivalent circuit and a buried power supply track equivalent circuit.The power supply voltage source is connected with the soldering point equivalent circuit.The soldering point equivalent circuit is connected with the back surface metal grid equivalent circuit.The back surface metal grid equivalent circuit is connected with the micro-silicon through hole equivalent circuit.The micro-silicon through hole equivalent circuit is connected with the buried power supply track equivalent circuit.The buried power supply track equivalent circuit is connected with the on-chip load equivalent current source.The application realizes higher accuracy and can simulate a real situation better.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a noise simulation circuit for the back-side power distribution network of an integrated circuit. Background Technology

[0002] In integrated circuit systems, most transistors are fabricated on single-crystal silicon wafers and are connected by metal wires to transmit signals and power. However, as the number of transistors in integrated circuits increases and their size shrinks, the interconnects also become smaller, leading to increasingly congested interconnect wiring. The reduction in interconnect size results in increased parasitic parameters, increasing latency and introducing noise. Interconnect congestion leads to increased crosstalk, severely impacting circuit performance. Power lines inevitably compete with signal lines for space. While many solutions exist to improve efficiency and reduce the footprint of the active portion of the Power Delivery Network (PDN), the design of on-chip power distribution networks must be reconsidered to address the current power supply challenges of integrated circuits.

[0003] A novel backside power supply scheme, the Backside Power Distribution Network (BS-PDN), has been proposed. In this scheme, the back side of the wafer is metallized and used for power supply, while the front side remains used for logic functions and signal interconnects. Bonding points transfer power from the outside of the die to the backside metal layer (BSM) on the back side of the wafer. Buried power rails (BPR) and micro-through-silicon vias (μTSV) efficiently transfer power from the back side of the wafer to active devices on the front side. This new backside power supply method reduces interconnect routing congestion, thereby reducing noise on interconnects and crosstalk between interconnects, improving chip performance. Noise analysis and optimization can be performed by building a noise simulation circuit for the backside power distribution network.

[0004] In their paper "PowerDelivery Network (PDN) Modeling for Backside-PDN Configurations With BuriedPower Rails and μTSVs" (doi:10.1109 / TED.2019.2954301), Md Obaidul Hossen and Geert Van der Plas et al. considered the equivalent resistance of the power grid and built a noise simulation circuit for a backside power distribution network of an integrated circuit.

[0005] The existing models are rather crude, failing to consider the actual back-side power distribution network structure, not fully taking into account the parasitic parameters of the power supply lines, and not considering the actual on-chip load operation. Summary of the Invention

[0006] This invention provides a noise simulation circuit for the back-side power distribution network of an integrated circuit, which solves the problems in the prior art that do not consider the actual back-side power distribution network structure, do not fully consider the parasitic parameters of the power supply lines, and do not consider the actual on-chip load operation. It achieves higher accuracy and can better simulate real-world conditions.

[0007] This invention provides a noise simulation circuit for the back power distribution network of an integrated circuit. The noise simulation circuit includes: a power supply voltage source, an equivalent circuit model of the back power distribution network, and an equivalent current source of the on-chip load. Specifically, the equivalent circuit model of the back power distribution network includes: an equivalent circuit of solder joints, an equivalent circuit of the back metal mesh, an equivalent circuit of micro-silicon vias, and an equivalent circuit of buried power rails.

[0008] The power supply voltage source is connected to the equivalent circuit of the welding point;

[0009] The equivalent circuit of the welding point is connected to the equivalent circuit of the back metal mesh;

[0010] The back metal mesh equivalent circuit is connected to the micro silicon via equivalent circuit, wherein the back metal mesh equivalent circuit includes multiple identical unit back metal mesh equivalent circuits;

[0011] The equivalent circuit of the microsilicon via is connected to the equivalent circuit of the buried power rail.

[0012] The buried power rail equivalent circuit is connected to the on-chip load equivalent current source, wherein the buried power rail equivalent circuit is composed of multiple identical unit buried power rail equivalent circuits connected in series.

[0013] In one possible implementation, the equivalent circuit of the solder joint specifically includes: a first parasitic resistance R of the solder joint. Bond / 2. The second parasitic resistance R of the welding point Bond / 2, First parasitic inductance L at the solder joint Bond / 2, The second parasitic inductance L at the welding point Bond / 2 and the parasitic capacitance C around the solder joint Bond ;

[0014] The first parasitic resistance R of the welding point Bond / 2, the first parasitic inductance L of the weld point Bond / 2, the second parasitic inductance L of the weld point Bond / 2 and the second parasitic resistance R of the weld point Bond / 2 are connected in series;

[0015] The parasitic capacitance C around the welding point Bond The first parasitic resistance R connected in parallel at the weld point Bond / 2 and the second parasitic resistance R of the weld point Bond Between / 2.

[0016] In one possible implementation, the equivalent circuit of the metal mesh on the back of the unit specifically includes: a first transverse circuit and a second transverse circuit, a longitudinal circuit and a series circuit.

[0017] The first lateral circuit and the second lateral circuit each include: the first parasitic inductance L of the grid line of the unit BSM2 layer. BSM2 / 2, The first parasitic resistance R of the BSM2 layer grid line BSM2 / 2, The second parasitic resistance R of the BSM2 layer grid line BSM2 / 2, The second parasitic inductance L of the BSM2 layer grid line in unit BSM BSM2 / 2 and MIM capacitor C MIM ;

[0018] The first parasitic inductance L of the BSM2 layer grid line of the unit BSM2 / 2. The first parasitic resistance R of the grid line of the unit BSM2 layer BSM2 / 2. The second parasitic resistance R of the grid line of the unit BSM2 layer BSM2 / 2 and the second parasitic inductance L of the BSM2 layer grid line of the unit BSM2 / 2 are connected in series; the MIM capacitor C MIM The first parasitic resistance R connected in parallel to the grid line of the BSM2 layer of the cell BSM2 / 2 and the second parasitic resistance R of the BSM2 layer grid lines of the unit BSM2 Between / 2;

[0019] The vertical circuit includes: n equivalent circuits of BSM1 layer grid lines connected in series, where n represents the spacing p between adjacent BSM2 layer grid lines. BSM2 Spacing p with adjacent buried power rails BPR The ratio;

[0020] The equivalent circuit of the unit BSM1 layer grid line includes the parasitic inductance L of the unit BSM1 layer grid line connected in series. BSM1 Parasitic resistance R of the BSM1 layer grid lines BSM1 ;

[0021] The series circuit specifically includes the parasitic resistance R of vias connected in series. ViaParasitic inductance L of the through hole Via ;

[0022] The first transverse circuit and the longitudinal circuit are connected through the series circuit.

[0023] In one possible implementation, the parasitic resistance R of the grid lines in the unit BSM1 layer... BSM1 The specific calculation formula is expressed as follows:

[0024]

[0025] The parasitic resistance R of the BSM2 layer grid lines in the unit cell BSM2 The specific calculation formula is expressed as follows:

[0026]

[0027] The parasitic inductance L of the grid lines in the unit BSM1 layer BSM1 The specific calculation formula is expressed as follows:

[0028]

[0029] The parasitic inductance L of the BSM2 layer grid lines of the unit BSM2 The specific calculation formula is expressed as follows:

[0030]

[0031] The parasitic inductance L of the through hole Via The specific calculation formula is expressed as follows:

[0032]

[0033] The parasitic resistance R of the through hole Via The specific calculation formula is expressed as follows:

[0034]

[0035] Where, ρ Cu Indicates the resistivity of copper; l BSM1 h represents the length of the grid lines in layer BSM1 of the cell. BSM1 Indicates the height of the BSM1 layer grid lines; w BSM1 Indicates the width of the BSM1 layer grid lines; l BSM2 Indicates the length of the BSM2 layer mesh line; h BSM2 Indicates the height of the BSM2 layer grid lines; w BSM2 The width of the BSM2 layer grid lines is represented by μ0; μ0 represents the permeability of free space; γ represents the empirical constant; h Via Indicates the height of the through hole; w Via This indicates the side length of the through hole.

[0036] In one possible implementation, the equivalent circuit of the microsilicon via specifically includes:

[0037] The first parasitic resistance R of the microsilicon via μTSV / 2. The second parasitic resistance R of the microsilicon via μTSV / 2, The first parasitic inductance L of the microsilicon via μTSV / 2, The second parasitic inductance L of the microsilicon via μTSV / 2. Parasitic capacitance C of the oxide layer μTSV_ox Parasitic capacitance C of silicon substrate μTSV_Si Parasitic conductivity G of silicon substrate μTSV_Si ;

[0038] The first parasitic inductance L of the microsilicon via μTSV / 2. The first parasitic resistance R of the microsilicon via μTSV / 2. The second parasitic inductance L of the microsilicon via μTSV / 2 and the second parasitic inductance L of the microsilicon via μTSV / 2 are connected in series;

[0039] The parasitic capacitance C of the oxide layer μTSV_ox The first parasitic resistance R connected in parallel to the microsilicon via μTSV / 2 and the second parasitic resistance R of the microsilicon via μTSV Between / 2;

[0040] The parasitic conductivity G of the silicon substrate μTSV_Si and the parasitic capacitance C of the silicon substrate μTSV_Si The parallel circuit is connected in series with the parasitic capacitance C of the two oxide layers. μTSV_ox between.

[0041] In conjunction with the first aspect, in one possible implementation, the first parasitic resistance R of the microsilicon via... μTSV / 2 and the second parasitic resistance R of the microsilicon via μTSV The parasitic resistance R of the microsilicon via is obtained by adding the two values. μTSV ;

[0042] The first parasitic inductance L of the microsilicon via μTSV / 2 and the second parasitic inductance L of the microsilicon via μTSV The parasitic inductance L of the microsilicon via is obtained by adding the two together. μTSV .

[0043] In one possible implementation, the parasitic resistance R of the microsilicon via... μTSV The specific calculation formula is expressed as follows:

[0044]

[0045] The parasitic inductance L of the microsilicon via μTSV The specific calculation formula is expressed as follows:

[0046]

[0047] The parasitic capacitance C of the oxide layer μTSV_ox The specific calculation formula is expressed as follows:

[0048]

[0049] The parasitic capacitance C of the silicon substrate μTSV_Si The specific calculation formula is expressed as follows:

[0050]

[0051] The parasitic conductivity G of the silicon substrate μTSV_Si The specific calculation formula is expressed as follows:

[0052]

[0053] Where, ρ Cu h represents the resistivity of copper. μTSV Indicates the height of the microsilicon via; r μTSV The radius of the micro-silicon via is represented by μ; μ0 represents the permeability of vacuum; ε ox ε represents the relative permittivity of the oxide layer; ε0 represents the permittivity of vacuum; t μTSV_ox Indicates the thickness of the oxide layer; ε Si Indicates the relative permittivity of silicon; s μTSV This indicates the distance between the microsilicon via and the surrounding microsilicon vias.

[0054] In one possible implementation, the equivalent circuit of the buried power rail specifically includes: a first parasitic resistance R of the buried power rail. BPR / 2. The second parasitic resistance R of the unit buried power rail BPR / 2, The first parasitic inductance L of the unit buried power rail BPR / 2, The second parasitic inductance L of the unit buried power rail BPR / 2. The first parasitic capacitance C of the oxide layer BPR_ox The second parasitic capacitance C of the oxide layer BPR_ox Parasitic capacitance C of silicon substrate BPR_Si Parasitic conductivity G of silicon substrate BPR_Si ;

[0055] The first parasitic inductance L of the buried power rail of the unit BPR / 2. The first parasitic resistance R of the buried power rail of the unit BPR / 2, the second parasitic resistance and the second parasitic inductance L of the unit buried power rail. BPR / 2 are connected in series;

[0056] The first parasitic capacitance C of the oxide layer BPR_ox The first parasitic resistance R connected in parallel with the buried power rail of the unit BPR / 2, between the second parasitic resistance of the buried power rail of the unit;

[0057] The parasitic conductivity G of the silicon substrate BPR_Si and the parasitic capacitance C of the silicon substrate BPR_Si The parallel circuit is connected in series with the first parasitic capacitance C of the oxide layer. BPR_ox and the second parasitic capacitance C of the oxide layer BPR_ox between.

[0058] In one possible implementation, the first parasitic resistance R of the buried power rail of the unit BPR / 2 and the second parasitic resistance R of the buried power rail of the unit BPR The parasitic resistance R of the buried power rail is obtained by adding the two values ​​together. BPR ;

[0059] The first parasitic inductance L of the buried power rail of the unit BPR / 2 and the second parasitic inductance L of the buried power rail of the unit BPR The parasitic inductance L of the buried power rail obtained by adding / 2 BPR .

[0060] In one possible implementation, the parasitic resistance R of the buried power rail of the unit BPR The specific calculation formula is as follows:

[0061]

[0062] The parasitic inductance L of the buried power rail of the unit BPR The specific calculation formula is as follows:

[0063]

[0064] The parasitic capacitance C of the oxide layer BPR_ox The specific calculation formula is as follows:

[0065]

[0066] The parasitic capacitance C of the silicon substrate BPR_Si The specific calculation formula is as follows:

[0067]

[0068] The parasitic conductivity G of the silicon substrate BPR_Si The specific calculation formula is as follows:

[0069]

[0070] Where, ρ W The resistivity of tungsten under high-temperature processing; l BPR Indicates the length of the buried power rail of the unit; h BPR Indicates the height of the buried power rail; w BPR The width of the buried power rail is represented by μ; μ0 represents the permeability of vacuum; γ represents the empirical constant; ε ox ε0 represents the relative permittivity of the oxide layer; ε0 represents the permittivity of vacuum; t BPR_ox Indicates the thickness of the oxide layer; ε Si t represents the relative permittivity of silicon; BPR_Si σ represents the thickness of the silicon dielectric between the buried power rails; Si This indicates the electrical conductivity of silicon.

[0071] One or more technical solutions provided in this invention have at least the following technical effects or advantages:

[0072] (1) The present invention takes into account the structure of the actual back power distribution network, segments and models the back power distribution network, and takes into account the influence of various parasitic parameters, which has higher accuracy compared with the prior art.

[0073] (2) It takes into account the actual working conditions of the on-chip load, which is closer to the real situation than existing technologies. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments of the present invention or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0075] Figure 1 A schematic diagram of a noise simulation circuit for the back-side power distribution network of an integrated circuit provided in an embodiment of the present invention;

[0076] Figure 2a This is a structural diagram of the back-side power distribution network provided in an embodiment of the present invention;

[0077] Figure 2b A schematic diagram of a rear power distribution network provided in an embodiment of the present invention;

[0078] Figure 3a A structural diagram of the welding point provided in an embodiment of the present invention;

[0079] Figure 3b A diagram showing the arrangement of welding points provided in an embodiment of the present invention;

[0080] Figure 3c Equivalent circuit diagram of the welding point provided in the embodiment of the present invention;

[0081] Figure 4a A structural diagram of the back metal mesh provided in an embodiment of the present invention;

[0082] Figure 4b An arrangement diagram of the back metal mesh provided in an embodiment of the present invention;

[0083] Figure 4c Equivalent circuit diagram of the metal mesh on the back of the unit provided in the embodiment of the present invention;

[0084] Figure 5a This is a structural diagram of a microsilicon via provided in an embodiment of the present invention;

[0085] Figure 5b This is an arrangement diagram of microsilicon vias provided in an embodiment of the present invention;

[0086] Figure 5c The equivalent circuit diagram of the microsilicon via provided in the embodiments of the present invention;

[0087] Figure 6a This is a structural diagram of a buried power rail provided in an embodiment of the present invention;

[0088] Figure 6b An arrangement diagram of buried power rails provided in an embodiment of the present invention;

[0089] Figure 6c An equivalent circuit diagram of a unit buried power rail provided in an embodiment of the present invention;

[0090] Figure 7 A schematic diagram of the equivalent current source of an on-chip load provided in an embodiment of the present invention;

[0091] Figure 8 A noise simulation circuit diagram of the back-side power distribution network provided for an embodiment of the present invention. Detailed Implementation

[0092] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0093] This invention provides a noise simulation circuit for the back-side power distribution network of an integrated circuit, such as... Figure 1 As shown, the noise simulation circuit includes: a power supply voltage source, an equivalent circuit model of the back power distribution network, and an equivalent current source of the on-chip load. Specifically, the equivalent circuit model of the back power distribution network includes: equivalent circuits of solder joints, equivalent circuits of the back metal mesh, equivalent circuits of through-silicon vias (TSVs), and equivalent circuits of buried power rails. The power supply voltage source is connected to the equivalent circuit of the solder joints; the equivalent circuit of the solder joints is connected to the equivalent circuit of the back metal mesh; the equivalent circuit of the back metal mesh is connected to the equivalent circuit of the TSVs; the equivalent circuit of the TSVs is connected to the equivalent circuit of the buried power rails; and the equivalent circuit of the buried power rails is connected to the equivalent current source of the on-chip load.

[0094] For example, the noise simulation circuit for the rear power distribution network of the present invention belongs to the on-chip power distribution network, thus ignoring the package-level and board-level power distribution networks. This noise simulation circuit is mainly divided into three parts: the supply voltage source, the equivalent circuit of the rear power distribution network, and the equivalent current source of the on-chip load. Among them, the rear power distribution network mainly considers the parasitic parameters of the power lines, while the ground lines are treated as ideal.

[0095] Power supply voltage source: Set an appropriate voltage source according to the actual circuit operating voltage.

[0096] Equivalent Circuit of Backside Power Distribution Network: Based on the structure of the backside power distribution network, its equivalent circuit can be divided into equivalent circuit models of the bonding points, backside metal, micro-through-silicon vias (μTSVs), and buried power rails (BPRs). Parasitic parameters for each of the four components are obtained, equivalent circuit models are established, and then these models are connected together to form the equivalent circuit of the backside power distribution network.

[0097] On-chip load equivalent current source: This can be used to represent the on-chip load as a triangular wave current source to simulate the switching operation of the on-chip load of the integrated circuit. The minimum and maximum currents are set according to the actual power consumption during operation.

[0098] Finally, the on-chip load equivalent current source is connected to the equivalent circuit of the buried power rail of each unit, and the voltage source is connected to the equivalent circuit of the solder joint, to obtain the noise simulation circuit of the complete back-side power distribution network.

[0099] For example, such as Figure 2a and Figure 2bAs shown, the structure of the back-side power distribution network is divided into four components: solder joints, back-side metal mesh, micro-silicon vias, and buried power rails. Therefore, the equivalent circuit of the back-side power distribution network is also divided into equivalent circuit models of these four parts.

[0100] Specifically, such as Figure 3c The diagram shows the equivalent circuit of the solder joint, specifically including: the first parasitic resistance R of the solder joint. Bond / 2. The second parasitic resistance R of the welding point Bond / 2, First parasitic inductance L at the solder joint Bond / 2, The second parasitic inductance L at the welding point Bond / 2 and the parasitic capacitance C around the solder joint Bond .

[0101] The first parasitic resistance R of the weld joint Bond / 2, First parasitic inductance L of the solder joint Bond / 2, The second parasitic inductance L at the welding point Bond / 2 and the second parasitic resistance R of the welding point Bond / 2 are connected in series;

[0102] Parasitic capacitance C around the solder joint Bond The first parasitic resistance R connected in parallel at the welding point Bond / 2 and the second parasitic resistance R of the welding point Bond Between / 2.

[0103] For example, such as Figure 3a and Figure 3b As shown, the solder joint includes a solder bump and a pad. Given the material, dimensions, and spacing, the parasitic parameters are obtained using the electromagnetic parameter extraction function of electromagnetic simulation software. Specifically, the solder bump is generally composed of various alloys and consists of small elliptical spheres encased in a polymer insulating material, typically manufactured on a copper pad base. Bump h represents the height of the solder bump. Pad Indicates the height of the pad, r Bump The radius r represents the solder bump radius. Pad p represents the radius of the pad. Bond This indicates the spacing between welding points.

[0104] The equivalent circuit of the solder joint considers the parasitic resistance R of the solder joint. Bond Parasitic inductance L at the solder joint Bond Parasitic capacitance C around the solder joint Bond When extracting parasitic capacitance related to a solder joint, the interaction between the solder joint and the four surrounding solder joints is mainly considered. Parasitic parameters are extracted using the Q3D tool.

[0105] Specifically, the equivalent circuit of the back metal mesh consists of repeating unit mesh equivalent circuits. For example... Figure 4c The equivalent circuit of the metal mesh on the back of the unit is shown, which specifically includes: a first transverse circuit, a second transverse circuit, a longitudinal circuit, and a series circuit.

[0106] The first lateral circuit and the second lateral circuit each include: the first parasitic inductance L of the grid line of the unit BSM2 layer. BSM2 / 2, The first parasitic resistance R of the BSM2 layer grid line BSM2 / 2, The second parasitic resistance R of the BSM2 layer grid line BSM2 / 2, The second parasitic inductance L of the BSM2 layer grid line in unit BSM BSM2 / 2 and MIM capacitor C MIM ;

[0107] The first parasitic inductance L of the BSM2 layer grid line in the unit BSM2 / 2, The first parasitic resistance R of the BSM2 layer grid line BSM2 / 2, The second parasitic resistance R of the BSM2 layer grid line BSM2 The second parasitic inductance L of / 2 and the BSM2 layer grid lines of the unit BSM2 / 2 are connected in series; MIM capacitor C MIM The first parasitic resistance R connected in parallel to the grid line of cell BSM2 layer BSM2 The second parasitic resistance R of / 2 and unit BSM2 layer grid lines BSM2 Between / 2;

[0108] The vertical circuit includes: an equivalent circuit of n BSM1 layer grid lines connected in series, where n represents the spacing p between adjacent BSM2 layer grid lines. BSM2 Spacing p with adjacent buried power rails BPR The ratio;

[0109] The equivalent circuit of a single-cell BSM1 layer grid line includes the parasitic inductance L of the series-connected single-cell BSM1 layer grid lines. BSM1 Parasitic resistance R of the BSM1 layer grid lines BSM1 ;

[0110] A series circuit, specifically including the parasitic resistance R of vias connected in series. Via Parasitic inductance L of the through hole Via ;

[0111] The first horizontal circuit and the first vertical circuit are connected in series.

[0112] For example, such as Figure 4a and Figure 4bAs shown, the back metal mesh consists of repeating unit back metal meshes. Each unit back metal mesh is divided into unit BSM1 layer mesh lines, unit BSM2 layer mesh lines, and vias. Given the material, dimensions, and spacing, the parasitic parameters are obtained using parasitic parameter calculation formulas or the electromagnetic parameter extraction function of electromagnetic simulation software. Specifically, the unit BSM1 layer mesh lines, unit BSM2 layer mesh lines, and vias in the unit back metal mesh are typically made of copper and encased in insulating filler material. During modeling, considering that the BSM1 layer mesh lines are physically connected to the buried power rails through micro-silicon vias and are perpendicular to them, the spacing p between adjacent buried power rails is used. BPR The length l of the BSM1 layer mesh line represents the length of the mesh line. BSM1 That is, l BSM1 =2p BPR Considering that the BSM2 layer grid lines are physically connected to the BSM1 layer grid lines through vias and are perpendicular to each other, the spacing p between adjacent BSM1 layer grid lines is used. BSM1 The length l of the BSM2 layer mesh line represents the length of the element. BSM2 That is, l BSM2 =2p BSM1 Therefore, the horizontal edge of each cell grid is a segment of cell BSM2 layer grid line, and the vertical edge is formed by connecting n segments of cell BSM1 layer grid lines, where n depends on the spacing p between adjacent BSM2 layer grid lines. BSM2 Spacing p between the adjacent buried power rail BPR ,Right now

[0113] The equivalent circuit of the metal mesh on the back of the cell considers the parasitic resistance R of the mesh lines in the BSM1 layer of the cell. BSM1 Parasitic inductance L of the BSM1 layer grid lines BSM1 Parasitic resistance R of the BSM2 layer grid line BSM2 Parasitic inductance L of the BSM2 layer grid lines in the unit BSM2 Parasitic resistance R of through-hole Via Parasitic inductance L of through-hole Via The MIM capacitor C between the power line and ground line of the metal mesh on the back MIM Parasitic parameters are extracted using the Q3D tool or determined by the formula below.

[0114] Specifically, the parasitic resistance R of the BSM1 layer grid lines. BSM1 The specific calculation formula is expressed as follows:

[0115]

[0116] Parasitic resistance R of the BSM2 layer grid line BSM2 The specific calculation formula is expressed as follows:

[0117]

[0118] Parasitic inductance L of the BSM1 layer grid line BSM1 The specific calculation formula is expressed as follows:

[0119]

[0120] Parasitic inductance L of the BSM2 layer grid lines in the unit BSM2 The specific calculation formula is expressed as follows:

[0121]

[0122] Parasitic inductance L of the through hole Via The specific calculation formula is expressed as follows:

[0123]

[0124] Parasitic resistance R of through hole Via The specific calculation formula is expressed as follows:

[0125]

[0126] Where, ρ Cu Indicates the resistivity of copper; l BSM1 h represents the length of the grid lines in layer BSM1 of the cell. BSM1 Indicates the height of the BSM1 layer grid lines; w BSM1 Indicates the width of the BSM1 layer grid lines; l BSM2 Indicates the length of the BSM2 layer mesh line; h BSM2 Indicates the height of the BSM2 layer grid lines; w BSM2 The width of the BSM2 layer grid lines is represented by μ0; μ0 represents the permeability of free space; γ represents the empirical constant; h Via Indicates the height of the through hole; w Via This indicates the side length of the through hole.

[0127] Specifically, such as Figure 5c The diagram shows the equivalent circuit of a microsilicon via, specifically including: the first parasitic resistance R of the microsilicon via. μTSV / 2. The second parasitic resistance R of the microsilicon via μTSV / 2, The first parasitic inductance L of the microsilicon via μTSV / 2, The second parasitic inductance L of the microsilicon via μTSV / 2. Parasitic capacitance C of the oxide layer μTSV_ox Parasitic capacitance C of silicon substrate μTSV_Si Parasitic conductivity G of silicon substrate μTSV_Si ;

[0128] The first parasitic inductance L of the microsilicon viaμTSV / 2. The first parasitic resistance R of the microsilicon via μTSV / 2, The second parasitic inductance L of the microsilicon via μTSV / 2 and the second parasitic inductance L of the microsilicon via μTSV / 2 are connected in series;

[0129] Parasitic capacitance C of oxide layer μTSV_ox The first parasitic resistance R connected in parallel to the microsilicon via μTSV / 2 and the second parasitic resistance R of the microsilicon via μTSV Between / 2;

[0130] Parasitic conductivity G of silicon substrate μTSV_Si Parasitic capacitance C of silicon substrate μTSV_Si The parasitic capacitance C of the parallel circuit connected in series with the two oxide layers μTSV_ox between.

[0131] Specifically, the first parasitic resistance R of the microsilicon via μTSV / 2 and the second parasitic resistance R of the microsilicon via μTSV The parasitic resistance R of the microsilicon via is obtained by adding the two values. μTSV ;

[0132] The first parasitic inductance L of the microsilicon via μTSV / 2 and the second parasitic inductance L of the microsilicon via μTSV The parasitic inductance L of the microsilicon via is obtained by adding the two together. μTSV .

[0133] For example, such as Figure 5a and Figure 5b As shown, given the material, size, and spacing of microsilicon vias (MSVs), their parasitic parameters can be obtained using parasitic parameter calculation formulas or the electromagnetic parameter extraction function of electromagnetic simulation software. Specifically, MSVs are fabricated in a thinned silicon substrate on the back side of a wafer. They are solid cylindrical copper pillars encased in a thin insulating layer of silicon dioxide, used for current transmission. They can most efficiently transmit current from the back side of the wafer to active devices at the front end. μTSV Indicates the height of the microsilicon via; r μTSV Indicates the radius of the microsilicon via; t μTSV_ox This indicates the thickness of the oxide layer. μTSV This indicates the spacing between adjacent vias connected to the same backside metal mesh line. μTSV This represents the distance between a micro-silicon via and its surrounding micro-silicon vias. Considering both the nearest and second nearest neighbor cases, it can be represented by the spacing p between adjacent micro-silicon vias. μTSV The spacing p between adjacent buried power rails BPR The spacing p between adjacent BSM1 layer grid lines BSM1 The calculation results are as follows: or

[0134] The equivalent circuit of a microsilicon via (TSV) considers the parasitic resistance R of the TSV. μTSV Parasitic inductance L of microsilicon vias μTSV Parasitic capacitance C of oxide layer μTSV_ox Parasitic capacitance C of silicon substrate μTSV_Si Parasitic conductivity G of silicon substrate μTSV_Si When extracting parasitic capacitance and conductance related to micro-silicon vias (MSVs), the interaction between the MSV and the four surrounding MSVs is primarily considered. Parasitic parameters are extracted using Q3D tools or determined by the formula below.

[0135] Specifically, the parasitic resistance R of a microsilicon via μTSV The specific calculation formula is expressed as follows:

[0136]

[0137] Parasitic inductance L of microsilicon via μTSV The specific calculation formula is expressed as follows:

[0138]

[0139] Parasitic capacitance C of oxide layer μTSV_ox The specific calculation formula is expressed as follows:

[0140]

[0141] Parasitic capacitance C of silicon substrate μTSV_Si The specific calculation formula is expressed as follows:

[0142]

[0143] Parasitic conductivity G of silicon substrate μTSV_Si The specific calculation formula is expressed as follows:

[0144]

[0145] Where, ρ Cu h represents the resistivity of copper. μTSV Indicates the height of the microsilicon via; r μTSV The radius of the micro-silicon via is represented by μ; μ0 represents the permeability of vacuum; ε ox ε0 represents the relative permittivity of the oxide layer; ε0 represents the permittivity of vacuum; t μTSV_ox Indicates the thickness of the oxide layer; ε Si Indicates the relative permittivity of silicon; s μTSV This indicates the distance between the microsilicon via and the surrounding microsilicon vias.

[0146] Specifically, the equivalent circuit of a buried power rail is formed by connecting unit buried power rail equivalent circuits in series. For example... Figure 6c The diagram shows the equivalent circuit of a unit buried power rail, specifically including: the first parasitic resistance R of the unit buried power rail. BPR / 2. The second parasitic resistance R of the unit buried power rail BPR / 2, The first parasitic inductance L of the unit buried power rail BPR / 2, The second parasitic inductance L of the unit buried power rail BPR / 2. The first parasitic capacitance C of the oxide layer BPR_ox The second parasitic capacitance C of the oxide layer BPR_ox Parasitic capacitance C of silicon substrate BPR_Si Parasitic conductivity G of silicon substrate BPR_Si ;

[0147] The first parasitic inductance L of the buried power rail of the unit BPR / 2. The first parasitic resistance R of the unit buried power rail BPR / 2. The second parasitic resistance and the second parasitic inductance L of the unit buried power rail BPR / 2 are connected in series;

[0148] The first parasitic capacitance C of the oxide layer BPR_ox The first parasitic resistance R of the parallel and unit buried power rail BPR / 2, between the second parasitic resistance of the unit buried power rail;

[0149] Parasitic conductivity G of silicon substrate BPR_Si Parasitic capacitance C of silicon substrate BPR_Si The parallel circuit is connected in series with the first parasitic capacitance C of the oxide layer. BPR_ox The second parasitic capacitance C of the oxide layer BPR_ox between.

[0150] Specifically, the first parasitic resistance R of the buried power rail of the unit BPR / 2 and the second parasitic resistance R of the buried power rail of the unit BPR The parasitic resistance R of the buried power rail is obtained by adding the two values ​​together. BPR ;

[0151] The first parasitic inductance L of the buried power rail of the unit BPR / 2 and the second parasitic inductance L of the buried power rail of the unit BPR The parasitic inductance L of the buried power rail is obtained by adding the two together. BPR .

[0152] For example, such as Figure 6a and Figure 6bAs shown, buried power rails are formed by connecting repeating unit buried power rails. Given the material, dimensions, and spacing, their parasitic parameters can be obtained using parasitic parameter calculation formulas or the electromagnetic parameter extraction function of electromagnetic simulation software. Specifically, buried power rails are metal lines buried beneath transistors, typically made of tungsten, partially encased in a thin insulating layer of silicon dioxide within a silicon substrate, and partially within shallow trench isolation oxides. BPR_Si The thickness of the silicon dielectric between adjacent buried power rails can be calculated, i.e., t. BPR_Si =p BPR -2t BPR_ox -w BPR ;w BPR Indicates the width of the buried power rail; h BPR Indicates the height of the buried power rail; t BPR_ox This indicates the thickness of the oxide layer. Based on the connection relationship between the buried power rail and the micro-silicon via, it can be disassembled into segmented unit buried power rails, with each segment having a length l. BPR The spacing p between adjacent buried power rails can be used. BPR The spacing p between adjacent BSM1 layer grid lines BSM1 The spacing p between adjacent micro-silicon vias μTSV To indicate, that is

[0153] The equivalent circuit of the buried power rail unit considers the parasitic resistance R of the buried power rail unit. BPR Parasitic inductance L of the buried power rail of the unit BPR Parasitic capacitance C of oxide layer BPR_ox Parasitic capacitance C of silicon substrate BPR_Si Parasitic conductivity G of silicon substrate BPR_Si When extracting parasitic capacitance and conductance related to buried power rails, the interaction between the buried power rail and two adjacent buried power rails is mainly considered. Parasitic parameters are extracted using Q3D tools or determined by the formula below.

[0154] Specifically, the parasitic resistance R of the buried power rail of the unit BPR The specific calculation formula is as follows:

[0155]

[0156] Parasitic inductance L of the buried power rail BPR The specific calculation formula is as follows:

[0157]

[0158] Parasitic capacitance C of oxide layer BPR_ox The specific calculation formula is as follows:

[0159]

[0160] Parasitic capacitance C of silicon substrate BPR_Si The specific calculation formula is as follows:

[0161]

[0162] Parasitic conductivity G of silicon substrate BPR_Si The specific calculation formula is as follows:

[0163]

[0164] Where, ρ W The resistivity of tungsten under high-temperature processing; l BPR Indicates the length of the buried power rail of the unit; h BPR Indicates the height of the buried power rail; w BPR The width of the buried power rail is represented by μ; μ0 represents the permeability of vacuum; γ represents the empirical constant; ε ox ε0 represents the relative permittivity of the oxide layer; ε0 represents the permittivity of vacuum; t BPR_ox Indicates the thickness of the oxide layer; ε Si t represents the relative permittivity of silicon; BPR_Si σ represents the thickness of the silicon dielectric between adjacent buried power rails; Si This indicates the electrical conductivity of silicon.

[0165] like Figure 7 The diagram shown illustrates the equivalent current source of an on-chip load. An on-chip load can be modeled as having… Ascent time Fall time A periodic triangular wave current source with a static time. The minimum current I is set based on the actual power consumption. min and maximum current I max The calculation formula is as follows:

[0166]

[0167]

[0168] P = P Static +P Dynamic (1.19)

[0169] Among them, P Static P represents static power consumption. Dynamic V represents dynamic power consumption, P represents total power consumption, and V represents total power consumption. dd This indicates the power supply voltage.

[0170] like Figure 8As shown, the on-chip load equivalent current source is connected to the buried power rail of each unit, and the voltage source is connected to the solder point to obtain the noise simulation circuit of the complete back power distribution network.

[0171] Furthermore, this embodiment describes the above method through experiments. A noise simulation circuit for the rear power distribution network is built in ADS, and the model parameters are shown in the table below:

[0172] Table 1 Basic parameters of the back power distribution network noise simulation circuit

[0173]

[0174] By using the controlled variable method, different parameters in the back-side power distribution network noise simulation circuit can be changed to study the influence of each parameter on the noise. The simulation results are shown in the table below:

[0175] Table 2. Influence of solder joint spacing on noise in the back-side power distribution network

[0176]

[0177]

[0178] Table 3. The Influence of the Spacing of the Rear Metal Mesh Lines on the Noise of the Rear Power Distribution Network

[0179]

[0180] Table 4. Impact of microsilicon via spacing on noise in the back-side power distribution network.

[0181]

[0182] Table 5. Impact of Buried Power Rail Aspect Ratio on Noise in Rear Power Distribution Network

[0183]

[0184] Table 6. Impact of MIM Capacitors on Noise in Backside Power Distribution Network

[0185]

[0186] Table 7. Impact of Static Power Consumption Ratio on Noise in Rear Power Distribution Network

[0187]

[0188] While this invention provides method operation steps as shown in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-inventive labor. The order of steps listed in this embodiment is merely one possible execution order among many and does not represent the only possible execution order. In actual device or client product execution, the method can be executed sequentially according to this embodiment or the accompanying drawings, or in parallel (e.g., in a parallel processor or multi-threaded processing environment).

[0189] The apparatus or module described in the above embodiments can be implemented by a computer chip or physical entity, or by a product with a certain function. For ease of description, the above apparatus is described by dividing it into various modules according to their functions. In implementing this invention, the functions of each module can be implemented in one or more software and / or hardware. Of course, a module that implements a certain function can also be implemented by combining multiple sub-modules or sub-units.

[0190] The methods, apparatus, or modules described in this invention can be implemented in a computer-readable program code manner. The controller can be implemented in any suitable manner, for example, as a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of a memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code manner, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included within it for implementing various functions can also be considered as structures within the hardware component. Alternatively, the device used to implement various functions can be viewed as either a software module that implements the method or a structure within a hardware component.

[0191] Some modules in the apparatus described in this invention can be described in the general context of computer-executable instructions that are executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, classes, etc., that perform a specific task or implement a specific abstract data type. This invention can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0192] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software plus necessary hardware. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, or it can be embodied in the process of data migration. The computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, mobile terminal, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of the present invention.

[0193] The various embodiments described in this specification are presented in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. All or part of this invention can be used in numerous general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices, etc.

[0194] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A noise simulation circuit for the back-side power distribution network of an integrated circuit, characterized in that, include: The equivalent circuit models of the power supply voltage source, the back power distribution network, and the on-chip load are defined. Specifically, the equivalent circuit model of the back power distribution network includes: the equivalent circuit of the solder joint, the equivalent circuit of the back metal mesh, the equivalent circuit of the micro-silicon via, and the equivalent circuit of the buried power rail. The power supply voltage source is connected to the equivalent circuit of the welding point; The equivalent circuit of the welding point is connected to the equivalent circuit of the back metal mesh; The back metal mesh equivalent circuit is connected to the microsilicon via equivalent circuit, wherein the back metal mesh equivalent circuit includes multiple identical unit back metal mesh equivalent circuits; the microsilicon via equivalent circuit specifically includes: the first parasitic resistance of the microsilicon via. Second parasitic resistance of microsilicon vias The first parasitic inductance of microsilicon vias Second parasitic inductance of microsilicon via Parasitic capacitance of oxide layer Parasitic capacitance of silicon substrate Parasitic conductivity of silicon substrate The first parasitic inductance of the microsilicon via The first parasitic resistance of microsilicon vias The second parasitic inductance of the microsilicon via and the second parasitic inductance of the microsilicon via The parasitic capacitance of the oxide layer is connected in series. The first parasitic resistance connected in parallel to the microsilicon via and the second parasitic resistance of the microsilicon via Between; the parasitic conductivity of the silicon substrate and the parasitic capacitance of the silicon substrate The parallel circuit is connected in series with the parasitic capacitance of the two oxide layers. between; The equivalent circuit of the microsilicon via is connected to the equivalent circuit of the buried power rail. The equivalent circuit of the buried power rail is connected to the equivalent current source of the on-chip load. The equivalent circuit of the buried power rail is composed of multiple identical unit buried power rail equivalent circuits connected in series. Specifically, the equivalent circuit of each unit buried power rail includes: a first parasitic resistance of the unit buried power rail. The second parasitic resistance of the buried power rail of the unit The first parasitic inductance of the unit buried power rail The second parasitic inductance of the buried power rail of the unit The first parasitic capacitance of the oxide layer The second parasitic capacitance of the oxide layer Parasitic capacitance of silicon substrate Parasitic conductivity of silicon substrate ; The first parasitic inductance of the unit's buried power rail The first parasitic resistance of the buried power rail of the unit The second parasitic resistance and the second parasitic inductance of the unit buried power rail. Connected in series; The first parasitic capacitance of the oxide layer The first parasitic resistance connected in parallel with the buried power rail of the unit Between the second parasitic resistance of the buried power rail of the unit; Parasitic conductivity of the silicon substrate and the parasitic capacitance of the silicon substrate The parallel circuit is connected in series with the first parasitic capacitance of the oxide layer. and the second parasitic capacitance of the oxide layer between.

2. The noise simulation circuit for the back-side power distribution network of the integrated circuit according to claim 1, characterized in that, The equivalent circuit of the solder joint specifically includes: the first parasitic resistance of the solder joint. Second parasitic resistance of the welding point The first parasitic inductance of the solder joint Second parasitic inductance of the solder joint Parasitic capacitance around the solder joint ; The first parasitic resistance of the welding point The first parasitic inductance of the weld joint The second parasitic inductance of the welding point and the second parasitic resistance of the weld point Connected in series; The parasitic capacitance around the welding point The first parasitic resistance connected in parallel at the welding point and the second parasitic resistance of the weld point between.

3. The noise simulation circuit for the back-side power distribution network of the integrated circuit according to claim 1, characterized in that, The equivalent circuit of the metal mesh on the back of the unit specifically includes: a first transverse circuit, a second transverse circuit, a longitudinal circuit, and a series circuit. The first lateral circuit and the second lateral circuit each include: the first parasitic inductance of the grid line of the unit BSM2 layer. The first parasitic resistance of the BSM2 layer grid line in the unit The second parasitic resistance of the BSM2 layer grid lines The second parasitic inductance of the BSM2 layer grid lines in the unit and MIM capacitors ; The first parasitic inductance of the BSM2 layer grid line of the unit The first parasitic resistance of the BSM2 layer grid lines of the unit The second parasitic resistance of the BSM2 layer grid lines of the unit and the second parasitic inductance of the BSM2 layer grid lines of the unit The MIM capacitors are connected in series. The first parasitic resistance connected in parallel to the grid line of the BSM2 layer of the cell and the second parasitic resistance of the BSM2 layer grid lines of the unit between; The vertical circuit comprises: connected in series. The equivalent circuit of the BSM1 layer grid lines of each unit, wherein... Represented as the spacing between adjacent BSM2 layer grid lines Spacing with adjacent buried power rails The ratio; The equivalent circuit of the unit BSM1 layer grid line includes the parasitic inductance of the unit BSM1 layer grid line connected in series. Parasitic resistance of the BSM1 layer grid lines ; The series circuit specifically includes the parasitic resistance of vias connected in series. Parasitic inductance of via ; The first transverse circuit and the longitudinal circuit are connected through the series circuit.

4. The noise simulation circuit for the back-side power distribution network of the integrated circuit according to claim 3, characterized in that, The parasitic resistance of the grid lines in the unit BSM1 layer The specific calculation formula is expressed as follows: The parasitic resistance of the BSM2 layer grid lines The specific calculation formula is expressed as follows: The parasitic inductance of the BSM1 layer grid lines The specific calculation formula is expressed as follows: The parasitic inductance of the BSM2 layer grid lines of the unit The specific calculation formula is expressed as follows: The parasitic inductance of the through hole The specific calculation formula is expressed as follows: The parasitic resistance of the through hole The specific calculation formula is expressed as follows: in, Indicates the resistivity of copper; Indicates the length of the grid lines in layer BSM1; Indicates the height of the BSM1 layer grid lines; Indicates the width of the grid lines in BSM1 layer; Indicates the length of the grid lines in the BSM2 layer of the cell; Indicates the height of the BSM2 layer grid lines; Indicates the width of the BSM2 layer grid lines; The magnetic permeability of vacuum; Represents an empirical constant; Indicates the height of the through hole; This indicates the side length of the through hole.

5. The noise simulation circuit for the back-side power distribution network of the integrated circuit according to claim 1, characterized in that, The first parasitic resistance of the microsilicon via The second parasitic resistance of microsilicon vias The parasitic resistance of the microsilicon via is obtained by summing the values. ; The first parasitic inductance of the microsilicon via and the second parasitic inductance of the microsilicon via The parasitic inductance of the microsilicon via is obtained by summing the results. .

6. The noise simulation circuit for the back-side power distribution network of the integrated circuit according to claim 5, characterized in that, The parasitic resistance of the microsilicon via The specific calculation formula is expressed as follows: The parasitic inductance of the microsilicon via The specific calculation formula is expressed as follows: The parasitic capacitance of the oxide layer The specific calculation formula is expressed as follows: The parasitic capacitance of the silicon substrate The specific calculation formula is expressed as follows: Parasitic conductivity of the silicon substrate The specific calculation formula is expressed as follows: in, Indicates the resistivity of copper; Indicates the height of the microsilicon via; Indicates the radius of the microsilicon via; The magnetic permeability of vacuum; This represents the relative permittivity of the oxide layer; The dielectric constant of vacuum; Indicates the thickness of the oxide layer; This represents the relative permittivity of silicon; This indicates the distance between the microsilicon via and the surrounding microsilicon vias; This indicates the electrical conductivity of silicon.

7. The noise simulation circuit for the back-side power distribution network of the integrated circuit according to claim 1, characterized in that, The first parasitic resistance of the unit's buried power rail The second parasitic resistance of the buried power rail of the unit The parasitic resistance of the buried power rail of the unit is obtained by summing them. ; The first parasitic inductance of the unit's buried power rail and the second parasitic inductance of the buried power rail of the unit The parasitic inductance of the buried power rail of the unit is obtained by summing them. .

8. The noise simulation circuit for the back-side power distribution network of the integrated circuit according to claim 7, characterized in that, The parasitic resistance of the unit buried power rail The specific calculation formula is as follows: The parasitic inductance of the unit buried power rail The specific calculation formula is as follows: The parasitic capacitance of the oxide layer The specific calculation formula is as follows: The parasitic capacitance of the silicon substrate The specific calculation formula is as follows: Parasitic conductivity of the silicon substrate The specific calculation formula is as follows: in, This indicates the resistivity of tungsten under high-temperature processing conditions. Indicates the length of the unit's buried power rail; Indicates the height of the buried power rail; Indicates the width of the buried power rail; The magnetic permeability of vacuum; Represents an empirical constant; This represents the relative permittivity of the oxide layer; The dielectric constant of vacuum; Indicates the thickness of the oxide layer; This represents the relative permittivity of silicon; Indicates the thickness of the silicon dielectric between the buried power rails; This indicates the electrical conductivity of silicon.

Images