Static random access memory, processing circuit chip and electronic device

Abstract

The application provides a static random access memory, a processing circuit chip and an electronic device, comprising: a first pull-up tube, a second pull-up tube, a first pull-down tube, a second pull-down tube, a first gating tube and a second gating tube; the first pull-up tube and the first pull-down tube are a first complementary field effect transistor, the second pull-up tube and the second pull-down tube are a second complementary field effect transistor, the orthographic projection of the first complementary field effect transistor on a first plane, the orthographic projection of the first gating tube on the first plane, the orthographic projection of the second gating tube on the first plane and the orthographic projection of the second complementary field effect transistor on the first plane are sequentially and separately arranged along a first direction; the orthographic projection of the first complementary field effect transistor and the first gating tube on a second plane and the orthographic projection of the second complementary field effect transistor and the second gating tube on the second plane are separately arranged, a new type of structure of a memory cell is provided, and the performance of the memory cell is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to static random access memory, processing circuit chips, and electronic devices. Background Technology

[0002] Static random access memory (SRAM) is a type of storage device that allows for static access without requiring a refresh circuit. It is widely used in the design of digital and various electronic circuit products. Typically, SRAM consists of an array of memory cells. The performance of the memory cells has a decisive impact on the overall performance of the SRAM, making cell performance extremely important. Summary of the Invention

[0003] This application provides static random access memory, processing circuit chips, and electronic devices to improve performance.

[0004] In a first aspect, this application provides a static random access memory (SRAM) including a plurality of memory cells. Each memory cell includes: a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first gate transistor, and a second gate transistor disposed on a substrate. The first pull-up transistor and the first pull-down transistor serve as first complementary field-effect transistors (CFPTs), and the second pull-up transistor and the second pull-down transistor serve as second complementary field-effect transistors. The orthographic projections of the first complementary field-effect transistors on a first plane, the orthographic projections of the first gate transistors on the first plane, and the orthographic projections of the second complementary field-effect transistors on the first plane are arranged sequentially and alternately along a first direction. Furthermore, the orthographic projections of the first complementary field-effect transistors on the substrate and the orthographic projections of the first gate transistors on the substrate are aligned along a straight line along the first direction, and the orthographic projections of the second complementary field-effect transistors on the substrate and the second gate transistors on the substrate are aligned along another straight line along the first direction. The orthographic projections of the first complementary field-effect transistors on a second plane are arranged alternately.

[0005] In this embodiment, the first and second directions are parallel to the plane of the substrate and intersect each other, while the third direction is perpendicular to the plane of the substrate. The first plane is parallel to the first and third directions, and the second plane is parallel to the second and third directions. This allows the width of the region containing the memory cell along the second direction to be smaller than its length along the first direction, thus providing a novel memory cell structure. Because the width of the region containing the memory cell in the prior art along the second direction is not less than its length along the first direction, the integration density of the static random access memory (SRAM) is relatively low. The memory cell in this embodiment has a width in the second direction that is smaller than its length in the first direction. Compared to the memory cells in the prior art, this increases the integration density of the SRAM and improves its performance.

[0006] Furthermore, each memory cell is connected to a word line, a first bit line, and a second bit line. The word line extends along a first direction, while the first and second bit lines extend along a second direction and are arranged along the first direction. The word line is connected to the gates of a first select transistor and a second select transistor, respectively, to drive the first and second select transistors. The first bit line is connected to the first terminal of the first select transistor for data transmission, and the second bit line is connected to the first terminal of the second select transistor for data transmission. This enables the function of driving memory cells to transmit and store data. Furthermore, the gate of the second pull-up transistor is interconnected with the gate of the second pull-down transistor, the first terminal of the first pull-up transistor, the first terminal of the first pull-down transistor, and the second terminal of the first gate transistor. The gates of the first pull-up transistor, the first pull-down transistor, the first terminals of the second pull-up transistor, the second pull-down transistor, and the second terminal of the second gate transistor are interconnected. The first terminal of the first pull-up transistor is the source or drain, the first terminal of the first pull-down transistor is the source or drain, the second terminal of the first gate transistor is the source or drain, the first terminal of the second pull-up transistor is the source or drain, the first terminal of the second pull-down transistor is the source or drain, the second terminal of the second gate transistor is the source or drain, the first terminal of the first gate transistor is the source or drain, and the first terminal of the second gate transistor is the source or drain.

[0007] For example, the areas occupied by the first complementary field-effect transistor (CFPT), the second CFPT, the first gate transistor, and the second gate transistor in the memory cell of the prior art are the same as those occupied by the first CFPT, the second CFPT, the first gate transistor, and the second gate transistor in the memory cell of the present application embodiment. That is, the area occupied by each transistor in the memory cell of the prior art and the memory cell of the present application embodiment remains unchanged. However, the arrangement of transistors in the memory cell of the present application embodiment differs from that in the prior art. Specifically, the width of the memory cell along the second direction in the prior art is not less than its length along the first direction, while the width of the memory cell along the second direction in the present application embodiment is greater than its length along the first direction. This allows the memory cell provided in the present application embodiment to be further squeezed in the second direction, making the width of the memory cell in the second direction shorter than that in the prior art, thereby reducing the area of ​​the memory cell in the present application embodiment and thus improving the performance of the memory cell in the present application embodiment.

[0008] Furthermore, the area of ​​a storage cell in the prior art can include the area of ​​four sub-cells bs', each with an area of ​​A2*B2. Here, A2 represents the length of the sub-cell bs' in the first direction F1, and A2 can be one gate pitch. B2 represents the length of the sub-cell bs' in the second direction F2, and B2 can be four fin pitches. In contrast, the area of ​​the storage cell in this embodiment can also include the area of ​​four sub-cells bs, each with an area of ​​A1*B1. Here, A1 represents the length of the sub-cell bs in the first direction, and A1 can be one gate pitch. B1 represents the length of the sub-cell bs in the second direction, and B1 < four fin pitches. Therefore, the area of ​​each sub-cell bs is smaller than the area of ​​each sub-cell bs', resulting in a smaller area of ​​the storage cell in this embodiment compared to the prior art, thus leading to better performance of the storage cell in this embodiment.

[0009] Furthermore, in the prior art, the first and second bit lines extend along a first direction, resulting in a length of two gate pitches for each memory cell. However, in this embodiment, the first and second bit lines extend along a second direction, resulting in a length of four fin pitches for each memory cell. Since four fin pitches in this embodiment are less than two gate pitches, the transmission performance of the first and second bit lines in this embodiment is better.

[0010] For example, the first direction, the second direction, and the third direction are set perpendicular to each other.

[0011] Exemplarily, the substrate is made of materials including, but not limited to, suitable elemental semiconductors such as silicon, diamond, or germanium; suitable alloys or compound semiconductors such as group IV compound semiconductors (e.g., silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), and group III-V compound semiconductors (e.g., gallium arsenide, indium gallium arsenide, indium arsenide, indium phosphide, indium antimonide, gallium arsenide phosphide, or indium gallium phosphide). Insulating materials such as glass can also be used as substrates.

[0012] For example, the first pull-up transistor, the second pull-up transistor, the first pull-down transistor, the second pull-down transistor, the first gate transistor, and the second gate transistor can be configured as field-effect transistors (FETs). Optionally, the FETs in the memory cell can be configured as P-type field-effect transistors (PFETs) or N-type field-effect transistors (NFETs). For example, the first pull-up transistor and the second pull-up transistor are respectively configured as PFETs, and the first pull-down transistor, the second pull-down transistor, the first gate transistor, and the second gate transistor are respectively configured as NFETs.

[0013] A Complementary Field Effect Transistor (CFET) is a three-dimensional electronic device formed by vertically stacking complementary field-effect transistors. A CFET device simultaneously possesses both an NFET and a PFET in the vertical direction, and circuits built using CFETs can significantly increase circuit integration density. In this application, the first pull-up transistor is configured as a PFET, the first pull-down transistor as an NFET, and the first pull-up transistor and the first pull-down transistor serve as the first complementary field-effect transistor; that is, the first CFET includes the first pull-up transistor and the first pull-down transistor. Furthermore, the orthographic projections of the first complementary field-effect transistor onto the substrate and the orthographic projections of the first select transistor onto the substrate are aligned along a first direction, such that the orthographic projections of the first complementary field-effect transistor onto the substrate and the orthographic projections of the first select transistor onto the substrate are aligned along a straight line, thereby ensuring that the orthographic projections of the first complementary field-effect transistor onto the substrate and the orthographic projections of the first select transistor onto the substrate are collinear. For example, if the orthographic projections of the channels of the first pull-up transistor and the first pull-down transistor in the first complementary field-effect transistor onto the substrate and the orthographic projection of the channel of the first gate transistor onto the substrate are aligned along a first direction, then the orthographic projections of the channels of the first pull-up transistor and the first pull-down transistor onto the substrate and the orthographic projection of the channel of the first gate transistor onto the substrate are aligned along a straight line along the first direction, so that the orthographic projections of the channels of the first pull-up transistor and the first pull-down transistor onto the substrate and the orthographic projection of the channel of the first gate transistor onto the substrate are collinear.

[0014] In some examples, the second pull-up transistor is configured as a PFET, the second pull-down transistor as an NFET, and the second pull-up transistor and the second pull-down transistor serve as a second complementary field-effect transistor (CFET), i.e., the second CFET includes the second pull-up transistor and the second pull-down transistor. Furthermore, if the orthographic projections of the second complementary field-effect transistor and the second gate transistor onto the substrate are aligned along a first direction, then the orthographic projections of the second complementary field-effect transistor and the second gate transistor onto the substrate are aligned along another straight line along the first direction, so that the orthographic projections of the second complementary field-effect transistor and the second gate transistor onto the substrate are collinear. For example, if the orthographic projections of the channels of the second pull-up transistor and the second pull-down transistor in the second complementary field-effect transistor onto the substrate and the orthographic projection of the channel of the second gate transistor onto the substrate are aligned along a first direction, then the orthographic projections of the channels of the second pull-up transistor and the second pull-down transistor onto the substrate and the orthographic projection of the channel of the second gate transistor onto the substrate are aligned along a straight line along the first direction, so that the orthographic projections of the channels of the second pull-up transistor and the second pull-down transistor onto the substrate and the orthographic projection of the channel of the second gate transistor onto the substrate are collinear.

[0015] For example, the aforementioned sequential arrangement along the first direction can refer to the channels being arranged sequentially along the first direction. For instance, the orthographic projections of the first complementary field-effect transistor (CFPT), the first gate transistor, the second gate transistor, and the second CFPT on the first plane being arranged sequentially along the first direction can be the orthographic projections of the channels of the first CFPT, the first gate transistor, the second gate transistor, and the second CFPT on the first plane being arranged sequentially along the first direction. Alternatively, the aforementioned sequential arrangement along the first direction can also refer to the gates being arranged sequentially along the first direction.

[0016] In some possible implementations, in the first complementary field-effect transistor, the orthogonal projection of the first pull-up transistor onto the substrate overlaps with the orthogonal projection of the first pull-down transistor onto the substrate. Similarly, in the second complementary field-effect transistor, the orthogonal projection of the second pull-up transistor onto the substrate overlaps with the orthogonal projection of the second pull-down transistor onto the substrate.

[0017] For example, in the first complementary field-effect transistor, the orthogonal projection of the first pull-up transistor onto the substrate overlaps with the orthogonal projection of the first pull-down transistor onto the substrate. Alternatively, in the first complementary field-effect transistor, the orthogonal projection of the channel of the first pull-up transistor onto the substrate overlaps with the orthogonal projection of the channel of the first pull-down transistor onto the substrate.

[0018] For example, in the second complementary field-effect transistor, the orthogonal projection of the second pull-up transistor onto the substrate overlaps with the orthogonal projection of the second pull-down transistor onto the substrate. Alternatively, in the second complementary field-effect transistor, the orthogonal projection of the channel of the second pull-up transistor onto the substrate overlaps with the orthogonal projection of the channel of the second pull-down transistor onto the substrate.

[0019] It should be noted that in actual processes, due to limitations in process conditions or other factors, the aforementioned overlapping relationships may not be completely identical and may have some deviations. Therefore, as long as the aforementioned overlapping relationships roughly meet the above conditions, they are all within the scope of protection of this application. For example, the aforementioned overlapping relationships can be overlapping relationships that are permissible within the allowable error range.

[0020] In some examples, a first device layer, a second device layer, a first wiring layer, a second wiring layer, and a third wiring layer are disposed on the substrate. The first and second device layers are disposed on the substrate, the first wiring layer is disposed on the side of the first and second device layers facing away from the substrate, the second wiring layer is disposed on the side of the first wiring layer away from the substrate, and the third wiring layer is disposed on the side of the second wiring layer away from the substrate. Furthermore, an insulating layer (which may be formed by one or more dielectric material layers) is disposed between the different layers. Of course, the positional relationship of the first, second, and third wiring layers can also be other forms, and this application does not limit this.

[0021] In some possible implementations, the first device layer and the second device layer may have the gate, channel, first electrode, and second electrode of the FET described above. That is, the gate, channel, first electrode, and second electrode of the FET are formed in the first device layer or the second device layer.

[0022] In some possible implementations, the first device layer is disposed between the second device layer and the substrate, or the second device layer may be disposed between the first device layer and the substrate, without limitation.

[0023] In some possible implementations, the first pull-down transistor and the second pull-down transistor are disposed on the first device layer, and the first pull-up transistor and the second pull-up transistor are disposed on the second device layer. This makes the first pull-down transistor and the second pull-down transistor closer to the substrate than the first pull-up transistor and the second pull-up transistor. That is, the channel of the first pull-down transistor is disposed between the channel of the first pull-up transistor and the substrate, and the channel of the second pull-down transistor is disposed between the channel of the second pull-up transistor and the substrate.

[0024] In some possible implementations, the first gate and the second gate can be disposed on the first device layer.

[0025] In some possible implementations, when the first selector and the second selector are disposed on the first device layer, the second electrode of the first selector and the first electrode of the first pull-down transistor are integrally formed, that is, the second electrode of the first selector and the first electrode of the first pull-down transistor are in contact with each other to form an integral structure. Similarly, the second electrode of the second selector and the first electrode of the second pull-down transistor are integrally formed, that is, the second electrode of the second selector and the first electrode of the second pull-down transistor are in contact with each other to form an integral structure. Furthermore, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, the second electrode of the first selector, the first electrode of the first pull-down transistor, the second electrode of the second selector, and the first electrode of the second pull-down transistor are both sources or drains.

[0026] In some possible implementations, the first and second gate transistors may also be disposed on the second device layer.

[0027] In some possible implementations, when the first selector and the second selector are disposed on the second device layer, the second electrode of the first selector and the first electrode of the first pull-up transistor are integrally formed, that is, the second electrode of the first selector and the first electrode of the first pull-up transistor are in contact with each other to form an integral structure. Similarly, the second electrode of the second selector and the first electrode of the second pull-up transistor are integrally formed, that is, the second electrode of the second selector and the first electrode of the second pull-up transistor are in contact with each other to form an integral structure. Furthermore, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, the second electrode of the first selector, the first electrode of the first pull-up transistor, the second electrode of the second selector, and the first electrode of the second pull-up transistor are all either the source or the drain.

[0028] In some possible implementations, the first select transistor and the second select transistor can each be configured as one, with the gate of the first select transistor surrounding its channel through a gate dielectric layer, and the gate of the second select transistor surrounding its channel through a gate dielectric layer. This allows the first select transistor and the second select transistor to form a gate all-around (GAA) FET.

[0029] In some possible implementations, the first selector and the second selector can be configured as two parallel-connected transistors. The first selector includes a first sub-selector and a second sub-selector. The first and second sub-selectors are stacked in a third-order layer, with the first sub-selector disposed on a first device layer and the second sub-selector disposed on a second device layer. The first terminal of the first sub-selector is connected to the first terminal of the second sub-selector, serving as the first terminal of the first selector, and the second terminal of the first sub-selector is connected to the second terminal of the second sub-selector, serving as the second terminal of the first selector. Furthermore, the first terminal can be either the source or the drain, and the second terminal can be either the source or the drain. For example, the first terminal of the first sub-selector is either the source or the drain, and the first terminal of the second sub-selector is either the source or the drain; the first terminal of the first selector is either the source or the drain, and the second terminal of the first sub-selector is either the source or the drain; the second terminal of the second sub-selector is either the source or the drain, and the second terminal of the first selector is either the source or the drain.

[0030] In some possible implementations, the third and fourth sub-gated transistors are stacked in a third-level upward configuration. The third sub-gated transistor is disposed on the first device layer, and the fourth sub-gated transistor is disposed on the second device layer. The first terminal of the third sub-gated transistor is connected to the first terminal of the fourth sub-gated transistor, serving as the first terminal of the second selected transistor. The second terminal of the third sub-gated transistor is connected to the second terminal of the fourth sub-gated transistor, serving as the second terminal of the second selected transistor. Furthermore, the first terminal and the second terminal can both be source or drain. For example, the first terminal of the third sub-gated transistor, the first terminal of the fourth sub-gated transistor, the first terminal of the second selected transistor, the second terminal of the third sub-gated transistor, the second terminal of the fourth sub-gated transistor, and the second terminal of the second selected transistor can all be source or drain.

[0031] Optionally, the second electrode of the first sub-gated transistor and the first electrode of the first pull-down transistor are integrally formed. That is, the second electrode of the first sub-gated transistor and the first electrode of the first pull-down transistor are in contact with each other to form an integral structure. Furthermore, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, the first electrode of the first pull-down transistor can be either the source or the drain.

[0032] Optionally, the second electrode of the second sub-selector and the first electrode of the first pull-up diode are integrally formed. That is, the second electrode of the second sub-selector and the first electrode of the first pull-up diode are in contact with each other to form an integral structure. Furthermore, the first electrode can be either the source or the drain, and the second electrode can also be either the source or the drain. For example, the first electrode of the first pull-up diode can be either the source or the drain.

[0033] Optionally, the second electrode of the third sub-gated transistor and the first electrode of the second pull-down transistor are integrally formed. That is, the second electrode of the third sub-gated transistor and the first electrode of the second pull-down transistor are in contact with each other to form an integral structure. Furthermore, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, the first electrode of the second pull-down transistor can be either the source or the drain.

[0034] Optionally, the second electrode of the fourth sub-selector and the first electrode of the second pull-up diode are integrally formed. That is, the second electrode of the fourth sub-selector and the first electrode of the second pull-up diode are in contact with each other to form an integral structure. Furthermore, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, the first electrode of the second pull-up diode can be either the source or the drain.

[0035] In some possible implementations, the gate of the first sub-gated transistor is disposed around the channel of the first sub-gated transistor through a gate dielectric layer, and the gate of the second sub-gated transistor is disposed around the channel of the second sub-gated transistor through a gate dielectric layer. The orthographic projection of the gate of the first sub-gated transistor on the substrate overlaps with the orthographic projection of the gate of the second sub-gated transistor on the substrate, and the gates of the first and second sub-gated transistors are integral structures, in which case the first and second sub-gated transistors share the same gate.

[0036] Furthermore, the gate of the third sub-selector is disposed around the channel of the third sub-selector through a gate dielectric layer, and the gate of the fourth sub-selector is disposed around the channel of the fourth sub-selector through a gate dielectric layer. The orthogonal projection of the gate of the third sub-selector on the substrate overlaps with the orthogonal projection of the gate of the fourth sub-selector on the substrate. Since the gates of the third and fourth sub-selectors are of an integral structure, the third and fourth sub-selectors share the same gate.

[0037] In some possible implementations, the orthographic projection of the gate of the first pull-up transistor onto the substrate overlaps with the orthographic projection of the gate of the first pull-down transistor onto the substrate, and the gates of the first pull-up transistor and the first pull-down transistor are integral structures, in which case the first pull-up transistor and the first pull-down transistor share the same gate.

[0038] Furthermore, the orthogonal projection of the gate of the second pull-up transistor onto the substrate overlaps with the orthogonal projection of the gate of the second pull-down transistor onto the substrate, and the gates of the second pull-up transistor and the second pull-down transistor are an integral structure, thus the second pull-up transistor and the second pull-down transistor share the same gate.

[0039] In some possible implementations, the gate of the first pull-up transistor is connected to the first terminal of the second pull-up transistor, the first terminal of the second pull-down transistor, and the second terminal of the second gate transistor via a second memory interconnect portion to form a second memory node. Furthermore, the gate of the second pull-up transistor is connected to the first terminal of the first pull-up transistor, the first terminal of the first pull-down transistor, and the second terminal of the first gate transistor via a first memory interconnect portion to form a first memory node. Exemplarily, the second memory interconnect portion and the first memory interconnect portion are spaced apart on a first wiring layer, which is disposed above the first device layer and the second device layer. Furthermore, the first terminal can be a source or a drain, and the second terminal can be a source or a drain. For example, the first terminal of the second pull-up transistor, the first terminal of the second pull-down transistor, the second terminal of the second gate transistor, the first terminal of the first pull-up transistor, the first terminal of the first pull-down transistor, and the second terminal of the first gate transistor are all source or drain.

[0040] In some possible implementations, the first bit line and the second bit line are disposed on the second wiring layer. Furthermore, the orthographic projections of the first bit line and the second bit line onto the substrate overlap with the orthographic projections of the memory cell onto the substrate. For example, the orthographic projections of the first bit line and the second bit line onto the substrate partially overlap with the orthographic projections of the memory cell onto the substrate. Optionally, the orthographic projections of the first bit line and the second bit line onto the substrate partially overlap with the orthographic projections of the FET structure in the memory cell onto the substrate.

[0041] In some possible implementations, word lines are connected to the gates of the first and second select transistors respectively via word line interconnects. Furthermore, the word line interconnects are disposed on a first wiring layer, which is located above the first and second device layers. This achieves the effect of connecting the word lines to the gates of the first and second select transistors respectively.

[0042] In some possible implementations, the substrate has a first trench, and the word lines are disposed within the first trench. This method of embedding the word lines within the substrate, achieving a buried word line configuration, can reduce signal interference between word lines and improve the performance of the memory cells. Optionally, the word lines can be directly disposed within the first trench, or they can be disposed within the first trench through a word line dielectric layer; this application does not limit this.

[0043] Alternatively, the word lines can be set in the first wiring layer.

[0044] In some possible implementations, the orthographic projection of the word line onto the substrate is located between the orthographic projection of the channel of the first select transistor onto the substrate and the orthographic projection of the channel of the second select transistor onto the substrate. Optionally, the channels of the first select transistor and the second select transistor in the memory cell are located on opposite sides of the connected word line.

[0045] In some possible implementations, the memory cell is also connected to a first voltage power line and a second voltage power line spaced apart from each other. Exemplarily, the first voltage power line is connected to the second terminals of a first pull-up transistor and a second pull-up transistor to transmit a first power supply voltage to the first and second pull-up transistors via the first voltage power line. Similarly, the second voltage power line is connected to the second terminals of a first pull-down transistor and a second pull-down transistor to transmit a second power supply voltage to the first and second pull-down transistors via the second voltage power line. Furthermore, the first terminal can be either a source or a drain, and the second terminal can be either a source or a drain. For example, the second terminal of the first pull-up transistor is either a source or a drain, the second terminal of the second pull-up transistor is either a source or a drain, the second terminal of the first pull-down transistor is either a source or a drain, and the second terminal of the second pull-down transistor is either a source or a drain.

[0046] For example, the first voltage power line and the second voltage power line can be disposed on the third wiring layer.

[0047] Alternatively, the first voltage power line and the second voltage power line can be embedded in the substrate. For example, the substrate has a second trench and a third trench that are spaced apart from each other, with the first voltage power line disposed in the second trench and the second voltage power line disposed in the third trench.

[0048] Alternatively, the first voltage power line can be placed on the third wiring layer, and the second voltage power line can be placed in the substrate using a buried wire method, for example, the second voltage power line can be placed in the third trench.

[0049] Alternatively, the second voltage power line can be placed on the third wiring layer, and the first voltage power line can be placed in the substrate using a buried wire method, for example, the first voltage power line can be placed in the second trench.

[0050] In some possible implementations, multiple memory cells are arranged along a second direction as multiple memory cell rows and along a first direction as multiple memory cell columns. Each memory cell column corresponds one-to-one with a first bit line and a second bit line, and each memory cell row corresponds one-to-one with a word line. This allows the memory cells in the static random access memory to form an array.

[0051] In some possible implementations, two adjacent storage cells arranged along the second direction are translationally or rotationally symmetrical.

[0052] In some possible implementations, two adjacent storage cells arranged along the second direction are rotationally symmetrical.

[0053] In some possible implementations, two adjacent rows of storage cells arranged along a first direction are mirror-symmetrical.

[0054] In some possible implementations, two adjacent memory cells in the same memory cell column may share the first bit interconnect.

[0055] In some possible implementations, two adjacent memory cells in the same memory cell column may share a second bit line interconnect.

[0056] Secondly, this application also provides a processing circuit chip, which includes any of the static random access memory (SRAM) described in the first aspect above and one or more processing circuits. The SRAM is used to store data required for the operation of one or more processing circuits.

[0057] Since any of the above-mentioned static random access memories (SRAMs) have good performance, applying them to processing circuit chips can also improve the performance of the processing circuit chips.

[0058] Thirdly, this application also provides an electronic device, which includes a power supply and the processing circuit chip described in the second aspect above, wherein the power supply powers the processing circuit chip. This electronic device can be any electrical device. For example, it can be a smartphone, smart TV, laptop computer, PDA, wearable device with wireless communication capabilities (such as a smartwatch, smart glasses, or smart bracelet), automotive microcontroller unit (MCU), on-board battery charger (OBC), etc. It should be noted that this application does not limit the specific type of electronic device. Attached Figure Description

[0059] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0060] Figure 2 A schematic diagram of the circuit structure of a storage cell of a static random access memory provided in an embodiment of this application;

[0061] Figure 3 A top view of a storage unit provided in one embodiment of this application;

[0062] Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure along the tangent direction of AA'.

[0063] Figure 5 for Figure 3 Some three-dimensional structural diagrams of the storage units in the diagram;

[0064] Figure 6a for Figure 3 Other three-dimensional structural diagrams of the storage units in the diagram;

[0065] Figure 6b for Figure 6a A simplified cross-sectional view of the storage cells along the BB' tangent direction;

[0066] Figure 7 for Figure 3 Some three-dimensional structural diagrams of the storage units in the image;

[0067] Figure 8 for Figure 3 Some three-dimensional structural diagrams of the storage units in the image;

[0068] Figure 9a A schematic diagram of a storage unit provided in the prior art;

[0069] Figure 9b A schematic diagram of a storage unit provided in an embodiment of this application;

[0070] Figure 10a A top view of the storage unit provided in another embodiment of this application;

[0071] Figure 10b for Figure 10a A schematic diagram of the cross-sectional structure along the tangent direction of AA'.

[0072] Figure 11 for Figure 10a Some three-dimensional structural diagrams of the storage units in the diagram;

[0073] Figure 12 A top view of the storage unit provided in another embodiment of this application;

[0074] Figure 13 This is a top view of a static random access memory provided in one embodiment of this application.

[0075] Figure 14 A top view of the static random access memory provided in another embodiment of this application;

[0076] Figure 15 This is a top view of a static random access memory provided in another embodiment of this application. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "at least one" refers to one or more, where "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, it should be understood that in the description of this application, words such as "first" and "second" are only used for distinguishing the purpose of description and should not be construed as indicating or implying relative importance or order.

[0078] It should be noted that in the embodiments of this application, "connection" refers to electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components, such as the connection between A and B. Alternatively, it can be a direct connection between A and C, a direct connection between C and B, with A and B connected through C.

[0079] Furthermore, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them are omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0080] It should be noted that specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below. The following description is a preferred embodiment for carrying out this application; however, the description is for the purpose of illustrating the general principles of this application and is not intended to limit the scope of this application.

[0081] To facilitate understanding of the static random access memory, processing circuit chip, and electronic device provided in the embodiments of this application, their application scenarios will be introduced first below.

[0082] Figure 1 An exemplary schematic diagram of an electronic device is shown, which can be any electrical device. Examples include smartphones, smart TVs, laptops, personal digital assistants (PDAs), wearable devices with wireless communication capabilities (such as smartwatches, smart glasses, and smart bracelets), in-vehicle microcontroller units (MCUs), and on-board battery chargers (OBCs). It should be noted that this application does not limit the specific type of electronic device.

[0083] Reference Figure 1The electronic device 01 may include a power supply 011 and a processing circuit chip 012. The power supply 011 supplies power to the components in the processing circuit chip 012. This application does not limit the power supply 011 and the processing circuit chip 012; the power supply 011 can be any device or component capable of outputting direct current, for example, a battery (e.g., a storage battery). The processing circuit chip 012 may be a central processing unit (CPU), a system-on-chip (SOC), an electronic control unit (ECU), etc.

[0084] Reference Figure 1 The processing circuit chip 012 may include a processing circuit 0121 and a static random access memory (SRAM) 0122. The SRAM 0122 mainly includes multiple storage cells 02, which form an N×M storage array, where M and N are both integers greater than or equal to 1. For example, the multiple storage cells 02 are arranged along a second direction F2 as multiple storage cell rows (e.g., row 1 to row N), and the multiple storage cells 02 are arranged along a first direction F1 as multiple storage cell columns (e.g., column 1 to column M).

[0085] The number of processing circuits in this application is one or more, for example, one, two, three, four or more. Figure 1 This is just an example of a processing circuit. In actual applications, the specific number of processing circuits can be determined according to the needs of the actual application, and is not limited here.

[0086] Reference Figure 1 The static random access memory 0122 also includes multiple word lines WL, multiple first bit lines BL, and multiple second bit lines BLB. The multiple word lines WL extend along a first direction F1 and are arranged along a second direction F2. The multiple first bit lines BL and multiple second bit lines BL extend along the second direction F2, and the multiple first bit lines BL and multiple second bit lines BLB are alternately arranged along the first direction F1 (i.e., a first bit line is positioned between two adjacent second bit lines). Multiple rows of memory cells correspond one-to-one with the multiple word lines, and each row of memory cells is connected to its corresponding word line to drive the memory cells via the word lines. Furthermore, multiple columns of memory cells correspond one-to-one with the multiple first bit lines BL and multiple second bit lines BLB, and each column of memory cells is connected to its corresponding first bit line BL and second bit line BLB to transmit data via the first bit line BL and the second bit line BLB.

[0087] Reference Figure 1The static random access memory 0122 further includes: a row decoding circuit 1021, word line circuits 1 to N, a read / write drive circuit 1022, and a column decoding circuit 1023. The input terminals of word line circuits 1 to N are connected to the output terminals of the row decoding circuit 1021, and the output terminals of word line circuits 1 to N are connected one-to-one with the word lines connecting the N memory cell rows. For example, word line circuit 1 is connected to the word line connecting the memory cell row (e.g., row 1), word line circuit 2 is connected to the word line connecting the memory cell row (e.g., row 2), and so on, with word line circuit N-1 connected to the word line connecting the memory cell row (e.g., row N-1), and word line circuit N connected to the word line connecting the memory cell row (e.g., row N). Furthermore, the read / write drive circuit 1022 is connected to the column decoding circuit 1023, as well as each first bit line and each second bit line.

[0088] During operation, the processing circuit 0121 can read and write data in the static random access memory 0122. Specifically, the processing circuit 0121 can send address information to the static random access memory 0122, which indicates the storage address of the target data in the static random access memory 0122. For example, the address information sent by the processing circuit 0121 includes row address information and column address information. The static random access memory 0122 is connected to the processing circuit 0121 and can receive the address information output by the processing circuit 0121. In the static random access memory 0122, the row decoding circuit 1021 is a row decoder that can decode the row address information to determine the target storage cell row where the target data is located, and the target word line circuit corresponding to that target storage cell row. In the example above, the row decoding circuit 1021 can determine that the target storage cell row is the second row of storage cells (i.e., the storage cell row corresponding to row 2), and the target word line circuit is word line circuit 2.

[0089] The row decoding circuit 1021 can then send decoding selection signals to word line circuits 1 to N respectively. Among them, the decoding selection signal sent to the target word line circuit can instruct the target word line circuit to operate, and the decoding selection signal sent to other word line circuits can instruct the other word line circuits to wait.

[0090] In the example above, if word line circuit 2 is the target word line circuit, then the decoding selection signal sent to word line circuit 2 can instruct word line circuit 2 to work, and the decoding selection signals sent to word line circuit 1 and word line circuit 3 to word line circuit N can instruct the word line circuit to wait.

[0091] In one possible example, the decode select signal can indicate whether a word line circuit is active or waiting through different level states. For example, a high level decode select signal can indicate that the word line circuit receiving the decode select signal is active, while a low level decode select signal can indicate that the word line circuit receiving the signal is waiting.

[0092] In yet another possible example, the decode select signal can also carry select information, and the word line circuit can determine whether to proceed or wait by parsing the select information carried by the decode select signal.

[0093] Word line circuits can operate or wait based on the decoder selection signal. They can output word line signals to connected word lines, which can enable or disable the corresponding memory row. Generally, word line signals enable or disable memory rows through different level states. For example, a high level word line signal enables a memory row, and a low level word line signal disables it. When the decoder selection signal indicates that the word line circuit is operating, the output word line signal can be high, thus enabling the corresponding memory row. When the decoder selection signal indicates that the word line circuit is waiting, it can remain low, thus disabling the corresponding memory row.

[0094] The column decoding circuit 1023 decodes the column address information to determine the target memory cell column where the target data is located. It then sends an instruction to the read / write driver circuit 1022, instructing it to read or write the data in the target memory cell column. At this time, the read / write driver circuit 1022 can only read or write the data in the target memory cell column when the target memory cell row is open.

[0095] Figure 2 An exemplary circuit diagram of a storage cell in a static random access memory (SRAM) is shown. (Refer to...) Figure 2The memory cell can be configured as a 6T Cell, which includes: a first pull-up transistor T1, a second pull-up transistor T2, a first pull-down transistor T3, a second pull-down transistor T4, a first gate transistor T5, and a second gate transistor T6. The second terminals of the first pull-up transistor T1 and the second pull-up transistor T2 receive a first power supply voltage VDD. The first terminal of the first pull-up transistor T1 is connected to the first terminal of the first pull-down transistor T3, and the first terminal of the second pull-up transistor T2 is connected to the first terminal of the second pull-down transistor T4. The second terminals of the first pull-down transistor T3 and the second pull-down transistor T4 receive a second power supply voltage VSS. The gate of the second pull-up transistor T2 is interconnected with the gate of the second pull-down transistor T4, the first terminal of the first pull-up transistor T1, the first terminal of the first pull-down transistor T3, and the second terminal of the first gate transistor T5, forming a first memory node Q. The gates of the first pull-up transistor T1, the first pull-down transistor T3, the first terminal of the second pull-up transistor T2, the first terminal of the second pull-down transistor T4, and the second terminal of the second selector transistor T6 are interconnected to form the second memory node QB. The gates of the first selector transistor T5 and the second selector transistor T6 are connected to the same word line, driving the conduction and cutoff of the first selector transistor T5 and the second selector transistor T6 through the word line. The first terminal of the first selector transistor T5 is connected to the first bit line BL, transmitting data through the first bit line BL. The first terminal of the second selector transistor T6 is connected to the second bit line BLB, transmitting data through the second bit line BLB. Furthermore, the first pull-up transistor T1 and the first pull-down transistor T3 act as the first inverter, and the second pull-up transistor T2 and the second pull-down transistor T4 act as the second inverter. The output terminal of the first inverter is electrically connected to the input terminal of the second inverter, forming the first memory node Q. The output terminal of the second inverter is connected to the input terminal of the first inverter, forming the second memory node QB. Because the first inverter and the second inverter are cross-coupled, they function as a latching circuit, meaning that when one storage node is pulled down to a low potential, the other storage node is pulled up to a high potential.

[0096] For example, when the memory cell is working, when the word line signal transmitted on the word line is at a high level, the word line signal can control the first selector T5 and the second selector T6 to be turned on, so that the data in the memory cell can be read and written through the first bit line and the second bit line.

[0097] For example, the first pull-up transistor T1, the second pull-up transistor T2, the first pull-down transistor T3, the second pull-down transistor T4, the first gate transistor T5, and the second gate transistor T6 can be configured as field-effect transistors (FETs). Optionally, the FETs in the memory cell can be configured as P-type field-effect transistors (PFETs) or N-type field-effect transistors (NFETs). For example, the first pull-up transistor T1 and the second pull-up transistor T2 are respectively configured as PFETs, and the first pull-down transistor T3, the second pull-down transistor T4, the first gate transistor T5, and the second gate transistor T6 are respectively configured as NFETs. The following explanation uses the example of the first pull-up transistor T1 and the second pull-up transistor T2 being configured as PFETs, and the first pull-down transistor T3, the second pull-down transistor T4, the first gate transistor T5, and the second gate transistor T6 being configured as NFETs.

[0098] Furthermore, for ease of description, the first terminal of each FET in this application can refer to the drain, and the second terminal can refer to the source. Alternatively, the first terminal can refer to the source, and the second terminal of the transistor can refer to the drain. For example, the first terminal of the first pull-up transistor T1 is the source or drain, the first terminal of the second pull-up transistor T2 is the source or drain, the first terminal of the first pull-down transistor T3 is the source or drain, the first terminal of the second pull-down transistor T4 is the source or drain, the first terminal of the first select transistor T5 is the source or drain, and the first terminal of the second select transistor T6 is the source or drain. The second terminal of the first pull-up transistor T1 is the source or drain, the second terminal of the second pull-up transistor T2 is the source or drain, the first terminal of the first pull-down transistor T3 is the source or drain, the second terminal of the second pull-down transistor T4 is the source or drain, the second terminal of the first select transistor T5 is the source or drain, and the second terminal of the second select transistor T6 is the source or drain.

[0099] Figure 3 An exemplary top view of a storage cell provided in one embodiment of this application is shown. Figure 4 An example is shown Figure 3 A schematic diagram of the cross-sectional structure along the tangent direction of AA'. Figure 5 An example is shown Figure 3 Some 3D structural diagrams of the storage units in the diagram. Figure 6a An example is shown Figure 3 Other three-dimensional structural diagrams of the storage cells in the diagram, Figure 6b An example is shown Figure 6a The diagram shows some simplified cross-sectional views of the storage cells along the BB' tangent direction. Figure 7 An example is shown Figure 3 Some more 3D structural diagrams of the storage units in the image. Figure 8An example is shown Figure 3 Here are some more 3D structural diagrams of the storage units in the image. Among them, Figure 4 The first and second bit lines are not shown in the text. Figure 6a , Figure 7 as well as Figure 8 The text line dielectric layer is not shown in the text.

[0100] Exemplarily, in this application, reference is made to Figures 3 to 8 The first pull-up transistor T1, the second pull-up transistor T2, the first pull-down transistor T3, the second pull-down transistor T4, the first gate transistor T5, and the second gate transistor T6 in the memory cell 02 are disposed on the substrate 10. Furthermore, the first direction F1 and the second direction F2 are parallel to the plane of the substrate 10 and intersect each other. For example, the first direction F1 and the second direction F2 are perpendicular.

[0101] Exemplarily, in this application, reference is made to Figure 3 The orthographic projections of the first pull-up transistor T1, the second pull-up transistor T2, the first pull-down transistor T3, the second pull-down transistor T4, the first gate transistor T5, and the second gate transistor T6 on the substrate 10 are all disposed within the boundary BS of the memory cell 02. That is, the boundary BS of the memory cell 02 surrounds the orthographic projections of the first pull-up transistor T1, the second pull-up transistor T2, the first pull-down transistor T3, the second pull-down transistor T4, the first gate transistor T5, and the second gate transistor T6 on the substrate 10.

[0102] In some possible examples, the substrate 10 is made of materials including, but not limited to, suitable elemental semiconductors such as silicon, diamond, or germanium; suitable alloys or compound semiconductors such as group IV compound semiconductors (e.g., silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), and group III-V compound semiconductors (e.g., gallium arsenide, indium gallium arsenide, indium arsenide, indium phosphide, indium antimonide, gallium arsenide phosphide, or indium gallium phosphide). Insulating materials such as glass can also be used as the substrate.

[0103] A Complementary Field Effect Transistor (CFET) is a three-dimensional electronic device formed by vertically stacking complementary field-effect transistors. A CFET device simultaneously possesses both NFET and PFET properties in the vertical direction. Using CFETs to build circuits can significantly increase circuit integration density. In some examples, continue to refer to... Figures 3 to 8The first pull-up transistor T1 is configured as a PFET, and the first pull-down transistor T3 is configured as an NFET. The first pull-up transistor T1 and the first pull-down transistor T3 serve as the first complementary field-effect transistor C1, meaning the first CFET C1 includes the first pull-up transistor T1 and the first pull-down transistor T3. Furthermore, the orthographic projections of the first complementary field-effect transistor C1 onto the substrate 10 and the first gate transistor T5 onto the substrate 10 are aligned along a first direction F1, such that the orthographic projections of the first complementary field-effect transistor C1 onto the substrate 10 and the first gate transistor T5 onto the substrate 10 are aligned along the first direction F1 in a straight line, so that the orthographic projections of the first complementary field-effect transistor C1 onto the substrate 10 and the first gate transistor T5 onto the substrate 10 are collinear. For example, if the orthographic projection of the channel of the first pull-up transistor T1 (or the first pull-down transistor T3) onto the substrate 10 and the orthographic projection of the channel of the first gate transistor T5 onto the substrate 10 are aligned along the first direction F1, then the orthographic projection of the channel of the first pull-up transistor T1 (or the first pull-down transistor T3) onto the substrate 10 and the orthographic projection of the channel of the first gate transistor T5 onto the substrate 10 are aligned along the first direction F1 in a straight line, so that the orthographic projection of the channel of the first pull-up transistor T1 (or the first pull-down transistor T3) onto the substrate 10 and the orthographic projection of the channel of the first gate transistor T5 onto the substrate 10 are collinear.

[0104] In some examples, continue to refer to Figures 3 to 8 The second pull-up transistor T2 is configured as a PFET, and the second pull-down transistor T4 is configured as an NFET. The second pull-up transistor T2 and the second pull-down transistor T4 also serve as the second complementary field-effect transistor C2, meaning the second CFET C2 includes the second pull-up transistor T2 and the second pull-down transistor T4. Furthermore, if the orthogonal projections of the second complementary field-effect transistor C2 and the second selector transistor T6 onto the substrate 10 are aligned along a first direction F1, then the orthogonal projections of the second complementary field-effect transistor C2 and the second selector transistor T6 onto the substrate 10 are aligned along another straight line, so that the orthogonal projections of the second complementary field-effect transistor C2 and the second selector transistor T6 onto the substrate 10 are collinear. For example, if the orthographic projection of the channel of the second pull-up transistor T2 (or the second pull-down transistor T4) onto the substrate 10 and the orthographic projection of the channel of the second gate transistor T6 onto the substrate 10 are aligned along the first direction F1, then the orthographic projection of the channel of the second pull-up transistor T2 (or the second pull-down transistor T4) onto the substrate 10 and the orthographic projection of the channel of the second gate transistor T6 onto the substrate 10 are aligned along the first direction F1 in a straight line, so that the orthographic projection of the channel of the second pull-up transistor T2 (or the second pull-down transistor T4) onto the substrate 10 and the orthographic projection of the channel of the second gate transistor T6 onto the substrate 10 are collinear.

[0105] In some examples, continue to refer to Figures 3 to 8The orthographic projections of the first complementary field-effect transistor C1 and the second complementary field-effect transistor C2 on the second plane are arranged alternately. That is, the orthographic projections of the first complementary field-effect transistor C1 on the substrate 10 and the orthographic projections of the first gate transistor T5 on the substrate 10 are aligned along the first direction F1 on a straight line, while the orthographic projections of the second complementary field-effect transistor C2 on the substrate 10 and the orthographic projections of the second gate transistor T6 on the substrate 10 are not collinear on the same straight line. Optionally, the orthographic projections of the first complementary field-effect transistor C1 and the first gate transistor T5 on the substrate 10 are aligned along the first direction F1 on a straight line, and the orthographic projections of the second complementary field-effect transistor C2 and the second gate transistor T6 on the substrate 10 are arranged parallel to the same straight line. For example, the channel of the first pull-up transistor T1 (or the first pull-down transistor T3) is arranged in a straight line along the first direction F1 with the orthogonal projection of the channel of the first gate transistor T5 on the substrate 10, and is arranged parallel to the straight line along the first direction F1 with the orthogonal projection of the channel of the second pull-up transistor T2 (or the second pull-down transistor T4) on the substrate 10 with the orthogonal projection of the channel of the second gate transistor T6 on the substrate 10.

[0106] Continue to refer to Figures 3 to 8 The orthographic projections of the first complementary field-effect transistor C1, the first gate transistor T5, the second gate transistor T6, and the second complementary field-effect transistor C2 on the first plane are arranged sequentially at intervals on the first plane.

[0107] For example, the aforementioned sequential arrangement along the first direction can refer to the channels being arranged sequentially along the first direction. For instance, the orthographic projections of the first complementary field-effect transistor (CFPT), the first gate transistor, the second gate transistor, and the second CFPT on the first plane being arranged sequentially along the first direction can be the orthographic projections of the channels of the first CFPT, the first gate transistor, the second gate transistor, and the second CFPT on the first plane being arranged sequentially along the first direction. Alternatively, the aforementioned sequential arrangement along the first direction can also refer to the gates being arranged sequentially along the first direction. For example, the orthographic projections of the first complementary field-effect transistor (CFPT) on the first plane, the orthographic projections of the first gate transistor (GMT) on the first plane, the orthographic projections of the second gate transistor (GMT) on the first plane, and the orthographic projections of the second CFPT on the first plane are arranged sequentially and alternately along the first direction. This can be achieved by arranging the orthographic projections of the gates of the first CFPT, the first gate transistor (GMT), the second gate transistor (GMT), and the second CFPT (GMT) on the first plane in a sequential order along the first direction.

[0108] In this application, the first plane is parallel to the first direction and the third direction, the second plane is parallel to the second direction and the third direction, the first direction and the second direction are parallel to the plane containing the substrate and intersect each other, and the third direction is perpendicular to the plane containing the substrate. For example, the first direction, the second direction, and the third direction are perpendicular to each other.

[0109] In this embodiment, by setting a first complementary field-effect transistor C1 and a second complementary field-effect transistor C2, and arranging the orthographic projections of the first complementary field-effect transistor C1, the first selector transistor T5, the second selector transistor T6, and the second complementary field-effect transistor C2 on the first plane sequentially and alternately along a first direction, and arranging the orthographic projections of the first complementary field-effect transistor C1 and the first selector transistor T5 on the substrate 10 along the first direction F1, and the orthographic projections of the second complementary field-effect transistor C2 and the second selector transistor T6 on the substrate 10 along the first direction F1, and arranging the orthographic projections of the first complementary field-effect transistor C1 and the second complementary field-effect transistor C2 on the second plane alternately, the width of the region where the memory cell is located along the second direction F2 is less than the length along the first direction F1, thereby providing a novel memory cell structure. Because the width of the region where the memory cell is located along the second direction in the prior art is not less than the length along the first direction, the integration density of the static random access memory (SRAM) it is applied to is relatively low. In this embodiment, the width of the storage cell in the second direction is smaller than its length in the first direction. Compared with the storage cells in the prior art, when applied to static random access memory, the integration density of static random access memory can be increased and the performance of static random access memory can be improved.

[0110] Figure 9a This is a schematic diagram of a storage unit provided in the prior art. Figure 9b A schematic diagram of a storage unit provided in an embodiment of this application, referring to... Figure 9a and Figure 9b02' represents a memory cell in the prior art, and 02 represents a memory cell in the embodiment of this application. Memory cell 02' also has a first complementary field-effect transistor C1, a second complementary field-effect transistor C2, a first gate transistor T5, and a second gate transistor T6. Furthermore, the areas occupied by the first complementary field-effect transistor C1, the second complementary field-effect transistor C2, the first gate transistor T5, and the second gate transistor T6 in memory cell 02' are the same as the areas occupied by the first complementary field-effect transistor C1, the second complementary field-effect transistor C2, the first gate transistor T5, and the second gate transistor T6 in memory cell 02, that is, the areas occupied by each FET in memory cell 02 and memory cell 02' are unchanged. In this embodiment, the arrangement of the FETs in the memory cell 02 is different from that in the memory cell 02'. Specifically, in the prior art, the width of the memory cell 02' along the second direction F2 is not less than its length along the first direction F1. However, in this embodiment, the width of the memory cell 02 along the second direction F2 is greater than its length along the first direction F1. This allows the memory cell provided in this embodiment to be further squeezed along the second direction F2, making its width along the second direction F2 shorter than that in the prior art. This results in a smaller area for the memory cell in this embodiment, and consequently, better performance for the memory cell 02 in this embodiment.

[0111] Furthermore, continue to refer to Figure 9a and Figure 9b The area of ​​storage unit 02' can include the area of ​​four sub-units bs', each sub-unit bs' having an area of ​​A2*B2, where A2 represents the length of sub-unit bs' in the first direction F1, and A2 can be one gate pitch. B2 represents the length of sub-unit bs' in the second direction F2, and B2 can be four fin pitches. Alternatively, the area of ​​storage unit 02 can also include the area of ​​four sub-units bs, each sub-unit bs having an area of ​​A1*B1, where A1 represents the length of sub-unit bs in the first direction F1, and A1 can be one gate pitch. B1 represents the length of sub-unit bs in the second direction F2, and B1 < four fin pitches. Therefore, the area of ​​each sub-unit bs is smaller than the area of ​​each sub-unit bs', resulting in a smaller area of ​​storage unit 02 than storage unit 02', thus improving the performance of storage unit 02 in this embodiment.

[0112] And, continue to refer to Figure 9a and Figure 9bIn the prior art, the first bit line BL and the second bit line BLB extend along the first direction F1, and the length of the first bit line BL and the second bit line BLB corresponding to one memory cell is two gate pitches. However, in the embodiment of this application, the first bit line BL and the second bit line BLB extend along the second direction F2, and the length of the first bit line BL and the second bit line BLB corresponding to one memory cell in this embodiment is four fin pitches. Since four fin pitches in this embodiment are less than two gate pitches, the transmission performance of the first bit line BL and the second bit line BLB in this embodiment is better.

[0113] Continue to refer to Figures 3 to 8 In the first complementary field-effect transistor C1, the orthogonal projection of the first pull-up transistor T1 onto the substrate 10 overlaps with the orthogonal projection of the first pull-down transistor T3 onto the substrate 10. Exemplarily, in the first complementary field-effect transistor C1, the channels of the first pull-up transistor T1 and the first pull-down transistor T3 are spaced apart on a third direction F3, and the orthogonal projection of the channel of the first pull-up transistor T1 onto the substrate 10 overlaps with the orthogonal projection of the channel of the first pull-down transistor T3 onto the substrate 10. For example, the channel C of the first pull-up transistor T1... T1 It has a first side and a second side in the first direction F1, and the channel C T1 The first side and the first pole A T1 Connection, second side and second pole B T1 Connection. Channel C of the first pull-down tube T3. T3 It has a first side and a second side in the first direction F1, and the channel C T3 The first side and the first pole A T3 Connection, second side and second pole B T3 Connection. And, the channel C of the first pull-up tube T1. T1 The orthogonal projection on substrate 10 and the channel C of the first pull-down diode T3 T3 The orthogonal projections on substrate 10 overlap.

[0114] Continue to refer to Figures 3 to 8 In the second complementary field-effect transistor C2, the orthogonal projection of the second pull-up transistor T2 onto the substrate 10 overlaps with the orthogonal projection of the second pull-down transistor T4 onto the substrate 10. For example, in the second complementary field-effect transistor C2, the orthogonal projection of the channel of the second pull-up transistor T2 onto the substrate 10 overlaps with the orthogonal projection of the channel of the second pull-down transistor T4 onto the substrate 10. For example, the channel C of the second pull-up transistor T2... T2 It has a first side and a second side in the first direction F1, and the channel C T2 The first side and the first pole A T2 Connection, second side and second pole B T2 Connection. Channel C of the second pull-down tube T4.T4 It has a first side and a second side in the first direction F1, and the channel C T4 The first side and the first pole A T4 Connection, second side and second pole B T4 Connection. And, the channel C of the second pull-up tube T2. T2 The orthogonal projection on substrate 10 and the channel C of the second pull-down diode T4 T4 The orthogonal projections on substrate 10 overlap.

[0115] It should be noted that in actual processes, due to limitations in process conditions or other factors, the aforementioned overlapping relationships may not be completely identical and may have some deviations. Therefore, as long as the aforementioned overlapping relationships roughly meet the above conditions, they are all within the scope of protection of this application. For example, the aforementioned overlapping relationships can be overlapping relationships that are permissible within the allowable error range.

[0116] For example, the first and second electrodes on both sides of the aforementioned channel can be formed after the channel is formed. Of course, in practical applications, the specific fabrication processes of the first and second electrodes can be determined according to the needs of the actual application, and are not limited here.

[0117] For example, continue to refer to Figures 3 to 8 The first pull-up transistor T1 is configured as one, and the gate of the first pull-up transistor T1 surrounds the channel C of the first pull-up transistor T1 through the gate dielectric layer 12. T1 This configuration allows the first pull-up transistor T1 to form a Gate All Around (GAA) FET. The configuration of the first pull-up transistor T1 as a GAA FET is merely illustrative; other feasible methods can be used to configure the gate and channel of the first pull-up transistor T1, and this application does not limit this to any particular method.

[0118] For example, continue to refer to Figures 3 to 8 The first pull-down transistor T3 is configured as one, and the gate of the first pull-down transistor T3 surrounds the channel C of the first pull-down transistor T3 through the gate dielectric layer 12. T3 This configuration allows the first pull-down transistor T3 to form a GAAFET. The configuration of the first pull-down transistor T3 as a GAAFET is merely illustrative; other feasible methods can be used to configure the gate and channel of the first pull-down transistor T3, and this application does not limit this to any particular method.

[0119] For example, continue to refer to Figures 3 to 8The orthographic projection of the gate of the first pull-up transistor T1 onto the substrate 10 overlaps with the orthographic projection of the gate of the first pull-down transistor T3 onto the substrate 10. Furthermore, the gates of the first pull-up transistor T1 and the first pull-down transistor T3 are a single integrated structure 111, sharing the same gate. Therefore, the first CFET can be configured as a Gate All Around (GAA) CFET. The formation of a Gate All Around (GAA) CFET for the first CFET is merely an example; the gate and channel arrangement in the first CFET can also employ other feasible methods, which are not limited in this application.

[0120] For example, continue to refer to Figures 3 to 8 A second pull-up transistor T2 is configured as one, and the gate of the second pull-up transistor T2 surrounds the channel C of the second pull-up transistor T2 through the gate dielectric layer 12. T2 This configuration allows the second pull-up transistor T2 to form a GAAFET. The configuration of the second pull-up transistor T2 as a GAAFET is merely illustrative; other feasible methods can be used to configure the gate and channel of the second pull-up transistor T2, and this application does not limit this to any particular method.

[0121] For example, continue to refer to Figures 3 to 8 The second pull-down transistor T4 is configured as one, and the gate of the second pull-down transistor T4 surrounds the channel C of the second pull-down transistor T4 through the gate dielectric layer 12. T4 This configuration allows the second pull-down transistor T4 to form a GAAFET. The configuration of the second pull-down transistor T4 as a GAAFET is merely illustrative; other feasible methods can be used to configure the gate and channel of the second pull-down transistor T4, and this application does not limit this to any particular method.

[0122] For example, continue to refer to Figures 3 to 8 The orthographic projection of the gate of the second pull-up transistor T2 onto the substrate 10 overlaps with the orthographic projection of the gate of the second pull-down transistor T4 onto the substrate 10. Furthermore, the gates of the second pull-up transistor T2 and the second pull-down transistor T4 are a single integrated structure 114, sharing the same gate. Therefore, the second CFET can be configured as a GAACFET. The formation of a Gate All Around (GAA) CFET in the second CFET is merely an example; the gate and channel arrangement in the second CFET can also employ other feasible methods, which are not limited in this application.

[0123] For example, continue to refer to Figures 3 to 8 The first selector transistor T5 is configured as one, and the gate 112 of the first selector transistor T5 surrounds the channel C of the first selector transistor T5 through the gate dielectric layer 12. T5This configuration allows the first selector transistor T5 to form a GAAFET. The configuration of the first selector transistor T5 as a GAAFET is merely illustrative; other feasible methods can be used to configure the gate and channel of the first selector transistor T5, and this application does not limit this to any particular method.

[0124] For example, continue to refer to Figures 3 to 8 The second selector T6 is configured as one, and the gate 113 of the second selector T6 surrounds the channel C of the second selector T6 through the gate dielectric layer 12. T6 This configuration allows the second selector transistor T6 to form a GAAFET. The configuration of the second selector transistor T6 as a GAAFET is merely illustrative; other feasible methods can be used to configure the gate and channel of the second selector transistor T6, and this application does not limit this to any particular method.

[0125] For example, continue to refer to Figures 3 to 8 The upper surfaces of the integrated structure 111 formed by the gates of the first pull-up transistor T1 and the first pull-down transistor T3, the upper surfaces of the integrated structure 114 formed by the gates of the second pull-up transistor T2 and the second pull-down transistor T4, the upper surfaces of the gate 112 of the first gate transistor T5 and the upper surfaces of the gate 113 of the second gate transistor T6 can be disposed on the same plane, that is, the upper surfaces of the integrated structure 111 formed by the gates of the first pull-up transistor T1 and the first pull-down transistor T3, the upper surfaces of the integrated structure 114 formed by the gates of the second pull-up transistor T2 and the second pull-down transistor T4, the upper surfaces of the gate 112 of the first gate transistor T5 and the upper surfaces of the gate 113 of the second gate transistor T6 can be disposed flush.

[0126] For example, continue to refer to Figures 3 to 8 The integrated structure 111 formed by the gates of the first pull-up transistor T1 and the first pull-down transistor T3, the integrated structure 114 formed by the gates of the second pull-up transistor T2 and the second pull-down transistor T4, the gate 112 of the first select transistor T5, and the gate 113 of the second select transistor T6 extend in the second direction F2. Furthermore, the integrated structure 111 formed by the gates of the first pull-up transistor T1 and the first pull-down transistor T3 and the gate 112 of the first select transistor T5 are arranged along the first direction F1, and the integrated structure 114 formed by the gate 113 of the second select transistor T6 and the gates of the second pull-up transistor T2 and the second pull-down transistor T4 is also arranged along the first direction F1.

[0127] In some examples, a first device layer, a second device layer, a first wiring layer, a second wiring layer, and a third wiring layer are disposed on the substrate 10. The first and second device layers are disposed on the substrate 10, the first wiring layer is disposed on the side of the first and second device layers facing away from the substrate 10, the second wiring layer is disposed on the side of the first wiring layer away from the substrate 10, and the third wiring layer is disposed on the side of the second wiring layer away from the substrate 10. Furthermore, an insulating layer (which may be formed by one or more dielectric material layers) is disposed between the different layers. Figures 3 to 8 An insulating layer is not shown. Of course, the positional relationship of the first wiring layer, the second wiring layer, and the third wiring layer can also be in other forms, and this application does not limit this.

[0128] Exemplarily, the first device layer and the second device layer may have the gate, channel, first electrode, and second electrode of the FET described above. Optionally, the first device layer is disposed between the second device layer and the substrate, in which case an insulating layer is also disposed between the first device layer and the substrate; or, the second device layer may be disposed between the first device layer and the substrate, in which case an insulating layer is also disposed between the second device layer and the substrate, which is not limited here. In this application, the example of the first device layer being disposed between the second device layer and the substrate is used for illustration.

[0129] For example, the insulating layer can be made of a dielectric material, such as, but not limited to, a dielectric material composed of any combination of silicon (Si) and carbon (C), oxygen (O) and nitrogen (N).

[0130] For example, refer to Figure 4 and Figure 5 In this application, the first pull-down transistor T3 and the second pull-down transistor T4 are disposed on the first device layer, that is, the first device layer has the channel C of the first pull-down transistor T3. T3 First pole A T3 And the second pole B T3 It also has a channel C for the second pull-down tube T4. T4 First pole A T4 And the second pole B T4 .

[0131] For example, refer to Figure 4 and Figure 5 In this application, the first pull-up transistor T1 and the second pull-up transistor T2 are disposed on the second device layer, that is, the second device layer has the channel C of the first pull-up transistor T1. T1 First pole A T1 And the second pole B T1 It also has a channel C for the second pull-up tube T2. T2 First pole A T2 And the second pole B T2 .

[0132] For example, refer to Figure 4 and Figure 5 In this application, the first selector T5 and the second selector T6 are disposed on the first device layer, that is, the first device layer also has the channel C of the first selector T5. T5 First pole A T5 And the second pole B T5 It also has a second selector channel C of T6. T6 First pole A T6 And the second pole B T6 .

[0133] Alternatively, the first and second gate transistors can be disposed on the second device layer, that is, the second device layer also has the channel, first electrode and second electrode of the first gate transistor, and also has the channel, first electrode and second electrode of the second gate transistor.

[0134] For example, the above-mentioned NFET and PFET can be formed by setting the channel type of the FET to N-type or P-type, and the specifics are not limited here.

[0135] For example, continue to refer to Figures 3 to 8 When the first selector transistor T5 and the second selector transistor T6 are disposed in the first device layer, the second electrode B of the first selector transistor T5 can be made to... T5 With the first electrode A of the first pull-down tube T3 T3 It is an integrated structure, and the second electrode B of the second selector tube T6 T6 With the first electrode A of the second pull-down tube T4 T4 It is a one-piece structure.

[0136] Alternatively, when the first and second gate transistors are disposed on the second device layer, the second electrode of the first gate transistor T5 and the first electrode of the first pull-up transistor T1 can be integrated into one structure, and the second electrode of the second gate transistor T6 and the first electrode of the second pull-up transistor T2 can be integrated into one structure.

[0137] For example, continue to refer to Figure 3 , Figure 4 , Figure 6a as well as Figure 6b The first wiring layer includes a second memory interconnect 211, a first memory interconnect 212, a first bit line interconnect 231, a second bit line interconnect 232, and a word line interconnect 22, all spaced apart from each other. The gate (or integrated structure 111) of the first pull-up transistor T1 is connected to the first electrode A of the second pull-up transistor T2 via the second memory interconnect 211. T2 The first electrode A of the second pull-down tube T4 T4 And the second electrode B of the second selector tube T6 T6Connection. The gate (or integrated structure 114) of the second pull-up transistor T2 is connected to the first terminal A of the first pull-up transistor T1 via the first memory interconnect 212. T1 The first electrode A of the first pull-down tube T3 T3 And the second electrode B of the first selector tube T5 T5 connect.

[0138] For example, continue to refer to Figure 3 , Figure 4 , Figure 6a as well as Figure 6b The word line WL is connected to the gate 112 of the first select transistor T5 and the gate 113 of the second select transistor T6 via word line interconnects. This achieves the effect of connecting the word line WL to the gates of the first select transistor T5 and the second select transistor T6 respectively.

[0139] For example, continue to refer to Figure 3 , Figure 4 , Figure 6a as well as Figure 6b The second end of the first line interconnect 231 is connected to the first pole A of the first selector tube T5. T5 Connection. The second end of the second bit line interconnect 232 is connected to the first pole A of the second selector T6. T6 connect.

[0140] For example, continue to refer to Figure 3 , Figure 4 , Figure 6a as well as Figure 6b The second memory interconnect 211, the first memory interconnect 212, the first bit line interconnect 231, the second bit line interconnect 232, and the word line interconnect 22 extend along the first direction F1. Specifically, the orthogonal projection of the word line interconnect 22 onto the substrate 10 is disposed between the orthogonal projection of the second memory interconnect 211 onto the substrate 10 and the orthogonal projection of the first memory interconnect 212 onto the substrate 10. The orthogonal projection of the first bit line interconnect 231 onto the substrate 10 is disposed on the side opposite to the orthogonal projection of the second memory interconnect 211 onto the substrate 10. The orthogonal projection of the second bit line interconnect 232 onto the substrate 10 is disposed on the side opposite to the orthogonal projection of the first memory interconnect 212 onto the substrate 10. Of course, the second memory interconnect 211, the first memory interconnect 212, the first bit line interconnect 231, the second bit line interconnect 232, and the word line interconnect 22 can also be configured in other ways, and this application does not limit them.

[0141] For example, continue to refer to Figure 3 , Figure 4 , Figure 6a as well as Figure 6bThe first line interconnect 231 is disposed on the substrate 10 in the channel C of the first gate transistor T5 connected thereto, with its orthographic projection onto the substrate 10. T5 The orthogonal projection of substrate 10 is opposite to the channel C of the first pull-down transistor T3. T3 On the orthogonal projection side of substrate 10.

[0142] For example, continue to refer to Figure 3 , Figure 4 , Figure 6a as well as Figure 6b The second bit line interconnect 232 is disposed on the substrate 10 in the channel C of the second gate transistor T6 connected thereto, as an orthographic projection of the second bit line interconnect 232. T6 The orthogonal projection of substrate 10 is opposite to the channel C of the second pull-down transistor T4. T4 On the orthogonal projection side of substrate 10.

[0143] For example, continue to refer to Figures 3 to 5 as well as Figure 7 The first bit line BL and the second bit line BLB are disposed on the second wiring layer. The first bit line BL is connected to the first end of the first bit line interconnection section 231, and the second end of the first bit line interconnection section 231 is connected to the first pole A of the first selector T5. T5 The second bit line BLB is connected to the first end of the second bit line interconnection section 232, and the second end of the second bit line interconnection section 232 is connected to the first pole A of the second selector T6. T6 connect.

[0144] For example, continue to refer to Figures 3 to 5 as well as Figure 7 The orthographic projection of the first bit line BL onto the substrate 10 and the orthographic projection of the second bit line BLB onto the substrate 10 overlap with the orthographic projection of the memory cell onto the substrate 10. For example, the orthographic projection of the first bit line BL onto the substrate 10 and the orthographic projection of the second bit line BLB onto the substrate 10 partially overlap with the orthographic projection of the memory cell onto the substrate 10. Optionally, the orthographic projection of the first bit line onto the substrate and the orthographic projection of the second bit line onto the substrate partially overlap with the orthographic projection of the FET structure in the memory cell onto the substrate.

[0145] For example, continue to refer to Figures 3 to 8 The substrate 10 has a first trench, and the word line WL is disposed in the first trench. This method of embedding the word line WL in the substrate 10 achieves a buried word line configuration, which can reduce signal interference between word lines and improve the performance of the memory cell. Optionally, the word line WL can be directly disposed in the first trench, or it can be disposed in the first trench through the word line dielectric layer 13; this application does not limit this.

[0146] This application does not limit the way word lines are set. For example, word lines can also be set in the first wiring layer.

[0147] For example, continue to refer to Figures 3 to 8 The word line WL, projected onto the substrate 10, is positioned in the channel C of the first selector T5. T5 The orthographic projection of substrate 10 and the channel C of the second selector T6 T6 Between the orthographic projections of substrate 10. That is, the channel C of the first select transistor T5 in this memory cell. T5 Channel C of the second selector tube T6 T6 They are located on either side of the connecting word line WL.

[0148] For example, continue to refer to Figures 3 to 8 The orthographic projection of the word line WL onto the substrate overlaps with the orthographic projections of the gate of the first complementary field-effect transistor C1 (e.g., integral structure 111), the gate of the second complementary field-effect transistor C2 (e.g., integral structure 114), the gate 112 of the first selector T5, and the gate 113 of the second selector T6 onto the substrate. For example, the orthographic projection of the word line WL onto the substrate overlaps only partially with the orthographic projections of the gate of the first complementary field-effect transistor C1 (e.g., integral structure 111), the gate of the second complementary field-effect transistor C2 (e.g., integral structure 114), the gate 112 of the first selector T5, and the gate 113 of the second selector T6 onto the substrate. Of course, they may not overlap, and this application does not limit this.

[0149] For example, continue to refer to Figures 3 to 8 The orthographic projection of the word line WL onto the substrate 10 covers the orthographic projection of the word line interconnect 22 connected to it onto the substrate 10. Of course, it is also possible not to cover it but to partially overlap or not overlap at all, and this application does not limit this.

[0150] For example, continue to refer to Figures 3 to 5 as well as Figure 8 The storage unit is also connected to a first voltage power line VDDL and a second voltage power line VSSL that are spaced apart from each other. Exemplarily, the first voltage power line VDDL and the second voltage power line VSSL extend along a first direction F1 and are arranged along a second direction F2. Alternatively, the first voltage power line VDDL extends along the first direction F1 and is arranged along the second direction F2, and the second voltage power line VSSL extends along the second direction F2 and is arranged along the first direction F1. Alternatively, the second voltage power line VSSL extends along the first direction F1 and is arranged along the second direction F2, and the first voltage power line VDDL extends along the second direction F2 and is arranged along the first direction F1. This application does not limit this to any particular configuration.

[0151] For example, continue to refer to Figures 3 to 5 as well as Figure 8The first voltage power supply line VDDL is connected to the second terminal B of the first pull-up transistor T1. T1 The second electrode B of the second pull-up tube T2 T2 The connection is established to transmit the first power supply voltage VDD to the first pull-up transistor T1 and the second pull-up transistor T2 via the first voltage power supply line VDDL. The second voltage power supply line VSSL is connected to the second terminal B of the first pull-down transistor T3. T3 The second electrode B of the second pull-down tube T4 T4 The connection is configured to transmit the second power supply voltage VSS to the first pull-down transistor T3 and the second pull-down transistor T4 via the second voltage power supply line VSSL.

[0152] For example, the first voltage power line VDDL and the second voltage power line VSSL can be set on the third wiring layer.

[0153] Alternatively, the first voltage power line and the second voltage power line can be embedded in the substrate. For example, the substrate has a second trench and a third trench that are spaced apart from each other, with the first voltage power line disposed in the second trench and the second voltage power line disposed in the third trench.

[0154] Alternatively, the first voltage power line can be placed on the third wiring layer, and the second voltage power line can be placed in the substrate using a buried wire method, for example, the second voltage power line can be placed in the third trench.

[0155] Alternatively, the second voltage power line can be placed on the third wiring layer, and the first voltage power line can be placed in the substrate using a buried wire method, for example, the first voltage power line can be placed in the second trench.

[0156] Figure 10a An exemplary top view of a storage unit provided in another embodiment of this application is shown. Figure 10b An example is shown Figure 10a A schematic diagram of the cross-sectional structure along the tangent direction of AA'. Figure 11 An example is shown Figure 10a Some three-dimensional structural diagrams of the storage units in the image.

[0157] Reference Figures 10a to 11 In some other embodiments provided in this application, the memory cell includes a first pull-up transistor T1, a second pull-up transistor T2, a first pull-down transistor T3, a second pull-down transistor T4, a first gate transistor T5, and a second gate transistor T6 disposed on a substrate. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0158] Reference Figures 10a to 11In this embodiment, the first selector T5 is configured as two connected in parallel. For example, the first selector T5 includes a first sub-selector T51 and a second sub-selector T52; wherein the first sub-selector T51 and the second sub-selector T52 are stacked on a third-direction F3, the first sub-selector T51 is disposed on the first device layer, the second sub-selector T52 is disposed on the second device layer, and the first electrode A of the first sub-selector T51 is... T51 With the first pole A of the second sub-selector T52 T52 The connection serves as the first pole of the first selector tube T5 and the second pole B of the first sub-selector tube T51. T51 With the second pole B of the second sub-selector T52 T52 The connection serves as the second pole of the first selector tube T5.

[0159] Furthermore, the first electrode of the first sub-selector T51 is the source or drain, the first electrode of the second sub-selector T52 is the source or drain, the second electrode of the first sub-selector T51 is the source or drain, and the second electrode of the second sub-selector T52 is the source or drain.

[0160] For example, refer to Figures 10a to 11 The gate of the first sub-gated transistor T51 surrounds the channel C of the first sub-gated transistor T51 through the gate dielectric layer 12. T51 The gate of the second sub-selector T52 is configured to surround the channel C of the second sub-selector T52 via a gate dielectric layer 12. T52 The gate of the first sub-selector T51 is projected onto the substrate in a positive projection that overlaps with the gate of the second sub-selector T52 on the substrate. Furthermore, the gates of the first sub-selector T51 and the second sub-selector T52 are integrated into a single structure 112. Thus, the first sub-selector T51 and the second sub-selector T52 share the same gate.

[0161] Reference Figures 10a to 11 In this embodiment, the second selector T6 includes a third sub-selector T61 and a fourth sub-selector T62; wherein the third sub-selector T61 and the fourth sub-selector T62 are stacked on the third-direction F3. The third sub-selector T61 is disposed on the first device layer, and the fourth sub-selector T62 is disposed on the second device layer. The first electrode A of the third sub-selector T61 is... T61 With the first pole A of the fourth sub-selector T62 T62 The connection serves as the first pole of the second selector tube T6 and the second pole B of the third sub-selector tube T61. T61 With the second pole B of the fourth sub-selector T62 T62 The connection serves as the second pole of the second selector tube T6.

[0162] Furthermore, the first electrode of the third sub-selector T61 is the source or drain, the first electrode of the fourth sub-selector T62 is the source or drain, the second electrode of the third sub-selector T61 is the source or drain, and the second electrode of the fourth sub-selector T62 is the source or drain.

[0163] For example, refer to Figures 10a to 11 The gate of the third sub-gated transistor T61 surrounds the channel C of the third sub-gated transistor T61 through the gate dielectric layer 12. T61 The gate of the fourth sub-gated transistor T62 is configured to surround the channel C of the fourth sub-gated transistor T62 through the gate dielectric layer 12. T62 If the orthogonal projection of the gate of the third sub-selector T61 onto the substrate overlaps with the orthogonal projection of the gate of the fourth sub-selector T62 onto the substrate, and the gates of the third sub-selector T61 and the fourth sub-selector T62 are an integral structure 113, then the third sub-selector T61 and the fourth sub-selector T62 share the same gate.

[0164] For example, refer to Figures 10a to 11 The second electrode B of the first sub-selector T51 T51 With the first pull-down tube T3, first electrode A T3 They come into contact with each other and form an integrated structure.

[0165] For example, refer to Figures 10a to 11 The second electrode B of the second sub-selector T52 T52 With the first pole A of the first pull-up tube T1 T1 They come into contact with each other and form an integrated structure.

[0166] For example, refer to Figures 10a to 11 The second electrode B of the third sub-selector T61 T61 With the first electrode A of the second pull-down tube T4 T4 They come into contact with each other and form an integrated structure.

[0167] For example, refer to Figures 10a to 11 The second electrode B of the fourth sub-selector T62 T62 With the first electrode A of the second pull-up tube T2 T2 They come into contact with each other and form an integrated structure.

[0168] Figure 12 A top view of the storage unit provided in another embodiment of this application is shown as an example.

[0169] Reference Figure 12In some other embodiments provided in this application, the memory cell includes a first pull-up transistor T1, a second pull-up transistor T2, a first pull-down transistor T3, a second pull-down transistor T4, a first gate transistor T5, and a second gate transistor T6 disposed on a substrate. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0170] Exemplarily, in this application, reference is made to Figure 12 The orthographic projections of the first pull-up transistor T1, the second pull-up transistor T2, the first pull-down transistor T3, the second pull-down transistor T4, the first gate transistor T5, and the second gate transistor T6 onto the substrate 10 are all located on the boundary BS of the memory cell 02. That is, the boundary BS of the memory cell 02 overlaps with a portion of the orthographic projections of the first pull-up transistor T1, the second pull-up transistor T2, the first pull-down transistor T3, the second pull-down transistor T4, the first gate transistor T5, and the second gate transistor T6 onto the substrate 10. This reduces the process difficulty of fabricating the aforementioned FETs.

[0171] For example, refer to Figure 12 This can make the channel C of the first pull-up transistor T1 in the first complementary field-effect transistor C1... T1 The orthographic projection of the centerline along the first direction F1 onto the substrate 10 is aligned with the boundary BS of the memory cell 02.

[0172] For example, refer to Figure 12 This can make the channel C of the first pull-down transistor T3 in the first complementary field-effect transistor C1... T3 The orthographic projection of the centerline along the first direction F1 onto the substrate 10 is aligned with the boundary BS of the memory cell 02.

[0173] For example, refer to Figure 12 This can make the channel C of the first selector tube T5 T5 The orthographic projection of the centerline along the first direction F1 onto the substrate 10 is aligned with the boundary BS of the memory cell 02.

[0174] For example, refer to Figure 12 This can make the channel C of the second pull-up transistor T2 in the second complementary field-effect transistor C2... T2 The orthographic projection of the centerline along the first direction F1 onto the substrate 10 is aligned with the boundary BS of the memory cell 02.

[0175] For example, refer to Figure 12 This can make the channel C of the second pull-down transistor T4 in the second complementary field-effect transistor C2... T4 The centerline along the first direction F1 and the boundary BS of the storage cell 02 are aligned on the third direction F3.

[0176] For example, refer to Figure 12 This allows the channel C of the second selector tube T6 to be... T6 The orthographic projection of the centerline along the first direction F1 onto the substrate 10 is aligned with the boundary BS of the memory cell 02.

[0177] For example, refer to Figure 12 The orthographic projection of the word line WL onto the substrate does not overlap with the orthographic projections of the gate of the first complementary field-effect transistor C1 (e.g., integral structure 111), the gate of the second complementary field-effect transistor C2 (e.g., integral structure 114), the gate 112 of the first select transistor T5, and the gate 113 of the second select transistor T6 onto the substrate. Alternatively, the orthographic projection of the word line WL onto the substrate may overlap only partially with the orthographic projections of the gate of the first complementary field-effect transistor C1 (e.g., integral structure 111), the gate of the second complementary field-effect transistor C2 (e.g., integral structure 114), the gate 112 of the first select transistor T5, and the gate 113 of the second select transistor T6 onto the substrate. This application does not limit this.

[0178] Figure 13 An exemplary top view of a static random access memory (SRAM) provided in one embodiment of this application is shown below. Figure 13 The adjacent memory cells arranged along the second direction F2 are symmetrical by translation or rotation. For example, the structure of the FET in memory cell 02b can be obtained by symmetrically translating or rotating the structure of the FET in memory cell 02a, and the structure of the FET in memory cell 02c can be obtained by symmetrically translating or rotating the structure of the FET in memory cell 02b.

[0179] In some examples, two adjacent memory cells in the same memory cell column share the first bit interconnect. This saves space. For example, see... Figure 13 The first memory cell 02a and the second memory cell 02b share the first bit line interconnect. Figure 13 (Taking the arrow of AR2 as an example), this achieves the effect of connecting the first selector T5 in the first memory cell 02a and the first selector T5 in the second memory cell 02b to the first bit line BL. Also, the first memory cell 02c and another second memory cell share the first bit line interconnect (…). Figure 13 (Taking the arrow of AR4 as an example), to achieve the effect of connecting the first gate transistor T5 in the first memory cell 02c and the first gate transistor in another second memory cell with the first bit line BL.

[0180] In some examples, two adjacent memory cells in the same memory cell column can also share the second bit line interconnect. This saves space. For example, see [reference 1]. Figure 13 The first memory cell 02c and the second memory cell 02b share the second bit line interconnect. Figure 13 (Taking the arrow in AR3 as an example), this achieves the effect of connecting the second selector T6 in the first memory cell 02c and the second selector T6 in the second memory cell 02b to the second bit line BLB. The first memory cell 02a and another second memory cell share the second bit line interconnection section (…). Figure 13 (Taking the arrow of AR1 as an example), to achieve the effect of connecting the second gate transistor T6 in the first memory cell 02a and the second gate transistor T6 in another second memory cell with the second bit line BLB.

[0181] In some examples, each storage cell column can be repeated. See, for example, [link to example]. Figure 13 Each storage cell column has the same structure.

[0182] Figure 14 An exemplary top view of a static random access memory (SRAM) provided in another embodiment of this application is shown below. Figure 14 For example, two adjacent columns of storage cells arranged along a first direction are mirror-symmetrical, meaning that two adjacent columns of storage cells are symmetrically arranged about an axis of symmetry along a second direction. For instance, storage cells 02a1, 02b1, and 02c1 are arranged in one column of storage cells, and storage cells 02a2, 02b2, and 02c2 are arranged in another column of storage cells, and these two columns of storage cells are adjacent to each other. Furthermore, storage cells 02a1 and 02a2 are arranged in the same row of storage cells, and are symmetrically arranged about an axis of symmetry along the second direction. Storage cells 02b1 and 02b2 are also arranged in the same row of storage cells, and are symmetrically arranged about an axis of symmetry along the second direction. Storage cells 02c1 and 02c2 are also arranged in the same row of storage cells, and are symmetrically arranged about an axis of symmetry along the second direction.

[0183] For example, FETs disposed in adjacent memory cells along the second direction F2 are arranged on the same straight line along the first direction F1. For example, refer to Figure 14The second selector transistor T6 and the second complementary field-effect transistor C2 in memory cell 02a1 and the second complementary field-effect transistor C2 and the second selector transistor T6 in memory cell 02a2 are arranged in a straight line along the first direction F1. The first selector transistor T5 and the first complementary field-effect transistor C1 in memory cell 02b1 and the first complementary field-effect transistor C1 and the first selector transistor T5 in memory cell 02b2 are arranged in a straight line along the first direction F1. The second selector transistor T6 and the second complementary field-effect transistor C2 in memory cell 02c1 and the second complementary field-effect transistor C2 and the second selector transistor T6 in memory cell 02c2 are arranged in a straight line along the first direction F1. This reduces the difficulty of FET fabrication. Furthermore, the implementation methods of the remaining FETs can be deduced by analogy, and will not be elaborated here.

[0184] For example, refer to Figure 14 In memory cell 02a1, the second electrode of the second pull-up transistor T2 of the second complementary field-effect transistor C2 and the second pull-up transistor T2 of the second complementary field-effect transistor C2 are in contact with each other, forming an integrated structure. Furthermore, the second electrode of the second pull-down transistor T4 (or the second pull-up transistor T2) of the second complementary field-effect transistor C2 in memory cell 02a1 and the second pull-down transistor T4 (or the second pull-up transistor T2) of the second complementary field-effect transistor C2 in memory cell 02a2 are in contact with each other, forming an integrated structure. This reduces the fabrication difficulty of the FET. The implementation methods of the remaining FETs can be deduced similarly and will not be elaborated here.

[0185] Figure 15 An exemplary top view of a static random access memory (SRAM) provided in another embodiment of this application is shown below. Figure 15 For example, two adjacent columns of storage cells arranged along a first direction are mirror-symmetrical, meaning that two adjacent columns of storage cells are symmetrically arranged about an axis of symmetry along a second direction. For instance, storage cells 02a1, 02b1, and 02c1 are arranged in one column of storage cells, and storage cells 02a2, 02b2, and 02c2 are arranged in another column of storage cells, and these two columns of storage cells are adjacent to each other. Furthermore, storage cells 02a1 and 02a2 are arranged in the same row of storage cells, and are symmetrically arranged about an axis of symmetry along the second direction. Storage cells 02b1 and 02b2 are also arranged in the same row of storage cells, and are symmetrically arranged about an axis of symmetry along the second direction. Storage cells 02c1 and 02c2 are also arranged in the same row of storage cells, and are symmetrically arranged about an axis of symmetry along the second direction.

[0186] For example, FETs disposed at the boundaries of adjacent memory cells along the second direction F2 are arranged in a straight line along the first direction F1. Furthermore, FETs disposed at the boundaries of adjacent memory cells along the first direction F1 are also arranged in a straight line along the first direction F1. For example, refer to... Figure 15 The first complementary field-effect transistor C1 and the first gate transistor T5 in memory cell 02a1, the first gate transistor T5 and the first complementary field-effect transistor C1 in memory cell 02b1, the first complementary field-effect transistor C1 and the first gate transistor T5 in memory cell 02b2, and the first gate transistor T5 and the first complementary field-effect transistor C1 in memory cell 02a2 are arranged on the same straight line along the first direction F1. This reduces the difficulty of FET fabrication. Furthermore, the implementation methods of the remaining FETs can be deduced similarly and will not be elaborated here.

[0187] For example, refer to Figure 15 The second terminals of the first selector transistor T5 in memory cell 02a1 and the first selector transistor T5 in memory cell 02b1 are in contact with each other, forming an integrated structure. Similarly, the second terminals of the first pull-up transistor T1 (or first pull-down transistor T3) in the first complementary field-effect transistor C1 in memory cell 02b1 and the first pull-up transistor T1 (or first pull-down transistor T3) in the first complementary field-effect transistor C1 in memory cell 02b2 are in contact with each other, forming an integrated structure. This reduces the fabrication difficulty of the FET. Furthermore, the implementation methods of the remaining FETs can be deduced similarly and will not be elaborated upon here.

[0188] In this application, features in different embodiments may be combined with each other without contradiction.

[0189] This application also provides a processing circuit chip, which includes the above-mentioned static random access memory and one or more processing circuits. The static random access memory is used to store data required for the operation of one or more processing circuits.

[0190] This application also provides an electronic device, which includes a power supply and a processing circuit chip, wherein the power supply is used to power the processing circuit chip.

[0191] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A static random access memory, characterized in that, It includes multiple storage units, each of which includes: A first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first gate transistor, and a second gate transistor are disposed on a substrate; wherein, the first pull-up transistor and the first pull-down transistor serve as first complementary field-effect transistors (CFPTs), and the second pull-up transistor and the second pull-down transistor serve as second complementary field-effect transistors (CFPTs). The orthographic projections of the first CFPTs onto a first plane, the orthographic projections of the first gate transistors onto the first plane, the orthographic projections of the second gate transistors onto the first plane, and the orthographic projections of the second CFPTs onto the first plane are arranged sequentially at intervals along a first direction; and the orthographic projections of the first CFPTs onto the substrate and... The first gate transistor's orthographic projection onto the substrate is arranged in a straight line along the first direction. The second complementary field-effect transistor's orthographic projection onto the substrate and the second gate transistor's orthographic projection onto the substrate are arranged in another straight line along the first direction. The orthographic projections of the first complementary field-effect transistor and the second complementary field-effect transistor on the second plane are arranged alternately. The first direction and the second direction are parallel to the plane containing the substrate and intersect each other. The third direction is perpendicular to the plane containing the substrate. The first plane is parallel to the first direction and the third direction, and the second plane is parallel to the second direction and the third direction. The storage unit is connected to a word line, a first bit line, and a second bit line, respectively; wherein the word line extends along the first direction, and the first bit line and the second bit line extend along the second direction and are arranged along the first direction.

2. The static random access memory as described in claim 1, characterized in that, In the first complementary field-effect transistor, the orthographic projection of the first pull-up transistor on the substrate overlaps with the orthographic projection of the first pull-down transistor on the substrate; In the second complementary field-effect transistor, the orthogonal projection of the second pull-up transistor on the substrate overlaps with the orthogonal projection of the second pull-down transistor on the substrate.

3. The static random access memory as described in claim 2, characterized in that, The first pull-down transistor and the second pull-down transistor are disposed on the first device layer; The first pull-up transistor and the second pull-up transistor are disposed on the second device layer; The first device layer is disposed between the second device layer and the substrate; or, the second device layer is disposed between the first device layer and the substrate.

4. The static random access memory as described in claim 3, characterized in that, The first gate and the second gate are disposed on the first device layer; Alternatively, the first gate and the second gate are disposed on the second device layer.

5. The static random access memory as described in claim 4, characterized in that, When the first gate transistor and the second gate transistor are disposed on the first device layer, the second electrode of the first gate transistor and the first electrode of the first pull-down transistor are integrally formed, and the second electrode of the second gate transistor and the first electrode of the second pull-down transistor are integrally formed; the second electrode of the first gate transistor is the source or drain, the first electrode of the first pull-down transistor is the source or drain, the second electrode of the second gate transistor is the source or drain, and the first electrode of the second pull-down transistor is the source or drain; Alternatively, when the first gate transistor and the second gate transistor are disposed on the second device layer, the second terminal of the first gate transistor and the first terminal of the first pull-up transistor are integrally formed, and the second terminal of the second gate transistor and the first terminal of the second pull-up transistor are integrally formed; the second terminal of the first gate transistor is the source or drain, the first terminal of the first pull-up transistor is the source or drain, the second terminal of the second gate transistor is the source or drain, and the first terminal of the second pull-up transistor is the source or drain.

6. The static random access memory as described in claim 3, characterized in that, The first selector includes a first sub-selector and a second sub-selector; wherein the first sub-selector and the second sub-selector are stacked in the third direction, the first sub-selector is disposed on the first device layer, the second sub-selector is disposed on the second device layer, the first terminal of the first sub-selector is connected to the first terminal of the second sub-selector as the first terminal of the first selector, and the second terminal of the first sub-selector is connected to the second terminal of the second sub-selector as the second terminal of the first selector; the first terminal of the first sub-selector is the source or drain, the first terminal of the second sub-selector is the source or drain, the first terminal of the first selector is the source or drain, the second terminal of the first sub-selector is the source or drain, the second terminal of the second selector is the source or drain, and the second terminal of the first selector is the source or drain; The second selector includes a third sub-selector and a fourth sub-selector; wherein the third sub-selector and the fourth sub-selector are stacked in the third direction, the third sub-selector is disposed on the first device layer, the fourth sub-selector is disposed on the second device layer, the first terminal of the third sub-selector is connected to the first terminal of the fourth sub-selector as the first terminal of the second selector, and the second terminal of the third sub-selector is connected to the second terminal of the fourth sub-selector as the second terminal of the second selector; the first terminal of the third sub-selector is either the source or the drain, the first terminal of the fourth sub-selector is either the source or the drain, the first terminal of the second selector is either the source or the drain, the second terminal of the third sub-selector is either the source or the drain, the second terminal of the fourth sub-selector is either the source or the drain, and the second terminal of the second selector is either the source or the drain.

7. The static random access memory as described in claim 6, characterized in that, The second electrode of the first sub-selector and the first electrode of the first pull-down transistor are integrally formed, and the first electrode of the first pull-down transistor is the source or drain. The second electrode of the second sub-selector and the first electrode of the first pull-up transistor are integrally formed, and the first electrode of the first pull-up transistor is the source or drain. The second electrode of the third sub-selector and the first electrode of the second pull-down transistor are integrally formed, and the first electrode of the second pull-down transistor is the source or drain. The second electrode of the fourth sub-selector and the first electrode of the second pull-up diode are integrally formed, and the first electrode of the second pull-up diode is either the source or the drain.

8. The static random access memory as described in claim 6 or 7, characterized in that, The first sub-gated transistor and the second sub-gated transistor share the same gate. The third sub-gated transistor and the fourth sub-gated transistor share the same gate.

9. The static random access memory as described in any one of claims 2-8, characterized in that, The orthographic projection of the gate of the first pull-up transistor onto the substrate overlaps with the orthographic projection of the gate of the first pull-down transistor onto the substrate, and the first pull-up transistor and the first pull-down transistor share the same gate. The orthographic projection of the gate of the second pull-up transistor onto the substrate overlaps with the orthographic projection of the gate of the second pull-down transistor onto the substrate, and the second pull-up transistor and the second pull-down transistor share the same gate.

10. The static random access memory as described in claim 9, characterized in that, The gate of the first pull-up transistor is connected to the first terminal of the second pull-up transistor, the first terminal of the second pull-down transistor, and the second terminal of the second gate transistor through the second memory interconnect portion; the first terminal of the second pull-up transistor is the source or drain, the first terminal of the second pull-down transistor is the source or drain, and the second terminal of the second gate transistor is the source or drain. The gate of the second pull-up transistor is connected to the first terminal of the first pull-up transistor, the first terminal of the first pull-down transistor, and the second terminal of the first gate transistor through the first memory interconnect portion; the first terminal of the first pull-up transistor is the source or drain, the first terminal of the first pull-down transistor is the source or drain, and the second terminal of the first gate transistor is the source or drain. The second memory interconnect and the first memory interconnect are disposed at intervals on the first wiring layer, and the first wiring layer is disposed above the first device layer and the second device layer.

11. The static random access memory as described in any one of claims 1-10, characterized in that, The word lines are respectively connected to the gate of the first select transistor and the gate of the second select transistor, the first bit line is connected to the first terminal of the first select transistor, and the second bit line is connected to the first terminal of the second select transistor. The first terminal of the first selector is either the source or the drain, and the first terminal of the second selector is either the source or the drain.

12. The static random access memory as claimed in claim 11, characterized in that, The first bit line and the second bit line are disposed on the second wiring layer; The orthographic projections of the first bit line on the substrate and the second bit line on the substrate overlap with the orthographic projections of the memory cell on the substrate, respectively.

13. The static random access memory as claimed in claim 11, characterized in that, The word lines are connected to the gates of the first select transistor and the second select transistor respectively via word line interconnects. The word line interconnection portion is disposed on the first wiring layer, which is disposed above the first device layer and the second device layer.

14. The static random access memory as claimed in claim 13, characterized in that, The substrate is provided with a first trench, and the word line is disposed in the first trench; Alternatively, the word lines may be disposed on the first wiring layer.

15. The static random access memory as described in any one of claims 1-14, characterized in that, The storage unit is also connected to a first voltage power line and a second voltage power line that are spaced apart from each other. The first voltage power supply line is connected to the second terminal of the first pull-up transistor and the second terminal of the second pull-up transistor, and the second voltage power supply line is connected to the second terminal of the first pull-down transistor and the second terminal of the second pull-down transistor; The second electrode of the first pull-up transistor is the source or drain, the second electrode of the second pull-up transistor is the source or drain, the second electrode of the first pull-down transistor is the source or drain, and the second electrode of the second pull-down transistor is the source or drain.

16. The static random access memory as claimed in claim 15, characterized in that, The first voltage power line is disposed on the third wiring layer, and / or the second voltage power line is disposed on the third wiring layer; The third wiring layer is disposed above the first device layer and the second device layer.

17. The static random access memory as claimed in claim 15, characterized in that, The substrate has a second trench, and the first voltage power line is disposed in the second trench, and / or the substrate has a third trench, and the second voltage power line is disposed in the second trench.

18. The static random access memory as claimed in any one of claims 1-17, characterized in that, The gate of the second pull-up transistor is connected to the gate of the second pull-down transistor, the first terminal of the first pull-up transistor, the first terminal of the first pull-down transistor, and the second terminal of the first gate transistor. The gate of the first pull-up transistor, the gate of the first pull-down transistor, the first terminal of the second pull-up transistor, the first terminal of the second pull-down transistor, and the second terminal of the second gate transistor are connected to each other. The first electrode of the first pull-up diode is the source or drain, the first electrode of the first pull-down diode is the source or drain, the second electrode of the first gate diode is the source or drain, the first electrode of the second pull-up diode is the source or drain, the first electrode of the second pull-down diode is the source or drain, and the second electrode of the second gate diode is the source or drain.

19. The static random access memory as described in any one of claims 1-18, characterized in that, The plurality of storage cells are arranged in multiple rows along the second direction and in multiple columns along the first direction. Each column of storage cells corresponds one-to-one with the first bit line and the second bit line, and each row of storage cells corresponds one-to-one with the word line.

20. The static random access memory as claimed in claim 19, characterized in that, Two adjacent storage cells arranged along the second direction are translationally or rotationally symmetrical.

21. The static random access memory as claimed in claim 19 or 20, characterized in that, Two adjacent storage cell columns arranged along the first direction are mirror symmetrical.

22. A processing circuit chip, characterized in that, It includes a static random access memory as described in any one of claims 1-21 and one or more processing circuits, wherein the static random access memory is used to store data required for the operation of the one or more processing circuits.

23. An electronic device, characterized in that, It includes a power supply and a processing circuit chip as described in claim 22, wherein the power supply is used to power the processing circuit chip.

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