CFET-SRAM DEVICE, LAYOUT AND METHOD

Abstract

An IC device includes a static random access memory device (SRAM device) positioned in a substrate, wherein the SRAM device comprises a first complementary field-effect transistor (CFET) having a first pass-gate transistor positioned at a first height, a second CFET having a first pull-down transistor positioned at the first height and a first pull-up transistor positioned at a second height, a third CFET having a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height, and a fourth CFET having a second pass-gate transistor positioned at the first height.Each of the first and second pull-down transistors has a gate extending in a gate direction and having a first output working configuration, and each of the first and second pass-gate transistors has a gate extending in the gate direction and having a second output working configuration that differs from the first output working configuration.

Description

PRIORITY CLAIM

[0001] This application claims priority over preliminary US patent application No. 63 / 707,609, filed on October 15, 2024, which is incorporated by reference into the present application. BACKGROUND

[0002] The ongoing trend toward miniaturization of integrated circuits (ICs) has led to ever smaller devices that consume less power but offer more functionality at higher speeds than previous technologies. This miniaturization has been achieved through design and manufacturing innovations that adhere to increasingly stringent specifications. Various electronic design automation (EDA) tools are used to create, revise, and verify designs for semiconductor devices while ensuring that IC structural design and manufacturing specifications are met. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a schematic diagram of a memory cell according to some embodiments. Fig. Figures 2A-2C are top views of an IC device and a layout diagram according to some embodiments. Fig. Figures 3A-3E are top and cross-sectional views of an IC device and a layout diagram according to some embodiments. Fig. Figures 4A-4C are a schematic diagram and top and cross-sectional views of an IC device and a layout diagram according to some embodiments. Fig. 5A and Fig. Figure 5B shows top views of an IC device and a layout diagram according to some embodiments. Fig. Figure 6 is a top view of an IC device and a layout diagram according to some embodiments. Fig. Figure 7 is a cross-sectional view of an IC device and a layout diagram according to some embodiments. Fig. Figure 8 is a flowchart of a method for manufacturing an IC device according to some embodiments. Fig. Figure 9 is a flowchart of a procedure for creating an IC layout diagram according to some embodiments. Fig. Figure 10 is a block diagram of an IC layout diagram creation system according to some embodiments. Fig. Figure 11 is a block diagram of an IC manufacturing system and an associated IC manufacturing process according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like are considered.For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves the purpose of simplification and clarity and does not itself establish a relationship between the different embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "underlying", "below", "under", "overlying", "above", and the like may be used herein to facilitate description and to describe the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0006] In various embodiments, an IC device, a layout diagram, and a manufacturing method refer to a static random-access memory (SRAM) device comprising complementary field-effect transistors (CFETs) in which first and second pass-gate transistors are arranged in a first height and have gates with a first output function configuration, and first and second pull-down transistors are arranged in the first height and have gates with a second output function configuration that differs from the first output function configuration.

[0007] The pass-gate and pull-down transistors, which have gates with different output configurations, are able to have tunable relative threshold voltage levels, so that, compared with other methods, e.g., those in which the pass-gate and pull-down transistors have the same threshold voltage level, the SRAM device is able to have improved read current characteristics, making operation at reduced power supply levels possible, and allowing shorter read windows corresponding to relatively higher operating speeds for a given power supply voltage level.

[0008] As discussed below, according to various embodiments Fig. 1 a schematic diagram of a memory cell 100, Fig. 2A-2C are top views of an IC device and a layout diagram 200, Fig. 3A-3E are top and cross-sectional views of an IC device and a layout diagram 300, Fig. 4A-4C are top and cross-sectional views of an IC device and a layout diagram 400, Fig. 5A and Fig. 5B are top views of an IC device and a 500 layout diagram. Fig. Figure 6 is a top view of an IC device and a layout diagram 600. Fig. Figure 7 is a cross-sectional view of an IC device and a layout diagram 700. Fig. Figure 8 is a flowchart of a process 800 for manufacturing an IC and Fig. Figure 9 is a flowchart of a procedure 900 for creating an IC layout diagram, e.g. using an IC layout diagram creation system 1000, which is in Fig. 10 is shown, and / or in accordance with an IC manufacturing process 1100, which is shown in Fig. 11 is shown.

[0009] Each of the figures presented, e.g. Fig. Figures 1-7 are simplified for illustrative purposes. The figures are views of IC schematics, structures, devices, and layout diagrams in which various structural elements are included or excluded to simplify the following discussion. In various embodiments, an IC, structure, device, and / or layout diagram has one or more structural elements corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures, source / drain (S / D) structures, active areas, bulk connections or other transistor elements, insulation structures, or the like, in addition to those shown in Figures 1-7. Fig. Structural elements shown in 1-7.

[0010] In each of the IC layout diagrams / each of the IC devices 200-700, reference symbols represent both IC device structural elements and the IC layout structural elements used to at least partially create the corresponding IC device structural elements in a manufacturing process, e.g., in process 800, which is described below in relation to Fig. 8 is discussed and / or in the IC manufacturing process linked to IC manufacturing system 1100, which is described below in relation to Fig. As discussed in section 11, each IC layout diagram / IC device 200-700 represents a view of both an IC layout diagram 200-700 and a corresponding IC device 200-700.

[0011] Each of the IC layout diagrams / IC devices 200-700, as discussed below, features arrangements of some or all of at least one of a substrate, an active region / area, an S / D region / structure, a contact and / or an interconnect region / structure, a gate region / structure, a metal region / segment, a via region / structure, and / or a dielectric region / layer, each of which is discussed below.

[0012] A substrate, e.g., a substrate SUB, is a part, e.g., a die, or the entirety of a semiconductor or other wafer, e.g., a silicon wafer (Si wafer) or an epitaxial Si layer, suitable for forming one or more IC devices, e.g., IC devices 200-600. In each of the embodiments discussed below, a substrate, e.g., a semiconductor substrate, has a front side, e.g., a front side FS, in which a first subset of the structural elements of the IC devices is formed by a first set of manufacturing processes, e.g., front-end-of-line (FEOL) processes, middle-end-of-line (MEOL) processes, and back-end-of-line (BEOL) processes, and a back side, e.g., a back side BS, in which a second subset of the structural elements of the IC devices is formed by a second set of manufacturing processes, e.g.,Reverse metallization processes are formed, which are carried out after the first set of manufacturing processes has been carried out.

[0013] An active region, e.g., an active region AA, is a region in an IC layout diagram that, in a manufacturing process, is incorporated as part of defining an active region, also referred to as oxide diffusion or definition (OD) in some embodiments, within the substrate, either directly or in an n-well or p-well region, in which one or more IC device structure elements, e.g., an S / D structure, are formed. In some embodiments, an active region is an n- or p-active region of a stacked complementary field-effect transistor (CFET) or other transistor configuration that incorporates a gate region / gate structure.

[0014] In various embodiments, an active region (an active structure) contains one or more materials of a semiconductor material, e.g. silicon (Si), silicon germanium (SiGe), silicon carbide (SiC) or the like, a dopant, e.g. boron (B), aluminum (Al), phosphorus (P), arsenic (As), gallium (Ga) or another suitable material.

[0015] In some embodiments, an active region is a region in an IC layout diagram that is included in the fabrication process as part of defining a nanosheet structure, e.g., a continuous volume of one or more layers of one or more semiconductor materials with either n- or p-doping. In various embodiments, individual nanosheet layers comprise a single monolayer or multiple monolayers of a given semiconductor material.

[0016] An S / D region / structure, e.g., an S / D region / structure SD, is a region in the IC layout diagram included in the manufacturing process as part of defining an S / D structure, also referred to as a semiconductor structure in some embodiments, configured to have a doping type opposite to that of the corresponding active region / area. In some embodiments, an S / D region / structure is configured to have lower resistance than an adjacent channel structure element, e.g., part of the corresponding active region / area of ​​a CFET or other transistor. In some embodiments, an S / D region / structure has one or more parts with higher doping concentrations than one or more doping concentrations present in the corresponding channel structure element.In some embodiments, an S / D region / structure comprises one or more epitaxial regions of a semiconductor material, e.g., Si, SiGe, and / or silicon carbide (SiC). An S / D region / structure, also referred to as an S / D terminal in some embodiments, may relate individually or collectively to a source or a drain, depending on the context.

[0017] A contact or interconnect area / structure, e.g., a contact area / structure CT or an interconnect area / structure ND or node, is a conductive area in the IC layout diagram that is included in and / or on the substrate during the manufacturing process as part of defining a contact or interconnect structure, also referred to as a conductive segment or metal-defined (MD) conductive line, trace, or structure. In some embodiments, a contact or interconnect area overlaps an active area at a location of one or more S / D areas in the IC layout diagram, and the corresponding contact or interconnect structure contacts or is electrically connected to one or more S / D structures of the active area.

[0018] In some embodiments, a contact or interconnect structure includes a portion of at least one metal layer, e.g., a contact layer, that lies above and is in contact with the substrate and has a sufficiently small thickness to allow the formation of an insulating layer between the contact or interconnect structure and an overlying metal layer, e.g., the first metal layer. In various embodiments, an MD segment contains one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing a low-resistance electrical connection between IC structural elements, i.e., a resistance value below a predetermined threshold corresponding to one or more tolerance values ​​of a resistance-based effect on circuit performance.

[0019] In various embodiments, a contact or interconnect structure comprises a section of a substrate and / or an epitaxial layer with a doping concentration, e.g., based on an implantation process, sufficient to cause the structure to exhibit a low resistance value. In various embodiments, a doped contact or interconnect structure contains one or more dopants with doping concentrations of approximately 1 × 10¹⁶ per cubic centimeter (cm⁻³) or more.

[0020] In some embodiments, a fabrication process comprises two or more contact or interconnect structural layers, and a contact or interconnect region / structure, e.g., contact region / structure CT or interconnect region / structure ND or node, refers to one or more of the two or more contact or interconnect structural layers in the fabrication process. In some embodiments, a contact or interconnect structure is configured to be electrically connected to the S / D structure of one of the p- or n-FETs of a CFET and to be electrically isolated from the S / D structure of the other of the p- or n-FETs of the CFET. In some embodiments, a contact or interconnect structure, also referred to as an MD local interconnect (MDLI) or local interconnect (LI) in some embodiments, is configured to be electrically connected to the S / D structures of both the p-FET and the n-FET of a CFET.

[0021] A gate region / gate structure, e.g., a gate region / gate structure G, also referred to as a gate G in some embodiments, is a region in the IC layout diagram that is included in the manufacturing process as part of defining a gate structure. A gate structure is a volume that has one or more conductive segments, e.g., a gate electrode, containing one or more conductive materials, e.g., polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, substantially surrounded by one or more insulating materials, wherein the one or more conductive segments are configured to control a voltage supplied to one or more adjacent dielectric gate layers, e.g., adjacent to or surrounding one or more channel regions of a corresponding active area.

[0022] A dielectric gate layer, e.g., a dielectric gate layer GD of a gate structure G, is a volume containing one or more insulating materials, e.g., silicon dioxide, silicon nitride (Si3N4), and / or one or more other suitable materials, such as a low-k material with a k-value less than 3.8 or a high-k material with a k-value greater than 3.8 or 7.0, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O3), or titanium oxide (TiO), which are suitable to provide a high electrical resistance between IC structural elements, i.e., a resistance value above a predetermined threshold corresponding to one or more tolerance values ​​of a resistance-based effect on circuit performance.

[0023] An exit work configuration, e.g., an exit work configuration WF1-WF4, is one or more regions in the IC layout diagram that are included in the manufacturing process as part of defining one or more layers of exit work materials positioned within a transistor gate electrode alongside the corresponding one or more dielectric gate layers.

[0024] The one or more layers of exit working materials contain n- and / or p-type exit working materials with one or more thicknesses, concentrations, dopants, impurities, or the like, configured to increase or decrease the gate electrode work function by a target value compared to the work function of an equivalent gate electrode that does not contain the one or more layers of exit working materials. Non-restrictive examples of exit working materials include Ti, Ag, Al, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr.

[0025] A transistor's threshold voltage level is a function of operating conditions, such as bias level and / or temperature, in combination with the work function of the corresponding gate electrode. For a predetermined set of operating conditions, such as within predetermined voltage and / or temperature ranges, a specific target value for increasing or decreasing the work function is translated into an increase or decrease in the threshold voltage level of the transistor with the corresponding gate, compared to the threshold voltage level of an equivalent transistor with the equivalent gate electrode that lacks one or more layers of work function material.

[0026] Each output function configuration thus corresponds to a predetermined threshold voltage level of the corresponding transistor, so that multiple output function configurations can be used to define a predetermined number of threshold voltage levels.

[0027] In some embodiments, a gate region / gate structure corresponds to a dummy gate region / dummy gate structure. In some embodiments, a dummy gate region / dummy gate structure has a gate electrode that is electrically connected, e.g., clamped, to one or more structural elements, e.g., a busbar or other metal segment, or an adjacent instance of an S / D region / S / D structure, such that a transistor corresponding to the dummy gate region / dummy gate structure and overlapping / lying beneath the active region / active area is by design switched off. In some embodiments, a dummy gate region / dummy gate structure that overlaps / lies above an edge of an active region / area is referred to as a CPODE region / CPODE structure (Continuous Poly on Oxide Definition Edge).

[0028] A cut-gate region, e.g., a cut-gate region CPO, also referred to as a cut-poly region in some embodiments, is a region in the IC layout diagram that is included in the manufacturing process as part of defining a discontinuity in a particular gate structure, e.g., a part that is etched away after the gate electrode is formed, resulting in adjacent and aligned gate electrode segments that are electrically isolated from each other.

[0029] A metal conductor or metal area, e.g., a front-facing metal area / segment VSS, BL, or BLB, or a back-facing metal area / segment BMo_VDD or BMo_WL, is an area in the IC layout diagram that is included in the manufacturing process as part of defining a metal conductor or metal segment containing one or more conductive materials, e.g., polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, in a given front-facing or back-facing metal layer of the manufacturing process.

[0030] In some embodiments, a metal region / segment, e.g., metal region / segment VSS, BL, or BLB, corresponds to a first, or lowest, front-facing metal layer (also referred to as metal layer zero or front-facing metal layer zero in some embodiments), e.g., metal layer M0, or to a second or higher-level, front-facing metal layer of the manufacturing process. In some embodiments, a second front-facing metal layer is referred to as metal layer one or front-facing metal layer one, and a second front-facing metal region / segment is referred to as metal region / segment one.

[0031] In some embodiments, a backside metal area / segment, e.g., metal area / segment BM0_VDD or BM0_WL, corresponds to a first or lowest backside metal layer (also referred to as a backside metal layer zero in some embodiments) or to a second or higher-level backside metal layer of the manufacturing process.

[0032] In some embodiments, a metal area / segment corresponds to a component of a power distribution network configured to distribute one or both of a power supply voltage, e.g., a power supply voltage VDD, and / or a reference or ground voltage, e.g., reference voltages VSS. The power distribution network component is electrically connected to one or more structural elements, e.g., additional metal areas / segments and / or vias, configured to distribute the corresponding power supply or reference voltage and to be electrically isolated from IC components outside the distribution network.

[0033] A via area / via structure, e.g., a via area / via structure VD, VG, VDR, or BM0_V, also referred to as a via or interconnect in some embodiments, is an area in the IC layout diagram included in the manufacturing process as part of defining a via / interconnect structure containing one or more conductive materials configured to provide an electrical connection between a first, e.g., overlying, conductive structure, e.g., a front-facing metal segment VSS, BL, or BLB or back-facing metal segment BM0_VDD or BM0_WL, and a second, e.g., underlying, conductive structure, e.g., a metal segment, a gate electrode of a gate structure G, a contact structure CT, an interconnect structure ND, or an S / D structure SD, aligned with the first conductive structure in the Z-direction.

[0034] In some embodiments, a via area / via structure VD corresponds to the underlying conductive structure, which is an S / D area / S / D structure SD, a contact area / contact structure CT, or an interconnect area / interconnect structure ND.

[0035] Fig. Figure 1 is a schematic diagram of SRAM cell 100, each of which has IC layouts / IC devices 200, 300 and 500, each of which Fig. 2A-2C contains a top view of the IC layout diagram / IC device 200 and X and Y directions, each of Fig. 3A and Fig. 3E contains a top view of IC layout diagram / IC device 300 and the X and Y directions and Fig. 3B-3D includes cross-sectional views of IC layout diagram / IC device 300 along corresponding lines A-A', BB' and CC' of Fig. 3B, the X direction and a Z direction.

[0036] Fig. 4A is a schematic diagram of an SRAM cell 400, also referred to as an IC layout diagram / IC device 400 in some embodiments, Fig. 4B contains a top view of IC layout diagram / IC device 400 and the X and Y directions and Fig. 4C contains a cross-sectional view of IC layout diagram / IC device 400 along line DD' of Fig. 4B and the X and Z directions, each of Fig. 5A and Fig. 5B contains a top view of IC layout diagram / IC device 500 and the X and Y directions, Fig. Figure 6 contains a top view of the IC layout diagram / IC device 600 and the X and Y directions and Fig. Figure 7 contains a cross-sectional view of a gate structure 700, also referred to as an IC layout diagram / IC device 700 in some embodiments, and the X and Z directions.

[0037] In some cases, for the sake of clarity, not all instances of each structural element included in IC layout diagrams / IC devices 200-700 are shown in Fig. 2A-7 marked.

[0038] As in Fig. As shown in Figures 1-5B, each of IC layout diagrams / IC devices 200-500 features one or more instances of a six-transistor SRAM cell (6T SRAM cell), and IC layout diagram / IC device 600 features one or more instances of a seven-transistor SRAM cell (7T SRAM cell). In each embodiment, the SRAM cell has a total of four CFETs arranged as discussed below.

[0039] In some embodiments, an IC layout diagram 200-600 corresponds to a single instance of an SRAM cell configured to be stored in a mass storage device, e.g., a cell library such as cell library 1007, discussed below in relation to IC layout diagram creation system 1000, which at least partially defines the corresponding SRAM device 200-600 within a corresponding area of ​​an IC manufactured based on the cell.

[0040] In some embodiments, an IC layout diagram 200-600 corresponds to several instances of the SRAM cell that is configured to be stored in a mass storage device, e.g., a layout library such as layout diagram(s) 1009, which is discussed below in relation to IC layout diagram creation system 1000, which defines at least partially corresponding several instances of SRAM device 200-600 within one or more corresponding areas of an IC that is manufactured based on the IC layout diagram.

[0041] The structural elements within a given instance of IC layout diagram / IC device 200, 300 or 500 are arranged according to the schematic diagram of SRAM cell 100, which is shown in Fig. 1 is shown. As in Fig. As shown in Figure 1, SRAM cell 100 corresponds to a 6T SRAM device comprising two series connections of a p-type pull-up transistor PU and an n-type pull-down transistor PD, which are cross-coupled between a power supply voltage node VDD and a reference voltage node VSS. Corresponding instances of an internal node ND (corresponding to one or more contact and / or interconnect regions / structures ND) are coupled to bit lines BL / BLB by instances of an n-type pass-gate transistor PG, each instance having a gate coupled to a word line WL. In some embodiments, one or both instances of pull-down transistor PG are p-type transistors and / or one or both instances of pass-gate transistor PG, also referred to as a single pass-gate PG in some embodiments, are p-type transistors.

[0042] The structural elements within a given instance of IC layout diagram / IC device 400 are arranged according to the schematic diagram of SRAM cell 400, which is shown in Fig. 4A is shown. As in Fig. As shown in Figure 4A, SRAM cell 400 corresponds to a 6T SRAM device having two series connections of an n-type pull-up transistor PU and a p-type pull-down transistor PD, which are cross-coupled between the power supply voltage node VDD and the reference voltage node VSS. The corresponding instances of internal node ND are coupled to bit lines BL / BLB by instances of a p-type pass-gate transistor PG, each instance having a gate coupled to a word line WL.

[0043] The structural elements of a given instance of IC layout diagram / IC device 600 are arranged according to the schematic diagram of SRAM cell 100, which is shown in Fig. Figure 1 shows the addition of a p-type read-pass-gate transistor RPG, also referred to as a read-pass-gate RPG in some embodiments, through which an instance of node ND is coupled to a read-bit line (not shown). In some embodiments, the read-pass-gate transistor RPG is an n-type transistor.

[0044] In operation, an instance of IC device 200-600 is configured to receive / output data bits from bit lines BL / BLB via pass-gate transistors PG, which respond to word line signals received on word line WL, and to store the data bits as complementary pairs on internal nodes ND. In some embodiments, bit lines BL / BLB are referred to as complementary bit lines BL / BLB, bit line pair BL / BLB, or complementary bit line pair BL / BLB.

[0045] In the embodiments described in Fig. As shown in Figures 2-6, each corresponding IC layout diagram / IC device 200-600 features a first CFET having a first instance of a pass-gate transistor PG positioned at a first height along the Z direction, a second CFET having a first pull-down transistor positioned at the first height and a first pull-up transistor positioned at a second height along the Z direction, a third CFET having a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height, and a fourth CFET having a second pass-gate transistor positioned at the first height.

[0046] In the embodiments described in Fig. As shown in Figures 2A-6, the first height lies further along a positive Z-direction than the second height lies along the positive Z-direction. In some embodiments, the second height lies further along the positive Z-direction than the first height.

[0047] Each of the first and second pull-down transistors has an instance of Gate G extending in the X direction and having output working configuration WF1, and each of the first and second pass-gate transistors has an instance of Gate G extending in the X direction and having a second output working configuration WF1 that differs from output working configuration WF2.

[0048] As in Fig. As shown in Figure 2A-7, a given exit working configuration WF1-WF4 refers either to a structure in a corresponding IC layout diagram 200-600 or to the corresponding arrangement of one or more exit working materials in the corresponding IC device 200-600.

[0049] As in Fig. 2C, Fig. 3E, Fig. 5B and Fig. As shown in Figure 6, an output working configuration WF1-WF,4 structure has one or more areas of the corresponding IC layout diagram 200-600 in which each instance of a corresponding n or p transistor is set up to contain the corresponding one or more output working materials in the corresponding one or more instances of IC device 200-600.

[0050] In various embodiments, one or more regions of an output work configuration WF1-WF4 structure are arranged in an IC layout diagram based on one or more SRAM cells that have been previously configured to have the corresponding output work configuration WF1-WF4 that is placed in the IC layout diagram, or based on the one or more SRAM cells that are placed in the IC layout diagram followed by the corresponding output work configuration WF1-WF4 that is applied to the previously placed one or more SRAM cells.

[0051] Fig. Figure 7 shows IC layout diagram / IC device 700, a non-restrictive example of an instance of Gate G containing one or more exit working materials in accordance with one of exit working configurations WF1-WF4, commonly referred to as exit working configuration WF in Fig. 7 are shown.

[0052] In the embodiment shown in Fig. Figure 7, comprising IC layout diagram / IC device 700, also referred to as Gate 700 in some embodiments, the one or more exit working materials surrounding three instances of Gate dielectric GD, each of which surrounds a corresponding channel region of an active area / region AA. In some embodiments, Gate 700 has fewer or more than three instances of Gate dielectric GD surrounding corresponding channel regions.

[0053] As in Fig. As shown in Figure 2A-2C, IC layout diagram / IC device 200 features the four CFETs arranged in two rows extending in the X direction (corresponding to instances of Gate G), in which a first pull-down transistor PD is aligned with a first pass-gate transistor PG in the X direction and with a second pass-gate transistor PG in the Y direction, and a second pull-down transistor PD is aligned with the first pass-gate transistor in the Y direction and with the second pass-gate transistor PG in the X direction.

[0054] Each of Fig. 2A and Fig. Figure 2B shows a non-restrictive example of IC layout diagram / IC device 200, which has an internal node ND configuration on the back side BS of substrate SUB (not labeled). In the embodiment shown in Fig. 2A exhibit internal nodes ND instances of a backside contact area / backside contact structure CT and a through-hole contact area / through-hole contact structure BM0_V and in the Fig. In the embodiment shown in Figure 2B, internal nodes ND have instances of interconnect area / structure ND. Other configurations of internal node ND are within the scope of this disclosure.

[0055] As in Fig. As shown in Figures 3A-3E, IC layout diagram / IC device 300 features the four CFETs arranged in two rows extending in the X direction (corresponding to instances of Gate G), in which a first pull-down transistor PD is aligned with a second pull-down transistor PD in the X direction and with a first pass-gate transistor PG in the Y direction, and a second pass-gate transistor PG is aligned with the first pass-gate transistor PG in the X direction and with the second pull-down transistor PD in the Y direction.

[0056] Fig. Figure 3A shows a non-restrictive example of IC layout diagram / IC device 300, which has the configuration(s) of internal node ND on each of the front FS and back BS of substrate SUB (unlabeled). In the Fig. In the embodiment shown in Figure 3A, the internal nodes ND have corresponding front- and back-facing instances of interconnect area / structure ND and through-hole areas / structures VG and VDR. Other front- and / or back-facing configurations of internal node ND are within the scope of this disclosure.

[0057] Fig. 3A further shows non-restrictive examples of reference voltage lines VSS and bit lines BL and BLB of front-side conductive structural elements and power supply voltage lines BM0_VDD and word lines BM0_WL of rear-side conductive structural elements, each of which is electrically connected to IC layout diagram / IC device 300 by corresponding vias VD and VG.

[0058] As in Fig. As shown in Figure 3B-3D, instances of vias VD and VDR extend in the Z direction through one or more dielectric layers, e.g., dielectric interlevel layers ILD1 and ILD2. Each instance of pass-gate transistor PG and pull-down transistor PD has one instance of gate G and two S / D regions SD, which have n-epitaxial regions / layers N epi, and each instance of pull-up transistor PU has one instance of gate G and two S / D regions SD, which have p-epitaxial regions / layers P epi. A substrate region SUB at the same height along the Z direction as pull-up transistors PU is not shown in a transistor and instead has a dielectric layer ILD.

[0059] As in Fig. As shown in 4A-4C, IC layout diagram / IC device 400 features the four CFETs in an arrangement similar to that of IC layout diagram / IC device 300, except that pass-gate transistors PG and pull-down transistors PD are implemented as p-transistors and not as n-transistors, and pull-down transistors PD are implemented as n-transistors and not as p-transistors.

[0060] Therefore, the positioning of pass-gate transistors PG, pull-down transistors PD, pull-down transistors PD and electrical connections to power supply voltage VDD, reference voltage VSS, bit lines BL and BLB and word lines WL in relation to the Z direction is reversed relative to the positioning in IC layout diagram / IC device 300.

[0061] Since IC layout diagrams / IC devices 300 and 400 have the same positioning with respect to the X and Y directions, the output working configuration structure of IC layout diagram / IC device 300, which is shown in Fig. 3E is shown for IC layout diagram / IC device 400.

[0062] As in Fig. 5A and Fig. As shown in Figure 5B, IC layout diagram / IC device 500 features the four CFETs arranged in a single column extending in the Y direction, in which pull-down transistors PD are positioned between pass-gate transistors PG.

[0063] As in Fig. Figure 5A shows an IC layout diagram / IC device with 500 configurations of internal node ND on each of the front FS and back BS of substrate SUB (not marked). In the Fig. In the embodiment shown in Figure 3A, the internal nodes ND have corresponding front and back instances of contact area / structure CT, interconnect area / structure ND, and through-hole contact areas / structures VD and VG. Other front and / or back configurations of internal node ND are within the scope of this disclosure.

[0064] As in Fig. As shown in Figure 6, IC layout diagram / IC device 600 features the four CFETs in an arrangement similar to that of IC layout diagram / IC device 500, with the addition of a read-pass-gate transistor RPG at the same height as the pull-up transistors PU. The pull-up transistors PU have instances of gate G having output function configuration WF3, and the read-pass-gate transistor RPG has an instance of gate G having output function configuration WF4, which differs from output function configuration WF3.

[0065] In various embodiments, the output working configuration WF3 is the same or different from the output working configuration WF1 and / or the output working configuration WF4 is the same or different from the output working configuration WF2.

[0066] Through the configurations discussed above, each of the IC layout diagrams / IC devices 200-600 has an SRAM device that has CFETs in which first and second pull-down transistors PD are positioned in a first height in the Z direction and have gates G with output function configuration WF1, and first and second pass-gate transistors PG are positioned in the first height and have gates G with output function configuration WF2, which differs from output function configuration WF.

[0067] Pass-gate transistors PG and pull-down transistors PD, which have gates G with different output function configurations WF1 and WF2, are able to have tunable relative threshold voltage levels, so that, compared with other methods, e.g., those in which pass-gate and pull-down transistors have the same threshold voltage level, each of IC layout diagrams / IC devices 200-600 is able to have improved read current characteristics, making operation at reduced power supply levels possible, and shortened read windows corresponding to relatively higher operating speeds are possible for a given power supply voltage level.

[0068] In some embodiments, for a given set of operating conditions, a pull-down transistor PD has a first saturation current Isat PD, a pass-gate transistor PG has a second saturation current Isat PG, and a ratio of Isat PD to Isat PG, in some embodiments referred to as a beta ratio, corresponds to a read window of an SRAM device, with increasing beta ratio values ​​corresponding to an increased operating speed.

[0069] For the given set of operating conditions, the saturation currents Isat PD and Isat PG have values ​​based on the threshold voltages of the pull-down transistor PD and the pass-gate transistor PG, as controlled by the output function configurations WF1 and WF2, respectively. With the configurations discussed above, each of the IC layout diagrams / IC devices 200-600 is therefore capable of achieving beta ratio values ​​greater than one, thus yielding the advantages discussed above.

[0070] Fig. Figure 8 is a flowchart of Method 800 for manufacturing an IC device according to some embodiments. Method 800 is operable to form some or all of one or more instances of one or more of IC devices 200-600, as above with respect to Fig. 1-7 discussed.

[0071] In some embodiments, performing some or all of the operations of Method 800 is part of constructing a plurality of IC devices, e.g. transistors, logic gates, memory cells, interconnect structures and / or other suitable devices, by performing several fabrication operations, e.g. one or more of lithography, diffusion, deposition, etching, planarization or other operations suitable for constructing the plurality of IC devices in a semiconductor substrate.

[0072] In some embodiments, the operations of method 800 are performed in the order described in Fig. Figure 8 is shown. In some embodiments, the operations of Method 800 are performed in a different order than the order shown in Figure 800. Fig. Figure 8 is shown. In some embodiments, one or more additional operations are performed before, during, and / or after the operations of Method 800. In some embodiments, performing some or all of the operations of Method 800 includes performing one or more operations as shown below with respect to IC fabrication system 1100 and Fig. 11 discussed.

[0073] In some embodiments of Operation 802, a substrate, e.g., a semiconductor substrate, is provided. In some embodiments, providing the substrate includes providing substrate SUB, as above in relation to Fig. 1-7 discussed.

[0074] In Operation 804, an SRAM device is constructed on a front face of the substrate, the SRAM device comprising the first through fourth CFETs. The first through fourth CFETs are constructed by constructing the first CFET, which has a first pass-gate transistor positioned at a first height along a first direction; the second CFET, which has a first pull-down transistor positioned at the first height and a first pull-up transistor positioned at a second height along the first direction; the third CFET, which has a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height; and the fourth CFET, which has a second pass-gate transistor positioned at the first height.Constructing each of the first and second pull-down transistors involves forming a gate that extends in a second direction perpendicular to the first direction and has a first output work configuration, and constructing each of the first and second pass-gate transistors involves forming a gate that extends in the second direction and has a second output work configuration that differs from the first output work configuration.

[0075] In some embodiments, designing the SRAM device includes designing one of 200-600 IC devices, as described above in relation to Fig. 1-7 discussed. In some embodiments, constructing the SRAM device includes constructing multiple SRAM devices containing the SRAM device, e.g., several of one or more IC devices 200-600, as above in relation to Fig. 1-7 discussed.

[0076] In some embodiments, forming the gates extending in the second direction and having the first and second output work configurations includes forming instances of Gate G having output work configuration WF1 or WF2 and / or having output work configuration WF3 or WF4, as described above in relation to Fig. 1-7 discussed.

[0077] In some embodiments, the first direction extends in a positive direction from a back side of the substrate to the front side of the substrate, and the construction of each of the first and second pull-down transistors and the first and second pass-gate transistors involves constructing the first and second pull-down transistors and the first and second pass-gate transistors in the first height that is further along the first direction in the positive direction than the second height, e.g., further along the positive Z-direction, as above with respect to Fig. 2-7 discussed.

[0078] In some embodiments, constructing each of the first and second pull-up transistors involves constructing a p-transistor, and constructing each of the first and second pull-down transistors and the first and second pass-gate transistors involves constructing an n-transistor, as e.g. above with respect to Fig. 1-7 discussed.

[0079] In some embodiments, constructing the first and second pull-down transistors involves aligning the first pull-down transistor with the first pass-gate transistor in the second direction and with the second pass-gate transistor in a third direction, perpendicular to both the first and second directions, and aligning the second pull-down transistor with the first pass-gate transistor in the third direction and with the second pass-gate transistor in the second direction, e.g., as above with reference to IC layout diagram / IC device 200 and Fig. 2A-2C discussed.

[0080] In some embodiments, constructing the first and second pull-down transistors involves aligning the first pull-down transistor with the second pull-down transistor in the second direction and with the first pass-gate transistor in the third direction, and aligning the second pass-gate transistor with the first pass-gate transistor in the second direction and with the second pull-down transistor in the third direction, e.g., as shown above with reference to IC layout diagrams / IC devices 300 and 400. Fig. 3A-4C discussed.

[0081] In some embodiments, constructing the first and second pull-down transistors involves aligning the first and second pull-down transistors and the first and second pass-gate transistors with each other in the third direction, and positioning the first and second pull-down transistors between the first and second pass-gate transistors, as shown above in relation to IC layout diagrams / IC devices 500 and 600. Fig. 5A-6 discussed.

[0082] In some embodiments, constructing each of the first and second pull-up transistors includes forming a gate extending in the second direction and having a third output working configuration, and constructing the first CFET includes constructing a read-pass gate transistor positioned at the second height, comprising forming a gate extending in the second direction and having a fourth output working configuration that differs from the third output working configuration, e.g., as above with respect to IC layout diagram / IC device 600 and Fig. 6 discussed.

[0083] Designing the SRAM device, which includes the first to fourth CFETs, involves performing several manufacturing processes, including one or more of lithography, diffusion, implantation, deposition, plasma treatment, etching, planarizing, spin coating, soft baking, exposure, post-baking, developing, rinsing, drying, or any other suitable operation.

[0084] In Operation 806, electrical connections to the SRAM device are formed in some embodiments. In some embodiments, forming the electrical connections includes forming one or more front and / or rear conductive lines, e.g., one or more instances of bit line BL / BLB, word line WL, power supply voltage line VDD, and / or reference voltage line VSS, as described above in relation to Fig. 1-7 discussed.

[0085] In some embodiments, forming the electrical connections includes forming one or more front and / or rear vias, e.g., those corresponding to one or more instances of bit line BL / BLB, word line WL, power supply voltage line VDD, and / or reference voltage line VSS, as described above in relation to Fig. 1-7 discussed.

[0086] Forming the electrical connections involves performing several manufacturing operations, including depositing and structuring one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, thereby establishing one or more conductive materials to form several continuous, low-resistance structures.

[0087] By performing some or all of the operations of Procedure 800, an IC device is produced in which an SRAM device has first and second pass-gate transistors positioned at a first height and having gates with a first output working configuration, and first and second pull-down transistors positioned at the first height and having gates with a second output working configuration that differs from the first output working configuration, thereby making it possible to achieve the advantages discussed above with respect to IC devices 200-700.

[0088] Fig. Figure 9 is a flowchart of procedure 900 for creating an IC layout diagram, e.g., one or more instances of one or more of IC layout diagrams 200-600, as above in relation to Fig. 1-7 discussed according to some embodiments.

[0089] In some embodiments, creating the IC layout diagram includes creating the IC layout diagram according to an IC device, e.g., one or more of IC devices 200-600, as described above in relation to Fig. 1-7 discussed, which are manufactured based on the created IC layout diagram.

[0090] In some embodiments, some or all of method 900 are performed by a computer processor, e.g., a processor 1002 of an IC layout diagram creation system 1000, as below with respect to Fig. 10 discussed.

[0091] Some or all of the operations of Procedure 900 can be performed as part of a design procedure carried out in a design house, e.g., a design house 1120, as described below in relation to Fig. 11 discussed.

[0092] In some embodiments, the operations of Method 900 are performed in the order described in Fig. Figure 9 is shown. In some embodiments, the operations of Method 900 are performed simultaneously and / or in a different order than the order shown in Figure 900. Fig. 9 is shown. In some embodiments, one or more operations are performed before, between, during and / or after performing one or more operations of method 900.

[0093] In Operation 902, in some embodiments, the first to fourth CFETs of an SRAM cell are arranged, comprising the first and second pass-gate transistors in a first row and the first and second pull-down transistors in a second row, as shown above in relation to IC layout diagrams / IC devices 300 and 400. Fig. 3A-4C discussed.

[0094] In some embodiments, arranging the first to fourth CFETs of the SRAM cell, which have the first and second pass-gate transistors in the first row and the first and second pull-down transistors in the second row, includes arranging each of the first and second pass-gate transistors and first and second pull-down transistors, which are n-transistors, e.g., as above with respect to IC layout diagram / IC device 300 and Fig. 3A-3E discussed.

[0095] In some embodiments, arranging the first to fourth CFETs of the SRAM cell, which have the first and second pass-gate transistors in the first row and the first and second pull-down transistors in the second row, includes arranging each of the first and second pass-gate transistors and first and second pull-down transistors, which are p-transistors, e.g., as above with respect to IC layout diagram / IC device 400 and Fig. 4A-4C discussed.

[0096] In Operation 904, in some embodiments, an SRAM cell is positioned in an IC layout diagram, wherein the SRAM cell has first through fourth CFETs, each having a first and second pass-gate transistor and a first and second pull-down transistor positioned at the same level. In some embodiments, positioning the SRAM cell in the IC layout diagram involves positioning one or more instances of one or more of IC layout diagrams 200-600, as described above. Fig. 1-7 discussed.

[0097] In some embodiments, positioning the SRAM cell in the IC layout diagram includes positioning the SRAM cell, which has the first to fourth CFETs arranged in two rows and two columns, as above with reference to IC layout diagrams 200-400 and Fig. 2A-4C discussed.

[0098] In some embodiments, positioning the SRAM cell in the IC layout diagram includes positioning the SRAM cell, which has the first to fourth CFETs arranged in a single column, e.g., as above with respect to IC layout diagrams 500 and 600. Fig. 5A-6 discussed.

[0099] In some embodiments, positioning the SRAM cell in the IC layout diagram includes positioning the SRAM cell, which has two or more output working configurations, e.g., two or more output working configurations WF1-WF4, as described above. Fig. 1-7 discussed.

[0100] In some embodiments, positioning the SRAM cell in the IC layout diagram includes positioning multiple instances of an SRAM cell in one or more of IC layout diagrams 200-600, as above in relation to Fig. 1-7 discussed.

[0101] In some embodiments, positioning the SRAM cell in the IC layout diagram includes arranging one or more electrical connections on the SRAM cell, e.g., one or more connections corresponding to the power supply voltage VDD, reference voltage VSS, bit lines BL / BLB, and / or word lines WL, as described above. Fig. 1-7 discussed.

[0102] In Operation 906, in some embodiments, a first structure of a first output-function configuration, comprising each of the first and second pull-down transistors, is arranged. In some embodiments, arranging the first structure of the first output-function configuration, comprising each of the first and second pull-down transistors, includes arranging the first structure according to output-function configuration WF1, as described above with respect to Fig. 1-7 discussed.

[0103] In some embodiments, arranging the first structure of the first output function configuration, which includes each of the first and second pull-down transistors, comprises arranging a third structure according to output function configuration WF3, as above with respect to Fig. 6 discussed.

[0104] In Operation 908, in some embodiments, a second structure of a second output-function configuration, comprising both the first and second pass-gate transistors, is arranged. In some embodiments, arranging the second structure of the second output-function configuration, comprising both the first and second pass-gate transistors, includes arranging the second structure according to output-function configuration WF2, as described above with respect to Fig. 1-7 discussed.

[0105] In some embodiments, arranging the second structure of the second output function configuration, which includes both the first and second pass-gate transistors, comprises arranging a fourth structure corresponding to output function configuration WF4, as described above in relation to Fig. 6 discussed.

[0106] In Operation 910, in some embodiments, the IC layout diagram comprising the SRAM cell(s) is stored in a mass storage device. In some embodiments, storing the IC layout diagram in the mass storage device comprises storing one or more instances of one or more of the IC layout diagrams 200-600, as described above. Fig. 1-7 discussed, in the mass storage device.

[0107] In some embodiments, storing the IC layout diagram in the mass storage device includes storing the IC layout diagram in non-volatile, computer-readable memory or a database and / or includes storing the IC layout diagram over a network. In some embodiments, storing the IC layout diagram in the mass storage device includes storing the IC layout diagram in cell library 1007 or layout diagrams 1009 and / or over a network 1014 from the IC layout diagram creation system 1000, which is described below in relation to Fig. 10 has been discussed.

[0108] In Operation 912, in some embodiments, one or more manufacturing operations, one or more lithographic exposures, are performed based on the IC layout diagram. Non-limiting examples of performing one or more manufacturing operations, e.g., one or more lithographic exposures, based on the IC layout diagram are given above in relation to Fig. 8 and below in relation to Fig. 11 discussed.

[0109] By performing some or all of the operations of Procedure 900, an IC layout diagram is created according to an IC device in which first and second pass-gate transistors are positioned in a first height and have gates with a first output working configuration, and first and second pull-down transistors are positioned in the first height and have gates with a second output working configuration that differs from the first output working configuration, thereby making it possible to achieve the advantages discussed above with respect to IC devices 200-700.

[0110] Fig. Figure 10 is a block diagram of IC layout diagram creation system 1000 according to some embodiments. Methods described herein for creating IC layout diagrams according to one or more embodiments can be implemented, for example, using IC layout diagram creation system 1000 according to some embodiments.

[0111] In some embodiments, the IC layout diagram creation system 1000 is a general-purpose computing device comprising a hardware processor 1002 and a non-transient, computer-readable mass storage medium 1004. The mass storage medium 1004 is encoded with, among other things, computer program code 1006, i.e., a set of executable instructions. Execution of instructions 1006 by the hardware processor 1002 provides (at least partially) an electronic design automation (EDA) tool that implements part or all of a method, e.g., method 600 for creating an IC layout diagram, as described above. Fig. 6 is described (hereinafter the processes and / or procedures mentioned).

[0112] Processor 1002 is electrically coupled to computer-readable mass storage medium 1004 via a bus 1008. Processor 1002 is also electrically coupled to an I / O interface 1010 via bus 1008. A network interface 1012 is also electrically connected to Processor 1002 via bus 1008. Network interface 1012 is connected to a network 1014, enabling Processor 1002 and computer-readable mass storage medium 1004 to connect to external elements via network 1014. Processor 1002 is configured to execute computer program code 1006 encoded in computer-readable mass storage medium 1004 to enable IC layout diagram creation system 1000 to perform some or all of the processes and / or procedures listed.In one or more embodiments, processor 1002 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0113] In one or more embodiments, computer-readable mass storage medium 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, computer-readable mass storage medium 1004 comprises semiconductor or solid-state memory, magnetic tape, removable computer disk, random-access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In one or more embodiments in which optical disks are used, computer-readable mass storage medium 1004 comprises read-only memory for compact discs (CD-ROM), a read / write compact disc (CD-R / W), and / or a digital video disc (DVD).

[0114] In one or more embodiments, computer-readable mass storage medium 1004 stores computer program code 1006, which is configured to enable the IC layout diagram creation system 1000 (where such an embodiment (at least partially) constitutes the EDA tool) to be used for carrying out some or all of the processes and / or procedures listed. In one or more embodiments, computer-readable mass storage medium 1004 also stores information that facilitates the carrying out some or all of the processes and / or procedures listed.

[0115] In one or more embodiments, a computer-readable mass storage medium 1004 stores a cell library 1007 of cells, containing such cells as disclosed herein, e.g., memory cells 200-600, as above in relation to Fig. 1-7 discussed.

[0116] In one or more embodiments, computer-readable mass storage medium 1004 stores layout diagrams 1009, containing such IC layout diagrams as disclosed herein, e.g., IC layout diagrams having memory cells 200-600, as above in relation to Fig. 1-7 discussed.

[0117] The IC layout diagram creation system 1000 has an I / O interface 1010. The I / O interface 1010 is coupled to an external circuit. In one or more embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, trackpad1, touchscreen, and / or cursor keys for transmitting information and commands to the processor 1002.

[0118] The IC layout diagram system 1000 also features a network interface 1012, which is coupled to the processor 1002. Network interface 1012 enables the system 1000 to communicate with a network 1014, to which one or more other computer systems are connected. Network interface 1012 features wireless network interfaces, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or procedures mentioned are implemented in two or more IC layout diagram systems 1000.

[0119] The IC layout diagram system 1000 is configured to receive information through I / O interface 1010. The information received through I / O interface 1010 contains one or more instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by processor 1002. The information is transmitted to processor 1002 via bus 1008. The IC layout diagram system 1000 is also configured to receive information regarding a user interface (UI) through I / O interface 1010. This information is stored on the computer-readable medium 1004 as a user interface (UI) 1042.

[0120] In some embodiments, some or all of the processes and / or methods listed are implemented as a standalone software application for execution by a processor. In some embodiments, some or all of the processes and / or methods listed are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the processes and / or methods listed are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods listed is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the processes and / or methods listed are implemented as a software application used by the IC Layout Diagram Creation System 1000.In some embodiments, a layout diagram containing standard cells is created using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout creation tool.

[0121] In some embodiments, the processes are implemented as functions of a program stored in a non-transient, computer-readable recording medium. Examples of a non-transient, computer-readable recording medium include, but are not limited to, external / removable and / or internal / built-in memory or storage units, such as one or more optical discs like a DVD, magnetic disks like a hard disk, semiconductor memory such as a ROM, RAM, memory card, and the like.

[0122] Fig. Figure 11 is a block diagram of IC fabrication system 1100 and an associated IC fabrication process according to some embodiments. In some embodiments, based on an IC layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor IC is fabricated using fabrication system 1100.

[0123] In Fig. System 11100 comprises IC manufacturing system 1100 units, such as a design house 1120, a mask house 1130, and an IC manufacturer / fabricator (“fab”) 1150, which interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of an IC device 1160. The units in system 1100 are interconnected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is a set of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each unit interacts with one or more of the other units, providing services to and / or receiving services from one or more of the other units.In some embodiments, two or more of Design House 1120, Mask House 1130, and IC fab 1150 are owned by a single larger company. In some embodiments, two or more of Design House 1120, Mask House 1130, and IC fab 1150 exist side-by-side in a shared facility and use common resources.

[0124] Design House (or Design Team) 1120 creates an IC design layout diagram 1122. IC design layout diagram 1122 exhibits various geometric structures, e.g., one or more of IC layout diagrams 200-700, as above in relation to Fig. 1-7 discussed. The geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of IC device 1160 to be manufactured. The different layers are combined to form various IC structural elements. For example, part of IC design layout diagram 1122 has various IC structural elements, such as an active region, gate electrode, source and drain, metal traces or vias of an interlayer interconnect, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers arranged on the semiconductor substrate. Design house 1120 implements a suitable design procedure to form IC design layout diagram 1122. The design procedure includes one or more steps of logic design, physical design, or placement and routing.IC design layout diagram 1122 is represented in one or more data files containing information about the geometric structures. For example, IC design layout diagram 1122 can be expressed in a GDSII or DFII file format.

[0125] Mask House 1130 includes Data Preparation 1132 and Mask Fabricator 1144. Mask House 1130 uses IC Design Layout Diagram 1122 to fabricate one or more masks 1145, which are used to fabricate the various layers of IC Device 1160 according to IC Design Layout Diagram 1122. Mask House 1130 performs Mask Data Preparation 1132, where IC Design Layout Diagram 1122 is translated into a representative data file (RDF). Mask Data Preparation 1132 provides the RDF to Mask Fabricator 1144. Mask Fabricator 1144 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticule) 1145 or a semiconductor wafer 1153. The design layout diagram 1122 is manipulated by the mask data preparation 1132 to meet certain properties of the mask writer and / or requirements of IC fab 1150. Fig.Figure 11 illustrates mask data preparation 1132 and mask production 1144 as separate elements. In some embodiments, mask data preparation 1132 and mask production 1144 can be referred to collectively as mask data preparation.

[0126] In some embodiments, mask data preparation 1132 incorporates optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image defects such as those that may arise from diffraction, interference, other process effects, and the like. OPC adapts the IC design layout diagram 1122. In some embodiments, mask data preparation 1132 further incorporates resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution supporting structural elements, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography (ILT) technology is also used, in which OPC is treated as an inverse imaging problem.

[0127] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that checks the IC design layout diagram 1122, which has undergone processes in OPC, against a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to accommodate variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout diagram 1122 to compensate for constraints during mask manufacturing 1144, which may undo some of the changes made by OPC to satisfy the mask creation rules.

[0128] In some embodiments, mask data preparation 1132 includes lithography process checking (LPC), which simulates the processing implemented by IC fab 1150 to manufacture IC fixture 1160. LPC simulates this processing based on IC design layout diagram 1122 to generate a simulated manufactured fixture, such as IC fixture 1160. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, after generating a simulated manufacturing fixture by LPC, if the simulated fixture does not come close enough to the design rules, OPC and / or MRC are repeated to further refine the IC design layout diagram 1122.

[0129] It should be clear that the preceding description of a mask data preparation 1132 has been simplified for clarity. In some embodiments, data preparation 1132 includes additional structural elements, such as a logical operation (LOP), to modify the IC design layout diagram 1122 according to manufacturing rules. Additionally, the processes applied to the IC design layout diagram 1122 during data preparation 1132 can be executed in various different sequences.

[0130] Following mask data preparation 1132 and during mask fabrication 1144, a mask 1145 or a group of masks 1145 is fabricated based on the modified IC design layout diagram 1122. In some embodiments, mask fabrication 1144 includes performing one or more lithographic exposures based on the IC design layout diagram 1122. In some embodiments, an electron beam (E-beam) or a mechanism of multiple E-beams is used to form a structure on a mask (photomask or reticulum) 1145 based on the modified IC design layout diagram 1122. The mask 1145 can be formed using various technologies. In some embodiments, the mask 1145 is formed using a binary technology. In some embodiments, a mask structure has opaque and transparent regions.An irradiation beam, such as an ultraviolet (UV) or EUV beam, used to expose the image-sensitive material layer (e.g., photoresist) deposited on a wafer, is blocked by the opaque region and passes through the transparent regions. In one example, a binary mask version of Mask 1145 has a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) deposited in the opaque regions of the binary mask. In another example, Mask 1145 is formed using a phase-shift technology. In a phase-shift mask version (PSM version, phase-shift mask) of Mask 1145, various structural elements in the structure formed on the phase-shift mask are configured to have appropriate phase differences to improve resolution and image quality.In various examples, the phase-shift mask can be a weakened PSM or an alternating PSM. The mask(s) produced by mask fabrication 1144 is / are used in numerous processes. For example, such a mask is / are used in an ion implantation process to form different doped regions in semiconductor wafer 1153, in an etching process to form different etched regions in semiconductor wafer 1153, and / or in other suitable processes.

[0131] IC-fab 1150 is an IC manufacturing facility that includes one or more production lines for manufacturing several different IC products. In some configurations, IC-fab 1150 is a semiconductor foundry. For example, there may be one production line for the front-end manufacturing of several IC products (front-end-of-line (FEOL) manufacturing), while a second production line can provide back-end manufacturing for interconnection and packaging of the IC products (back-end-of-line (BEOL) manufacturing), and a third production line can provide other services for the foundry business.

[0132] IC fab 1150 comprises wafer fabrication tools 1152 configured to perform various fabrication operations on semiconductor wafers 1153, such that the IC device 1160 is fabricated in accordance with the mask(s), e.g., mask 1145. In various embodiments, the fabrication tools 1152 include one or more wafer steppers, ion implanters, photoresist coaters, process chambers (e.g., CVD chambers or LPCVD furnaces), CMP systems, plasma etching systems, wafer cleaning systems, or other fabrication equipment capable of performing one or more suitable fabrication processes as described herein.

[0133] IC fab 1150 uses mask(s) 1145, manufactured by mask house 1130, to fabricate IC device 1160. Therefore, IC fab 1150 uses at least indirectly IC design layout diagram 1122 to fabricate IC device 1160. In some embodiments, semiconductor wafer 1153 is fabricated by IC fab 1150 using mask(s) 1145 to form IC device 1160. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram 1122. Semiconductor wafer 1153 has a silicon substrate or other suitable substrate with material layers formed on it. Semiconductor wafer 1153 further features one or more different doped areas, dielectric structural elements, multi-level interconnects and the like (which are formed in subsequent manufacturing steps).

[0134] In some embodiments, an IC device includes an SRAM device positioned in a substrate, wherein the SRAM device comprises a first CFET having a first pass-gate transistor positioned at a first height along a first direction, a second CFET having a first pull-down transistor positioned at the first height and a first pull-up transistor positioned at a second height along the first direction, a third CFET having a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height, and a fourth CFET having a second pass-gate transistor positioned at the first height, each of the first and second pull-down transistors having a gate.which extends in a second direction perpendicular to the first direction and has a first output function configuration, and each of the first and second pass-gate transistors has a gate extending in the second direction and having a second output function configuration,which differs from the first output work configuration. In some embodiments, each of the first and second pull-down transistors and the first and second pass-gate transistors comprises an n-type transistor, and each of the first and second pull-up transistors comprises a p-type transistor. In some embodiments, the first direction extends in a positive direction from a back side of the substrate to a front side of the substrate, and the first height is further along the first direction in the positive direction than the second height. In some embodiments, the first pull-down transistor is aligned with the first pass-gate transistor in the second direction and with the second pass-gate transistor in a third direction, perpendicular to both the first and second directions.The first pull-down transistor is aligned in the first direction, and the second pull-down transistor is aligned in the third direction with the first pass-gate transistor and in the second direction with the second pass-gate transistor. In some embodiments, the first pull-down transistor is aligned in the second direction with the second pull-down transistor and in a third direction with the first pass-gate transistor, perpendicular to both the first and second directions. In some embodiments, the SRAM device has a first internal node having a first contact structure positioned on a front side of the substrate, and a second internal node having a second contact structure.which is positioned on a back side of the substrate. In some embodiments, each of the first and second pull-down transistors and the first and second pass-gate transistors has a p-type transistor, and each of the first and second pull-up transistors has an n-type transistor. In some embodiments, the first and second pull-down transistors and the first and second pass-gate transistors are aligned with each other in a third direction, perpendicular to both the first and second directions, and the first and second pull-down transistors are positioned between the first and second pass-gate transistors. In some embodiments, each of the first and second pull-up transistors has a gate extending in the second direction and having a third output work configuration; the first CFET has a read-pass-gate transistor positioned in the second height, and the read-pass-gate transistor has a gate,which extends in the second direction and has a fourth outlet work configuration that differs from the third outlet work configuration. In some embodiments, the ratio of a first saturation flow corresponding to the first outlet work configuration to a second saturation flow corresponding to the second outlet work configuration is greater than one.

[0135] In some embodiments, a method for fabricating an IC device comprises constructing, on a front face of a substrate, an SRAM device by constructing a first CFET having a first pass-gate transistor positioned at a first height along a first direction, constructing a second CFET having a first pull-down transistor positioned at the first height and a first pull-up transistor positioned at a second height along the first direction, constructing a third CFET having a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height, and constructing a fourth CFET having a second pass-gate transistor positioned at the first height, wherein constructing each of the first and second pull-down transistors comprises forming a gate.which extends in a second direction perpendicular to the first direction and has a first output function configuration, and constructing each of the first and second pass-gate transistors includes forming a gate that extends in the second direction and has a second output function configuration that differs from the first output function configuration. In some embodiments, the first direction extends in a positive direction from a back side of the substrate to a front side of the substrate. Constructing each of the first and second pull-up transistors includes constructing a p-transistor, and constructing each of the first and second pull-down transistors and the first and second pass-gate transistors includes constructing an n-transistor in the first height.which is further along the first direction in the positive direction than the second height. In some embodiments, constructing the first pull-down transistor includes aligning the first pull-down transistor with the first pass-gate transistor in the second direction and aligning it with the second pass-gate transistor in a third direction, perpendicular to both the first and second directions. Constructing the second pull-down transistor includes aligning it with the first pass-gate transistor in the third direction and aligning it with the second pass-gate transistor in the second direction. In some embodiments, constructing the first pull-down transistor includes aligning it with the second pull-down transistor in the second direction and aligning it with the first pass-gate transistor in a third direction.Constructing the second pull-down transistor includes aligning the second pass-gate transistor perpendicular to both the first and second directions, and aligning it with the first pass-gate transistor in the second direction and with the second pull-down transistor in the third direction. In some embodiments, constructing the first and second pull-down transistors and the first and second pass-gate transistors includes aligning them with each other in a third direction, perpendicular to both the first and second directions, with the first and second pull-down transistors positioned between the first and second pass-gate transistors. In some embodiments, constructing each of the first and second pull-up transistors includes forming a gate,which extends in the second direction and has a third output working configuration, constructing the first CFET includes constructing a read-pass-gate transistor positioned in the second height, and constructing the read-pass-gate transistor includes forming a gate that extends in the second direction and has a fourth output working configuration that differs from the third output working configuration.

[0136] In some embodiments, a method for creating an IC layout diagram comprises positioning an SRAM cell in the IC layout diagram, wherein the SRAM cell has a first CFET having a first pass-gate transistor positioned at a first height along a first direction, a second CFET having a first pull-down transistor positioned at the first height and a first pull-up transistor positioned at a second height along the first direction, a third CFET having a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height, and a fourth CFET having a second pass-gate transistor positioned at the first height, and arranging a first structure of a first output-work configuration having gates of each of the first and second pull-down transistors.Arranging a second structure of a second output-work configuration, different from the first output-work configuration, which includes gates of each of the first and second pass-gate transistors, and storing the IC layout diagram, which includes the SRAM cell, in a mass storage device. In some embodiments, positioning the SRAM cell in the IC layout diagram includes positioning the SRAM cell, which includes the first through fourth CFETs, arranged in two rows and two columns. In some embodiments, positioning the SRAM cell in the IC layout diagram includes positioning the SRAM cell, which includes the first through fourth CFETs, arranged in a single column. In some embodiments, positioning the SRAM cell in the IC layout diagram includes positioning multiple SRAM cells, which include the SRAM cell,which are aligned with each other in the IC layout diagram along a gate direction of the multiple SRAM cells, arranging the first structure of the first output-work configuration includes arranging a first continuous region of the first output-work configuration, which has corresponding gates of each corresponding first and second pull-down transistor of each SRAM cell of the multiple SRAM cells, and arranging the second structure of the second output-work configuration includes arranging a second continuous region of the second output-work configuration, which has corresponding gates of each corresponding first and second pass-gate transistor of each SRAM cell of the multiple SRAM cells.

[0137] The foregoing outlines features of some embodiments so that those skilled in the art will better understand the aspects of this disclosure. Those skilled in the art will appreciate that they can already use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent designs do not deviate from the nature and scope of this disclosure and that they can make various changes, substitutions, and modifications herein without deviating from the nature and scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 707,609

[0001]

Claims

[1] Integrated circuit device (IC device) comprising: a direct access memory device (SRAM device) positioned in a substrate, wherein the SRAM device comprises: a first complementary field-effect transistor (CFET) comprising a first pass-gate transistor positioned at a first height along a first direction, a second CFET which has a first pull-down transistor positioned at the first height and a first pull-up transistor positioned at a second height along the first direction, a third CFET, which has a second pull-down transistor positioned in the first height and a second pull-up transistor positioned in the second height, and a fourth CFET which has a second pass-gate transistor positioned in the first height, where Each of the first and second pull-down transistors has a gate that extends in a second direction perpendicular to the first direction and has a first output work configuration, and Each of the first and second pass-gate transistors has a gate that extends in the second direction and has a second output working configuration that differs from the first output working configuration. [2] IC device according to claim 1, wherein Each of the first and second pull-down transistors and of the first and second pass-gate transistors has an n-transistor and Each of the first and second pull-up transistors has a p-transistor. [3] IC device according to claim 1 or 2, wherein the first direction extends in a positive direction from a back of the substrate to a front of the substrate and The first height is further along the first direction in the positive direction than the second height. [4] IC device according to any one of claims 1 to 3, wherein the first pull-down transistor is aligned with the first pass-gate transistor in the second direction and with the second pass-gate transistor in a third direction, perpendicular to both the first and second directions, and the second pull-down transistor is aligned with the first pass-gate transistor in the third direction and with the second pass-gate transistor in the second direction. [5] IC device according to any one of claims 1 to 3, wherein the first pull-down transistor is aligned with the second pull-down transistor in the second direction and with the first pass-gate transistor in a third direction, perpendicular to both the first and second directions, and the second pass-gate transistor is aligned with the first pass-gate transistor in the second direction and with the second pull-down transistor in the third direction. [6] IC device according to claim 5, wherein the SRAM device further comprises: a first internal node that has a first contact structure positioned on a front side of the substrate; and a second internal node that has a second contact structure positioned on a back side of the substrate. [7] IC device according to claim 5 or 6, wherein Each of the first and second pull-down transistors and the first and second pass-gate transistors has a p-transistor and Each of the first and second pull-up transistors has an n-transistor. [8] IC device according to claim 1, wherein the first and second pull-down transistors and the first and second pass-gate transistors are aligned with each other in a third direction, perpendicular to both the first and second directions, and The first and second pull-down transistors are positioned between the first and second pass-gate transistors. [9] IC device according to claim 8, wherein Each of the first and second pull-up transistors has a gate extending in the second direction and a third output working configuration, the first CFET further features a read-pass-gate transistor positioned at the second height, and The read-pass-gate transistor has a gate that extends in the second direction and has a fourth output working configuration that differs from the third output working configuration. [10] IC device according to any one of claims 1 to 9, wherein a ratio of a first saturation current corresponding to the first work function configuration to a second saturation current corresponding to the second work function configuration is greater than one. [11] Method for manufacturing an IC device, comprising: Constructing, on a front face of a substrate, a static random access memory device (SRAM device), wherein the construction of the SRAM device comprises: Designing a first complementary field-effect transistor (CFET) comprising a first pass-gate transistor positioned at a first height along a first direction, Constructing a second CFET that has a first pull-down transistor positioned at the first height and a first pull-up transistor positioned at a second height along the first direction, Constructing a third CFET that has a second pull-down transistor positioned in the first height and a second pull-up transistor positioned in the second height, and Constructing a fourth CFET that has a second pass-gate transistor positioned at the first level, wherein The construction of each of the first and second pull-down transistors involves forming a gate that extends in a second direction perpendicular to the first direction and has a first output work configuration, and The construction of each of the first and second pass-gate transistors includes forming a gate that extends in the second direction and has a second output working configuration that differs from the first output working configuration. [12] Method according to claim 11, wherein the first direction extends in a positive direction from a back side of the substrate to a front side of the substrate, The construction of each of the first and second pull-up transistors includes the construction of a p-transistor and The construction of each of the first and second pull-down transistors and the first and second pass-gate transistors includes constructing an n-transistor in the first height, which is further along the first direction in the positive direction than the second height. [13] Method according to claim 11 or 12, wherein The construction of the first pull-down transistor involves aligning the first pull-down transistor with the first pass-gate transistor in the second direction and with the second pass-gate transistor in a third direction, perpendicular to both the first and second directions, and The construction of the second pull-down transistor involves aligning the second pull-down transistor with the first pass-gate transistor in the third direction and with the second pass-gate transistor in the second direction. [14] Method according to claim 11 or 12, wherein The construction of the first pull-down transistor involves aligning the first pull-down transistor with the second pull-down transistor in the second direction and with the first pass-gate transistor in a third direction, perpendicular to both the first and second directions, and The construction of the second pull-down transistor involves aligning the second pass-gate transistor with the first pass-gate transistor in the second direction and aligning it with the second pull-down transistor in the third direction. [15] Method according to any one of claims 11 to 14, comprising constructing the first and second pull-down transistor and the first and second pass-gate transistor: That the first and second pull-down transistors and the first and second pass-gate transistors are aligned with each other in a third direction, perpendicular to both the first and second directions, where the first and second pull-down transistors are positioned between the first and second pass-gate transistors. [16] Method according to claim 15, wherein The construction of each of the first and second pull-up transistors involves forming a gate that extends in the second direction and has a third output work configuration, The construction of the first CFET further includes the construction of a read-pass-gate transistor positioned at the second height, and Constructing the read-pass-gate transistor involves forming a gate that extends in the second direction and has a fourth output working configuration that differs from the third output working configuration. [17] Method for creating an IC layout diagram, the method comprising: Positioning a static random access memory cell (SRAM cell) in the IC layout diagram, wherein the SRAM cell has: a first complementary field-effect transistor (CFET) having a first pass-gate transistor positioned at a first height along a first direction; a second CFET comprising a first pull-down transistor positioned at the first height and a first pull-up transistor positioned at a second height along the first direction; a third CFET comprising a second pull-down transistor positioned in the first height and a second pull-up transistor positioned in the second height; and a fourth CFET which has a second pass-gate transistor positioned in the first height; Arranging a first structure of a first output work configuration, which includes gates of each of the first and second pull-down transistors; Arranging a second structure of a second output-function configuration, different from the first output-function configuration, which has gates of each of the first and second pass-gate transistors; and Storing the IC layout diagram that features the SRAM cell in a mass storage device. [18] Method according to claim 17, wherein positioning the SRAM cell in the IC layout diagram comprises positioning the SRAM cell having the first to fourth CFETs arranged in two rows and two columns. [19] Method according to claim 17, wherein positioning the SRAM cell in the IC layout diagram comprises positioning the SRAM cell having the first to fourth CFETs arranged in a single column. [20] Method according to any one of claims 17 to 19, wherein Positioning the SRAM cell in the IC layout diagram; positioning multiple SRAM cells, showing the SRAM cell in the IC layout diagram, aligned with each other along a gate direction that includes multiple SRAM cells, The arrangement of the first structure of the first output work configuration includes arranging a first continuous region of the first output work configuration, which has corresponding gates of each corresponding first and second pull-down transistor of each SRAM cell of the multiple SRAM cells, and The arrangement of the second structure of the second output work configuration includes arranging a second continuous region of the second output work configuration, which has corresponding gates of each corresponding first and second pass-gate transistor of each SRAM cell of the multiple SRAM cells.

Images