A GaN-based inverter and its preparation method

Abstract

The present invention relates to a GaN-based inverter. The GaN-based inverter includes an epitaxial substrate having a trench isolation groove formed therein. An E-mode device and a D-mode device are respectively provided on either side of the trench isolation groove. The E-mode device and the D-mode device are connected via metal wiring. The present invention applies the same CTL dielectric layer to the D-mode HEMT device to achieve regulation of the D-mode threshold voltage, thereby affecting the on-resistance of the D-mode device. This adjusts the resistance ratio of the E / D-mode devices in the on-state and the off-state, thereby optimizing the output swing and gain characteristics of the inverter. By adjusting the threshold voltage of the GaN D-mode device, the output swing and gain characteristics of the inverter are optimized, thereby maximizing the operating performance of the GaN-based inverter.

Description

Technical Field

[0001] The present invention belongs to the field of organic semiconductors, and in particular relates to a GaN-based inverter and a preparation method thereof. Background Art

[0002] GaN is a key semiconductor material for high-frequency power switching. The high switching frequency of GaN-based power converters can significantly reduce the size of passive components, such as capacitors and inductors, thereby increasing the power density of the entire system. Despite the many advantages of GaN power devices, separate Si-based logic control and gate drive remain the mainstream choice for controlling GaN power devices. As a result, in practical applications, GaN chips must deliberately reduce the switching speed of the device (hundreds of kHz) to avoid voltage spikes, electromagnetic interference, and ringing caused by parasitic capacitance and inductance between the peripheral drive circuit and the GaN device. This contradicts the high switching speed advantage of GaN power devices. On the other hand, the trend towards miniaturization of power electronic systems has created an urgent need for GaN power electronic devices with monolithic integrated drive circuits. Therefore, the monolithic integration of GaN drive circuits with GaN HEMMT power electronic devices is of great significance.

[0003] Due to the difficulty in implementing GaN p-FET process technology, research on GaN-based inverters has primarily focused on E / D mode n-FET (DCFL) inverters. The realization of GaN E-mode HEMTs has been a research hotspot in GaN fabrication processes. Numerous methods exist for realizing E-mode devices in GaN HEMT fabrication, including recessed gate etching, fluoride ion implantation, and p-GaN gate technology. Traditional recessed gate etching suffers from poor process repeatability and controllability, making it difficult to precisely control the etch depth, leading to over-etching or under-etching and making it difficult to stably control the threshold voltage of E-mode devices. Fluoride ion implantation, with its high ion energy, can easily introduce significant damage. Furthermore, the process suffers from weak controllability and poor uniformity, leading to unstable threshold voltages and thermal stability issues during the fabrication of E-mode devices. p-GaN gate technology has high requirements for epitaxial growth, and p-GaN etching is also a major difficulty in the current process preparation. If the p-GaN layer is not completely etched, the source-drain ohmic contact cannot be formed. Over-etching will damage the two-dimensional electron gas in the channel, thereby increasing the square resistance of the channel, resulting in an increase in the on-resistance of the device and a decrease in the device output current. There are also major defects in etching uniformity.

[0004] Therefore, in view of the above shortcomings, it is necessary to find a technical solution to solve the above problems in voltage regulation. Summary of the Invention

[0005] In response to the above-mentioned shortcomings, the present invention discloses a GaN-based inverter. The present invention is based on oxide materials such as Al2O3, HfAlO, and HfO2, which serve as the CTL dielectric layer of the E-mode device and the D-mode device in the inverter, thereby capturing the electrons in the two-dimensional electron gas channel in the gate region of the device, thereby changing the threshold voltage of the E-mode device and the D-mode device.

[0006] An object of the present invention is to provide a GaN-based inverter, comprising an epitaxial substrate having a trench isolation groove formed therein, an E-mode device and a D-mode device disposed on either side of the trench isolation groove, the E-mode device and the D-mode device being connected via metal wiring;

[0007] Wherein, the E-mode device and the D-mode device are both provided with a structural layer and a passivation layer, and the passivation layer partially or completely wraps the structural layer;

[0008] The structural layer includes a source electrode, a drain electrode, a gate electrode, and a CTL dielectric layer;

[0009] The source electrode and the drain electrode are deposited on both sides of the upper end surface of the epitaxial substrate, a CTL dielectric layer is deposited between the source electrode and the drain, and a gate electrode is deposited on the upper end surface of the CTL dielectric layer;

[0010] Metal pins penetrating the passivation layer are deposited on the source, the drain, and the gate, and the metal pin of the drain of the E-mode device is connected to the metal pin of the drain and the metal pin of the gate of the D-mode device through metal wires;

[0011] The CTL dielectric layer includes a tunneling layer, a charge trapping layer and a diffusion barrier layer in the direction away from the substrate;

[0012] The tunneling layer is selected from Al2O3;

[0013] The charge trapping layer is selected from one or more of HfAlO, ZnO, and HfO2;

[0014] The diffusion barrier layer is selected from one or more of Al2O3 and HfO2.

[0015] Preferably, the charge trapping layer is a HfAlO charge trapping layer;

[0016] Specifically, in the charge trapping layer, the deposition pulse ratio of Hf and Al is 1:1-10:1;

[0017] Furthermore, the thickness of the tunneling layer is 1-30 nm.

[0018] Furthermore, the charge trapping layer has a thickness of 1-15 nm.

[0019] Furthermore, the diffusion barrier layer has a thickness of 1-30 nm.

[0020] The CTL dielectric layer and tunneling layer in the technical solution of the present invention can ensure the effective writing of electrons and the stability of electrons in the off state after writing, and can maintain good interface properties with the barrier layer to reduce the interface state density; the diffusion barrier layer can prevent the captured electrons from leaking to the gate electrode and improve the gate voltage resistance of the device.

[0021] Specifically, in order to ensure the stability of the trapped charges, the conduction band bottom of the charge trapping layer is lower than the conduction band bottoms of the diffusion barrier layer and the tunneling layer.

[0022] Furthermore, the epitaxial substrate includes, from bottom to top, a substrate, a buffer layer, a GaN layer, an AlN layer, and a barrier layer.

[0023] Furthermore, the thickness of the barrier layer is 1-30 nm; the thickness of the AlN layer is 1-3 nm; the thickness of the GaN layer is 100-500 nm; the thickness of the buffer layer is 3-5 μm; and the thickness of the substrate is 0.5-2 μm.

[0024] Furthermore, the substrate is selected from one or more of Si, sapphire, GaN or SiC; the buffer layer is selected from one or more of GaN, AlGaN, and AlN; the barrier layer is selected from one or more of AlGaN, InAlN, AlN, and InAlGaN; the passivation layer is selected from one or more of SiO2, SiN, and AlN;

[0025] Furthermore, the thickness of the passivation layer is 1-200 nm.

[0026] Specifically, the GaN-based inverter undergoes initialization before normal operation, that is, a positive voltage is applied to the gate to allow the charge trapping layer to capture a sufficient amount of charge, thereby depleting the two-dimensional electron gas under the gate and realizing an enhanced E-mode device.

[0027] The present invention also provides a method for preparing a GaN-based inverter, which is characterized by comprising the following steps:

[0028] S1. Preparation of epitaxial substrate;

[0029] Etching trench isolation grooves on the epitaxial substrate and evaporating the source and drain electrodes of the E-mode device and the D-mode device;

[0030] S2. Preparation of CTL dielectric layer:

[0031] S2. Pulse growth of a tunneling layer on the surface of the barrier layer;

[0032] Performing pulse growth of a charge trapping layer on the surface of the tunneling layer;

[0033] Performing pulse growth of a diffusion barrier layer on the surface of the charge trapping layer;

[0034] The gate electrodes of the E-mode device and the D-mode device are evaporated on the surface of the diffusion barrier layer to obtain a structural layer;

[0035] and evaporating the gates of the E-mode device and the D-mode device on the surface of the diffusion barrier layer;

[0036] S3. Preparation of passivation layer:

[0037] A passivation layer is deposited on the structural layer, and metal pins for the source, drain and gate, as well as metal connections for the E-mode device and the D-mode device are deposited.

[0038] The present invention applies a CTL dielectric layer to E-mode devices and D-mode devices to achieve regulation of the D-mode threshold voltage, thereby affecting the on-resistance of the D-mode device. This adjusts the resistance ratio of the E-mode and D-mode devices in the on-state and near-on states, optimizes the output swing and gain characteristics of the inverter, eliminates the complex process of preparing E-mode and D-mode devices in batches, and achieves better GaN-based inverter performance.

[0039] Furthermore, in step S1, the annealing treatment is performed in a vacuum environment or in a protective atmosphere formed by at least one inert gas, the annealing temperature is 800-900° C., and the annealing time is 60-70 seconds.

[0040] Furthermore, the gate is selected from one of Ni / Au and Pt / Au.

[0041] Furthermore, trimethylaluminum (TMA) and an O3 source are used for pulse growth to obtain a tunneling layer;

[0042] Specifically, the charge trapping layer is a HfAlO charge trapping layer, which is grown by alternating pulses of trimethylaluminum (TMA), tetrakis(methylethylamino)hafnium (TEMAH) and H2O sources to obtain the HfAlO charge trapping layer;

[0043] The charge trapping layer is a ZnO charge trapping layer, which is pulse grown using diethyl zinc (DEZ) and H2O source to obtain the ZnO charge trapping layer;

[0044] The charge trapping layer is a HfO2 charge trapping layer, which is obtained by pulse growth using tetrakis(methylethylamino)hafnium (TEMAH) and H2O source;

[0045] The diffusion barrier layer is an Al2O3 diffusion barrier layer, which is pulse grown using trimethylaluminum (TMA) and an O3 source to obtain the Al2O3 diffusion barrier layer;

[0046] The diffusion barrier layer is a HfO2 diffusion barrier layer, which is obtained by pulse growth using tetrakis(methylethylamino)hafnium (TEMAH) and an O3 source.

[0047] The present invention has the following beneficial effects:

[0048] 1. The GaN-based inverter of the present invention achieves capture of two-dimensional electron gas channel electrons in the gate region by providing a CTL dielectric layer in the E-mode device and the D-mode device, thereby changing the threshold voltage of the E-mode device and the D-mode device, achieving optimized output swing and gain, and realizing a wide range of threshold voltage control, thereby obtaining an ultra-high threshold voltage that cannot be achieved by conventional E-mode device preparation technology.

[0049] 2. The GaN-based inverter of the present invention can avoid the relatively complex recessed gate etching, fluorine ion implantation and p-GaN gate technology; moreover, the GaN-based inverter of the present invention can effectively adjust the threshold voltage of the D-mode device, thereby realizing the regulation of the on-resistance of the D-mode device, thereby further optimizing the output swing and gain characteristics of the GaN-based inverter, thereby maximizing the operating performance of the GaN-based inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 shows a structural diagram of a GaN-based inverter according to Example 1-2;

[0051] Figure 2 shows a structural diagram of the CTL dielectric layer;

[0052] In the figure: 1. Epitaxial substrate; 11. Substrate; 12. Buffer layer; 13. GaN layer; 14. AlN layer; 15. Barrier layer; 2. CTL dielectric layer; 21. Tunneling layer; 22. Charge trapping layer; 23. Diffusion barrier layer; 3. Passivation layer; 4. Channel isolation groove; 5. Drain; 6. Gate; 7. Source. DETAILED DESCRIPTION

[0053] In order to more clearly illustrate the technical solutions of the present invention, the following examples are given. Unless otherwise stated, the raw materials, reactions and post-processing methods mentioned in the examples are common raw materials on the market and technical methods well known to those skilled in the art.

[0054] Example 1

[0055] A GaN-based inverter includes an epitaxial substrate 1, a trench isolation groove 4 is formed on the epitaxial substrate 1, an E-mode device and a D-mode device are respectively provided on both sides of the trench isolation groove 4, and the E-mode device and the D-mode device are connected by metal wiring;

[0056] Wherein, the E-mode device and the D-mode device are both provided with a structural layer and a passivation layer 3, and the passivation layer 3 partially wraps the structural layer;

[0057] The structural layer includes a source electrode 7, a drain electrode 5, a gate electrode 6, and a CTL dielectric layer 2;

[0058] The source electrode 7 and the drain electrode 5 are deposited on both sides of the upper end surface of the epitaxial substrate 1 , a CTL dielectric layer 2 is deposited between the source electrode 7 and the drain electrode 5 , and a gate electrode 6 is deposited on the upper end surface of the CTL dielectric layer 2 ;

[0059] The source electrode 7, the drain electrode 5, and the gate electrode 6 are all deposited with metal pins penetrating the passivation layer 3. The metal pin of the drain electrode 5 of the E-mode device is connected to the metal pin of the drain electrode 5 and the metal pin of the gate electrode 6 of the D-mode device through metal wires.

[0060] in,

[0061] The epitaxial substrate 1 includes, from bottom to top, a substrate 11 (1 μm), a buffer layer 12 (4 μm), a GaN layer 13 (300 nm), an AlN layer 14 (1 nm), and a barrier layer 15 (25 nm);

[0062] The CTL dielectric layer includes, from bottom to top, a tunneling layer 21 (10 nm), a charge trapping layer 22 (5 nm), and a diffusion barrier layer 23 (25 nm);

[0063] The substrate 11 is a Si substrate, the buffer layer 12 is a GaN buffer layer, and the barrier layer 15 is an Al 0.25 Ga 0.75 N barrier layer;

[0064] The tunneling layer 21 is an Al2O3 tunneling layer, the charge trapping layer 22 is a HfAlO charge trapping layer; the diffusion barrier layer 23 is an Al2O3 layer and a HfO2 layer;

[0065] The preparation method of the GaN-based inverter is as follows:

[0066] S1. The epitaxial substrate sample 1 was ultrasonically cleaned with acetone for 10 min, ultrasonically cleaned with isopropanol for 5 min, rinsed with deionized water for 5 min, and dried with nitrogen to remove impurities on the sample surface;

[0067] The sample is subjected to coating, pre-baking, photolithography, development, and post-baking to define device isolation patterns;

[0068] The sample was placed in the transmission chamber of the ICP-RIE etching equipment, and the isolated Al was etched away in an etching gas of BCl3 and Cl2 (the volume ratio of BCl3 and Cl2 was 1:9). 0.25 Ga 0.75 The N barrier layer and the GaN layer are etched to form a trench isolation groove 4 with a depth of 400 nm and a width of 150 μm;

[0069] The etched samples were ultrasonically cleaned with acetone for 10 min, ultrasonically cleaned with isopropyl alcohol for 5 min, rinsed with deionized water for 5 min, and dried with nitrogen.

[0070] The cleaned sample is subjected to sequential coating, pre-baking, photolithography, development, and post-baking to define the metal regions of the source 7 and drain 5 of the E-mode device and the D-mode device, respectively;

[0071] The sample was immersed in a diluted hydrochloric acid solution for 3 minutes to remove the natural oxide layer on the surface of the sample, and then rinsed with deionized water for 15 minutes, and finally dried with nitrogen, wherein the volume ratio of HCl:H2O in the hydrochloric acid solution was 1:4;

[0072] The processed sample is placed in the transmission cavity of the magnetron sputtering evaporation equipment to evaporate the ohmic contact metal of the source electrode 7 and the drain electrode 5;

[0073] The sample with the ohmic metal of the source electrode 7 and the drain electrode 5 deposited was immersed in a 99.5wt% dimethyl sulfoxide solution and heated in an 80°C water bath for metal stripping. The sample was rinsed with isopropyl alcohol for 10 minutes, rinsed with deionized water for 10 minutes, and dried with nitrogen to obtain the source electrode 7 (Ti / Au 60nm / 150nm) and the drain electrode 5 (Ti / Au, 60nm / 150nm).

[0074] The metal stripped samples were thermally annealed in a N2 atmosphere at a temperature of 800°C for 60 seconds.

[0075] S2. Place the thermally annealed sample into an atomic layer deposition apparatus to deposit a CTL dielectric layer;

[0076] Preparation of tunneling layer 21:

[0077] Trimethylaluminum (TMA) and O3 were used as the source in Al 0.25 Ga 0.75 Pulse growth was performed on the N barrier layer for 100 cycles to obtain an Al2O3 tunneling layer;

[0078] Preparation of the charge trapping layer 22:

[0079] A HfAlO charge trapping layer is obtained by performing 50 cycles of alternating pulse growth on an Al2O3 tunneling layer using trimethylaluminum (TMA), tetrakis(methylethylamino)hafnium (TEMAH) and a H2O source; in the HfAlO charge trapping layer, the deposition pulse ratio of Hf to Al is 5:1;

[0080] Preparation of the diffusion barrier layer 23:

[0081] The Al2O3 layer was obtained by pulse growth of trimethylaluminum (TMA) and O3 source on the HfAlO charge trapping layer for 50 cycles.

[0082] The HfO2 layer was obtained by pulsed growth of 200 cycles on the Al2O3 layer using tetrakis(methylethylamino)hafnium (TEMAH) and an O3 source.

[0083] In the diffusion barrier layer, the proportion of Al2O3 is 20%, and the proportion of HfO2 is 80%.

[0084] The processed samples were subjected to coating, pre-baking, photolithography, development, and post-baking in sequence to define the gate 6 metal areas of the E-mode device and the D-mode device respectively;

[0085] Place the processed sample into an electron beam evaporation device to deposit gate metal;

[0086] The sample with the gate metal deposited was immersed in a 99.5 wt% dimethyl sulfoxide solution and heated in an 80°C water bath for metal stripping. The sample was then rinsed with isopropyl alcohol for 10 min, deionized water for 10 min, and dried with nitrogen to obtain gate 6 (Ni / Au, 50 nm / 200 nm).

[0087] The processed sample is placed in the transfer chamber of the ICP-RIE etching equipment, and the CTL dielectric layer 2 outside the gate area is etched in an etching gas of BCl3 and Cl2 (the volume ratio of BCl3 and Cl2 is 1:9) to form a structural layer;

[0088] S3. The processed sample was deposited with SiN material by chemical vapor deposition as the passivation layer 3 of the device, with a thickness of 100nm;

[0089] The processed samples were subjected to coating, pre-baking, photolithography, development, and post-baking in sequence to define the opening areas of the metal pins of the source 7, drain 5, and gate 6 of the E-mode device and the D-mode device respectively;

[0090] The processed sample is placed in the transfer chamber of the ICP-RIE etching equipment, and the passivation layer 3 in the opening area of ​​the metal pins of the source 7, drain 5 and gate 6 is etched in an etching gas of SF6 and CHF3 (the volume ratio of SF6 and CHF3 is 1:3);

[0091] The etched samples were ultrasonically cleaned with acetone for 10 min, ultrasonically cleaned with isopropyl alcohol for 5 min, rinsed with deionized water for 5 min, and dried with nitrogen.

[0092] The processed samples are sequentially subjected to coating, pre-baking, photolithography, development, and post-baking, and then placed in an electron beam evaporation device to deposit the metal pins of the source 7, drain 6, and gate 5, as well as the metal connections of the E-mode device and the D-mode device;

[0093] The sample was immersed in a 99.5wt% dimethyl sulfoxide solution, heated in a water bath at 80°C for metal stripping, and then rinsed with isopropyl alcohol for 10 minutes, deionized water for 10 minutes, and dried with nitrogen to obtain a GaN-based inverter.

[0094] Example 2

[0095] A GaN-based inverter includes an epitaxial substrate 1, a trench isolation groove 4 is formed on the epitaxial substrate 1, an E-mode device and a D-mode device are respectively provided on both sides of the trench isolation groove 4, and the E-mode device and the D-mode device are connected by metal wiring;

[0096] Wherein, the E-mode device and the D-mode device are both provided with a structural layer and a passivation layer 3, and the passivation layer 3 partially wraps the structural layer;

[0097] The structural layer includes a source electrode 7, a drain electrode 5, a gate electrode 6, and a CTL dielectric layer 2;

[0098] The source electrode 7 and the drain electrode 5 are deposited on both sides of the upper end surface of the epitaxial substrate 1 , a CTL dielectric layer 2 is deposited between the source electrode 7 and the drain electrode 5 , and a gate electrode 6 is deposited on the upper end surface of the CTL dielectric layer 2 ;

[0099] The source electrode 7, the drain electrode 5, and the gate electrode 6 are all deposited with metal pins extending to the upper end surface of the passivation layer 3. The metal pin of the drain electrode 5 of the E-mode device is connected to the metal pin of the drain electrode 5 and the metal pin of the gate electrode 6 of the D-mode device through metal wires.

[0100] in,

[0101] The epitaxial substrate 1 includes, from bottom to top, a substrate 11 (700 nm), a buffer layer 12 (4 μm), a GaN layer 13 (300 nm), an AlN layer 14 (1 nm), and a barrier layer 15 (10 nm);

[0102] The CTL dielectric layer includes, from bottom to top, a tunneling layer 21 (15 nm), a charge trapping layer 22 (10 nm), and a diffusion barrier layer 23 (30 nm);

[0103] The substrate 11 is a Si substrate, the buffer layer 12 is a GaN buffer layer, and the barrier layer 15 is an In 0.17 Al 0.83 N barrier layer;

[0104] The tunneling layer 21 is an Al2O3 tunneling layer, the charge trapping layer 22 is a HfO2 charge trapping layer; the diffusion barrier layer 23 is an Al2O3 diffusion barrier layer;

[0105] The preparation method of the GaN-based inverter is as follows:

[0106] S1. The epitaxial substrate sample 1 was ultrasonically cleaned with acetone for 10 min, ultrasonically cleaned with isopropanol for 5 min, rinsed with deionized water for 5 min, and dried with nitrogen to remove impurities on the sample surface;

[0107] Perform coating, pre-baking, photolithography, development, post-baking on the sample to define the device isolation pattern;

[0108] The sample was placed in the transfer chamber of the ICP-RIE etching equipment, and the In isolation part was etched away in the etching gas of BCl3 and Cl2 (the volume ratio of BCl3 and Cl2 was 1:9). 0.17 Al 0.83 N barrier layer / GaN layer, forming a trench isolation groove 4 with an etching depth of 300nm and a width of 150μm;

[0109] The etched samples were ultrasonically cleaned with acetone for 10 min, ultrasonically cleaned with isopropyl alcohol for 5 min, rinsed with deionized water for 5 min, and dried with nitrogen.

[0110] The cleaned sample is subjected to sequential coating, pre-baking, photolithography, development, and post-baking to define the source 7 and drain 5 of the E-mode device and the D-mode device respectively;

[0111] The sample was immersed in a diluted hydrochloric acid solution for 3 minutes to remove the natural oxide layer on the surface of the sample, and then rinsed with deionized water for 15 minutes, and finally dried with nitrogen gas, wherein the volume ratio of HCl:H2O in the hydrochloric acid solution was 1:4;

[0112] The processed sample is placed in the transmission cavity of the magnetron sputtering evaporation equipment to evaporate the ohmic contact metal of the source electrode 7 and the drain electrode 5;

[0113] The sample of the ohmic metal of the source electrode 7 and the drain electrode 5 after evaporation was immersed in a 99.5wt% dimethyl sulfoxide solution, and the metal was stripped in a water bath heated at 80°C. The sample was rinsed with isopropyl alcohol for 10 minutes, rinsed with deionized water for 10 minutes, and dried with nitrogen to obtain the source electrode 7 (Ti / Au, 60 / 150nm) and the drain electrode 5 (Ti / Au, 60 / 150nm).

[0114] The metal stripped samples were thermally annealed in N2 atmosphere at 900℃;

[0115] S2. Place the thermally annealed sample into an atomic layer deposition apparatus to deposit a CTL dielectric layer 2;

[0116] Preparation of tunneling layer 21:

[0117] Trimethylaluminum (TMA) and O3 source were used in In 0.17 Al 0.83 The Al2O3 tunneling layer was obtained by pulse growth on the N barrier layer for 150 cycles;

[0118] Preparation of the charge trapping layer 22:

[0119] The HfO2 charge trapping layer was obtained by alternating pulse growth of hafnium tetrakis(methylethylamino) (TEMAH) and H2O sources on the Al2O3 tunneling layer for 100 cycles.

[0120] Preparation of the diffusion barrier layer 23:

[0121] The Al2O3 diffusion barrier layer was obtained by pulse growth of trimethylaluminum (TMA) and O3 source on the HfO2 charge trapping layer for 300 cycles.

[0122] The processed samples are sequentially subjected to coating, pre-baking, photolithography, development, and post-baking to define the metal regions of the gate 6 of the E-mode device and the D-mode device respectively;

[0123] Place the processed sample into an electron beam evaporation device to deposit gate metal;

[0124] The sample with the gate metal deposited was immersed in a 99.5 wt% dimethyl sulfoxide solution and heated in an 80°C water bath for metal stripping. The sample was then rinsed with isopropyl alcohol for 10 min, deionized water for 10 min, and dried with nitrogen to obtain gate 6 (Ni / Au, 50 / 200 nm).

[0125] The processed sample is placed in the transfer chamber of the ICP-RIE etching equipment, and the CTL dielectric layer 2 outside the gate area is etched away in an etching gas of BCl3 and Cl2 (the volume ratio of BCl3 and Cl2 is 1:9);

[0126] S3. Preparation of passivation layer:

[0127] The processed samples were deposited with AlN material by chemical vapor deposition as the passivation layer 3 of the device, with a deposition thickness of 50 nm;

[0128] The processed samples are sequentially subjected to coating, pre-baking, photolithography, development, and post-baking to define the metal pin regions of the source 7, drain 5, and gate 6 of the E-mode device and the D-mode device respectively;

[0129] The processed sample is placed in the transfer chamber of the ICP-RIE etching equipment, and the passivation layer 3 in the opening area of ​​the metal pins of the source 7, drain 5 and gate 6 is etched in SF6 and CHF3 etching gas (the volume ratio of SF6 and CHF3 is 1:3);

[0130] The etched samples were ultrasonically cleaned with acetone for 10 min, ultrasonically cleaned with isopropyl alcohol for 5 min, rinsed with deionized water for 5 min, and dried with nitrogen.

[0131] The processed samples are sequentially subjected to coating, pre-baking, photolithography, development, and post-baking, and then placed in an electron beam evaporation device to deposit the metal pins of the source 7, drain 5, and gate 6, as well as the metal connections of the E-mode device and the D-mode device;

[0132] The sample was immersed in a 99.5wt% dimethyl sulfoxide solution, heated in a water bath at 80°C for metal stripping, and then rinsed with isopropyl alcohol for 10 minutes, deionized water for 10 minutes, and dried with nitrogen to obtain a GaN-based inverter.

[0133] from Figure 1-2 As can be seen from the figure, 1 is the epitaxial base; 11 is the substrate; 12 is the buffer layer; 13 is the GaN layer; 14 is the AlN layer; 15 is the barrier layer; 2 is the CTL dielectric layer; 21 is the tunneling layer; 22 is the charge trapping layer; 23 is the diffusion barrier layer; 3 is the passivation layer; 4 is the channel isolation groove; 5 is the drain; 6 is the gate; and 7 is the source.

[0134] Comparative Example 1

[0135] The GaN-based inverter structures of Comparative Example 1 are the same as those of Example 1, with the only difference being that the thickness of HfAlO in the CTL dielectric layer in Example 1 is adjusted to 10 nm.

[0136] Comparative Example 2

[0137] The GaN-based inverter structure of Comparative Example 2 is the same as that of Example 1, with the only difference being that the CTL dielectric layer in Example 1 is replaced by only an AlN dielectric layer.

[0138] Test Example 1

[0139] Conducting single device electrical testing on the GaN-based inverters of Example 1 and Comparative Examples 1-2;

[0140] Test method: Probe station electrical test, apply initialization charging voltage to the gate of GaN-based inverter E-mode device of Example 1 and Comparative Examples 1-2, and d -V g Transfer characteristic curve test, get the E-mode device threshold voltage (V th , the largest positive value);

[0141] A charging voltage is applied to the gate of the GaN-based inverter D-mode device of Example 1 and Comparative Examples 1-2, and the charging voltage is applied to the gate of the GaN-based inverter D-mode device of Example 1 and Comparative Examples 1-2. d -V g Transfer characteristic curve test, adjust the D-mode device threshold voltage to near 0V to increase the D-mode device on-resistance.

[0142] The test results are shown in Table 1;

[0143] Table 1 Electrical tests on GaN-based inverters of Example 1 and Comparative Examples 1-2

[0144] sample Initial threshold voltage Initialization voltage Threshold voltage after modulation Modulation amount Example 1 (E-mode) -8V 20V 5V 13V Comparative Example 1 (E-mode) -7.5V 20V 3V 10.5V Comparative Example 2 (E-mode) -8V 20V -7.5V 0.5V Example 1 (D-mode) -8V 14V 0V 8V Comparative Example 1 (D-mode) -7.5V 16V 0V 7.5V Comparative Example 2 (D-mode) -8V 20V -7.5V 0.5V

[0145] It can be seen from Table 1 that the GaN-based E-mode device of Example 1 can achieve positive regulation of the threshold voltage. This is because the charge trapping layer captures electrons in the two-dimensional electron gas channel, achieving channel electron depletion, which leads to a positive bias in the threshold voltage. The GaN-based E-mode device of Comparative Example 1 has a smaller charge trapping layer thickness and a weaker ability to capture electrons, so the maximum threshold voltage of the E-mode device achieved is lower than that of Example 1. The GaN-based E-mode device of Comparative Example 2 has only an AlN dielectric layer and is basically unable to capture electrons, so it is impossible to achieve threshold voltage modulation of the E-mode device. At the same time, the threshold voltages of the D-mode devices of Example 1 and Comparative Example 1 can be adjusted to near 0V, but Example 1 requires a higher initialization voltage to complete the correct modulation of the D-mode device due to its weak electron capture ability. The GaN-based E-mode device of Comparative Example 2 has only an AlN dielectric layer and is basically unable to capture electrons, so it is impossible to modulate the threshold voltage of the D-mode device to near 0V.

[0146] Test Example 2

[0147] The GaN-based inverters of Example 1 and Comparative Examples 1-2 were subjected to inverter electrical testing;

[0148] Test method: Use a probe station to test the GaN-based inverters of Example 1 and Comparative Examples 1-2. in -V out Test and obtain the input and output characteristics of GaN-based inverter;

[0149] The test results are shown in Table 2;

[0150] Table 2 Electrical tests of GaN-based inverters of Example 1 and Comparative Examples 1-2

[0151] sample <![CDATA[V DD ]]> Output swing <![CDATA[NM H ]]> <![CDATA[NM L ]]> Gain Example 1 10V 9.2V 4.2V 4.1V 15 Comparative Example 1 6V 5.1V 2.0V 1.7V 8 Comparative Example 2 / / / / /

[0152] It can be seen from Table 2 that the GaN-based inverter of Example 1 can support a 10V operating voltage and has a high output swing and good noise margin. This is because the threshold voltage of the inverter E / D-mode device is adjustable. The GaN-based inverter of Comparative Example 1 has a lower supported inverter operating voltage, which can only reach 6V applications, because the threshold voltage of the E-mdoe device is lower. The GaN-based inverter of Comparative Example 2 cannot exhibit the basic performance of the inverter because the threshold voltage of the E-mdoe device cannot be modulated to a positive value.

[0153] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations that come within the meaning and range of equivalents of the claims be embraced therein.

[0154] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A GaN-based inverter, characterized in that: The GaN-based inverter includes an epitaxial substrate, a trench isolation groove is formed on the epitaxial substrate, an E-mode device and a D-mode device are respectively provided on both sides of the trench isolation groove, and the E-mode device and the D-mode device are connected by metal wiring; Wherein, the E-mode device and the D-mode device are both provided with a structural layer and a passivation layer, and the passivation layer partially or completely wraps the structural layer; The structural layer includes a source electrode, a drain electrode, a gate electrode, and a CTL dielectric layer; The source electrode and the drain electrode are deposited on both sides of the upper end surface of the epitaxial substrate, a CTL dielectric layer is deposited between the source electrode and the drain, and a gate electrode is deposited on the upper end surface of the CTL dielectric layer; Metal pins penetrating the passivation layer are deposited on the source, the drain, and the gate, and the metal pin of the drain of the E-mode device is connected to the metal pin of the drain and the metal pin of the gate of the D-mode device through metal wires; The CTL dielectric layer includes a tunneling layer, a charge trapping layer and a diffusion barrier layer in the direction away from the substrate; The tunneling layer is selected from Al2O3; The charge trapping layer is selected from one or more of HfAlO, ZnO, and HfO2; The diffusion barrier layer is selected from one or more of Al2O3 and HfO2.

2. The GaN-based inverter according to claim 1, characterized in that: The thickness of the tunneling layer is 1-30 nm; the thickness of the charge trapping layer is 1-15 nm; and the thickness of the diffusion barrier layer is 1-30 nm.

3. The GaN-based inverter according to claim 1, characterized in that: The depth of the trench isolation groove is 300-500 nm.

4. The GaN-based inverter according to claim 1, characterized in that: The thickness of the passivation layer is 1-200 nm.

5. The GaN-based inverter according to claim 4, characterized in that: The epitaxial substrate includes, from bottom to top, a substrate, a buffer layer, a GaN layer, an AlN layer, and a barrier layer.

6. The GaN-based inverter according to claim 5, characterized in that: The thickness of the barrier layer is 1-30 nm; the thickness of the AlN layer is 1-3 nm; the thickness of the GaN layer is 100-500 nm; the thickness of the buffer layer is 3-5 μm; and the thickness of the substrate is 0.5-2 μm.

7. The GaN-based inverter according to claim 6, characterized in that: The substrate is selected from one or more of Si, sapphire, GaN, and SiC; the buffer layer is selected from one or more of GaN, AlGaN, and AlN; the barrier layer is selected from one or more of AlGaN, InAlN, AlN, and InAlGaN; and the passivation layer is selected from one or more of SiO2, SiN, and AlN.

8. The method for preparing a GaN-based inverter according to any one of claims 1 to 7, characterized in that: The steps include: S1. Etching trench isolation grooves on the epitaxial substrate, and evaporating the source and drain of the E-mode device and the D-mode device, and annealing; S2. Pulse growth of a tunneling layer on the surface of the barrier layer; Performing pulse growth of a charge trapping layer on the surface of the tunneling layer; Performing pulse growth of a diffusion barrier layer on the surface of the charge trapping layer; The gate electrodes of the E-mode device and the D-mode device are evaporated on the surface of the diffusion barrier layer to obtain a structural layer; S3. Depositing a passivation layer on the structural layer, depositing metal pins of the source, drain and gate, and metal connections of the E-mode device and the D-mode device to obtain an inverter.

9. The method for preparing a GaN-based inverter according to claim 8, wherein: In step S1 , the annealing treatment is performed in a vacuum environment or in a protective atmosphere formed by at least one inert gas, the annealing temperature is 800-900° C., and the annealing time is 60-70 seconds.

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